@@ -189,6 +189,10 ARCHITECTURE beh OF MINI_LFR_top IS | |||||
189 | SIGNAL rstn_50_d1 : STD_LOGIC; |
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189 | SIGNAL rstn_50_d1 : STD_LOGIC; | |
190 | SIGNAL rstn_50_d2 : STD_LOGIC; |
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190 | SIGNAL rstn_50_d2 : STD_LOGIC; | |
191 | SIGNAL rstn_50_d3 : STD_LOGIC; |
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191 | SIGNAL rstn_50_d3 : STD_LOGIC; | |
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192 | ||||
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193 | SIGNAL lfr_debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0); | |||
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194 | SIGNAL lfr_debug_vector_ms : STD_LOGIC_VECTOR(11 DOWNTO 0); | |||
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195 | ||||
192 | BEGIN -- beh |
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196 | BEGIN -- beh | |
193 |
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197 | |||
194 | ----------------------------------------------------------------------------- |
|
198 | ----------------------------------------------------------------------------- | |
@@ -232,7 +236,7 BEGIN -- beh | |||||
232 | rstn_50_d2 <= '0'; |
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236 | rstn_50_d2 <= '0'; | |
233 | rstn_50_d3 <= '0'; |
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237 | rstn_50_d3 <= '0'; | |
234 |
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238 | |||
235 |
ELSIF clk_50' |
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239 | ELSIF clk_50'EVENT AND clk_50 = '1' THEN -- rising clock edge | |
236 | clk_50_s <= NOT clk_50_s; |
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240 | clk_50_s <= NOT clk_50_s; | |
237 | rstn_50_d1 <= '1'; |
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241 | rstn_50_d1 <= '1'; | |
238 | rstn_50_d2 <= rstn_50_d1; |
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242 | rstn_50_d2 <= rstn_50_d1; | |
@@ -249,7 +253,7 BEGIN -- beh | |||||
249 | rstn_25_d1 <= '0'; |
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253 | rstn_25_d1 <= '0'; | |
250 | rstn_25_d2 <= '0'; |
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254 | rstn_25_d2 <= '0'; | |
251 | rstn_25_d3 <= '0'; |
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255 | rstn_25_d3 <= '0'; | |
252 |
ELSIF clk_50_s' |
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256 | ELSIF clk_50_s'EVENT AND clk_50_s = '1' THEN -- rising clock edge | |
253 | clk_25 <= NOT clk_25; |
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257 | clk_25 <= NOT clk_25; | |
254 | rstn_25_d1 <= '1'; |
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258 | rstn_25_d1 <= '1'; | |
255 | rstn_25_d2 <= rstn_25_d1; |
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259 | rstn_25_d2 <= rstn_25_d1; | |
@@ -262,7 +266,7 BEGIN -- beh | |||||
262 | BEGIN -- PROCESS |
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266 | BEGIN -- PROCESS | |
263 | IF reset = '0' THEN -- asynchronous reset (active low) |
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267 | IF reset = '0' THEN -- asynchronous reset (active low) | |
264 | clk_24 <= '0'; |
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268 | clk_24 <= '0'; | |
265 |
ELSIF clk_49' |
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269 | ELSIF clk_49'EVENT AND clk_49 = '1' THEN -- rising clock edge | |
266 |
clk_24 <= NOT clk_24; |
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270 | clk_24 <= NOT clk_24; | |
267 | END IF; |
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271 | END IF; | |
268 | END PROCESS; |
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272 | END PROCESS; | |
@@ -439,7 +443,7 BEGIN -- beh | |||||
439 | dconnect => swni.dconnect(j*2+1 DOWNTO j*2)); |
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443 | dconnect => swni.dconnect(j*2+1 DOWNTO j*2)); | |
440 | END GENERATE spw_inputloop; |
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444 | END GENERATE spw_inputloop; | |
441 |
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445 | |||
442 |
swni.rmapnodeaddr <= ( |
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446 | swni.rmapnodeaddr <= (OTHERS => '0'); | |
443 |
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447 | |||
444 | -- SPW core |
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448 | -- SPW core | |
445 | sw0 : grspwm GENERIC MAP( |
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449 | sw0 : grspwm GENERIC MAP( | |
@@ -485,8 +489,8 BEGIN -- beh | |||||
485 | ------------------------------------------------------------------------------- |
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489 | ------------------------------------------------------------------------------- | |
486 |
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490 | |||
487 |
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491 | |||
488 |
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492 | LFR_rstn <= LFR_soft_rstn AND rstn_25; | |
489 | LFR_rstn <= rstn_25; |
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493 | --LFR_rstn <= rstn_25; | |
490 |
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494 | |||
491 | lpp_lfr_1 : lpp_lfr |
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495 | lpp_lfr_1 : lpp_lfr | |
492 | GENERIC MAP ( |
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496 | GENERIC MAP ( | |
@@ -501,7 +505,7 BEGIN -- beh | |||||
501 | pirq_ms => 6, |
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505 | pirq_ms => 6, | |
502 | pirq_wfp => 14, |
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506 | pirq_wfp => 14, | |
503 | hindex => 2, |
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507 | hindex => 2, | |
504 |
top_lfr_version => X"00012 |
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508 | top_lfr_version => X"000123") -- aa.bb.cc version | |
505 | PORT MAP ( |
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509 | PORT MAP ( | |
506 | clk => clk_25, |
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510 | clk => clk_25, | |
507 | rstn => LFR_rstn, |
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511 | rstn => LFR_rstn, | |
@@ -514,11 +518,23 BEGIN -- beh | |||||
514 | ahbo => ahbo_m_ext(2), |
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518 | ahbo => ahbo_m_ext(2), | |
515 | coarse_time => coarse_time, |
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519 | coarse_time => coarse_time, | |
516 | fine_time => fine_time, |
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520 | fine_time => fine_time, | |
517 |
data_shaping_BW => bias_fail_sw_sig |
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521 | data_shaping_BW => bias_fail_sw_sig, | |
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522 | debug_vector => lfr_debug_vector, | |||
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523 | debug_vector_ms => lfr_debug_vector_ms | |||
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524 | ); | |||
518 |
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525 | |||
519 | observation_reg <= (others => '0'); |
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526 | observation_reg(11 DOWNTO 0) <= lfr_debug_vector; | |
520 | observation_vector_0 <= (others => '0'); |
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527 | observation_reg(31 DOWNTO 12) <= (OTHERS => '0'); | |
521 | observation_vector_1 <= (others => '0'); |
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528 | observation_vector_0(11 DOWNTO 0) <= lfr_debug_vector; | |
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529 | observation_vector_1(11 DOWNTO 0) <= lfr_debug_vector; | |||
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530 | IO0 <= rstn_25; | |||
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531 | IO1 <= lfr_debug_vector_ms(0); -- LFR MS FFT data_valid | |||
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532 | IO2 <= lfr_debug_vector_ms(0); -- LFR MS FFT ready | |||
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533 | IO3 <= lfr_debug_vector(0); -- LFR APBREG error_buffer_full | |||
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534 | IO4 <= lfr_debug_vector(1); -- LFR APBREG reg_sp.status_error_buffer_full | |||
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535 | IO5 <= lfr_debug_vector(8); -- LFR APBREG ready_matrix_f2 | |||
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536 | IO6 <= lfr_debug_vector(9); -- LFR APBREG reg0_ready_matrix_f2 | |||
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537 | IO7 <= lfr_debug_vector(10); -- LFR APBREG reg0_ready_matrix_f2 | |||
522 |
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538 | |||
523 | all_sample: FOR I IN 7 DOWNTO 0 GENERATE |
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539 | all_sample : FOR I IN 7 DOWNTO 0 GENERATE | |
524 | sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0'; |
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540 | sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0'; | |
@@ -560,9 +576,9 BEGIN -- beh | |||||
560 | GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8) |
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576 | GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8) | |
561 | PORT MAP(rstn_25, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo); |
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577 | PORT MAP(rstn_25, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo); | |
562 |
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578 | |||
563 |
gpioi.sig_en <= ( |
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579 | gpioi.sig_en <= (OTHERS => '0'); | |
564 |
gpioi.sig_in <= ( |
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580 | gpioi.sig_in <= (OTHERS => '0'); | |
565 |
gpioi.din <= ( |
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581 | gpioi.din <= (OTHERS => '0'); | |
566 | --pio_pad_0 : iopad |
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582 | --pio_pad_0 : iopad | |
567 | -- GENERIC MAP (tech => CFG_PADTECH) |
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583 | -- GENERIC MAP (tech => CFG_PADTECH) | |
568 | -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0)); |
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584 | -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0)); | |
@@ -591,81 +607,81 BEGIN -- beh | |||||
591 | PROCESS (clk_25, rstn_25) |
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607 | PROCESS (clk_25, rstn_25) | |
592 | BEGIN -- PROCESS |
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608 | BEGIN -- PROCESS | |
593 |
IF rstn_25 = '0' THEN |
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609 | IF rstn_25 = '0' THEN -- asynchronous reset (active low) | |
594 | IO0 <= '0'; |
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610 | -- --IO0 <= '0'; | |
595 | IO1 <= '0'; |
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611 | -- IO1 <= '0'; | |
596 | IO2 <= '0'; |
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612 | -- IO2 <= '0'; | |
597 | IO3 <= '0'; |
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613 | -- IO3 <= '0'; | |
598 | IO4 <= '0'; |
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614 | -- IO4 <= '0'; | |
599 | IO5 <= '0'; |
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615 | -- IO5 <= '0'; | |
600 | IO6 <= '0'; |
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616 | -- IO6 <= '0'; | |
601 | IO7 <= '0'; |
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617 | -- IO7 <= '0'; | |
602 | IO8 <= '0'; |
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618 | IO8 <= '0'; | |
603 | IO9 <= '0'; |
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619 | IO9 <= '0'; | |
604 | IO10 <= '0'; |
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620 | IO10 <= '0'; | |
605 | IO11 <= '0'; |
|
621 | IO11 <= '0'; | |
606 |
ELSIF clk_25' |
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622 | ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge | |
607 | CASE gpioo.dout(2 DOWNTO 0) IS |
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623 | CASE gpioo.dout(2 DOWNTO 0) IS | |
608 |
WHEN "011" => |
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624 | WHEN "011" => | |
609 | IO0 <= observation_reg(0 ); |
|
625 | -- --IO0 <= observation_reg(0 ); | |
610 | IO1 <= observation_reg(1 ); |
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626 | -- IO1 <= observation_reg(1 ); | |
611 | IO2 <= observation_reg(2 ); |
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627 | -- IO2 <= observation_reg(2 ); | |
612 | IO3 <= observation_reg(3 ); |
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628 | -- IO3 <= observation_reg(3 ); | |
613 | IO4 <= observation_reg(4 ); |
|
629 | -- IO4 <= observation_reg(4 ); | |
614 | IO5 <= observation_reg(5 ); |
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630 | -- IO5 <= observation_reg(5 ); | |
615 | IO6 <= observation_reg(6 ); |
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631 | -- IO6 <= observation_reg(6 ); | |
616 | IO7 <= observation_reg(7 ); |
|
632 | -- IO7 <= observation_reg(7 ); | |
617 |
IO8 <= observation_reg(8 |
|
633 | IO8 <= observation_reg(8); | |
618 |
IO9 <= observation_reg(9 |
|
634 | IO9 <= observation_reg(9); | |
619 | IO10 <= observation_reg(10); |
|
635 | IO10 <= observation_reg(10); | |
620 | IO11 <= observation_reg(11); |
|
636 | IO11 <= observation_reg(11); | |
621 |
WHEN "001" => |
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637 | WHEN "001" => | |
622 | IO0 <= observation_reg(0 + 12); |
|
638 | -- --IO0 <= observation_reg(0 + 12); | |
623 | IO1 <= observation_reg(1 + 12); |
|
639 | -- IO1 <= observation_reg(1 + 12); | |
624 | IO2 <= observation_reg(2 + 12); |
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640 | -- IO2 <= observation_reg(2 + 12); | |
625 | IO3 <= observation_reg(3 + 12); |
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641 | -- IO3 <= observation_reg(3 + 12); | |
626 | IO4 <= observation_reg(4 + 12); |
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642 | -- IO4 <= observation_reg(4 + 12); | |
627 | IO5 <= observation_reg(5 + 12); |
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643 | -- IO5 <= observation_reg(5 + 12); | |
628 | IO6 <= observation_reg(6 + 12); |
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644 | -- IO6 <= observation_reg(6 + 12); | |
629 | IO7 <= observation_reg(7 + 12); |
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645 | -- IO7 <= observation_reg(7 + 12); | |
630 |
IO8 <= observation_reg(8 |
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646 | IO8 <= observation_reg(8 + 12); | |
631 |
IO9 <= observation_reg(9 |
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647 | IO9 <= observation_reg(9 + 12); | |
632 | IO10 <= observation_reg(10 + 12); |
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648 | IO10 <= observation_reg(10 + 12); | |
633 | IO11 <= observation_reg(11 + 12); |
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649 | IO11 <= observation_reg(11 + 12); | |
634 |
WHEN "010" => |
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650 | WHEN "010" => | |
635 | IO0 <= observation_reg(0 + 12 + 12); |
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651 | -- --IO0 <= observation_reg(0 + 12 + 12); | |
636 | IO1 <= observation_reg(1 + 12 + 12); |
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652 | -- IO1 <= observation_reg(1 + 12 + 12); | |
637 | IO2 <= observation_reg(2 + 12 + 12); |
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653 | -- IO2 <= observation_reg(2 + 12 + 12); | |
638 | IO3 <= observation_reg(3 + 12 + 12); |
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654 | -- IO3 <= observation_reg(3 + 12 + 12); | |
639 | IO4 <= observation_reg(4 + 12 + 12); |
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655 | -- IO4 <= observation_reg(4 + 12 + 12); | |
640 | IO5 <= observation_reg(5 + 12 + 12); |
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656 | -- IO5 <= observation_reg(5 + 12 + 12); | |
641 | IO6 <= observation_reg(6 + 12 + 12); |
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657 | -- IO6 <= observation_reg(6 + 12 + 12); | |
642 | IO7 <= observation_reg(7 + 12 + 12); |
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658 | -- IO7 <= observation_reg(7 + 12 + 12); | |
643 | IO8 <= '0'; |
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659 | IO8 <= '0'; | |
644 | IO9 <= '0'; |
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660 | IO9 <= '0'; | |
645 | IO10 <= '0'; |
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661 | IO10 <= '0'; | |
646 | IO11 <= '0'; |
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662 | IO11 <= '0'; | |
647 |
WHEN "000" => |
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663 | WHEN "000" => | |
648 | IO0 <= observation_vector_0(0 ); |
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664 | -- --IO0 <= observation_vector_0(0 ); | |
649 | IO1 <= observation_vector_0(1 ); |
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665 | -- IO1 <= observation_vector_0(1 ); | |
650 | IO2 <= observation_vector_0(2 ); |
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666 | -- IO2 <= observation_vector_0(2 ); | |
651 | IO3 <= observation_vector_0(3 ); |
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667 | -- IO3 <= observation_vector_0(3 ); | |
652 | IO4 <= observation_vector_0(4 ); |
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668 | -- IO4 <= observation_vector_0(4 ); | |
653 | IO5 <= observation_vector_0(5 ); |
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669 | -- IO5 <= observation_vector_0(5 ); | |
654 | IO6 <= observation_vector_0(6 ); |
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670 | -- IO6 <= observation_vector_0(6 ); | |
655 | IO7 <= observation_vector_0(7 ); |
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671 | -- IO7 <= observation_vector_0(7 ); | |
656 |
IO8 <= observation_vector_0(8 |
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672 | IO8 <= observation_vector_0(8); | |
657 |
IO9 <= observation_vector_0(9 |
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673 | IO9 <= observation_vector_0(9); | |
658 | IO10 <= observation_vector_0(10); |
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674 | IO10 <= observation_vector_0(10); | |
659 | IO11 <= observation_vector_0(11); |
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675 | IO11 <= observation_vector_0(11); | |
660 |
WHEN "100" => |
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676 | WHEN "100" => | |
661 | IO0 <= observation_vector_1(0 ); |
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677 | -- --IO0 <= observation_vector_1(0 ); | |
662 | IO1 <= observation_vector_1(1 ); |
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678 | -- IO1 <= observation_vector_1(1 ); | |
663 | IO2 <= observation_vector_1(2 ); |
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679 | -- IO2 <= observation_vector_1(2 ); | |
664 | IO3 <= observation_vector_1(3 ); |
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680 | -- IO3 <= observation_vector_1(3 ); | |
665 | IO4 <= observation_vector_1(4 ); |
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681 | -- IO4 <= observation_vector_1(4 ); | |
666 | IO5 <= observation_vector_1(5 ); |
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682 | -- IO5 <= observation_vector_1(5 ); | |
667 | IO6 <= observation_vector_1(6 ); |
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683 | -- IO6 <= observation_vector_1(6 ); | |
668 | IO7 <= observation_vector_1(7 ); |
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684 | -- IO7 <= observation_vector_1(7 ); | |
669 |
IO8 <= observation_vector_1(8 |
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685 | IO8 <= observation_vector_1(8); | |
670 |
IO9 <= observation_vector_1(9 |
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686 | IO9 <= observation_vector_1(9); | |
671 | IO10 <= observation_vector_1(10); |
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687 | IO10 <= observation_vector_1(10); | |
@@ -695,4 +711,4 BEGIN -- beh | |||||
695 | END GENERATE ahbo_m_ext_not_used; |
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711 | END GENERATE ahbo_m_ext_not_used; | |
696 | END GENERATE all_ahbo_m_ext; |
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712 | END GENERATE all_ahbo_m_ext; | |
697 |
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713 | |||
698 | END beh; No newline at end of file |
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714 | END beh; |
@@ -19,8 +19,6 USE lpp.lpp_sim_pkg.ALL; | |||||
19 | USE lpp.lpp_lfr_apbreg_pkg.ALL; |
|
19 | USE lpp.lpp_lfr_apbreg_pkg.ALL; | |
20 | USE lpp.lpp_lfr_time_management_apbreg_pkg.ALL; |
|
20 | USE lpp.lpp_lfr_time_management_apbreg_pkg.ALL; | |
21 |
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21 | |||
22 | LIBRARY postlayout; |
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|||
23 | USE postlayout.ALL; |
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|||
24 |
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22 | |||
25 | ENTITY testbench IS |
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23 | ENTITY testbench IS | |
26 | END; |
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24 | END; | |
@@ -194,18 +192,18 BEGIN | |||||
194 | ADC_SDO <= x"AA"; |
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192 | ADC_SDO <= x"AA"; | |
195 |
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193 | |||
196 | SRAM_DQ <= (OTHERS => 'Z'); |
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194 | SRAM_DQ <= (OTHERS => 'Z'); | |
197 | IO0 <= 'Z'; |
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195 | --IO0 <= 'Z'; | |
198 | IO1 <= 'Z'; |
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196 | --IO1 <= 'Z'; | |
199 | IO2 <= 'Z'; |
|
197 | --IO2 <= 'Z'; | |
200 | IO3 <= 'Z'; |
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198 | --IO3 <= 'Z'; | |
201 | IO4 <= 'Z'; |
|
199 | --IO4 <= 'Z'; | |
202 | IO5 <= 'Z'; |
|
200 | --IO5 <= 'Z'; | |
203 | IO6 <= 'Z'; |
|
201 | --IO6 <= 'Z'; | |
204 | IO7 <= 'Z'; |
|
202 | --IO7 <= 'Z'; | |
205 | IO8 <= 'Z'; |
|
203 | --IO8 <= 'Z'; | |
206 | IO9 <= 'Z'; |
|
204 | --IO9 <= 'Z'; | |
207 | IO10 <= 'Z'; |
|
205 | --IO10 <= 'Z'; | |
208 | IO11 <= 'Z'; |
|
206 | --IO11 <= 'Z'; | |
209 |
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207 | |||
210 | ----------------------------------------------------------------------------- |
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208 | ----------------------------------------------------------------------------- | |
211 | -- DUT |
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209 | -- DUT |
@@ -58,7 +58,10 ENTITY lpp_lfr IS | |||||
58 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo |
|
58 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo | |
59 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo |
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59 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo | |
60 | -- |
|
60 | -- | |
61 | data_shaping_BW : OUT STD_LOGIC |
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61 | data_shaping_BW : OUT STD_LOGIC; | |
|
62 | -- | |||
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63 | debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); | |||
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64 | debug_vector_ms : OUT STD_LOGIC_VECTOR(11 DOWNTO 0) | |||
62 |
|
|
65 | ); | |
63 | END lpp_lfr; |
|
66 | END lpp_lfr; | |
64 |
|
67 | |||
@@ -223,10 +226,14 ARCHITECTURE beh OF lpp_lfr IS | |||||
223 | SIGNAL dma_buffer_full_err : STD_LOGIC_VECTOR(4 DOWNTO 0); |
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226 | SIGNAL dma_buffer_full_err : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
224 | SIGNAL dma_grant_error : STD_LOGIC; |
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227 | SIGNAL dma_grant_error : STD_LOGIC; | |
225 |
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228 | |||
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229 | SIGNAL apb_reg_debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0); | |||
226 | ----------------------------------------------------------------------------- |
|
230 | ----------------------------------------------------------------------------- | |
227 | -- SIGNAL run_dma : STD_LOGIC; |
|
231 | -- SIGNAL run_dma : STD_LOGIC; | |
228 | BEGIN |
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232 | BEGIN | |
229 |
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233 | |||
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234 | debug_vector <= apb_reg_debug_vector; | |||
|
235 | ----------------------------------------------------------------------------- | |||
|
236 | ||||
230 | sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0); |
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237 | sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0); | |
231 | sample_s(7 DOWNTO 5) <= sample_B(2 DOWNTO 0); |
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238 | sample_s(7 DOWNTO 5) <= sample_B(2 DOWNTO 0); | |
232 |
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239 | |||
@@ -334,7 +341,8 BEGIN | |||||
334 |
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341 | |||
335 | wfp_ready_buffer => wfp_ready_buffer,-- TODO |
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342 | wfp_ready_buffer => wfp_ready_buffer,-- TODO | |
336 | wfp_buffer_time => wfp_buffer_time,-- TODO |
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343 | wfp_buffer_time => wfp_buffer_time,-- TODO | |
337 | wfp_error_buffer_full => wfp_error_buffer_full -- TODO |
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344 | wfp_error_buffer_full => wfp_error_buffer_full, -- TODO | |
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345 | debug_vector => apb_reg_debug_vector | |||
338 | ); |
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346 | ); | |
339 |
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347 | |||
340 | ----------------------------------------------------------------------------- |
|
348 | ----------------------------------------------------------------------------- | |
@@ -480,7 +488,9 BEGIN | |||||
480 |
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488 | |||
481 | matrix_time_f0 => matrix_time_f0, |
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489 | matrix_time_f0 => matrix_time_f0, | |
482 | matrix_time_f1 => matrix_time_f1, |
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490 | matrix_time_f1 => matrix_time_f1, | |
483 |
matrix_time_f2 => matrix_time_f2 |
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491 | matrix_time_f2 => matrix_time_f2, | |
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492 | ||||
|
493 | debug_vector => debug_vector_ms); | |||
484 |
|
494 | |||
485 | ----------------------------------------------------------------------------- |
|
495 | ----------------------------------------------------------------------------- | |
486 | --run_dma <= run_ms OR run; |
|
496 | --run_dma <= run_ms OR run; |
@@ -137,7 +137,9 ENTITY lpp_lfr_apbreg IS | |||||
137 | wfp_length_buffer : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); |
|
137 | wfp_length_buffer : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); | |
138 | wfp_ready_buffer : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
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138 | wfp_ready_buffer : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
139 | wfp_buffer_time : IN STD_LOGIC_VECTOR(48*4-1 DOWNTO 0); |
|
139 | wfp_buffer_time : IN STD_LOGIC_VECTOR(48*4-1 DOWNTO 0); | |
140 | wfp_error_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0) |
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140 | wfp_error_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
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141 | --------------------------------------------------------------------------- | |||
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142 | debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0) | |||
141 |
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143 | |||
142 | ); |
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144 | ); | |
143 |
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145 | |||
@@ -269,6 +271,15 ARCHITECTURE beh OF lpp_lfr_apbreg IS | |||||
269 |
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271 | |||
270 | BEGIN -- beh |
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272 | BEGIN -- beh | |
271 |
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273 | |||
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274 | debug_vector(0) <= error_buffer_full; | |||
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275 | debug_vector(1) <= reg_sp.status_error_buffer_full; | |||
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276 | debug_vector(4 DOWNTO 2) <= error_input_fifo_write; | |||
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277 | debug_vector(7 DOWNTO 5) <= reg_sp.status_error_input_fifo_write; | |||
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278 | debug_vector(8) <= ready_matrix_f2; | |||
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279 | debug_vector(9) <= reg0_ready_matrix_f2; | |||
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280 | debug_vector(10) <= reg1_ready_matrix_f2; | |||
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281 | debug_vector(11) <= HRESETn; | |||
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282 | ||||
272 | -- status_ready_matrix_f0 <= reg_sp.status_ready_matrix_f0; |
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283 | -- status_ready_matrix_f0 <= reg_sp.status_ready_matrix_f0; | |
273 | -- status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1; |
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284 | -- status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1; | |
274 | -- status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2; |
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285 | -- status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2; | |
@@ -778,4 +789,4 BEGIN -- beh | |||||
778 |
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789 | |||
779 | END beh; |
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790 | END beh; | |
780 |
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791 | |||
781 |
------------------------------------------------------------------------------ |
|
792 | ------------------------------------------------------------------------------ |
@@ -76,8 +76,9 ENTITY lpp_lfr_ms IS | |||||
76 |
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76 | |||
77 | matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO |
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77 | matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO | |
78 | matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO |
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78 | matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO | |
79 | matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) -- TODO |
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79 | matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO | |
80 |
|
80 | --------------------------------------------------------------------------- | ||
|
81 | debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0) | |||
81 | ); |
|
82 | ); | |
82 | END; |
|
83 | END; | |
83 |
|
84 | |||
@@ -442,7 +443,7 BEGIN | |||||
442 | ReUse => (OTHERS => '0'), |
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443 | ReUse => (OTHERS => '0'), | |
443 | run => (OTHERS => '1'), |
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444 | run => (OTHERS => '1'), | |
444 |
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445 | |||
445 | wen => sample_f2_wen, |
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446 | wen => sample_f2_wen_s, | |
446 | wdata => sample_f2_wdata, |
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447 | wdata => sample_f2_wdata, | |
447 | ren => sample_f2_ren, |
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448 | ren => sample_f2_ren, | |
448 | rdata => sample_f2_rdata, |
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449 | rdata => sample_f2_rdata, | |
@@ -688,6 +689,11 BEGIN | |||||
688 | fft_data_valid => fft_data_valid, |
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689 | fft_data_valid => fft_data_valid, | |
689 | fft_ready => fft_ready); |
|
690 | fft_ready => fft_ready); | |
690 |
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691 | |||
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692 | debug_vector(0) <= fft_data_valid; | |||
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693 | debug_vector(1) <= fft_ready; | |||
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694 | debug_vector(11 DOWNTO 2) <= (OTHERS => '0'); | |||
|
695 | ||||
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696 | ||||
691 |
|
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697 | ----------------------------------------------------------------------------- | |
692 | fft_ready_rising_down <= fft_ready_reg AND NOT fft_ready; |
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698 | fft_ready_rising_down <= fft_ready_reg AND NOT fft_ready; | |
693 | sample_load_rising_down <= sample_load_reg AND NOT sample_load; |
|
699 | sample_load_rising_down <= sample_load_reg AND NOT sample_load; |
@@ -107,7 +107,8 PACKAGE lpp_lfr_pkg IS | |||||
107 | length_matrix_f2 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); |
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107 | length_matrix_f2 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); | |
108 | matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
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108 | matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
109 | matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
109 | matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
110 |
matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) |
|
110 | matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
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111 | debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)); | |||
111 | END COMPONENT; |
|
112 | END COMPONENT; | |
112 |
|
113 | |||
113 | COMPONENT lpp_lfr_ms_fsmdma |
|
114 | COMPONENT lpp_lfr_ms_fsmdma | |
@@ -213,7 +214,9 PACKAGE lpp_lfr_pkg IS | |||||
213 | ahbo : OUT AHB_Mst_Out_Type; |
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214 | ahbo : OUT AHB_Mst_Out_Type; | |
214 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
215 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
215 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
216 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); | |
216 | data_shaping_BW : OUT STD_LOGIC |
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217 | data_shaping_BW : OUT STD_LOGIC ; | |
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218 | debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); | |||
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219 | debug_vector_ms : OUT STD_LOGIC_VECTOR(11 DOWNTO 0) | |||
217 | ); |
|
220 | ); | |
218 | END COMPONENT; |
|
221 | END COMPONENT; | |
219 |
|
222 | |||
@@ -315,7 +318,8 PACKAGE lpp_lfr_pkg IS | |||||
315 | wfp_length_buffer : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); |
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318 | wfp_length_buffer : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); | |
316 | wfp_ready_buffer : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
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319 | wfp_ready_buffer : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
317 | wfp_buffer_time : IN STD_LOGIC_VECTOR(48*4-1 DOWNTO 0); |
|
320 | wfp_buffer_time : IN STD_LOGIC_VECTOR(48*4-1 DOWNTO 0); | |
318 |
wfp_error_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0) |
|
321 | wfp_error_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
322 | debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)); | |||
319 | END COMPONENT; |
|
323 | END COMPONENT; | |
320 |
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324 | |||
321 | COMPONENT lpp_top_ms |
|
325 | COMPONENT lpp_top_ms |
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