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Correction du bugs 266 (a confirmer) :...
pellion -
r465:8e656681264f (MINI-LFR) WFP_MS-0-1-35 JC
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1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -------------------------------------------------------------------------------
22 22 LIBRARY IEEE;
23 23 USE IEEE.numeric_std.ALL;
24 24 USE IEEE.std_logic_1164.ALL;
25 25 LIBRARY grlib;
26 26 USE grlib.amba.ALL;
27 27 USE grlib.stdlib.ALL;
28 28 LIBRARY techmap;
29 29 USE techmap.gencomp.ALL;
30 30 LIBRARY gaisler;
31 31 USE gaisler.memctrl.ALL;
32 32 USE gaisler.leon3.ALL;
33 33 USE gaisler.uart.ALL;
34 34 USE gaisler.misc.ALL;
35 35 USE gaisler.spacewire.ALL;
36 36 LIBRARY esa;
37 37 USE esa.memoryctrl.ALL;
38 38 LIBRARY lpp;
39 39 USE lpp.lpp_memory.ALL;
40 40 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 43 USE lpp.iir_filter.ALL;
44 44 USE lpp.general_purpose.ALL;
45 45 USE lpp.lpp_lfr_time_management.ALL;
46 46 USE lpp.lpp_leon3_soc_pkg.ALL;
47 47
48 48 ENTITY MINI_LFR_top IS
49 49
50 50 PORT (
51 51 clk_50 : IN STD_LOGIC;
52 52 clk_49 : IN STD_LOGIC;
53 53 reset : IN STD_LOGIC;
54 54 --BPs
55 55 BP0 : IN STD_LOGIC;
56 56 BP1 : IN STD_LOGIC;
57 57 --LEDs
58 58 LED0 : OUT STD_LOGIC;
59 59 LED1 : OUT STD_LOGIC;
60 60 LED2 : OUT STD_LOGIC;
61 61 --UARTs
62 62 TXD1 : IN STD_LOGIC;
63 63 RXD1 : OUT STD_LOGIC;
64 64 nCTS1 : OUT STD_LOGIC;
65 65 nRTS1 : IN STD_LOGIC;
66 66
67 67 TXD2 : IN STD_LOGIC;
68 68 RXD2 : OUT STD_LOGIC;
69 69 nCTS2 : OUT STD_LOGIC;
70 70 nDTR2 : IN STD_LOGIC;
71 71 nRTS2 : IN STD_LOGIC;
72 72 nDCD2 : OUT STD_LOGIC;
73 73
74 74 --EXT CONNECTOR
75 75 IO0 : INOUT STD_LOGIC;
76 76 IO1 : INOUT STD_LOGIC;
77 77 IO2 : INOUT STD_LOGIC;
78 78 IO3 : INOUT STD_LOGIC;
79 79 IO4 : INOUT STD_LOGIC;
80 80 IO5 : INOUT STD_LOGIC;
81 81 IO6 : INOUT STD_LOGIC;
82 82 IO7 : INOUT STD_LOGIC;
83 83 IO8 : INOUT STD_LOGIC;
84 84 IO9 : INOUT STD_LOGIC;
85 85 IO10 : INOUT STD_LOGIC;
86 86 IO11 : INOUT STD_LOGIC;
87 87
88 88 --SPACE WIRE
89 89 SPW_EN : OUT STD_LOGIC; -- 0 => off
90 90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
91 91 SPW_NOM_SIN : IN STD_LOGIC;
92 92 SPW_NOM_DOUT : OUT STD_LOGIC;
93 93 SPW_NOM_SOUT : OUT STD_LOGIC;
94 94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
95 95 SPW_RED_SIN : IN STD_LOGIC;
96 96 SPW_RED_DOUT : OUT STD_LOGIC;
97 97 SPW_RED_SOUT : OUT STD_LOGIC;
98 98 -- MINI LFR ADC INPUTS
99 99 ADC_nCS : OUT STD_LOGIC;
100 100 ADC_CLK : OUT STD_LOGIC;
101 101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
102 102
103 103 -- SRAM
104 104 SRAM_nWE : OUT STD_LOGIC;
105 105 SRAM_CE : OUT STD_LOGIC;
106 106 SRAM_nOE : OUT STD_LOGIC;
107 107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
108 108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
109 109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
110 110 );
111 111
112 112 END MINI_LFR_top;
113 113
114 114
115 115 ARCHITECTURE beh OF MINI_LFR_top IS
116 116 SIGNAL clk_50_s : STD_LOGIC := '0';
117 117 SIGNAL clk_25 : STD_LOGIC := '0';
118 118 SIGNAL clk_24 : STD_LOGIC := '0';
119 119 -----------------------------------------------------------------------------
120 120 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
121 121 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
122 122 --
123 123 SIGNAL errorn : STD_LOGIC;
124 124 -- UART AHB ---------------------------------------------------------------
125 125 -- SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
126 126 -- SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
127 127
128 128 -- UART APB ---------------------------------------------------------------
129 129 -- SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
130 130 -- SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
131 --
131 --
132 132 SIGNAL I00_s : STD_LOGIC;
133 133
134 134 -- CONSTANTS
135 135 CONSTANT CFG_PADTECH : INTEGER := inferred;
136 136 --
137 137 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
138 138 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
139 139 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
140 140
141 141 SIGNAL apbi_ext : apb_slv_in_type;
142 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5);-- := (OTHERS => apb_none);
142 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5); -- := (OTHERS => apb_none);
143 143 SIGNAL ahbi_s_ext : ahb_slv_in_type;
144 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3);-- := (OTHERS => ahbs_none);
144 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3); -- := (OTHERS => ahbs_none);
145 145 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
146 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1);-- := (OTHERS => ahbm_none);
146 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1); -- := (OTHERS => ahbm_none);
147 147
148 148 -- Spacewire signals
149 149 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 150 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
151 151 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
152 152 SIGNAL spw_rxtxclk : STD_ULOGIC;
153 153 SIGNAL spw_rxclkn : STD_ULOGIC;
154 154 SIGNAL spw_clk : STD_LOGIC;
155 155 SIGNAL swni : grspw_in_type;
156 156 SIGNAL swno : grspw_out_type;
157 157 -- SIGNAL clkmn : STD_ULOGIC;
158 158 -- SIGNAL txclk : STD_ULOGIC;
159 159
160 160 --GPIO
161 161 SIGNAL gpioi : gpio_in_type;
162 162 SIGNAL gpioo : gpio_out_type;
163 163
164 164 -- AD Converter ADS7886
165 165 SIGNAL sample : Samples14v(7 DOWNTO 0);
166 166 SIGNAL sample_s : Samples(7 DOWNTO 0);
167 167 SIGNAL sample_val : STD_LOGIC;
168 168 SIGNAL ADC_nCS_sig : STD_LOGIC;
169 169 SIGNAL ADC_CLK_sig : STD_LOGIC;
170 170 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
171 171
172 172 SIGNAL bias_fail_sw_sig : STD_LOGIC;
173 173
174 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
175 SIGNAL observation_vector_0: STD_LOGIC_VECTOR(11 DOWNTO 0);
176 SIGNAL observation_vector_1: STD_LOGIC_VECTOR(11 DOWNTO 0);
174 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
175 SIGNAL observation_vector_0 : STD_LOGIC_VECTOR(11 DOWNTO 0);
176 SIGNAL observation_vector_1 : STD_LOGIC_VECTOR(11 DOWNTO 0);
177 177 -----------------------------------------------------------------------------
178 178
179 179 SIGNAL LFR_soft_rstn : STD_LOGIC;
180 SIGNAL LFR_rstn : STD_LOGIC;
180 SIGNAL LFR_rstn : STD_LOGIC;
181 181
182 182
183 183 SIGNAL rstn_25 : STD_LOGIC;
184 184 SIGNAL rstn_25_d1 : STD_LOGIC;
185 185 SIGNAL rstn_25_d2 : STD_LOGIC;
186 186 SIGNAL rstn_25_d3 : STD_LOGIC;
187
187
188 188 SIGNAL rstn_50 : STD_LOGIC;
189 189 SIGNAL rstn_50_d1 : STD_LOGIC;
190 190 SIGNAL rstn_50_d2 : STD_LOGIC;
191 191 SIGNAL rstn_50_d3 : STD_LOGIC;
192
193 SIGNAL lfr_debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
194 SIGNAL lfr_debug_vector_ms : STD_LOGIC_VECTOR(11 DOWNTO 0);
195
192 196 BEGIN -- beh
193 197
194 198 -----------------------------------------------------------------------------
195 199 -- CLK
196 200 -----------------------------------------------------------------------------
197 201
198 202 --PROCESS(clk_50)
199 203 --BEGIN
200 204 -- IF clk_50'EVENT AND clk_50 = '1' THEN
201 205 -- clk_50_s <= NOT clk_50_s;
202 206 -- END IF;
203 207 --END PROCESS;
204 208
205 209 --PROCESS(clk_50_s)
206 210 --BEGIN
207 211 -- IF clk_50_s'EVENT AND clk_50_s = '1' THEN
208 212 -- clk_25 <= NOT clk_25;
209 213 -- END IF;
210 214 --END PROCESS;
211 215
212 216 --PROCESS(clk_49)
213 217 --BEGIN
214 218 -- IF clk_49'EVENT AND clk_49 = '1' THEN
215 219 -- clk_24 <= NOT clk_24;
216 220 -- END IF;
217 221 --END PROCESS;
218
222
219 223 --PROCESS(clk_25)
220 224 --BEGIN
221 225 -- IF clk_25'EVENT AND clk_25 = '1' THEN
222 226 -- rstn_25 <= reset;
223 227 -- END IF;
224 228 --END PROCESS;
225 229
226 230 PROCESS (clk_50, reset)
227 231 BEGIN -- PROCESS
228 232 IF reset = '0' THEN -- asynchronous reset (active low)
229 233 clk_50_s <= '0';
230 234 rstn_50 <= '0';
231 235 rstn_50_d1 <= '0';
232 236 rstn_50_d2 <= '0';
233 237 rstn_50_d3 <= '0';
234 238
235 ELSIF clk_50'event AND clk_50 = '1' THEN -- rising clock edge
236 clk_50_s <= NOT clk_50_s;
239 ELSIF clk_50'EVENT AND clk_50 = '1' THEN -- rising clock edge
240 clk_50_s <= NOT clk_50_s;
237 241 rstn_50_d1 <= '1';
238 242 rstn_50_d2 <= rstn_50_d1;
239 243 rstn_50_d3 <= rstn_50_d2;
240 244 rstn_50 <= rstn_50_d3;
241 245 END IF;
242 246 END PROCESS;
243 247
244 248 PROCESS (clk_50_s, rstn_50)
245 249 BEGIN -- PROCESS
246 250 IF rstn_50 = '0' THEN -- asynchronous reset (active low)
247 clk_25 <= '0';
251 clk_25 <= '0';
248 252 rstn_25 <= '0';
249 253 rstn_25_d1 <= '0';
250 254 rstn_25_d2 <= '0';
251 255 rstn_25_d3 <= '0';
252 ELSIF clk_50_s'event AND clk_50_s = '1' THEN -- rising clock edge
256 ELSIF clk_50_s'EVENT AND clk_50_s = '1' THEN -- rising clock edge
253 257 clk_25 <= NOT clk_25;
254 258 rstn_25_d1 <= '1';
255 259 rstn_25_d2 <= rstn_25_d1;
256 260 rstn_25_d3 <= rstn_25_d2;
257 261 rstn_25 <= rstn_25_d3;
258 262 END IF;
259 263 END PROCESS;
260 264
261 265 PROCESS (clk_49, reset)
262 266 BEGIN -- PROCESS
263 267 IF reset = '0' THEN -- asynchronous reset (active low)
264 268 clk_24 <= '0';
265 ELSIF clk_49'event AND clk_49 = '1' THEN -- rising clock edge
266 clk_24 <= NOT clk_24;
269 ELSIF clk_49'EVENT AND clk_49 = '1' THEN -- rising clock edge
270 clk_24 <= NOT clk_24;
267 271 END IF;
268 272 END PROCESS;
269
273
270 274 -----------------------------------------------------------------------------
271 275
272 276 PROCESS (clk_25, rstn_25)
273 277 BEGIN -- PROCESS
274 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
278 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
275 279 LED0 <= '0';
276 280 LED1 <= '0';
277 281 LED2 <= '0';
278 282 --IO1 <= '0';
279 283 --IO2 <= '1';
280 284 --IO3 <= '0';
281 285 --IO4 <= '0';
282 286 --IO5 <= '0';
283 287 --IO6 <= '0';
284 288 --IO7 <= '0';
285 289 --IO8 <= '0';
286 290 --IO9 <= '0';
287 291 --IO10 <= '0';
288 292 --IO11 <= '0';
289 293 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
290 294 LED0 <= '0';
291 295 LED1 <= '1';
292 296 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
293 297 --IO1 <= '1';
294 298 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
295 299 --IO3 <= ADC_SDO(0);
296 300 --IO4 <= ADC_SDO(1);
297 301 --IO5 <= ADC_SDO(2);
298 302 --IO6 <= ADC_SDO(3);
299 303 --IO7 <= ADC_SDO(4);
300 304 --IO8 <= ADC_SDO(5);
301 305 --IO9 <= ADC_SDO(6);
302 306 --IO10 <= ADC_SDO(7);
303 307 --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
304 308 END IF;
305 309 END PROCESS;
306 310
307 311 PROCESS (clk_24, rstn_25)
308 312 BEGIN -- PROCESS
309 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
313 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
310 314 I00_s <= '0';
311 315 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
312 I00_s <= NOT I00_s ;
316 I00_s <= NOT I00_s;
313 317 END IF;
314 318 END PROCESS;
315 319 -- IO0 <= I00_s;
316 320
317 321 --UARTs
318 322 nCTS1 <= '1';
319 323 nCTS2 <= '1';
320 324 nDCD2 <= '1';
321 325
322 326 --EXT CONNECTOR
323 327
324 328 --SPACE WIRE
325 329
326 330 leon3_soc_1 : leon3_soc
327 331 GENERIC MAP (
328 332 fabtech => apa3e,
329 333 memtech => apa3e,
330 334 padtech => inferred,
331 335 clktech => inferred,
332 336 disas => 0,
333 337 dbguart => 0,
334 338 pclow => 2,
335 339 clk_freq => 25000,
336 340 NB_CPU => 1,
337 341 ENABLE_FPU => 1,
338 342 FPU_NETLIST => 0,
339 343 ENABLE_DSU => 1,
340 344 ENABLE_AHB_UART => 1,
341 345 ENABLE_APB_UART => 1,
342 346 ENABLE_IRQMP => 1,
343 347 ENABLE_GPT => 1,
344 348 NB_AHB_MASTER => NB_AHB_MASTER,
345 349 NB_AHB_SLAVE => NB_AHB_SLAVE,
346 350 NB_APB_SLAVE => NB_APB_SLAVE,
347 351 ADDRESS_SIZE => 20)
348 352 PORT MAP (
349 353 clk => clk_25,
350 354 reset => rstn_25,
351 355 errorn => errorn,
352 356 ahbrxd => TXD1,
353 357 ahbtxd => RXD1,
354 358 urxd1 => TXD2,
355 359 utxd1 => RXD2,
356 360 address => SRAM_A,
357 361 data => SRAM_DQ,
358 362 nSRAM_BE0 => SRAM_nBE(0),
359 363 nSRAM_BE1 => SRAM_nBE(1),
360 364 nSRAM_BE2 => SRAM_nBE(2),
361 365 nSRAM_BE3 => SRAM_nBE(3),
362 366 nSRAM_WE => SRAM_nWE,
363 367 nSRAM_CE => SRAM_CE,
364 368 nSRAM_OE => SRAM_nOE,
365 369
366 370 apbi_ext => apbi_ext,
367 371 apbo_ext => apbo_ext,
368 372 ahbi_s_ext => ahbi_s_ext,
369 373 ahbo_s_ext => ahbo_s_ext,
370 374 ahbi_m_ext => ahbi_m_ext,
371 375 ahbo_m_ext => ahbo_m_ext);
372 376
373 377 -------------------------------------------------------------------------------
374 378 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
375 379 -------------------------------------------------------------------------------
376 380 apb_lfr_time_management_1 : apb_lfr_time_management
377 381 GENERIC MAP (
378 pindex => 6,
379 paddr => 6,
380 pmask => 16#fff#,
381 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
382 pindex => 6,
383 paddr => 6,
384 pmask => 16#fff#,
385 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
382 386 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
383 387 PORT MAP (
384 clk25MHz => clk_25,
385 clk24_576MHz => clk_24, -- 49.152MHz/2
386 resetn => rstn_25,
387 grspw_tick => swno.tickout,
388 apbi => apbi_ext,
389 apbo => apbo_ext(6),
390 coarse_time => coarse_time,
391 fine_time => fine_time,
388 clk25MHz => clk_25,
389 clk24_576MHz => clk_24, -- 49.152MHz/2
390 resetn => rstn_25,
391 grspw_tick => swno.tickout,
392 apbi => apbi_ext,
393 apbo => apbo_ext(6),
394 coarse_time => coarse_time,
395 fine_time => fine_time,
392 396 LFR_soft_rstn => LFR_soft_rstn
393 397 );
394 398
395 399 -----------------------------------------------------------------------
396 400 --- SpaceWire --------------------------------------------------------
397 401 -----------------------------------------------------------------------
398 402
399 403 SPW_EN <= '1';
400 404
401 405 spw_clk <= clk_50_s;
402 406 spw_rxtxclk <= spw_clk;
403 407 spw_rxclkn <= NOT spw_rxtxclk;
404 408
405 409 -- PADS for SPW1
406 410 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
407 411 PORT MAP (SPW_NOM_DIN, dtmp(0));
408 412 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
409 413 PORT MAP (SPW_NOM_SIN, stmp(0));
410 414 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
411 415 PORT MAP (SPW_NOM_DOUT, swno.d(0));
412 416 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
413 417 PORT MAP (SPW_NOM_SOUT, swno.s(0));
414 418 -- PADS FOR SPW2
415 419 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
416 420 PORT MAP (SPW_RED_SIN, dtmp(1));
417 421 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
418 422 PORT MAP (SPW_RED_DIN, stmp(1));
419 423 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
420 424 PORT MAP (SPW_RED_DOUT, swno.d(1));
421 425 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
422 426 PORT MAP (SPW_RED_SOUT, swno.s(1));
423 427
424 428 -- GRSPW PHY
425 429 --spw1_input: if CFG_SPW_GRSPW = 1 generate
426 430 spw_inputloop : FOR j IN 0 TO 1 GENERATE
427 431 spw_phy0 : grspw_phy
428 432 GENERIC MAP(
429 433 tech => apa3e,
430 434 rxclkbuftype => 1,
431 435 scantest => 0)
432 436 PORT MAP(
433 437 rxrst => swno.rxrst,
434 438 di => dtmp(j),
435 439 si => stmp(j),
436 440 rxclko => spw_rxclk(j),
437 441 do => swni.d(j),
438 442 ndo => swni.nd(j*5+4 DOWNTO j*5),
439 443 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
440 444 END GENERATE spw_inputloop;
441 445
442 swni.rmapnodeaddr <= (others => '0');
446 swni.rmapnodeaddr <= (OTHERS => '0');
443 447
444 448 -- SPW core
445 449 sw0 : grspwm GENERIC MAP(
446 450 tech => apa3e,
447 451 hindex => 1,
448 452 pindex => 5,
449 453 paddr => 5,
450 454 pirq => 11,
451 455 sysfreq => 25000, -- CPU_FREQ
452 456 rmap => 1,
453 457 rmapcrc => 1,
454 458 fifosize1 => 16,
455 459 fifosize2 => 16,
456 460 rxclkbuftype => 1,
457 461 rxunaligned => 0,
458 462 rmapbufs => 4,
459 463 ft => 0,
460 464 netlist => 0,
461 465 ports => 2,
462 466 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
463 467 memtech => apa3e,
464 468 destkey => 2,
465 469 spwcore => 1
466 470 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
467 471 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
468 472 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
469 473 )
470 474 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
471 475 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
472 476 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
473 477 swni, swno);
474 478
475 479 swni.tickin <= '0';
476 480 swni.rmapen <= '1';
477 481 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
478 482 swni.tickinraw <= '0';
479 483 swni.timein <= (OTHERS => '0');
480 484 swni.dcrstval <= (OTHERS => '0');
481 485 swni.timerrstval <= (OTHERS => '0');
482 486
483 487 -------------------------------------------------------------------------------
484 488 -- LFR ------------------------------------------------------------------------
485 489 -------------------------------------------------------------------------------
486 490
487 491
488 --LFR_rstn <= LFR_soft_rstn AND rstn_25;
489 LFR_rstn <= rstn_25;
490
492 LFR_rstn <= LFR_soft_rstn AND rstn_25;
493 --LFR_rstn <= rstn_25;
494
491 495 lpp_lfr_1 : lpp_lfr
492 496 GENERIC MAP (
493 497 Mem_use => use_RAM,
494 498 nb_data_by_buffer_size => 32,
495 499 nb_snapshot_param_size => 32,
496 500 delta_vector_size => 32,
497 delta_vector_size_f0_2 => 7, -- log2(96)
501 delta_vector_size_f0_2 => 7, -- log2(96)
498 502 pindex => 15,
499 503 paddr => 15,
500 504 pmask => 16#fff#,
501 505 pirq_ms => 6,
502 506 pirq_wfp => 14,
503 507 hindex => 2,
504 top_lfr_version => X"000122") -- aa.bb.cc version
508 top_lfr_version => X"000123") -- aa.bb.cc version
505 509 PORT MAP (
506 510 clk => clk_25,
507 511 rstn => LFR_rstn,
508 512 sample_B => sample_s(2 DOWNTO 0),
509 513 sample_E => sample_s(7 DOWNTO 3),
510 514 sample_val => sample_val,
511 515 apbi => apbi_ext,
512 516 apbo => apbo_ext(15),
513 517 ahbi => ahbi_m_ext,
514 518 ahbo => ahbo_m_ext(2),
515 519 coarse_time => coarse_time,
516 520 fine_time => fine_time,
517 data_shaping_BW => bias_fail_sw_sig);
521 data_shaping_BW => bias_fail_sw_sig,
522 debug_vector => lfr_debug_vector,
523 debug_vector_ms => lfr_debug_vector_ms
524 );
518 525
519 observation_reg <= (others => '0');
520 observation_vector_0 <= (others => '0');
521 observation_vector_1 <= (others => '0');
526 observation_reg(11 DOWNTO 0) <= lfr_debug_vector;
527 observation_reg(31 DOWNTO 12) <= (OTHERS => '0');
528 observation_vector_0(11 DOWNTO 0) <= lfr_debug_vector;
529 observation_vector_1(11 DOWNTO 0) <= lfr_debug_vector;
530 IO0 <= rstn_25;
531 IO1 <= lfr_debug_vector_ms(0); -- LFR MS FFT data_valid
532 IO2 <= lfr_debug_vector_ms(0); -- LFR MS FFT ready
533 IO3 <= lfr_debug_vector(0); -- LFR APBREG error_buffer_full
534 IO4 <= lfr_debug_vector(1); -- LFR APBREG reg_sp.status_error_buffer_full
535 IO5 <= lfr_debug_vector(8); -- LFR APBREG ready_matrix_f2
536 IO6 <= lfr_debug_vector(9); -- LFR APBREG reg0_ready_matrix_f2
537 IO7 <= lfr_debug_vector(10); -- LFR APBREG reg0_ready_matrix_f2
522 538
523 all_sample: FOR I IN 7 DOWNTO 0 GENERATE
539 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
524 540 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
525 541 END GENERATE all_sample;
526 542
527 543 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
528 544 GENERIC MAP(
529 545 ChannelCount => 8,
530 546 SampleNbBits => 14,
531 547 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
532 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
548 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
533 549 PORT MAP (
534 550 -- CONV
535 551 cnv_clk => clk_24,
536 552 cnv_rstn => rstn_25,
537 553 cnv => ADC_nCS_sig,
538 554 -- DATA
539 555 clk => clk_25,
540 556 rstn => rstn_25,
541 557 sck => ADC_CLK_sig,
542 558 sdo => ADC_SDO_sig,
543 559 -- SAMPLE
544 560 sample => sample,
545 561 sample_val => sample_val);
546 562
547 563 --IO10 <= ADC_SDO_sig(5);
548 564 --IO9 <= ADC_SDO_sig(4);
549 565 --IO8 <= ADC_SDO_sig(3);
550 566
551 567 ADC_nCS <= ADC_nCS_sig;
552 568 ADC_CLK <= ADC_CLK_sig;
553 569 ADC_SDO_sig <= ADC_SDO;
554 570
555 571 ----------------------------------------------------------------------
556 572 --- GPIO -----------------------------------------------------------
557 573 ----------------------------------------------------------------------
558 574
559 575 grgpio0 : grgpio
560 576 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
561 577 PORT MAP(rstn_25, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
562 578
563 gpioi.sig_en <= (others => '0');
564 gpioi.sig_in <= (others => '0');
565 gpioi.din <= (others => '0');
579 gpioi.sig_en <= (OTHERS => '0');
580 gpioi.sig_in <= (OTHERS => '0');
581 gpioi.din <= (OTHERS => '0');
566 582 --pio_pad_0 : iopad
567 583 -- GENERIC MAP (tech => CFG_PADTECH)
568 584 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
569 585 --pio_pad_1 : iopad
570 586 -- GENERIC MAP (tech => CFG_PADTECH)
571 587 -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
572 588 --pio_pad_2 : iopad
573 589 -- GENERIC MAP (tech => CFG_PADTECH)
574 590 -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
575 591 --pio_pad_3 : iopad
576 592 -- GENERIC MAP (tech => CFG_PADTECH)
577 593 -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
578 594 --pio_pad_4 : iopad
579 595 -- GENERIC MAP (tech => CFG_PADTECH)
580 596 -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
581 597 --pio_pad_5 : iopad
582 598 -- GENERIC MAP (tech => CFG_PADTECH)
583 599 -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
584 600 --pio_pad_6 : iopad
585 601 -- GENERIC MAP (tech => CFG_PADTECH)
586 602 -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
587 603 --pio_pad_7 : iopad
588 604 -- GENERIC MAP (tech => CFG_PADTECH)
589 605 -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
590 606
591 607 PROCESS (clk_25, rstn_25)
592 608 BEGIN -- PROCESS
593 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
594 IO0 <= '0';
595 IO1 <= '0';
596 IO2 <= '0';
597 IO3 <= '0';
598 IO4 <= '0';
599 IO5 <= '0';
600 IO6 <= '0';
601 IO7 <= '0';
609 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
610 -- --IO0 <= '0';
611 -- IO1 <= '0';
612 -- IO2 <= '0';
613 -- IO3 <= '0';
614 -- IO4 <= '0';
615 -- IO5 <= '0';
616 -- IO6 <= '0';
617 -- IO7 <= '0';
602 618 IO8 <= '0';
603 619 IO9 <= '0';
604 620 IO10 <= '0';
605 621 IO11 <= '0';
606 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
622 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
607 623 CASE gpioo.dout(2 DOWNTO 0) IS
608 WHEN "011" =>
609 IO0 <= observation_reg(0 );
610 IO1 <= observation_reg(1 );
611 IO2 <= observation_reg(2 );
612 IO3 <= observation_reg(3 );
613 IO4 <= observation_reg(4 );
614 IO5 <= observation_reg(5 );
615 IO6 <= observation_reg(6 );
616 IO7 <= observation_reg(7 );
617 IO8 <= observation_reg(8 );
618 IO9 <= observation_reg(9 );
624 WHEN "011" =>
625 -- --IO0 <= observation_reg(0 );
626 -- IO1 <= observation_reg(1 );
627 -- IO2 <= observation_reg(2 );
628 -- IO3 <= observation_reg(3 );
629 -- IO4 <= observation_reg(4 );
630 -- IO5 <= observation_reg(5 );
631 -- IO6 <= observation_reg(6 );
632 -- IO7 <= observation_reg(7 );
633 IO8 <= observation_reg(8);
634 IO9 <= observation_reg(9);
619 635 IO10 <= observation_reg(10);
620 636 IO11 <= observation_reg(11);
621 WHEN "001" =>
622 IO0 <= observation_reg(0 + 12);
623 IO1 <= observation_reg(1 + 12);
624 IO2 <= observation_reg(2 + 12);
625 IO3 <= observation_reg(3 + 12);
626 IO4 <= observation_reg(4 + 12);
627 IO5 <= observation_reg(5 + 12);
628 IO6 <= observation_reg(6 + 12);
629 IO7 <= observation_reg(7 + 12);
630 IO8 <= observation_reg(8 + 12);
631 IO9 <= observation_reg(9 + 12);
637 WHEN "001" =>
638 -- --IO0 <= observation_reg(0 + 12);
639 -- IO1 <= observation_reg(1 + 12);
640 -- IO2 <= observation_reg(2 + 12);
641 -- IO3 <= observation_reg(3 + 12);
642 -- IO4 <= observation_reg(4 + 12);
643 -- IO5 <= observation_reg(5 + 12);
644 -- IO6 <= observation_reg(6 + 12);
645 -- IO7 <= observation_reg(7 + 12);
646 IO8 <= observation_reg(8 + 12);
647 IO9 <= observation_reg(9 + 12);
632 648 IO10 <= observation_reg(10 + 12);
633 649 IO11 <= observation_reg(11 + 12);
634 WHEN "010" =>
635 IO0 <= observation_reg(0 + 12 + 12);
636 IO1 <= observation_reg(1 + 12 + 12);
637 IO2 <= observation_reg(2 + 12 + 12);
638 IO3 <= observation_reg(3 + 12 + 12);
639 IO4 <= observation_reg(4 + 12 + 12);
640 IO5 <= observation_reg(5 + 12 + 12);
641 IO6 <= observation_reg(6 + 12 + 12);
642 IO7 <= observation_reg(7 + 12 + 12);
650 WHEN "010" =>
651 -- --IO0 <= observation_reg(0 + 12 + 12);
652 -- IO1 <= observation_reg(1 + 12 + 12);
653 -- IO2 <= observation_reg(2 + 12 + 12);
654 -- IO3 <= observation_reg(3 + 12 + 12);
655 -- IO4 <= observation_reg(4 + 12 + 12);
656 -- IO5 <= observation_reg(5 + 12 + 12);
657 -- IO6 <= observation_reg(6 + 12 + 12);
658 -- IO7 <= observation_reg(7 + 12 + 12);
643 659 IO8 <= '0';
644 660 IO9 <= '0';
645 661 IO10 <= '0';
646 662 IO11 <= '0';
647 WHEN "000" =>
648 IO0 <= observation_vector_0(0 );
649 IO1 <= observation_vector_0(1 );
650 IO2 <= observation_vector_0(2 );
651 IO3 <= observation_vector_0(3 );
652 IO4 <= observation_vector_0(4 );
653 IO5 <= observation_vector_0(5 );
654 IO6 <= observation_vector_0(6 );
655 IO7 <= observation_vector_0(7 );
656 IO8 <= observation_vector_0(8 );
657 IO9 <= observation_vector_0(9 );
663 WHEN "000" =>
664 -- --IO0 <= observation_vector_0(0 );
665 -- IO1 <= observation_vector_0(1 );
666 -- IO2 <= observation_vector_0(2 );
667 -- IO3 <= observation_vector_0(3 );
668 -- IO4 <= observation_vector_0(4 );
669 -- IO5 <= observation_vector_0(5 );
670 -- IO6 <= observation_vector_0(6 );
671 -- IO7 <= observation_vector_0(7 );
672 IO8 <= observation_vector_0(8);
673 IO9 <= observation_vector_0(9);
658 674 IO10 <= observation_vector_0(10);
659 675 IO11 <= observation_vector_0(11);
660 WHEN "100" =>
661 IO0 <= observation_vector_1(0 );
662 IO1 <= observation_vector_1(1 );
663 IO2 <= observation_vector_1(2 );
664 IO3 <= observation_vector_1(3 );
665 IO4 <= observation_vector_1(4 );
666 IO5 <= observation_vector_1(5 );
667 IO6 <= observation_vector_1(6 );
668 IO7 <= observation_vector_1(7 );
669 IO8 <= observation_vector_1(8 );
670 IO9 <= observation_vector_1(9 );
676 WHEN "100" =>
677 -- --IO0 <= observation_vector_1(0 );
678 -- IO1 <= observation_vector_1(1 );
679 -- IO2 <= observation_vector_1(2 );
680 -- IO3 <= observation_vector_1(3 );
681 -- IO4 <= observation_vector_1(4 );
682 -- IO5 <= observation_vector_1(5 );
683 -- IO6 <= observation_vector_1(6 );
684 -- IO7 <= observation_vector_1(7 );
685 IO8 <= observation_vector_1(8);
686 IO9 <= observation_vector_1(9);
671 687 IO10 <= observation_vector_1(10);
672 688 IO11 <= observation_vector_1(11);
673 689 WHEN OTHERS => NULL;
674 690 END CASE;
675 691
676 692 END IF;
677 693 END PROCESS;
678 694 -----------------------------------------------------------------------------
679 695 --
680 696 -----------------------------------------------------------------------------
681 all_apbo_ext: FOR I IN NB_APB_SLAVE-1+5 DOWNTO 5 GENERATE
682 apbo_ext_not_used: IF I /= 5 AND I /= 6 AND I /= 11 AND I /= 15 GENERATE
697 all_apbo_ext : FOR I IN NB_APB_SLAVE-1+5 DOWNTO 5 GENERATE
698 apbo_ext_not_used : IF I /= 5 AND I /= 6 AND I /= 11 AND I /= 15 GENERATE
683 699 apbo_ext(I) <= apb_none;
684 700 END GENERATE apbo_ext_not_used;
685 701 END GENERATE all_apbo_ext;
686
702
687 703
688 all_ahbo_ext: FOR I IN NB_AHB_SLAVE-1+3 DOWNTO 3 GENERATE
704 all_ahbo_ext : FOR I IN NB_AHB_SLAVE-1+3 DOWNTO 3 GENERATE
689 705 ahbo_s_ext(I) <= ahbs_none;
690 706 END GENERATE all_ahbo_ext;
691
692 all_ahbo_m_ext: FOR I IN NB_AHB_MASTER-1+1 DOWNTO 1 GENERATE
693 ahbo_m_ext_not_used: IF I /=1 AND I /= 2 GENERATE
707
708 all_ahbo_m_ext : FOR I IN NB_AHB_MASTER-1+1 DOWNTO 1 GENERATE
709 ahbo_m_ext_not_used : IF I /= 1 AND I /= 2 GENERATE
694 710 ahbo_m_ext(I) <= ahbm_none;
695 711 END GENERATE ahbo_m_ext_not_used;
696 712 END GENERATE all_ahbo_m_ext;
697 713
698 END beh; No newline at end of file
714 END beh;
Show file before | Show file after | Hide comments
@@ -1,273 +1,271
1 1 LIBRARY ieee;
2 2 USE ieee.std_logic_1164.ALL;
3 3 USE ieee.numeric_std.ALL;
4 4 use IEEE.std_logic_textio.all;
5 5 LIBRARY STD;
6 6 use std.textio.all;
7 7
8 8 LIBRARY grlib;
9 9 USE grlib.stdlib.ALL;
10 10 LIBRARY gaisler;
11 11 USE gaisler.libdcom.ALL;
12 12 USE gaisler.sim.ALL;
13 13 USE gaisler.jtagtst.ALL;
14 14 LIBRARY techmap;
15 15 USE techmap.gencomp.ALL;
16 16
17 17 LIBRARY lpp;
18 18 USE lpp.lpp_sim_pkg.ALL;
19 19 USE lpp.lpp_lfr_apbreg_pkg.ALL;
20 20 USE lpp.lpp_lfr_time_management_apbreg_pkg.ALL;
21 21
22 LIBRARY postlayout;
23 USE postlayout.ALL;
24 22
25 23 ENTITY testbench IS
26 24 END;
27 25
28 26 ARCHITECTURE behav OF testbench IS
29 27
30 28 COMPONENT MINI_LFR_top
31 29 PORT (
32 30 clk_50 : IN STD_LOGIC;
33 31 clk_49 : IN STD_LOGIC;
34 32 reset : IN STD_LOGIC;
35 33 BP0 : IN STD_LOGIC;
36 34 BP1 : IN STD_LOGIC;
37 35 LED0 : OUT STD_LOGIC;
38 36 LED1 : OUT STD_LOGIC;
39 37 LED2 : OUT STD_LOGIC;
40 38 TXD1 : IN STD_LOGIC;
41 39 RXD1 : OUT STD_LOGIC;
42 40 nCTS1 : OUT STD_LOGIC;
43 41 nRTS1 : IN STD_LOGIC;
44 42 TXD2 : IN STD_LOGIC;
45 43 RXD2 : OUT STD_LOGIC;
46 44 nCTS2 : OUT STD_LOGIC;
47 45 nDTR2 : IN STD_LOGIC;
48 46 nRTS2 : IN STD_LOGIC;
49 47 nDCD2 : OUT STD_LOGIC;
50 48 IO0 : INOUT STD_LOGIC;
51 49 IO1 : INOUT STD_LOGIC;
52 50 IO2 : INOUT STD_LOGIC;
53 51 IO3 : INOUT STD_LOGIC;
54 52 IO4 : INOUT STD_LOGIC;
55 53 IO5 : INOUT STD_LOGIC;
56 54 IO6 : INOUT STD_LOGIC;
57 55 IO7 : INOUT STD_LOGIC;
58 56 IO8 : INOUT STD_LOGIC;
59 57 IO9 : INOUT STD_LOGIC;
60 58 IO10 : INOUT STD_LOGIC;
61 59 IO11 : INOUT STD_LOGIC;
62 60 SPW_EN : OUT STD_LOGIC;
63 61 SPW_NOM_DIN : IN STD_LOGIC;
64 62 SPW_NOM_SIN : IN STD_LOGIC;
65 63 SPW_NOM_DOUT : OUT STD_LOGIC;
66 64 SPW_NOM_SOUT : OUT STD_LOGIC;
67 65 SPW_RED_DIN : IN STD_LOGIC;
68 66 SPW_RED_SIN : IN STD_LOGIC;
69 67 SPW_RED_DOUT : OUT STD_LOGIC;
70 68 SPW_RED_SOUT : OUT STD_LOGIC;
71 69 ADC_nCS : OUT STD_LOGIC;
72 70 ADC_CLK : OUT STD_LOGIC;
73 71 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
74 72 SRAM_nWE : OUT STD_LOGIC;
75 73 SRAM_CE : OUT STD_LOGIC;
76 74 SRAM_nOE : OUT STD_LOGIC;
77 75 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
78 76 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
79 77 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0));
80 78 END COMPONENT;
81 79
82 80 -----------------------------------------------------------------------------
83 81 SIGNAL clk_50 : STD_LOGIC := '0';
84 82 SIGNAL clk_49 : STD_LOGIC := '0';
85 83 SIGNAL reset : STD_LOGIC;
86 84 SIGNAL BP0 : STD_LOGIC;
87 85 SIGNAL BP1 : STD_LOGIC;
88 86 SIGNAL LED0 : STD_LOGIC;
89 87 SIGNAL LED1 : STD_LOGIC;
90 88 SIGNAL LED2 : STD_LOGIC;
91 89 SIGNAL TXD1 : STD_LOGIC;
92 90 SIGNAL RXD1 : STD_LOGIC;
93 91 SIGNAL nCTS1 : STD_LOGIC;
94 92 SIGNAL nRTS1 : STD_LOGIC;
95 93 SIGNAL TXD2 : STD_LOGIC;
96 94 SIGNAL RXD2 : STD_LOGIC;
97 95 SIGNAL nCTS2 : STD_LOGIC;
98 96 SIGNAL nDTR2 : STD_LOGIC;
99 97 SIGNAL nRTS2 : STD_LOGIC;
100 98 SIGNAL nDCD2 : STD_LOGIC;
101 99 SIGNAL IO0 : STD_LOGIC;
102 100 SIGNAL IO1 : STD_LOGIC;
103 101 SIGNAL IO2 : STD_LOGIC;
104 102 SIGNAL IO3 : STD_LOGIC;
105 103 SIGNAL IO4 : STD_LOGIC;
106 104 SIGNAL IO5 : STD_LOGIC;
107 105 SIGNAL IO6 : STD_LOGIC;
108 106 SIGNAL IO7 : STD_LOGIC;
109 107 SIGNAL IO8 : STD_LOGIC;
110 108 SIGNAL IO9 : STD_LOGIC;
111 109 SIGNAL IO10 : STD_LOGIC;
112 110 SIGNAL IO11 : STD_LOGIC;
113 111 SIGNAL SPW_EN : STD_LOGIC;
114 112 SIGNAL SPW_NOM_DIN : STD_LOGIC;
115 113 SIGNAL SPW_NOM_SIN : STD_LOGIC;
116 114 SIGNAL SPW_NOM_DOUT : STD_LOGIC;
117 115 SIGNAL SPW_NOM_SOUT : STD_LOGIC;
118 116 SIGNAL SPW_RED_DIN : STD_LOGIC;
119 117 SIGNAL SPW_RED_SIN : STD_LOGIC;
120 118 SIGNAL SPW_RED_DOUT : STD_LOGIC;
121 119 SIGNAL SPW_RED_SOUT : STD_LOGIC;
122 120 SIGNAL ADC_nCS : STD_LOGIC;
123 121 SIGNAL ADC_CLK : STD_LOGIC;
124 122 SIGNAL ADC_SDO : STD_LOGIC_VECTOR(7 DOWNTO 0);
125 123 SIGNAL SRAM_nWE : STD_LOGIC;
126 124 SIGNAL SRAM_CE : STD_LOGIC;
127 125 SIGNAL SRAM_nOE : STD_LOGIC;
128 126 SIGNAL SRAM_nBE : STD_LOGIC_VECTOR(3 DOWNTO 0);
129 127 SIGNAL SRAM_A : STD_LOGIC_VECTOR(19 DOWNTO 0);
130 128 SIGNAL SRAM_DQ : STD_LOGIC_VECTOR(31 DOWNTO 0);
131 129 -----------------------------------------------------------------------------
132 130
133 131 CONSTANT ADDR_BASE_LFR : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000F";
134 132 CONSTANT ADDR_BASE_TIME_MANAGMENT : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"800006";
135 133 CONSTANT ADDR_BASE_GPIO : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000B";
136 134
137 135
138 136 SIGNAL message_simu : STRING(1 TO 15) := "---------------";
139 137
140 138 BEGIN
141 139
142 140 -----------------------------------------------------------------------------
143 141 -- TB
144 142 -----------------------------------------------------------------------------
145 143 PROCESS
146 144 CONSTANT txp : TIME := 320 ns;
147 145 BEGIN -- PROCESS
148 146 TXD1 <= '1';
149 147 reset <= '0';
150 148 WAIT FOR 500 ns;
151 149 reset <= '1';
152 150 WAIT FOR 10000 ns;
153 151 message_simu <= "0 - UART init ";
154 152 UART_INIT(TXD1,txp);
155 153
156 154 message_simu <= "1 - UART test ";
157 155 UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000010",X"0000FFFF");
158 156 UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000001",X"00000A0A");
159 157 UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000001",X"00000B0B");
160 158
161 159 -- UNSET the LFR reset
162 160 message_simu <= "2 - LFR UNRESET";
163 161 UART_WRITE(TXD1,txp,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_CONTROL , X"00000000");
164 162 UART_WRITE(TXD1,txp,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_TIME_LOAD , X"00000000");
165 163 --
166 164 message_simu <= "3 - LFR CONFIG ";
167 165 UART_WRITE(TXD1,txp,ADDR_BASE_LFR & ADDR_LFR_SM_F0_0_ADDR , X"00000B0B");
168 166
169 167 WAIT;
170 168 END PROCESS;
171 169
172 170 -----------------------------------------------------------------------------
173 171 -- CLOCK
174 172 -----------------------------------------------------------------------------
175 173 clk_50 <= NOT clk_50 AFTER 5 ns;
176 174 clk_49 <= NOT clk_49 AFTER 10172 ps;
177 175
178 176 -----------------------------------------------------------------------------
179 177 -- DON'T CARE
180 178 -----------------------------------------------------------------------------
181 179 BP0 <= '0';
182 180 BP1 <= '0';
183 181 nRTS1 <= '0' ;
184 182
185 183 TXD2 <= '1';
186 184 nRTS2 <= '1';
187 185 nDTR2 <= '1';
188 186
189 187 SPW_NOM_DIN <= '1';
190 188 SPW_NOM_SIN <= '1';
191 189 SPW_RED_DIN <= '1';
192 190 SPW_RED_SIN <= '1';
193 191
194 192 ADC_SDO <= x"AA";
195 193
196 194 SRAM_DQ <= (OTHERS => 'Z');
197 IO0 <= 'Z';
198 IO1 <= 'Z';
199 IO2 <= 'Z';
200 IO3 <= 'Z';
201 IO4 <= 'Z';
202 IO5 <= 'Z';
203 IO6 <= 'Z';
204 IO7 <= 'Z';
205 IO8 <= 'Z';
206 IO9 <= 'Z';
207 IO10 <= 'Z';
208 IO11 <= 'Z';
195 --IO0 <= 'Z';
196 --IO1 <= 'Z';
197 --IO2 <= 'Z';
198 --IO3 <= 'Z';
199 --IO4 <= 'Z';
200 --IO5 <= 'Z';
201 --IO6 <= 'Z';
202 --IO7 <= 'Z';
203 --IO8 <= 'Z';
204 --IO9 <= 'Z';
205 --IO10 <= 'Z';
206 --IO11 <= 'Z';
209 207
210 208 -----------------------------------------------------------------------------
211 209 -- DUT
212 210 -----------------------------------------------------------------------------
213 211 MINI_LFR_top_1: MINI_LFR_top
214 212 PORT MAP (
215 213 clk_50 => clk_50,
216 214 clk_49 => clk_49,
217 215 reset => reset,
218 216
219 217 BP0 => BP0,
220 218 BP1 => BP1,
221 219
222 220 LED0 => LED0,
223 221 LED1 => LED1,
224 222 LED2 => LED2,
225 223
226 224 TXD1 => TXD1,
227 225 RXD1 => RXD1,
228 226 nCTS1 => nCTS1,
229 227 nRTS1 => nRTS1,
230 228
231 229 TXD2 => TXD2,
232 230 RXD2 => RXD2,
233 231 nCTS2 => nCTS2,
234 232 nDTR2 => nDTR2,
235 233 nRTS2 => nRTS2,
236 234 nDCD2 => nDCD2,
237 235
238 236 IO0 => IO0,
239 237 IO1 => IO1,
240 238 IO2 => IO2,
241 239 IO3 => IO3,
242 240 IO4 => IO4,
243 241 IO5 => IO5,
244 242 IO6 => IO6,
245 243 IO7 => IO7,
246 244 IO8 => IO8,
247 245 IO9 => IO9,
248 246 IO10 => IO10,
249 247 IO11 => IO11,
250 248
251 249 SPW_EN => SPW_EN,
252 250 SPW_NOM_DIN => SPW_NOM_DIN,
253 251 SPW_NOM_SIN => SPW_NOM_SIN,
254 252 SPW_NOM_DOUT => SPW_NOM_DOUT,
255 253 SPW_NOM_SOUT => SPW_NOM_SOUT,
256 254 SPW_RED_DIN => SPW_RED_DIN,
257 255 SPW_RED_SIN => SPW_RED_SIN,
258 256 SPW_RED_DOUT => SPW_RED_DOUT,
259 257 SPW_RED_SOUT => SPW_RED_SOUT,
260 258
261 259 ADC_nCS => ADC_nCS,
262 260 ADC_CLK => ADC_CLK,
263 261 ADC_SDO => ADC_SDO,
264 262
265 263 SRAM_nWE => SRAM_nWE,
266 264 SRAM_CE => SRAM_CE,
267 265 SRAM_nOE => SRAM_nOE,
268 266 SRAM_nBE => SRAM_nBE,
269 267 SRAM_A => SRAM_A,
270 268 SRAM_DQ => SRAM_DQ);
271 269
272 270
273 271 END;
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@@ -1,509 +1,519
1 1 LIBRARY ieee;
2 2 USE ieee.std_logic_1164.ALL;
3 3 USE ieee.numeric_std.ALL;
4 4
5 5 LIBRARY lpp;
6 6 USE lpp.lpp_ad_conv.ALL;
7 7 USE lpp.iir_filter.ALL;
8 8 USE lpp.FILTERcfg.ALL;
9 9 USE lpp.lpp_memory.ALL;
10 10 USE lpp.lpp_waveform_pkg.ALL;
11 11 USE lpp.lpp_dma_pkg.ALL;
12 12 USE lpp.lpp_top_lfr_pkg.ALL;
13 13 USE lpp.lpp_lfr_pkg.ALL;
14 14 USE lpp.general_purpose.ALL;
15 15
16 16 LIBRARY techmap;
17 17 USE techmap.gencomp.ALL;
18 18
19 19 LIBRARY grlib;
20 20 USE grlib.amba.ALL;
21 21 USE grlib.stdlib.ALL;
22 22 USE grlib.devices.ALL;
23 23 USE GRLIB.DMA2AHB_Package.ALL;
24 24
25 25 ENTITY lpp_lfr IS
26 26 GENERIC (
27 27 Mem_use : INTEGER := use_RAM;
28 28 nb_data_by_buffer_size : INTEGER := 11;
29 29 nb_snapshot_param_size : INTEGER := 11;
30 30 delta_vector_size : INTEGER := 20;
31 31 delta_vector_size_f0_2 : INTEGER := 7;
32 32
33 33 pindex : INTEGER := 4;
34 34 paddr : INTEGER := 4;
35 35 pmask : INTEGER := 16#fff#;
36 36 pirq_ms : INTEGER := 0;
37 37 pirq_wfp : INTEGER := 1;
38 38
39 39 hindex : INTEGER := 2;
40 40
41 41 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0')
42 42
43 43 );
44 44 PORT (
45 45 clk : IN STD_LOGIC;
46 46 rstn : IN STD_LOGIC;
47 47 -- SAMPLE
48 48 sample_B : IN Samples(2 DOWNTO 0);
49 49 sample_E : IN Samples(4 DOWNTO 0);
50 50 sample_val : IN STD_LOGIC;
51 51 -- APB
52 52 apbi : IN apb_slv_in_type;
53 53 apbo : OUT apb_slv_out_type;
54 54 -- AHB
55 55 ahbi : IN AHB_Mst_In_Type;
56 56 ahbo : OUT AHB_Mst_Out_Type;
57 57 -- TIME
58 58 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
59 59 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
60 60 --
61 data_shaping_BW : OUT STD_LOGIC
61 data_shaping_BW : OUT STD_LOGIC;
62 --
63 debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
64 debug_vector_ms : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
62 65 );
63 66 END lpp_lfr;
64 67
65 68 ARCHITECTURE beh OF lpp_lfr IS
66 69 SIGNAL sample_s : Samples(7 DOWNTO 0);
67 70 --
68 71 SIGNAL data_shaping_SP0 : STD_LOGIC;
69 72 SIGNAL data_shaping_SP1 : STD_LOGIC;
70 73 SIGNAL data_shaping_R0 : STD_LOGIC;
71 74 SIGNAL data_shaping_R1 : STD_LOGIC;
72 75 SIGNAL data_shaping_R2 : STD_LOGIC;
73 76 --
74 77 SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
75 78 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
76 79 SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
77 80 --
78 81 SIGNAL sample_f0_val : STD_LOGIC;
79 82 SIGNAL sample_f1_val : STD_LOGIC;
80 83 SIGNAL sample_f2_val : STD_LOGIC;
81 84 SIGNAL sample_f3_val : STD_LOGIC;
82 85 --
83 86 SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
84 87 SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
85 88 SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
86 89 SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
87 90 --
88 91 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
89 92 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
90 93 SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
91 94
92 95 -- SM
93 96 SIGNAL ready_matrix_f0 : STD_LOGIC;
94 97 -- SIGNAL ready_matrix_f0_1 : STD_LOGIC;
95 98 SIGNAL ready_matrix_f1 : STD_LOGIC;
96 99 SIGNAL ready_matrix_f2 : STD_LOGIC;
97 100 SIGNAL status_ready_matrix_f0 : STD_LOGIC;
98 101 -- SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
99 102 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
100 103 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
101 104 SIGNAL addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
102 105 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
103 106 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
104 107 SIGNAL length_matrix_f0 : STD_LOGIC_VECTOR(25 DOWNTO 0);
105 108 SIGNAL length_matrix_f1 : STD_LOGIC_VECTOR(25 DOWNTO 0);
106 109 SIGNAL length_matrix_f2 : STD_LOGIC_VECTOR(25 DOWNTO 0);
107 110
108 111 -- WFP
109 112 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
110 113 SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
111 114 SIGNAL delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
112 115 SIGNAL delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
113 116 SIGNAL delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
114 117 SIGNAL delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
115 118
116 119 SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
117 120 SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
118 121 SIGNAL enable_f0 : STD_LOGIC;
119 122 SIGNAL enable_f1 : STD_LOGIC;
120 123 SIGNAL enable_f2 : STD_LOGIC;
121 124 SIGNAL enable_f3 : STD_LOGIC;
122 125 SIGNAL burst_f0 : STD_LOGIC;
123 126 SIGNAL burst_f1 : STD_LOGIC;
124 127 SIGNAL burst_f2 : STD_LOGIC;
125 128
126 129 --SIGNAL run : STD_LOGIC;
127 130 SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
128 131
129 132 -----------------------------------------------------------------------------
130 133 --
131 134 -----------------------------------------------------------------------------
132 135 -- SIGNAL data_f0_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
133 136 -- SIGNAL data_f0_data_out_valid_s : STD_LOGIC;
134 137 -- SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC;
135 138 --f1
136 139 -- SIGNAL data_f1_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
137 140 -- SIGNAL data_f1_data_out_valid_s : STD_LOGIC;
138 141 -- SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC;
139 142 --f2
140 143 -- SIGNAL data_f2_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
141 144 -- SIGNAL data_f2_data_out_valid_s : STD_LOGIC;
142 145 -- SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC;
143 146 --f3
144 147 -- SIGNAL data_f3_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
145 148 -- SIGNAL data_f3_data_out_valid_s : STD_LOGIC;
146 149 -- SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC;
147 150
148 151 SIGNAL wfp_status_buffer_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
149 152 SIGNAL wfp_addr_buffer : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
150 153 SIGNAL wfp_length_buffer : STD_LOGIC_VECTOR(25 DOWNTO 0);
151 154 SIGNAL wfp_ready_buffer : STD_LOGIC_VECTOR(3 DOWNTO 0);
152 155 SIGNAL wfp_buffer_time : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
153 156 SIGNAL wfp_error_buffer_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
154 157 -----------------------------------------------------------------------------
155 158 -- DMA RR
156 159 -----------------------------------------------------------------------------
157 160 -- SIGNAL dma_sel_valid : STD_LOGIC;
158 161 -- SIGNAL dma_rr_valid : STD_LOGIC_VECTOR(3 DOWNTO 0);
159 162 -- SIGNAL dma_rr_grant_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
160 163 -- SIGNAL dma_rr_grant_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
161 164 -- SIGNAL dma_rr_valid_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
162 165
163 166 -- SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(4 DOWNTO 0);
164 167 -- SIGNAL dma_sel : STD_LOGIC_VECTOR(4 DOWNTO 0);
165 168
166 169 -----------------------------------------------------------------------------
167 170 -- DMA_REG
168 171 -----------------------------------------------------------------------------
169 172 -- SIGNAL ongoing_reg : STD_LOGIC;
170 173 -- SIGNAL dma_sel_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
171 174 -- SIGNAL dma_send_reg : STD_LOGIC;
172 175 -- SIGNAL dma_valid_burst_reg : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
173 176 -- SIGNAL dma_address_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
174 177 -- SIGNAL dma_data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
175 178
176 179
177 180 -----------------------------------------------------------------------------
178 181 -- DMA
179 182 -----------------------------------------------------------------------------
180 183 -- SIGNAL dma_send : STD_LOGIC;
181 184 -- SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
182 185 -- SIGNAL dma_done : STD_LOGIC;
183 186 -- SIGNAL dma_ren : STD_LOGIC;
184 187 -- SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0);
185 188 -- SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
186 189 -- SIGNAL dma_data_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
187 190
188 191 -----------------------------------------------------------------------------
189 192 -- MS
190 193 -----------------------------------------------------------------------------
191 194
192 195 -- SIGNAL data_ms_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
193 196 -- SIGNAL data_ms_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
194 197 -- SIGNAL data_ms_valid : STD_LOGIC;
195 198 -- SIGNAL data_ms_valid_burst : STD_LOGIC;
196 199 -- SIGNAL data_ms_ren : STD_LOGIC;
197 200 -- SIGNAL data_ms_done : STD_LOGIC;
198 201 -- SIGNAL dma_ms_ongoing : STD_LOGIC;
199 202
200 203 -- SIGNAL run_ms : STD_LOGIC;
201 204 -- SIGNAL ms_softandhard_rstn : STD_LOGIC;
202 205
203 206 SIGNAL matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
204 207 -- SIGNAL matrix_time_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
205 208 SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
206 209 SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
207 210
208 211
209 212 SIGNAL error_buffer_full : STD_LOGIC;
210 213 SIGNAL error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0);
211 214
212 215 -- SIGNAL debug_ms : STD_LOGIC_VECTOR(31 DOWNTO 0);
213 216 -- SIGNAL debug_signal : STD_LOGIC_VECTOR(31 DOWNTO 0);
214 217
215 218 -----------------------------------------------------------------------------
216 219 SIGNAL dma_fifo_burst_valid : STD_LOGIC_VECTOR(4 DOWNTO 0);
217 220 SIGNAL dma_fifo_data : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
218 221 SIGNAL dma_fifo_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
219 222 SIGNAL dma_buffer_new : STD_LOGIC_VECTOR(4 DOWNTO 0);
220 223 SIGNAL dma_buffer_addr : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
221 224 SIGNAL dma_buffer_length : STD_LOGIC_VECTOR(26*5-1 DOWNTO 0);
222 225 SIGNAL dma_buffer_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
223 226 SIGNAL dma_buffer_full_err : STD_LOGIC_VECTOR(4 DOWNTO 0);
224 227 SIGNAL dma_grant_error : STD_LOGIC;
225 228
229 SIGNAL apb_reg_debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
226 230 -----------------------------------------------------------------------------
227 231 -- SIGNAL run_dma : STD_LOGIC;
228 232 BEGIN
233
234 debug_vector <= apb_reg_debug_vector;
235 -----------------------------------------------------------------------------
229 236
230 237 sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
231 238 sample_s(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
232 239
233 240 --all_channel : FOR i IN 7 DOWNTO 0 GENERATE
234 241 -- sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i);
235 242 --END GENERATE all_channel;
236 243
237 244 -----------------------------------------------------------------------------
238 245 lpp_lfr_filter_1 : lpp_lfr_filter
239 246 GENERIC MAP (
240 247 Mem_use => Mem_use)
241 248 PORT MAP (
242 249 sample => sample_s,
243 250 sample_val => sample_val,
244 251 clk => clk,
245 252 rstn => rstn,
246 253 data_shaping_SP0 => data_shaping_SP0,
247 254 data_shaping_SP1 => data_shaping_SP1,
248 255 data_shaping_R0 => data_shaping_R0,
249 256 data_shaping_R1 => data_shaping_R1,
250 257 data_shaping_R2 => data_shaping_R2,
251 258 sample_f0_val => sample_f0_val,
252 259 sample_f1_val => sample_f1_val,
253 260 sample_f2_val => sample_f2_val,
254 261 sample_f3_val => sample_f3_val,
255 262 sample_f0_wdata => sample_f0_data,
256 263 sample_f1_wdata => sample_f1_data,
257 264 sample_f2_wdata => sample_f2_data,
258 265 sample_f3_wdata => sample_f3_data);
259 266
260 267 -----------------------------------------------------------------------------
261 268 lpp_lfr_apbreg_1 : lpp_lfr_apbreg
262 269 GENERIC MAP (
263 270 nb_data_by_buffer_size => nb_data_by_buffer_size,
264 271 -- nb_word_by_buffer_size => nb_word_by_buffer_size, -- TODO
265 272 nb_snapshot_param_size => nb_snapshot_param_size,
266 273 delta_vector_size => delta_vector_size,
267 274 delta_vector_size_f0_2 => delta_vector_size_f0_2,
268 275 pindex => pindex,
269 276 paddr => paddr,
270 277 pmask => pmask,
271 278 pirq_ms => pirq_ms,
272 279 pirq_wfp => pirq_wfp,
273 280 top_lfr_version => top_lfr_version)
274 281 PORT MAP (
275 282 HCLK => clk,
276 283 HRESETn => rstn,
277 284 apbi => apbi,
278 285 apbo => apbo,
279 286
280 287 run_ms => OPEN,--run_ms,
281 288
282 289 ready_matrix_f0 => ready_matrix_f0,
283 290 ready_matrix_f1 => ready_matrix_f1,
284 291 ready_matrix_f2 => ready_matrix_f2,
285 292 error_buffer_full => error_buffer_full, -- TODO
286 293 error_input_fifo_write => error_input_fifo_write, -- TODO
287 294 status_ready_matrix_f0 => status_ready_matrix_f0,
288 295 status_ready_matrix_f1 => status_ready_matrix_f1,
289 296 status_ready_matrix_f2 => status_ready_matrix_f2,
290 297
291 298 matrix_time_f0 => matrix_time_f0,
292 299 matrix_time_f1 => matrix_time_f1,
293 300 matrix_time_f2 => matrix_time_f2,
294 301
295 302 addr_matrix_f0 => addr_matrix_f0,
296 303 addr_matrix_f1 => addr_matrix_f1,
297 304 addr_matrix_f2 => addr_matrix_f2,
298 305
299 306 length_matrix_f0 => length_matrix_f0,
300 307 length_matrix_f1 => length_matrix_f1,
301 308 length_matrix_f2 => length_matrix_f2,
302 309 -------------------------------------------------------------------------
303 310 --status_full => status_full, -- TODo
304 311 --status_full_ack => status_full_ack, -- TODo
305 312 --status_full_err => status_full_err, -- TODo
306 313 status_new_err => status_new_err,
307 314 data_shaping_BW => data_shaping_BW,
308 315 data_shaping_SP0 => data_shaping_SP0,
309 316 data_shaping_SP1 => data_shaping_SP1,
310 317 data_shaping_R0 => data_shaping_R0,
311 318 data_shaping_R1 => data_shaping_R1,
312 319 data_shaping_R2 => data_shaping_R2,
313 320 delta_snapshot => delta_snapshot,
314 321 delta_f0 => delta_f0,
315 322 delta_f0_2 => delta_f0_2,
316 323 delta_f1 => delta_f1,
317 324 delta_f2 => delta_f2,
318 325 nb_data_by_buffer => nb_data_by_buffer,
319 326 -- nb_word_by_buffer => nb_word_by_buffer, -- TODO
320 327 nb_snapshot_param => nb_snapshot_param,
321 328 enable_f0 => enable_f0,
322 329 enable_f1 => enable_f1,
323 330 enable_f2 => enable_f2,
324 331 enable_f3 => enable_f3,
325 332 burst_f0 => burst_f0,
326 333 burst_f1 => burst_f1,
327 334 burst_f2 => burst_f2,
328 335 run => OPEN, --run,
329 336 start_date => start_date,
330 337 -- debug_signal => debug_signal,
331 338 wfp_status_buffer_ready => wfp_status_buffer_ready,-- TODO
332 339 wfp_addr_buffer => wfp_addr_buffer,-- TODO
333 340 wfp_length_buffer => wfp_length_buffer,-- TODO
334 341
335 342 wfp_ready_buffer => wfp_ready_buffer,-- TODO
336 343 wfp_buffer_time => wfp_buffer_time,-- TODO
337 wfp_error_buffer_full => wfp_error_buffer_full -- TODO
344 wfp_error_buffer_full => wfp_error_buffer_full, -- TODO
345 debug_vector => apb_reg_debug_vector
338 346 );
339 347
340 348 -----------------------------------------------------------------------------
341 349 -----------------------------------------------------------------------------
342 350 lpp_waveform_1 : lpp_waveform
343 351 GENERIC MAP (
344 352 tech => inferred,
345 353 data_size => 6*16,
346 354 nb_data_by_buffer_size => nb_data_by_buffer_size,
347 355 nb_snapshot_param_size => nb_snapshot_param_size,
348 356 delta_vector_size => delta_vector_size,
349 357 delta_vector_size_f0_2 => delta_vector_size_f0_2
350 358 )
351 359 PORT MAP (
352 360 clk => clk,
353 361 rstn => rstn,
354 362
355 363 reg_run => '1',--run,
356 364 reg_start_date => start_date,
357 365 reg_delta_snapshot => delta_snapshot,
358 366 reg_delta_f0 => delta_f0,
359 367 reg_delta_f0_2 => delta_f0_2,
360 368 reg_delta_f1 => delta_f1,
361 369 reg_delta_f2 => delta_f2,
362 370
363 371 enable_f0 => enable_f0,
364 372 enable_f1 => enable_f1,
365 373 enable_f2 => enable_f2,
366 374 enable_f3 => enable_f3,
367 375 burst_f0 => burst_f0,
368 376 burst_f1 => burst_f1,
369 377 burst_f2 => burst_f2,
370 378
371 379 nb_data_by_buffer => nb_data_by_buffer,
372 380 nb_snapshot_param => nb_snapshot_param,
373 381 status_new_err => status_new_err,
374 382
375 383 status_buffer_ready => wfp_status_buffer_ready,
376 384 addr_buffer => wfp_addr_buffer,
377 385 length_buffer => wfp_length_buffer,
378 386 ready_buffer => wfp_ready_buffer,
379 387 buffer_time => wfp_buffer_time,
380 388 error_buffer_full => wfp_error_buffer_full,
381 389
382 390 coarse_time => coarse_time,
383 391 fine_time => fine_time,
384 392
385 393 --f0
386 394 data_f0_in_valid => sample_f0_val,
387 395 data_f0_in => sample_f0_data,
388 396 --f1
389 397 data_f1_in_valid => sample_f1_val,
390 398 data_f1_in => sample_f1_data,
391 399 --f2
392 400 data_f2_in_valid => sample_f2_val,
393 401 data_f2_in => sample_f2_data,
394 402 --f3
395 403 data_f3_in_valid => sample_f3_val,
396 404 data_f3_in => sample_f3_data,
397 405 -- OUTPUT -- DMA interface
398 406
399 407 dma_fifo_valid_burst => dma_fifo_burst_valid(3 DOWNTO 0),
400 408 dma_fifo_data => dma_fifo_data(32*4-1 DOWNTO 0),
401 409 dma_fifo_ren => dma_fifo_ren(3 DOWNTO 0),
402 410 dma_buffer_new => dma_buffer_new(3 DOWNTO 0),
403 411 dma_buffer_addr => dma_buffer_addr(32*4-1 DOWNTO 0),
404 412 dma_buffer_length => dma_buffer_length(26*4-1 DOWNTO 0),
405 413 dma_buffer_full => dma_buffer_full(3 DOWNTO 0),
406 414 dma_buffer_full_err => dma_buffer_full_err(3 DOWNTO 0)
407 415
408 416 );
409 417
410 418 -----------------------------------------------------------------------------
411 419 -- Matrix Spectral
412 420 -----------------------------------------------------------------------------
413 421 sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) &
414 422 NOT(sample_f0_val) & NOT(sample_f0_val);
415 423 sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) &
416 424 NOT(sample_f1_val) & NOT(sample_f1_val);
417 425 sample_f2_wen <= NOT(sample_f2_val) & NOT(sample_f2_val) & NOT(sample_f2_val) &
418 426 NOT(sample_f2_val) & NOT(sample_f2_val);
419 427
420 428 sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB)
421 429 sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16));
422 430 sample_f2_wdata <= sample_f2_data((3*16)-1 DOWNTO (1*16)) & sample_f2_data((6*16)-1 DOWNTO (3*16));
423 431
424 432 -------------------------------------------------------------------------------
425 433
426 434 --ms_softandhard_rstn <= rstn AND run_ms AND run;
427 435
428 436 -----------------------------------------------------------------------------
429 437 lpp_lfr_ms_1 : lpp_lfr_ms
430 438 GENERIC MAP (
431 439 Mem_use => Mem_use)
432 440 PORT MAP (
433 441 clk => clk,
434 442 --rstn => ms_softandhard_rstn, --rstn,
435 443 rstn => rstn,
436 444
437 445 run => '1',--run_ms,
438 446
439 447 start_date => start_date,
440 448
441 449 coarse_time => coarse_time,
442 450 fine_time => fine_time,
443 451
444 452 sample_f0_wen => sample_f0_wen,
445 453 sample_f0_wdata => sample_f0_wdata,
446 454 sample_f1_wen => sample_f1_wen,
447 455 sample_f1_wdata => sample_f1_wdata,
448 456 sample_f2_wen => sample_f2_wen,
449 457 sample_f2_wdata => sample_f2_wdata,
450 458
451 459 --DMA
452 460 dma_fifo_burst_valid => dma_fifo_burst_valid(4), -- OUT
453 461 dma_fifo_data => dma_fifo_data((4+1)*32-1 DOWNTO 4*32), -- OUT
454 462 dma_fifo_ren => dma_fifo_ren(4), -- IN
455 463 dma_buffer_new => dma_buffer_new(4), -- OUT
456 464 dma_buffer_addr => dma_buffer_addr((4+1)*32-1 DOWNTO 4*32), -- OUT
457 465 dma_buffer_length => dma_buffer_length((4+1)*26-1 DOWNTO 4*26), -- OUT
458 466 dma_buffer_full => dma_buffer_full(4), -- IN
459 467 dma_buffer_full_err => dma_buffer_full_err(4), -- IN
460 468
461 469
462 470
463 471 --REG
464 472 ready_matrix_f0 => ready_matrix_f0,
465 473 ready_matrix_f1 => ready_matrix_f1,
466 474 ready_matrix_f2 => ready_matrix_f2,
467 475 error_buffer_full => error_buffer_full,
468 476 error_input_fifo_write => error_input_fifo_write,
469 477
470 478 status_ready_matrix_f0 => status_ready_matrix_f0,
471 479 status_ready_matrix_f1 => status_ready_matrix_f1,
472 480 status_ready_matrix_f2 => status_ready_matrix_f2,
473 481 addr_matrix_f0 => addr_matrix_f0,
474 482 addr_matrix_f1 => addr_matrix_f1,
475 483 addr_matrix_f2 => addr_matrix_f2,
476 484
477 485 length_matrix_f0 => length_matrix_f0,
478 486 length_matrix_f1 => length_matrix_f1,
479 487 length_matrix_f2 => length_matrix_f2,
480 488
481 489 matrix_time_f0 => matrix_time_f0,
482 490 matrix_time_f1 => matrix_time_f1,
483 matrix_time_f2 => matrix_time_f2);
491 matrix_time_f2 => matrix_time_f2,
492
493 debug_vector => debug_vector_ms);
484 494
485 495 -----------------------------------------------------------------------------
486 496 --run_dma <= run_ms OR run;
487 497
488 498 DMA_SubSystem_1 : DMA_SubSystem
489 499 GENERIC MAP (
490 500 hindex => hindex)
491 501 PORT MAP (
492 502 clk => clk,
493 503 rstn => rstn,
494 504 run => '1',--run_dma,
495 505 ahbi => ahbi,
496 506 ahbo => ahbo,
497 507
498 508 fifo_burst_valid => dma_fifo_burst_valid, --fifo_burst_valid,
499 509 fifo_data => dma_fifo_data, --fifo_data,
500 510 fifo_ren => dma_fifo_ren, --fifo_ren,
501 511
502 512 buffer_new => dma_buffer_new, --buffer_new,
503 513 buffer_addr => dma_buffer_addr, --buffer_addr,
504 514 buffer_length => dma_buffer_length, --buffer_length,
505 515 buffer_full => dma_buffer_full, --buffer_full,
506 516 buffer_full_err => dma_buffer_full_err, --buffer_full_err,
507 517 grant_error => dma_grant_error); --grant_error);
508 518
509 519 END beh;
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@@ -1,781 +1,792
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -- jean-christophe.pellion@easii-ic.com
22 22 -------------------------------------------------------------------------------
23 23 LIBRARY ieee;
24 24 USE ieee.std_logic_1164.ALL;
25 25 USE ieee.numeric_std.ALL;
26 26
27 27 LIBRARY grlib;
28 28 USE grlib.amba.ALL;
29 29 USE grlib.stdlib.ALL;
30 30 USE grlib.devices.ALL;
31 31
32 32 LIBRARY lpp;
33 33 USE lpp.lpp_lfr_pkg.ALL;
34 34 USE lpp.apb_devices_list.ALL;
35 35 USE lpp.lpp_memory.ALL;
36 36 USE lpp.lpp_lfr_apbreg_pkg.ALL;
37 37
38 38 LIBRARY techmap;
39 39 USE techmap.gencomp.ALL;
40 40
41 41 ENTITY lpp_lfr_apbreg IS
42 42 GENERIC (
43 43 nb_data_by_buffer_size : INTEGER := 11;
44 44 nb_snapshot_param_size : INTEGER := 11;
45 45 delta_vector_size : INTEGER := 20;
46 46 delta_vector_size_f0_2 : INTEGER := 3;
47 47
48 48 pindex : INTEGER := 4;
49 49 paddr : INTEGER := 4;
50 50 pmask : INTEGER := 16#fff#;
51 51 pirq_ms : INTEGER := 0;
52 52 pirq_wfp : INTEGER := 1;
53 53 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := X"000000");
54 54 PORT (
55 55 -- AMBA AHB system signals
56 56 HCLK : IN STD_ULOGIC;
57 57 HRESETn : IN STD_ULOGIC;
58 58
59 59 -- AMBA APB Slave Interface
60 60 apbi : IN apb_slv_in_type;
61 61 apbo : OUT apb_slv_out_type;
62 62
63 63 ---------------------------------------------------------------------------
64 64 -- Spectral Matrix Reg
65 65 run_ms : OUT STD_LOGIC;
66 66 -- IN
67 67 ready_matrix_f0 : IN STD_LOGIC;
68 68 ready_matrix_f1 : IN STD_LOGIC;
69 69 ready_matrix_f2 : IN STD_LOGIC;
70 70
71 71 -- error_bad_component_error : IN STD_LOGIC;
72 72 error_buffer_full : IN STD_LOGIC; -- TODO
73 73 error_input_fifo_write : IN STD_LOGIC_VECTOR(2 DOWNTO 0); -- TODO
74 74
75 75 -- debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
76 76
77 77 -- OUT
78 78 status_ready_matrix_f0 : OUT STD_LOGIC;
79 79 status_ready_matrix_f1 : OUT STD_LOGIC;
80 80 status_ready_matrix_f2 : OUT STD_LOGIC;
81 81
82 82 --config_active_interruption_onNewMatrix : OUT STD_LOGIC;
83 83 --config_active_interruption_onError : OUT STD_LOGIC;
84 84
85 85 addr_matrix_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
86 86 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
87 87 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
88 88
89 89 length_matrix_f0 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
90 90 length_matrix_f1 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
91 91 length_matrix_f2 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
92 92
93 93 matrix_time_f0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
94 94 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
95 95 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
96 96
97 97 ---------------------------------------------------------------------------
98 98 ---------------------------------------------------------------------------
99 99 -- WaveForm picker Reg
100 100 --status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
101 101 --status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
102 102 --status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
103 103 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
104 104
105 105 -- OUT
106 106 data_shaping_BW : OUT STD_LOGIC;
107 107 data_shaping_SP0 : OUT STD_LOGIC;
108 108 data_shaping_SP1 : OUT STD_LOGIC;
109 109 data_shaping_R0 : OUT STD_LOGIC;
110 110 data_shaping_R1 : OUT STD_LOGIC;
111 111 data_shaping_R2 : OUT STD_LOGIC;
112 112
113 113 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
114 114 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
115 115 delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
116 116 delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
117 117 delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
118 118 nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
119 119 --nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
120 120 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
121 121
122 122 enable_f0 : OUT STD_LOGIC;
123 123 enable_f1 : OUT STD_LOGIC;
124 124 enable_f2 : OUT STD_LOGIC;
125 125 enable_f3 : OUT STD_LOGIC;
126 126
127 127 burst_f0 : OUT STD_LOGIC;
128 128 burst_f1 : OUT STD_LOGIC;
129 129 burst_f2 : OUT STD_LOGIC;
130 130
131 131 run : OUT STD_LOGIC;
132 132
133 133 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
134 134
135 135 wfp_status_buffer_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
136 136 wfp_addr_buffer : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
137 137 wfp_length_buffer : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
138 138 wfp_ready_buffer : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
139 139 wfp_buffer_time : IN STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
140 wfp_error_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0)
140 wfp_error_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
141 ---------------------------------------------------------------------------
142 debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
141 143
142 144 );
143 145
144 146 END lpp_lfr_apbreg;
145 147
146 148 ARCHITECTURE beh OF lpp_lfr_apbreg IS
147 149
148 150 CONSTANT REVISION : INTEGER := 1;
149 151
150 152 CONSTANT pconfig : apb_config_type := (
151 153 0 => ahb_device_reg (lpp.apb_devices_list.VENDOR_LPP, lpp.apb_devices_list.LPP_LFR, 0, REVISION, pirq_wfp),
152 154 1 => apb_iobar(paddr, pmask));
153 155
154 156 --CONSTANT pconfig : apb_config_type := (
155 157 -- 0 => ahb_device_reg (16#19#, 16#19#, 0, REVISION, pirq_wfp),
156 158 -- 1 => apb_iobar(paddr, pmask));
157 159
158 160 TYPE lpp_SpectralMatrix_regs IS RECORD
159 161 config_active_interruption_onNewMatrix : STD_LOGIC;
160 162 config_active_interruption_onError : STD_LOGIC;
161 163 config_ms_run : STD_LOGIC;
162 164 status_ready_matrix_f0_0 : STD_LOGIC;
163 165 status_ready_matrix_f1_0 : STD_LOGIC;
164 166 status_ready_matrix_f2_0 : STD_LOGIC;
165 167 status_ready_matrix_f0_1 : STD_LOGIC;
166 168 status_ready_matrix_f1_1 : STD_LOGIC;
167 169 status_ready_matrix_f2_1 : STD_LOGIC;
168 170 -- status_error_bad_component_error : STD_LOGIC;
169 171 status_error_buffer_full : STD_LOGIC;
170 172 status_error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0);
171 173
172 174 addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
173 175 addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
174 176 addr_matrix_f1_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
175 177 addr_matrix_f1_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
176 178 addr_matrix_f2_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
177 179 addr_matrix_f2_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
178 180
179 181 length_matrix : STD_LOGIC_VECTOR(25 DOWNTO 0);
180 182
181 183 time_matrix_f0_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
182 184 time_matrix_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
183 185 time_matrix_f1_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
184 186 time_matrix_f1_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
185 187 time_matrix_f2_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
186 188 time_matrix_f2_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
187 189 END RECORD;
188 190 SIGNAL reg_sp : lpp_SpectralMatrix_regs;
189 191
190 192 TYPE lpp_WaveformPicker_regs IS RECORD
191 193 -- status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
192 194 -- status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
193 195 status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
194 196 data_shaping_BW : STD_LOGIC;
195 197 data_shaping_SP0 : STD_LOGIC;
196 198 data_shaping_SP1 : STD_LOGIC;
197 199 data_shaping_R0 : STD_LOGIC;
198 200 data_shaping_R1 : STD_LOGIC;
199 201 data_shaping_R2 : STD_LOGIC;
200 202 delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
201 203 delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
202 204 delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
203 205 delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
204 206 delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
205 207 nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
206 208 -- nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
207 209 nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
208 210 enable_f0 : STD_LOGIC;
209 211 enable_f1 : STD_LOGIC;
210 212 enable_f2 : STD_LOGIC;
211 213 enable_f3 : STD_LOGIC;
212 214 burst_f0 : STD_LOGIC;
213 215 burst_f1 : STD_LOGIC;
214 216 burst_f2 : STD_LOGIC;
215 217 run : STD_LOGIC;
216 218 status_ready_buffer_f : STD_LOGIC_VECTOR(4*2-1 DOWNTO 0);
217 219 addr_buffer_f : STD_LOGIC_VECTOR(4*2*32-1 DOWNTO 0);
218 220 time_buffer_f : STD_LOGIC_VECTOR(4*2*48-1 DOWNTO 0);
219 221 length_buffer : STD_LOGIC_VECTOR(25 DOWNTO 0);
220 222 error_buffer_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
221 223 start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
222 224 END RECORD;
223 225 SIGNAL reg_wp : lpp_WaveformPicker_regs;
224 226
225 227 SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
226 228
227 229 -----------------------------------------------------------------------------
228 230 -- IRQ
229 231 -----------------------------------------------------------------------------
230 232 CONSTANT IRQ_WFP_SIZE : INTEGER := 12;
231 233 SIGNAL irq_wfp_ZERO : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
232 234 SIGNAL irq_wfp_reg_s : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
233 235 SIGNAL irq_wfp_reg : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
234 236 SIGNAL irq_wfp : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
235 237 SIGNAL ored_irq_wfp : STD_LOGIC;
236 238
237 239 -----------------------------------------------------------------------------
238 240 --
239 241 -----------------------------------------------------------------------------
240 242 SIGNAL reg0_ready_matrix_f0 : STD_LOGIC;
241 243 -- SIGNAL reg0_addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
242 244 -- SIGNAL reg0_matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
243 245
244 246 SIGNAL reg1_ready_matrix_f0 : STD_LOGIC;
245 247 -- SIGNAL reg1_addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
246 248 -- SIGNAL reg1_matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
247 249
248 250 SIGNAL reg0_ready_matrix_f1 : STD_LOGIC;
249 251 -- SIGNAL reg0_addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
250 252 -- SIGNAL reg0_matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
251 253
252 254 SIGNAL reg1_ready_matrix_f1 : STD_LOGIC;
253 255 -- SIGNAL reg1_addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
254 256 -- SIGNAL reg1_matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
255 257
256 258 SIGNAL reg0_ready_matrix_f2 : STD_LOGIC;
257 259 -- SIGNAL reg0_addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
258 260 -- SIGNAL reg0_matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
259 261
260 262 SIGNAL reg1_ready_matrix_f2 : STD_LOGIC;
261 263 -- SIGNAL reg1_addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
262 264 -- SIGNAL reg1_matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
263 265 SIGNAL apbo_irq_ms : STD_LOGIC;
264 266 SIGNAL apbo_irq_wfp : STD_LOGIC;
265 267 -----------------------------------------------------------------------------
266 268 SIGNAL reg_ready_buffer_f : STD_LOGIC_VECTOR( 2*4-1 DOWNTO 0);
267 269
268 270 SIGNAL pirq_temp : STD_LOGIC_VECTOR(31 DOWNTO 0);
269 271
270 272 BEGIN -- beh
271 273
274 debug_vector(0) <= error_buffer_full;
275 debug_vector(1) <= reg_sp.status_error_buffer_full;
276 debug_vector(4 DOWNTO 2) <= error_input_fifo_write;
277 debug_vector(7 DOWNTO 5) <= reg_sp.status_error_input_fifo_write;
278 debug_vector(8) <= ready_matrix_f2;
279 debug_vector(9) <= reg0_ready_matrix_f2;
280 debug_vector(10) <= reg1_ready_matrix_f2;
281 debug_vector(11) <= HRESETn;
282
272 283 -- status_ready_matrix_f0 <= reg_sp.status_ready_matrix_f0;
273 284 -- status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1;
274 285 -- status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2;
275 286
276 287 -- config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix;
277 288 -- config_active_interruption_onError <= reg_sp.config_active_interruption_onError;
278 289
279 290
280 291 -- addr_matrix_f0 <= reg_sp.addr_matrix_f0;
281 292 -- addr_matrix_f1 <= reg_sp.addr_matrix_f1;
282 293 -- addr_matrix_f2 <= reg_sp.addr_matrix_f2;
283 294
284 295
285 296 data_shaping_BW <= NOT reg_wp.data_shaping_BW;
286 297 data_shaping_SP0 <= reg_wp.data_shaping_SP0;
287 298 data_shaping_SP1 <= reg_wp.data_shaping_SP1;
288 299 data_shaping_R0 <= reg_wp.data_shaping_R0;
289 300 data_shaping_R1 <= reg_wp.data_shaping_R1;
290 301 data_shaping_R2 <= reg_wp.data_shaping_R2;
291 302
292 303 delta_snapshot <= reg_wp.delta_snapshot;
293 304 delta_f0 <= reg_wp.delta_f0;
294 305 delta_f0_2 <= reg_wp.delta_f0_2;
295 306 delta_f1 <= reg_wp.delta_f1;
296 307 delta_f2 <= reg_wp.delta_f2;
297 308 nb_data_by_buffer <= reg_wp.nb_data_by_buffer;
298 309 nb_snapshot_param <= reg_wp.nb_snapshot_param;
299 310
300 311 enable_f0 <= reg_wp.enable_f0;
301 312 enable_f1 <= reg_wp.enable_f1;
302 313 enable_f2 <= reg_wp.enable_f2;
303 314 enable_f3 <= reg_wp.enable_f3;
304 315
305 316 burst_f0 <= reg_wp.burst_f0;
306 317 burst_f1 <= reg_wp.burst_f1;
307 318 burst_f2 <= reg_wp.burst_f2;
308 319
309 320 run <= reg_wp.run;
310 321
311 322 --addr_data_f0 <= reg_wp.addr_data_f0;
312 323 --addr_data_f1 <= reg_wp.addr_data_f1;
313 324 --addr_data_f2 <= reg_wp.addr_data_f2;
314 325 --addr_data_f3 <= reg_wp.addr_data_f3;
315 326
316 327 start_date <= reg_wp.start_date;
317 328
318 329 length_matrix_f0 <= reg_sp.length_matrix;
319 330 length_matrix_f1 <= reg_sp.length_matrix;
320 331 length_matrix_f2 <= reg_sp.length_matrix;
321 332 wfp_length_buffer <= reg_wp.length_buffer;
322 333
323 334
324 335 lpp_lfr_apbreg : PROCESS (HCLK, HRESETn)
325 336 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
326 337 BEGIN -- PROCESS lpp_dma_top
327 338 IF HRESETn = '0' THEN -- asynchronous reset (active low)
328 339 reg_sp.config_active_interruption_onNewMatrix <= '0';
329 340 reg_sp.config_active_interruption_onError <= '0';
330 341 reg_sp.config_ms_run <= '0';
331 342 reg_sp.status_ready_matrix_f0_0 <= '0';
332 343 reg_sp.status_ready_matrix_f1_0 <= '0';
333 344 reg_sp.status_ready_matrix_f2_0 <= '0';
334 345 reg_sp.status_ready_matrix_f0_1 <= '0';
335 346 reg_sp.status_ready_matrix_f1_1 <= '0';
336 347 reg_sp.status_ready_matrix_f2_1 <= '0';
337 348 reg_sp.status_error_buffer_full <= '0';
338 349 reg_sp.status_error_input_fifo_write <= (OTHERS => '0');
339 350
340 351 reg_sp.addr_matrix_f0_0 <= (OTHERS => '0');
341 352 reg_sp.addr_matrix_f1_0 <= (OTHERS => '0');
342 353 reg_sp.addr_matrix_f2_0 <= (OTHERS => '0');
343 354
344 355 reg_sp.addr_matrix_f0_1 <= (OTHERS => '0');
345 356 reg_sp.addr_matrix_f1_1 <= (OTHERS => '0');
346 357 reg_sp.addr_matrix_f2_1 <= (OTHERS => '0');
347 358
348 359 reg_sp.length_matrix <= (OTHERS => '0');
349 360
350 361 -- reg_sp.time_matrix_f0_0 <= (OTHERS => '0'); -- ok
351 362 -- reg_sp.time_matrix_f1_0 <= (OTHERS => '0'); -- ok
352 363 -- reg_sp.time_matrix_f2_0 <= (OTHERS => '0'); -- ok
353 364
354 365 -- reg_sp.time_matrix_f0_1 <= (OTHERS => '0'); -- ok
355 366 --reg_sp.time_matrix_f1_1 <= (OTHERS => '0'); -- ok
356 367 -- reg_sp.time_matrix_f2_1 <= (OTHERS => '0'); -- ok
357 368
358 369 prdata <= (OTHERS => '0');
359 370
360 371
361 372 apbo_irq_ms <= '0';
362 373 apbo_irq_wfp <= '0';
363 374
364 375
365 376 -- status_full_ack <= (OTHERS => '0');
366 377
367 378 reg_wp.data_shaping_BW <= '0';
368 379 reg_wp.data_shaping_SP0 <= '0';
369 380 reg_wp.data_shaping_SP1 <= '0';
370 381 reg_wp.data_shaping_R0 <= '0';
371 382 reg_wp.data_shaping_R1 <= '0';
372 383 reg_wp.data_shaping_R2 <= '0';
373 384 reg_wp.enable_f0 <= '0';
374 385 reg_wp.enable_f1 <= '0';
375 386 reg_wp.enable_f2 <= '0';
376 387 reg_wp.enable_f3 <= '0';
377 388 reg_wp.burst_f0 <= '0';
378 389 reg_wp.burst_f1 <= '0';
379 390 reg_wp.burst_f2 <= '0';
380 391 reg_wp.run <= '0';
381 392 -- reg_wp.status_full <= (OTHERS => '0');
382 393 -- reg_wp.status_full_err <= (OTHERS => '0');
383 394 reg_wp.status_new_err <= (OTHERS => '0');
384 395 reg_wp.error_buffer_full <= (OTHERS => '0');
385 396 reg_wp.delta_snapshot <= (OTHERS => '0');
386 397 reg_wp.delta_f0 <= (OTHERS => '0');
387 398 reg_wp.delta_f0_2 <= (OTHERS => '0');
388 399 reg_wp.delta_f1 <= (OTHERS => '0');
389 400 reg_wp.delta_f2 <= (OTHERS => '0');
390 401 reg_wp.nb_data_by_buffer <= (OTHERS => '0');
391 402 reg_wp.nb_snapshot_param <= (OTHERS => '0');
392 403 reg_wp.start_date <= (OTHERS => '1');
393 404
394 405 reg_wp.status_ready_buffer_f <= (OTHERS => '0');
395 406 reg_wp.length_buffer <= (OTHERS => '0');
396 407
397 408 pirq_temp <= (OTHERS => '0');
398 409
399 410 reg_wp.addr_buffer_f <= (OTHERS => '0');
400 411
401 412 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
402 413
403 414 -- status_full_ack <= (OTHERS => '0');
404 415
405 416 reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR reg0_ready_matrix_f0;
406 417 reg_sp.status_ready_matrix_f1_0 <= reg_sp.status_ready_matrix_f1_0 OR reg0_ready_matrix_f1;
407 418 reg_sp.status_ready_matrix_f2_0 <= reg_sp.status_ready_matrix_f2_0 OR reg0_ready_matrix_f2;
408 419
409 420 reg_sp.status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1 OR reg1_ready_matrix_f0;
410 421 reg_sp.status_ready_matrix_f1_1 <= reg_sp.status_ready_matrix_f1_1 OR reg1_ready_matrix_f1;
411 422 reg_sp.status_ready_matrix_f2_1 <= reg_sp.status_ready_matrix_f2_1 OR reg1_ready_matrix_f2;
412 423
413 424 all_status_ready_buffer_bit: FOR I IN 4*2-1 DOWNTO 0 LOOP
414 425 reg_wp.status_ready_buffer_f(I) <= reg_wp.status_ready_buffer_f(I) OR reg_ready_buffer_f(I);
415 426 END LOOP all_status_ready_buffer_bit;
416 427
417 428
418 429 reg_sp.status_error_buffer_full <= reg_sp.status_error_buffer_full OR error_buffer_full;
419 430 reg_sp.status_error_input_fifo_write(0) <= reg_sp.status_error_input_fifo_write(0) OR error_input_fifo_write(0);
420 431 reg_sp.status_error_input_fifo_write(1) <= reg_sp.status_error_input_fifo_write(1) OR error_input_fifo_write(1);
421 432 reg_sp.status_error_input_fifo_write(2) <= reg_sp.status_error_input_fifo_write(2) OR error_input_fifo_write(2);
422 433
423 434
424 435
425 436 all_status : FOR I IN 3 DOWNTO 0 LOOP
426 437 reg_wp.error_buffer_full(I) <= reg_wp.error_buffer_full(I) OR wfp_error_buffer_full(I);
427 438 reg_wp.status_new_err(I) <= reg_wp.status_new_err(I) OR status_new_err(I);
428 439 END LOOP all_status;
429 440
430 441 paddr := "000000";
431 442 paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
432 443 prdata <= (OTHERS => '0');
433 444 IF apbi.psel(pindex) = '1' THEN
434 445 -- APB DMA READ --
435 446 CASE paddr(7 DOWNTO 2) IS
436 447
437 448 WHEN ADDR_LFR_SM_CONFIG =>
438 449 prdata(0) <= reg_sp.config_active_interruption_onNewMatrix;
439 450 prdata(1) <= reg_sp.config_active_interruption_onError;
440 451 prdata(2) <= reg_sp.config_ms_run;
441 452
442 453 WHEN ADDR_LFR_SM_STATUS =>
443 454 prdata(0) <= reg_sp.status_ready_matrix_f0_0;
444 455 prdata(1) <= reg_sp.status_ready_matrix_f0_1;
445 456 prdata(2) <= reg_sp.status_ready_matrix_f1_0;
446 457 prdata(3) <= reg_sp.status_ready_matrix_f1_1;
447 458 prdata(4) <= reg_sp.status_ready_matrix_f2_0;
448 459 prdata(5) <= reg_sp.status_ready_matrix_f2_1;
449 460 -- prdata(6) <= reg_sp.status_error_bad_component_error;
450 461 prdata(7) <= reg_sp.status_error_buffer_full;
451 462 prdata(8) <= reg_sp.status_error_input_fifo_write(0);
452 463 prdata(9) <= reg_sp.status_error_input_fifo_write(1);
453 464 prdata(10) <= reg_sp.status_error_input_fifo_write(2);
454 465
455 466 WHEN ADDR_LFR_SM_F0_0_ADDR => prdata <= reg_sp.addr_matrix_f0_0;
456 467 WHEN ADDR_LFR_SM_F0_1_ADDR => prdata <= reg_sp.addr_matrix_f0_1;
457 468 WHEN ADDR_LFR_SM_F1_0_ADDR => prdata <= reg_sp.addr_matrix_f1_0;
458 469 WHEN ADDR_LFR_SM_F1_1_ADDR => prdata <= reg_sp.addr_matrix_f1_1;
459 470 WHEN ADDR_LFR_SM_F2_0_ADDR => prdata <= reg_sp.addr_matrix_f2_0;
460 471 WHEN ADDR_LFR_SM_F2_1_ADDR => prdata <= reg_sp.addr_matrix_f2_1;
461 472 WHEN ADDR_LFR_SM_F0_0_TIME_COARSE => prdata <= reg_sp.time_matrix_f0_0(47 DOWNTO 16);
462 473 WHEN ADDR_LFR_SM_F0_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f0_0(15 DOWNTO 0);
463 474 WHEN ADDR_LFR_SM_F0_1_TIME_COARSE => prdata <= reg_sp.time_matrix_f0_1(47 DOWNTO 16);
464 475 WHEN ADDR_LFR_SM_F0_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f0_1(15 DOWNTO 0);
465 476 WHEN ADDR_LFR_SM_F1_0_TIME_COARSE => prdata <= reg_sp.time_matrix_f1_0(47 DOWNTO 16);
466 477 WHEN ADDR_LFR_SM_F1_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f1_0(15 DOWNTO 0);
467 478 WHEN ADDR_LFR_SM_F1_1_TIME_COARSE => prdata <= reg_sp.time_matrix_f1_1(47 DOWNTO 16);
468 479 WHEN ADDR_LFR_SM_F1_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f1_1(15 DOWNTO 0);
469 480 WHEN ADDR_LFR_SM_F2_0_TIME_COARSE => prdata <= reg_sp.time_matrix_f2_0(47 DOWNTO 16);
470 481 WHEN ADDR_LFR_SM_F2_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_0(15 DOWNTO 0);
471 482 WHEN ADDR_LFR_SM_F2_1_TIME_COARSE => prdata <= reg_sp.time_matrix_f2_1(47 DOWNTO 16);
472 483 WHEN ADDR_LFR_SM_F2_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_1(15 DOWNTO 0);
473 484 WHEN ADDR_LFR_SM_LENGTH => prdata(25 DOWNTO 0) <= reg_sp.length_matrix;
474 485 ---------------------------------------------------------------------
475 486 WHEN ADDR_LFR_WP_DATASHAPING =>
476 487 prdata(0) <= reg_wp.data_shaping_BW;
477 488 prdata(1) <= reg_wp.data_shaping_SP0;
478 489 prdata(2) <= reg_wp.data_shaping_SP1;
479 490 prdata(3) <= reg_wp.data_shaping_R0;
480 491 prdata(4) <= reg_wp.data_shaping_R1;
481 492 prdata(5) <= reg_wp.data_shaping_R2;
482 493 WHEN ADDR_LFR_WP_CONTROL =>
483 494 prdata(0) <= reg_wp.enable_f0;
484 495 prdata(1) <= reg_wp.enable_f1;
485 496 prdata(2) <= reg_wp.enable_f2;
486 497 prdata(3) <= reg_wp.enable_f3;
487 498 prdata(4) <= reg_wp.burst_f0;
488 499 prdata(5) <= reg_wp.burst_f1;
489 500 prdata(6) <= reg_wp.burst_f2;
490 501 prdata(7) <= reg_wp.run;
491 502 WHEN ADDR_LFR_WP_F0_0_ADDR => prdata <= reg_wp.addr_buffer_f(32*1-1 DOWNTO 32*0);--0
492 503 WHEN ADDR_LFR_WP_F0_1_ADDR => prdata <= reg_wp.addr_buffer_f(32*2-1 DOWNTO 32*1);
493 504 WHEN ADDR_LFR_WP_F1_0_ADDR => prdata <= reg_wp.addr_buffer_f(32*3-1 DOWNTO 32*2);--1
494 505 WHEN ADDR_LFR_WP_F1_1_ADDR => prdata <= reg_wp.addr_buffer_f(32*4-1 DOWNTO 32*3);
495 506 WHEN ADDR_LFR_WP_F2_0_ADDR => prdata <= reg_wp.addr_buffer_f(32*5-1 DOWNTO 32*4);--2
496 507 WHEN ADDR_LFR_WP_F2_1_ADDR => prdata <= reg_wp.addr_buffer_f(32*6-1 DOWNTO 32*5);
497 508 WHEN ADDR_LFR_WP_F3_0_ADDR => prdata <= reg_wp.addr_buffer_f(32*7-1 DOWNTO 32*6);--3
498 509 WHEN ADDR_LFR_WP_F3_1_ADDR => prdata <= reg_wp.addr_buffer_f(32*8-1 DOWNTO 32*7);
499 510
500 511 WHEN ADDR_LFR_WP_STATUS =>
501 512 prdata(7 DOWNTO 0) <= reg_wp.status_ready_buffer_f;
502 513 prdata(11 DOWNTO 8) <= reg_wp.error_buffer_full;
503 514 prdata(15 DOWNTO 12) <= reg_wp.status_new_err;
504 515
505 516 WHEN ADDR_LFR_WP_DELTASNAPSHOT => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_snapshot;
506 517 WHEN ADDR_LFR_WP_DELTA_F0 => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f0;
507 518 WHEN ADDR_LFR_WP_DELTA_F0_2 => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2;
508 519 WHEN ADDR_LFR_WP_DELTA_F1 => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f1;
509 520 WHEN ADDR_LFR_WP_DELTA_F2 => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2;
510 521 WHEN ADDR_LFR_WP_DATA_IN_BUFFER => prdata(nb_data_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_data_by_buffer;
511 522 WHEN ADDR_LFR_WP_NBSNAPSHOT => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param;
512 523 WHEN ADDR_LFR_WP_START_DATE => prdata(30 DOWNTO 0) <= reg_wp.start_date;
513 524
514 525 WHEN ADDR_LFR_WP_F0_0_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*0 + 31 DOWNTO 48*0);
515 526 WHEN ADDR_LFR_WP_F0_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*0 + 47 DOWNTO 48*0 + 32);
516 527 WHEN ADDR_LFR_WP_F0_1_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*1 + 31 DOWNTO 48*1);
517 528 WHEN ADDR_LFR_WP_F0_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*1 + 47 DOWNTO 48*1 + 32);
518 529
519 530 WHEN ADDR_LFR_WP_F1_0_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*2 + 31 DOWNTO 48*2);
520 531 WHEN ADDR_LFR_WP_F1_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*2 + 47 DOWNTO 48*2 + 32);
521 532 WHEN ADDR_LFR_WP_F1_1_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*3 + 31 DOWNTO 48*3);
522 533 WHEN ADDR_LFR_WP_F1_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*3 + 47 DOWNTO 48*3 + 32);
523 534
524 535 WHEN ADDR_LFR_WP_F2_0_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*4 + 31 DOWNTO 48*4);
525 536 WHEN ADDR_LFR_WP_F2_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*4 + 47 DOWNTO 48*4 + 32);
526 537 WHEN ADDR_LFR_WP_F2_1_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*5 + 31 DOWNTO 48*5);
527 538 WHEN ADDR_LFR_WP_F2_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*5 + 47 DOWNTO 48*5 + 32);
528 539
529 540 WHEN ADDR_LFR_WP_F3_0_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*6 + 31 DOWNTO 48*6);
530 541 WHEN ADDR_LFR_WP_F3_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*6 + 47 DOWNTO 48*6 + 32);
531 542 WHEN ADDR_LFR_WP_F3_1_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*7 + 31 DOWNTO 48*7);
532 543 WHEN ADDR_LFR_WP_F3_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*7 + 47 DOWNTO 48*7 + 32);
533 544
534 545 WHEN ADDR_LFR_WP_LENGTH => prdata(25 DOWNTO 0) <= reg_wp.length_buffer;
535 546 ---------------------------------------------------------------------
536 547 WHEN ADDR_LFR_VERSION => prdata(23 DOWNTO 0) <= top_lfr_version(23 DOWNTO 0);
537 548 WHEN OTHERS => NULL;
538 549
539 550 END CASE;
540 551 IF (apbi.pwrite AND apbi.penable) = '1' THEN
541 552 -- APB DMA WRITE --
542 553 CASE paddr(7 DOWNTO 2) IS
543 554 --
544 555 WHEN ADDR_LFR_SM_CONFIG =>
545 556 reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0);
546 557 reg_sp.config_active_interruption_onError <= apbi.pwdata(1);
547 558 reg_sp.config_ms_run <= apbi.pwdata(2);
548 559
549 560 WHEN ADDR_LFR_SM_STATUS =>
550 561 reg_sp.status_ready_matrix_f0_0 <= ((NOT apbi.pwdata(0) ) AND reg_sp.status_ready_matrix_f0_0 ) OR reg0_ready_matrix_f0;
551 562 reg_sp.status_ready_matrix_f0_1 <= ((NOT apbi.pwdata(1) ) AND reg_sp.status_ready_matrix_f0_1 ) OR reg1_ready_matrix_f0;
552 563 reg_sp.status_ready_matrix_f1_0 <= ((NOT apbi.pwdata(2) ) AND reg_sp.status_ready_matrix_f1_0 ) OR reg0_ready_matrix_f1;
553 564 reg_sp.status_ready_matrix_f1_1 <= ((NOT apbi.pwdata(3) ) AND reg_sp.status_ready_matrix_f1_1 ) OR reg1_ready_matrix_f1;
554 565 reg_sp.status_ready_matrix_f2_0 <= ((NOT apbi.pwdata(4) ) AND reg_sp.status_ready_matrix_f2_0 ) OR reg0_ready_matrix_f2;
555 566 reg_sp.status_ready_matrix_f2_1 <= ((NOT apbi.pwdata(5) ) AND reg_sp.status_ready_matrix_f2_1 ) OR reg1_ready_matrix_f2;
556 567 reg_sp.status_error_buffer_full <= ((NOT apbi.pwdata(7) ) AND reg_sp.status_error_buffer_full ) OR error_buffer_full;
557 568 reg_sp.status_error_input_fifo_write(0) <= ((NOT apbi.pwdata(8) ) AND reg_sp.status_error_input_fifo_write(0)) OR error_input_fifo_write(0);
558 569 reg_sp.status_error_input_fifo_write(1) <= ((NOT apbi.pwdata(9) ) AND reg_sp.status_error_input_fifo_write(1)) OR error_input_fifo_write(1);
559 570 reg_sp.status_error_input_fifo_write(2) <= ((NOT apbi.pwdata(10)) AND reg_sp.status_error_input_fifo_write(2)) OR error_input_fifo_write(2);
560 571 WHEN ADDR_LFR_SM_F0_0_ADDR => reg_sp.addr_matrix_f0_0 <= apbi.pwdata;
561 572 WHEN ADDR_LFR_SM_F0_1_ADDR => reg_sp.addr_matrix_f0_1 <= apbi.pwdata;
562 573 WHEN ADDR_LFR_SM_F1_0_ADDR => reg_sp.addr_matrix_f1_0 <= apbi.pwdata;
563 574 WHEN ADDR_LFR_SM_F1_1_ADDR => reg_sp.addr_matrix_f1_1 <= apbi.pwdata;
564 575 WHEN ADDR_LFR_SM_F2_0_ADDR => reg_sp.addr_matrix_f2_0 <= apbi.pwdata;
565 576 WHEN ADDR_LFR_SM_F2_1_ADDR => reg_sp.addr_matrix_f2_1 <= apbi.pwdata;
566 577
567 578 WHEN ADDR_LFR_SM_LENGTH => reg_sp.length_matrix <= apbi.pwdata(25 DOWNTO 0);
568 579 ---------------------------------------------------------------------
569 580 WHEN ADDR_LFR_WP_DATASHAPING =>
570 581 reg_wp.data_shaping_BW <= apbi.pwdata(0);
571 582 reg_wp.data_shaping_SP0 <= apbi.pwdata(1);
572 583 reg_wp.data_shaping_SP1 <= apbi.pwdata(2);
573 584 reg_wp.data_shaping_R0 <= apbi.pwdata(3);
574 585 reg_wp.data_shaping_R1 <= apbi.pwdata(4);
575 586 reg_wp.data_shaping_R2 <= apbi.pwdata(5);
576 587 WHEN ADDR_LFR_WP_CONTROL =>
577 588 reg_wp.enable_f0 <= apbi.pwdata(0);
578 589 reg_wp.enable_f1 <= apbi.pwdata(1);
579 590 reg_wp.enable_f2 <= apbi.pwdata(2);
580 591 reg_wp.enable_f3 <= apbi.pwdata(3);
581 592 reg_wp.burst_f0 <= apbi.pwdata(4);
582 593 reg_wp.burst_f1 <= apbi.pwdata(5);
583 594 reg_wp.burst_f2 <= apbi.pwdata(6);
584 595 reg_wp.run <= apbi.pwdata(7);
585 596 WHEN ADDR_LFR_WP_F0_0_ADDR => reg_wp.addr_buffer_f(32*1-1 DOWNTO 32*0) <= apbi.pwdata;
586 597 WHEN ADDR_LFR_WP_F0_1_ADDR => reg_wp.addr_buffer_f(32*2-1 DOWNTO 32*1) <= apbi.pwdata;
587 598 WHEN ADDR_LFR_WP_F1_0_ADDR => reg_wp.addr_buffer_f(32*3-1 DOWNTO 32*2) <= apbi.pwdata;
588 599 WHEN ADDR_LFR_WP_F1_1_ADDR => reg_wp.addr_buffer_f(32*4-1 DOWNTO 32*3) <= apbi.pwdata;
589 600 WHEN ADDR_LFR_WP_F2_0_ADDR => reg_wp.addr_buffer_f(32*5-1 DOWNTO 32*4) <= apbi.pwdata;
590 601 WHEN ADDR_LFR_WP_F2_1_ADDR => reg_wp.addr_buffer_f(32*6-1 DOWNTO 32*5) <= apbi.pwdata;
591 602 WHEN ADDR_LFR_WP_F3_0_ADDR => reg_wp.addr_buffer_f(32*7-1 DOWNTO 32*6) <= apbi.pwdata;
592 603 WHEN ADDR_LFR_WP_F3_1_ADDR => reg_wp.addr_buffer_f(32*8-1 DOWNTO 32*7) <= apbi.pwdata;
593 604 WHEN ADDR_LFR_WP_STATUS =>
594 605 all_reg_wp_status_bit: FOR I IN 3 DOWNTO 0 LOOP
595 606 reg_wp.status_ready_buffer_f(I*2) <= ((NOT apbi.pwdata(I*2) ) AND reg_wp.status_ready_buffer_f(I*2) ) OR reg_ready_buffer_f(I*2);
596 607 reg_wp.status_ready_buffer_f(I*2+1) <= ((NOT apbi.pwdata(I*2+1)) AND reg_wp.status_ready_buffer_f(I*2+1)) OR reg_ready_buffer_f(I*2+1);
597 608 reg_wp.error_buffer_full(I) <= ((NOT apbi.pwdata(I+8) ) AND reg_wp.error_buffer_full(I) ) OR wfp_error_buffer_full(I);
598 609 reg_wp.status_new_err(I) <= ((NOT apbi.pwdata(I+12) ) AND reg_wp.status_new_err(I) ) OR status_new_err(I);
599 610 END LOOP all_reg_wp_status_bit;
600 611
601 612 WHEN ADDR_LFR_WP_DELTASNAPSHOT => reg_wp.delta_snapshot <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
602 613 WHEN ADDR_LFR_WP_DELTA_F0 => reg_wp.delta_f0 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
603 614 WHEN ADDR_LFR_WP_DELTA_F0_2 => reg_wp.delta_f0_2 <= apbi.pwdata(delta_vector_size_f0_2-1 DOWNTO 0);
604 615 WHEN ADDR_LFR_WP_DELTA_F1 => reg_wp.delta_f1 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
605 616 WHEN ADDR_LFR_WP_DELTA_F2 => reg_wp.delta_f2 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
606 617 WHEN ADDR_LFR_WP_DATA_IN_BUFFER => reg_wp.nb_data_by_buffer <= apbi.pwdata(nb_data_by_buffer_size-1 DOWNTO 0);
607 618 WHEN ADDR_LFR_WP_NBSNAPSHOT => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0);
608 619 WHEN ADDR_LFR_WP_START_DATE => reg_wp.start_date <= apbi.pwdata(30 DOWNTO 0);
609 620
610 621 WHEN ADDR_LFR_WP_LENGTH => reg_wp.length_buffer <= apbi.pwdata(25 DOWNTO 0);
611 622
612 623 WHEN OTHERS => NULL;
613 624 END CASE;
614 625 END IF;
615 626 END IF;
616 627 --apbo.pirq(pirq_ms) <=
617 628 pirq_temp( pirq_ms) <= apbo_irq_ms;
618 629 pirq_temp(pirq_wfp) <= apbo_irq_wfp;
619 630 apbo_irq_ms <= ((reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0 OR
620 631 ready_matrix_f1 OR
621 632 ready_matrix_f2)
622 633 )
623 634 OR
624 635 (reg_sp.config_active_interruption_onError AND (
625 636 -- error_bad_component_error OR
626 637 error_buffer_full
627 638 OR error_input_fifo_write(0)
628 639 OR error_input_fifo_write(1)
629 640 OR error_input_fifo_write(2))
630 641 ));
631 642 -- apbo.pirq(pirq_wfp)
632 643 apbo_irq_wfp<= ored_irq_wfp;
633 644
634 645 END IF;
635 646 END PROCESS lpp_lfr_apbreg;
636 647
637 648 apbo.pirq <= pirq_temp;
638 649
639 650
640 651 --all_irq: FOR I IN 31 DOWNTO 0 GENERATE
641 652 -- IRQ_is_PIRQ_MS: IF I = pirq_ms GENERATE
642 653 -- apbo.pirq(I) <= apbo_irq_ms;
643 654 -- END GENERATE IRQ_is_PIRQ_MS;
644 655 -- IRQ_is_PIRQ_WFP: IF I = pirq_wfp GENERATE
645 656 -- apbo.pirq(I) <= apbo_irq_wfp;
646 657 -- END GENERATE IRQ_is_PIRQ_WFP;
647 658 -- IRQ_OTHERS: IF I /= pirq_ms AND pirq_wfp /= pirq_wfp GENERATE
648 659 -- apbo.pirq(I) <= '0';
649 660 -- END GENERATE IRQ_OTHERS;
650 661
651 662 --END GENERATE all_irq;
652 663
653 664
654 665
655 666 apbo.pindex <= pindex;
656 667 apbo.pconfig <= pconfig;
657 668 apbo.prdata <= prdata;
658 669
659 670 -----------------------------------------------------------------------------
660 671 -- IRQ
661 672 -----------------------------------------------------------------------------
662 673 irq_wfp_reg_s <= wfp_ready_buffer & wfp_error_buffer_full & status_new_err;
663 674
664 675 PROCESS (HCLK, HRESETn)
665 676 BEGIN -- PROCESS
666 677 IF HRESETn = '0' THEN -- asynchronous reset (active low)
667 678 irq_wfp_reg <= (OTHERS => '0');
668 679 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
669 680 irq_wfp_reg <= irq_wfp_reg_s;
670 681 END IF;
671 682 END PROCESS;
672 683
673 684 all_irq_wfp : FOR I IN IRQ_WFP_SIZE-1 DOWNTO 0 GENERATE
674 685 irq_wfp(I) <= (NOT irq_wfp_reg(I)) AND irq_wfp_reg_s(I);
675 686 END GENERATE all_irq_wfp;
676 687
677 688 irq_wfp_ZERO <= (OTHERS => '0');
678 689 ored_irq_wfp <= '0' WHEN irq_wfp = irq_wfp_ZERO ELSE '1';
679 690
680 691 run_ms <= reg_sp.config_ms_run;
681 692
682 693 -----------------------------------------------------------------------------
683 694 --
684 695 -----------------------------------------------------------------------------
685 696 lpp_apbreg_ms_pointer_f0 : lpp_apbreg_ms_pointer
686 697 PORT MAP (
687 698 clk => HCLK,
688 699 rstn => HRESETn,
689 700
690 701 run => '1',--reg_sp.config_ms_run,
691 702
692 703 reg0_status_ready_matrix => reg_sp.status_ready_matrix_f0_0,
693 704 reg0_ready_matrix => reg0_ready_matrix_f0,
694 705 reg0_addr_matrix => reg_sp.addr_matrix_f0_0, --reg0_addr_matrix_f0,
695 706 reg0_matrix_time => reg_sp.time_matrix_f0_0, --reg0_matrix_time_f0,
696 707
697 708 reg1_status_ready_matrix => reg_sp.status_ready_matrix_f0_1,
698 709 reg1_ready_matrix => reg1_ready_matrix_f0,
699 710 reg1_addr_matrix => reg_sp.addr_matrix_f0_1, --reg1_addr_matrix_f0,
700 711 reg1_matrix_time => reg_sp.time_matrix_f0_1, --reg1_matrix_time_f0,
701 712
702 713 ready_matrix => ready_matrix_f0,
703 714 status_ready_matrix => status_ready_matrix_f0,
704 715 addr_matrix => addr_matrix_f0,
705 716 matrix_time => matrix_time_f0);
706 717
707 718 lpp_apbreg_ms_pointer_f1 : lpp_apbreg_ms_pointer
708 719 PORT MAP (
709 720 clk => HCLK,
710 721 rstn => HRESETn,
711 722
712 723 run => '1',--reg_sp.config_ms_run,
713 724
714 725 reg0_status_ready_matrix => reg_sp.status_ready_matrix_f1_0,
715 726 reg0_ready_matrix => reg0_ready_matrix_f1,
716 727 reg0_addr_matrix => reg_sp.addr_matrix_f1_0, --reg0_addr_matrix_f1,
717 728 reg0_matrix_time => reg_sp.time_matrix_f1_0, --reg0_matrix_time_f1,
718 729
719 730 reg1_status_ready_matrix => reg_sp.status_ready_matrix_f1_1,
720 731 reg1_ready_matrix => reg1_ready_matrix_f1,
721 732 reg1_addr_matrix => reg_sp.addr_matrix_f1_1, --reg1_addr_matrix_f1,
722 733 reg1_matrix_time => reg_sp.time_matrix_f1_1, --reg1_matrix_time_f1,
723 734
724 735 ready_matrix => ready_matrix_f1,
725 736 status_ready_matrix => status_ready_matrix_f1,
726 737 addr_matrix => addr_matrix_f1,
727 738 matrix_time => matrix_time_f1);
728 739
729 740 lpp_apbreg_ms_pointer_f2 : lpp_apbreg_ms_pointer
730 741 PORT MAP (
731 742 clk => HCLK,
732 743 rstn => HRESETn,
733 744
734 745 run => '1',--reg_sp.config_ms_run,
735 746
736 747 reg0_status_ready_matrix => reg_sp.status_ready_matrix_f2_0,
737 748 reg0_ready_matrix => reg0_ready_matrix_f2,
738 749 reg0_addr_matrix => reg_sp.addr_matrix_f2_0, --reg0_addr_matrix_f2,
739 750 reg0_matrix_time => reg_sp.time_matrix_f2_0, --reg0_matrix_time_f2,
740 751
741 752 reg1_status_ready_matrix => reg_sp.status_ready_matrix_f2_1,
742 753 reg1_ready_matrix => reg1_ready_matrix_f2,
743 754 reg1_addr_matrix => reg_sp.addr_matrix_f2_1, --reg1_addr_matrix_f2,
744 755 reg1_matrix_time => reg_sp.time_matrix_f2_1, --reg1_matrix_time_f2,
745 756
746 757 ready_matrix => ready_matrix_f2,
747 758 status_ready_matrix => status_ready_matrix_f2,
748 759 addr_matrix => addr_matrix_f2,
749 760 matrix_time => matrix_time_f2);
750 761
751 762 -----------------------------------------------------------------------------
752 763 all_wfp_pointer: FOR I IN 3 DOWNTO 0 GENERATE
753 764 lpp_apbreg_wfp_pointer_fi : lpp_apbreg_ms_pointer
754 765 PORT MAP (
755 766 clk => HCLK,
756 767 rstn => HRESETn,
757 768
758 769 run => '1',--reg_wp.run,
759 770
760 771 reg0_status_ready_matrix => reg_wp.status_ready_buffer_f(2*I),
761 772 reg0_ready_matrix => reg_ready_buffer_f(2*I),
762 773 reg0_addr_matrix => reg_wp.addr_buffer_f((2*I+1)*32-1 DOWNTO (2*I)*32),
763 774 reg0_matrix_time => reg_wp.time_buffer_f((2*I+1)*48-1 DOWNTO (2*I)*48),
764 775
765 776 reg1_status_ready_matrix => reg_wp.status_ready_buffer_f(2*I+1),
766 777 reg1_ready_matrix => reg_ready_buffer_f(2*I+1),
767 778 reg1_addr_matrix => reg_wp.addr_buffer_f((2*I+2)*32-1 DOWNTO (2*I+1)*32),
768 779 reg1_matrix_time => reg_wp.time_buffer_f((2*I+2)*48-1 DOWNTO (2*I+1)*48),
769 780
770 781 ready_matrix => wfp_ready_buffer(I),
771 782 status_ready_matrix => wfp_status_buffer_ready(I),
772 783 addr_matrix => wfp_addr_buffer((I+1)*32-1 DOWNTO I*32),
773 784 matrix_time => wfp_buffer_time((I+1)*48-1 DOWNTO I*48)
774 785 );
775 786
776 787 END GENERATE all_wfp_pointer;
777 788 -----------------------------------------------------------------------------
778 789
779 790 END beh;
780 791
781 ------------------------------------------------------------------------------- No newline at end of file
792 ------------------------------------------------------------------------------
Show file before | Show file after | Hide comments
@@ -1,1207 +1,1213
1 1 LIBRARY ieee;
2 2 USE ieee.std_logic_1164.ALL;
3 3 USE ieee.numeric_std.ALL;
4 4
5 5
6 6 LIBRARY lpp;
7 7 USE lpp.lpp_memory.ALL;
8 8 USE lpp.iir_filter.ALL;
9 9 USE lpp.spectral_matrix_package.ALL;
10 10 USE lpp.lpp_dma_pkg.ALL;
11 11 USE lpp.lpp_Header.ALL;
12 12 USE lpp.lpp_matrix.ALL;
13 13 USE lpp.lpp_matrix.ALL;
14 14 USE lpp.lpp_lfr_pkg.ALL;
15 15 USE lpp.lpp_fft.ALL;
16 16 USE lpp.fft_components.ALL;
17 17
18 18 ENTITY lpp_lfr_ms IS
19 19 GENERIC (
20 20 Mem_use : INTEGER := use_RAM
21 21 );
22 22 PORT (
23 23 clk : IN STD_LOGIC;
24 24 rstn : IN STD_LOGIC;
25 25 run : IN STD_LOGIC;
26 26
27 27 ---------------------------------------------------------------------------
28 28 -- DATA INPUT
29 29 ---------------------------------------------------------------------------
30 30 start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
31 31 -- TIME
32 32 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
33 33 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
34 34 --
35 35 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
36 36 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
37 37 --
38 38 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
39 39 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
40 40 --
41 41 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
42 42 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
43 43
44 44 ---------------------------------------------------------------------------
45 45 -- DMA
46 46 ---------------------------------------------------------------------------
47 47 dma_fifo_burst_valid: OUT STD_LOGIC; --TODO
48 48 dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --TODO
49 49 dma_fifo_ren : IN STD_LOGIC; --TODO
50 50 dma_buffer_new : OUT STD_LOGIC; --TODOx
51 51 dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --TODO
52 52 dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); --TODO
53 53 dma_buffer_full : IN STD_LOGIC; --TODO
54 54 dma_buffer_full_err : IN STD_LOGIC; --TODO
55 55
56 56 -- Reg out
57 57 ready_matrix_f0 : OUT STD_LOGIC; -- TODO
58 58 ready_matrix_f1 : OUT STD_LOGIC; -- TODO
59 59 ready_matrix_f2 : OUT STD_LOGIC; -- TODO
60 60 -- error_bad_component_error : OUT STD_LOGIC; -- TODO
61 61 error_buffer_full : OUT STD_LOGIC; -- TODO
62 62 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
63 63
64 64 -- Reg In
65 65 status_ready_matrix_f0 : IN STD_LOGIC; -- TODO
66 66 status_ready_matrix_f1 : IN STD_LOGIC; -- TODO
67 67 status_ready_matrix_f2 : IN STD_LOGIC; -- TODO
68 68
69 69 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
70 70 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
71 71 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
72 72
73 73 length_matrix_f0 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); -- TODO
74 74 length_matrix_f1 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); -- TODO
75 75 length_matrix_f2 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); -- TODO
76 76
77 77 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
78 78 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
79 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) -- TODO
80
79 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
80 ---------------------------------------------------------------------------
81 debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
81 82 );
82 83 END;
83 84
84 85 ARCHITECTURE Behavioral OF lpp_lfr_ms IS
85 86
86 87 SIGNAL sample_f0_A_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
87 88 SIGNAL sample_f0_A_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
88 89 SIGNAL sample_f0_A_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
89 90 SIGNAL sample_f0_A_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
90 91 SIGNAL sample_f0_A_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
91 92
92 93 SIGNAL sample_f0_B_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
93 94 SIGNAL sample_f0_B_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
94 95 SIGNAL sample_f0_B_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
95 96 SIGNAL sample_f0_B_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
96 97 SIGNAL sample_f0_B_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
97 98
98 99 SIGNAL sample_f1_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
99 100 SIGNAL sample_f1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
100 101 SIGNAL sample_f1_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
101 102 SIGNAL sample_f1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
102 103
103 104 SIGNAL sample_f1_almost_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
104 105
105 106 SIGNAL sample_f2_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
106 107 SIGNAL sample_f2_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
107 108 SIGNAL sample_f2_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
108 109 SIGNAL sample_f2_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
109 110
110 111 SIGNAL error_wen_f0 : STD_LOGIC;
111 112 SIGNAL error_wen_f1 : STD_LOGIC;
112 113 SIGNAL error_wen_f2 : STD_LOGIC;
113 114
114 115 SIGNAL one_sample_f1_full : STD_LOGIC;
115 116 SIGNAL one_sample_f1_wen : STD_LOGIC;
116 117 SIGNAL one_sample_f2_full : STD_LOGIC;
117 118 SIGNAL one_sample_f2_wen : STD_LOGIC;
118 119
119 120 -----------------------------------------------------------------------------
120 121 -- FSM / SWITCH SELECT CHANNEL
121 122 -----------------------------------------------------------------------------
122 123 TYPE fsm_select_channel IS (IDLE, SWITCH_F0_A, SWITCH_F0_B, SWITCH_F1, SWITCH_F2);
123 124 SIGNAL state_fsm_select_channel : fsm_select_channel;
124 125 -- SIGNAL pre_state_fsm_select_channel : fsm_select_channel;
125 126 SIGNAL select_channel : STD_LOGIC_VECTOR(1 DOWNTO 0);
126 127 SIGNAL select_channel_reg : STD_LOGIC_VECTOR(1 DOWNTO 0);
127 128
128 129 SIGNAL sample_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
129 130 SIGNAL sample_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
130 131 SIGNAL sample_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
131 132 SIGNAL sample_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
132 133
133 134 -----------------------------------------------------------------------------
134 135 -- FSM LOAD FFT
135 136 -----------------------------------------------------------------------------
136 137 TYPE fsm_load_FFT IS (IDLE, FIFO_1, FIFO_2, FIFO_3, FIFO_4, FIFO_5);
137 138 SIGNAL state_fsm_load_FFT : fsm_load_FFT;
138 139 -- SIGNAL next_state_fsm_load_FFT : fsm_load_FFT;
139 140 SIGNAL select_fifo : STD_LOGIC_VECTOR(2 DOWNTO 0);
140 141 SIGNAL select_fifo_reg : STD_LOGIC_VECTOR(2 DOWNTO 0);
141 142
142 143 SIGNAL sample_ren_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
143 144 SIGNAL sample_load : STD_LOGIC;
144 145 SIGNAL sample_valid : STD_LOGIC;
145 146 SIGNAL sample_valid_r : STD_LOGIC;
146 147 SIGNAL sample_data : STD_LOGIC_VECTOR(15 DOWNTO 0);
147 148
148 149
149 150 -----------------------------------------------------------------------------
150 151 -- FFT
151 152 -----------------------------------------------------------------------------
152 153 SIGNAL fft_read : STD_LOGIC;
153 154 SIGNAL fft_pong : STD_LOGIC;
154 155 SIGNAL fft_data_im : STD_LOGIC_VECTOR(15 DOWNTO 0);
155 156 SIGNAL fft_data_re : STD_LOGIC_VECTOR(15 DOWNTO 0);
156 157 SIGNAL fft_data_valid : STD_LOGIC;
157 158 SIGNAL fft_ready : STD_LOGIC;
158 159 -----------------------------------------------------------------------------
159 160 -- SIGNAL fft_linker_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
160 161 -----------------------------------------------------------------------------
161 162 TYPE fsm_load_MS_memory IS (IDLE, LOAD_FIFO, TRASH_FFT);
162 163 SIGNAL state_fsm_load_MS_memory : fsm_load_MS_memory;
163 164 SIGNAL current_fifo_load : STD_LOGIC_VECTOR(4 DOWNTO 0);
164 165 SIGNAL current_fifo_empty : STD_LOGIC;
165 166 SIGNAL current_fifo_locked : STD_LOGIC;
166 167 SIGNAL current_fifo_full : STD_LOGIC;
167 168 SIGNAL MEM_IN_SM_locked : STD_LOGIC_VECTOR(4 DOWNTO 0);
168 169
169 170 -----------------------------------------------------------------------------
170 171 SIGNAL MEM_IN_SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
171 172 SIGNAL MEM_IN_SM_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
172 173 SIGNAL MEM_IN_SM_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
173 174 SIGNAL MEM_IN_SM_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
174 175 SIGNAL MEM_IN_SM_wData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
175 176 SIGNAL MEM_IN_SM_rData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
176 177 SIGNAL MEM_IN_SM_Full : STD_LOGIC_VECTOR(4 DOWNTO 0);
177 178 SIGNAL MEM_IN_SM_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
178 179 -----------------------------------------------------------------------------
179 180 SIGNAL SM_in_data : STD_LOGIC_VECTOR(32*2-1 DOWNTO 0);
180 181 SIGNAL SM_in_ren : STD_LOGIC_VECTOR(1 DOWNTO 0);
181 182 SIGNAL SM_in_empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
182 183
183 184 SIGNAL SM_correlation_start : STD_LOGIC;
184 185 SIGNAL SM_correlation_auto : STD_LOGIC;
185 186 SIGNAL SM_correlation_done : STD_LOGIC;
186 187 SIGNAL SM_correlation_done_reg1 : STD_LOGIC;
187 188 SIGNAL SM_correlation_done_reg2 : STD_LOGIC;
188 189 SIGNAL SM_correlation_done_reg3 : STD_LOGIC;
189 190 SIGNAL SM_correlation_begin : STD_LOGIC;
190 191
191 192 SIGNAL MEM_OUT_SM_Full_s : STD_LOGIC;
192 193 SIGNAL MEM_OUT_SM_Data_in_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
193 194 SIGNAL MEM_OUT_SM_Write_s : STD_LOGIC;
194 195
195 196 SIGNAL current_matrix_write : STD_LOGIC;
196 197 SIGNAL current_matrix_wait_empty : STD_LOGIC;
197 198 -----------------------------------------------------------------------------
198 199 SIGNAL fifo_0_ready : STD_LOGIC;
199 200 SIGNAL fifo_1_ready : STD_LOGIC;
200 201 SIGNAL fifo_ongoing : STD_LOGIC;
201 202
202 203 SIGNAL FSM_DMA_fifo_ren : STD_LOGIC;
203 204 SIGNAL FSM_DMA_fifo_empty : STD_LOGIC;
204 205 SIGNAL FSM_DMA_fifo_empty_threshold : STD_LOGIC;
205 206 SIGNAL FSM_DMA_fifo_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
206 207 SIGNAL FSM_DMA_fifo_status : STD_LOGIC_VECTOR(53 DOWNTO 4);
207 208 -----------------------------------------------------------------------------
208 209 SIGNAL MEM_OUT_SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0);
209 210 SIGNAL MEM_OUT_SM_Read : STD_LOGIC_VECTOR(1 DOWNTO 0);
210 211 SIGNAL MEM_OUT_SM_Data_in : STD_LOGIC_VECTOR(63 DOWNTO 0);
211 212 SIGNAL MEM_OUT_SM_Data_out : STD_LOGIC_VECTOR(63 DOWNTO 0);
212 213 SIGNAL MEM_OUT_SM_Full : STD_LOGIC_VECTOR(1 DOWNTO 0);
213 214 SIGNAL MEM_OUT_SM_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
214 215 SIGNAL MEM_OUT_SM_Empty_Threshold : STD_LOGIC_VECTOR(1 DOWNTO 0);
215 216
216 217 -----------------------------------------------------------------------------
217 218 -- TIME REG & INFOs
218 219 -----------------------------------------------------------------------------
219 220 SIGNAL all_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
220 221
221 222 SIGNAL f_empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
222 223 SIGNAL f_empty_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
223 224 SIGNAL time_update_f : STD_LOGIC_VECTOR(3 DOWNTO 0);
224 225 SIGNAL time_reg_f : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
225 226
226 227 SIGNAL time_reg_f0_A : STD_LOGIC_VECTOR(47 DOWNTO 0);
227 228 SIGNAL time_reg_f0_B : STD_LOGIC_VECTOR(47 DOWNTO 0);
228 229 SIGNAL time_reg_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
229 230 SIGNAL time_reg_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
230 231
231 232 --SIGNAL time_update_f0_A : STD_LOGIC;
232 233 --SIGNAL time_update_f0_B : STD_LOGIC;
233 234 --SIGNAL time_update_f1 : STD_LOGIC;
234 235 --SIGNAL time_update_f2 : STD_LOGIC;
235 236 --
236 237 SIGNAL status_channel : STD_LOGIC_VECTOR(49 DOWNTO 0);
237 238 SIGNAL status_MS_input : STD_LOGIC_VECTOR(49 DOWNTO 0);
238 239 SIGNAL status_component : STD_LOGIC_VECTOR(53 DOWNTO 0);
239 240
240 241 SIGNAL status_component_fifo_0 : STD_LOGIC_VECTOR(53 DOWNTO 4);
241 242 SIGNAL status_component_fifo_1 : STD_LOGIC_VECTOR(53 DOWNTO 4);
242 243 SIGNAL status_component_fifo_0_end : STD_LOGIC;
243 244 SIGNAL status_component_fifo_1_end : STD_LOGIC;
244 245 -----------------------------------------------------------------------------
245 246 SIGNAL fft_ongoing_counter : STD_LOGIC;--_VECTOR(1 DOWNTO 0);
246 247
247 248 SIGNAL fft_ready_reg : STD_LOGIC;
248 249 SIGNAL fft_ready_rising_down : STD_LOGIC;
249 250
250 251 SIGNAL sample_load_reg : STD_LOGIC;
251 252 SIGNAL sample_load_rising_down : STD_LOGIC;
252 253
253 254 -----------------------------------------------------------------------------
254 255 SIGNAL sample_f1_wen_head : STD_LOGIC_VECTOR(4 DOWNTO 0);
255 256 SIGNAL sample_f1_wen_head_in : STD_LOGIC;
256 257 SIGNAL sample_f1_wen_head_out : STD_LOGIC;
257 258 SIGNAL sample_f1_full_head_in : STD_LOGIC;
258 259 SIGNAL sample_f1_full_head_out : STD_LOGIC;
259 260 SIGNAL sample_f1_empty_head_in : STD_LOGIC;
260 261
261 262 SIGNAL sample_f1_wdata_head : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
262 263 -----------------------------------------------------------------------------
263 264 SIGNAL sample_f0_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
264 265 SIGNAL sample_f1_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
265 266 SIGNAL sample_f2_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
266 267 SIGNAL ongoing : STD_LOGIC;
267 268
268 269 BEGIN
269 270
270 271 PROCESS (clk, rstn)
271 272 BEGIN -- PROCESS
272 273 IF rstn = '0' THEN -- asynchronous reset (active low)
273 274 sample_f0_wen_s <= (OTHERS => '1');
274 275 sample_f1_wen_s <= (OTHERS => '1');
275 276 sample_f2_wen_s <= (OTHERS => '1');
276 277 ongoing <= '0';
277 278 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
278 279 IF ongoing = '1' THEN
279 280 sample_f0_wen_s <= sample_f0_wen;
280 281 sample_f1_wen_s <= sample_f1_wen;
281 282 sample_f2_wen_s <= sample_f2_wen;
282 283 ELSE
283 284 IF start_date = coarse_time(30 DOWNTO 0) THEN
284 285 ongoing <= '1';
285 286 END IF;
286 287 sample_f0_wen_s <= (OTHERS => '1');
287 288 sample_f1_wen_s <= (OTHERS => '1');
288 289 sample_f2_wen_s <= (OTHERS => '1');
289 290 END IF;
290 291 END IF;
291 292 END PROCESS;
292 293
293 294
294 295 error_input_fifo_write <= error_wen_f2 & error_wen_f1 & error_wen_f0;
295 296
296 297
297 298 switch_f0_inst : spectral_matrix_switch_f0
298 299 PORT MAP (
299 300 clk => clk,
300 301 rstn => rstn,
301 302
302 303 sample_wen => sample_f0_wen_s,
303 304
304 305 fifo_A_empty => sample_f0_A_empty,
305 306 fifo_A_full => sample_f0_A_full,
306 307 fifo_A_wen => sample_f0_A_wen,
307 308
308 309 fifo_B_empty => sample_f0_B_empty,
309 310 fifo_B_full => sample_f0_B_full,
310 311 fifo_B_wen => sample_f0_B_wen,
311 312
312 313 error_wen => error_wen_f0); -- TODO
313 314
314 315 -----------------------------------------------------------------------------
315 316 -- FIFO IN
316 317 -----------------------------------------------------------------------------
317 318 lppFIFOxN_f0_a : lppFIFOxN
318 319 GENERIC MAP (
319 320 tech => 0,
320 321 Mem_use => Mem_use,
321 322 Data_sz => 16,
322 323 Addr_sz => 8,
323 324 FifoCnt => 5)
324 325 PORT MAP (
325 326 clk => clk,
326 327 rstn => rstn,
327 328
328 329 ReUse => (OTHERS => '0'),
329 330
330 331 run => (OTHERS => '1'),
331 332
332 333 wen => sample_f0_A_wen,
333 334 wdata => sample_f0_wdata,
334 335
335 336 ren => sample_f0_A_ren,
336 337 rdata => sample_f0_A_rdata,
337 338
338 339 empty => sample_f0_A_empty,
339 340 full => sample_f0_A_full,
340 341 almost_full => OPEN);
341 342
342 343 lppFIFOxN_f0_b : lppFIFOxN
343 344 GENERIC MAP (
344 345 tech => 0,
345 346 Mem_use => Mem_use,
346 347 Data_sz => 16,
347 348 Addr_sz => 8,
348 349 FifoCnt => 5)
349 350 PORT MAP (
350 351 clk => clk,
351 352 rstn => rstn,
352 353
353 354 ReUse => (OTHERS => '0'),
354 355 run => (OTHERS => '1'),
355 356
356 357 wen => sample_f0_B_wen,
357 358 wdata => sample_f0_wdata,
358 359 ren => sample_f0_B_ren,
359 360 rdata => sample_f0_B_rdata,
360 361 empty => sample_f0_B_empty,
361 362 full => sample_f0_B_full,
362 363 almost_full => OPEN);
363 364
364 365 -----------------------------------------------------------------------------
365 366 -- sample_f1_wen in
366 367 -- sample_f1_wdata in
367 368 -- sample_f1_full OUT
368 369
369 370 sample_f1_wen_head_in <= '0' WHEN sample_f1_wen_s = "00000" ELSE '1';
370 371 sample_f1_full_head_in <= '0' WHEN sample_f1_full = "00000" ELSE '1';
371 372 sample_f1_empty_head_in <= '1' WHEN sample_f1_empty = "11111" ELSE '0';
372 373
373 374 lpp_lfr_ms_reg_head_1:lpp_lfr_ms_reg_head
374 375 PORT MAP (
375 376 clk => clk,
376 377 rstn => rstn,
377 378 in_wen => sample_f1_wen_head_in,
378 379 in_data => sample_f1_wdata,
379 380 in_full => sample_f1_full_head_in,
380 381 in_empty => sample_f1_empty_head_in,
381 382 out_wen => sample_f1_wen_head_out,
382 383 out_data => sample_f1_wdata_head,
383 384 out_full => sample_f1_full_head_out);
384 385
385 386 sample_f1_wen_head <= sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out;
386 387
387 388
388 389 lppFIFOxN_f1 : lppFIFOxN
389 390 GENERIC MAP (
390 391 tech => 0,
391 392 Mem_use => Mem_use,
392 393 Data_sz => 16,
393 394 Addr_sz => 8,
394 395 FifoCnt => 5)
395 396 PORT MAP (
396 397 clk => clk,
397 398 rstn => rstn,
398 399
399 400 ReUse => (OTHERS => '0'),
400 401 run => (OTHERS => '1'),
401 402
402 403 wen => sample_f1_wen_head,
403 404 wdata => sample_f1_wdata_head,
404 405 ren => sample_f1_ren,
405 406 rdata => sample_f1_rdata,
406 407 empty => sample_f1_empty,
407 408 full => sample_f1_full,
408 409 almost_full => sample_f1_almost_full);
409 410
410 411
411 412 one_sample_f1_wen <= '0' WHEN sample_f1_wen_s = "11111" ELSE '1';
412 413
413 414 PROCESS (clk, rstn)
414 415 BEGIN -- PROCESS
415 416 IF rstn = '0' THEN -- asynchronous reset (active low)
416 417 one_sample_f1_full <= '0';
417 418 error_wen_f1 <= '0';
418 419 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
419 420 IF sample_f1_full_head_out = '0' THEN
420 421 one_sample_f1_full <= '0';
421 422 ELSE
422 423 one_sample_f1_full <= '1';
423 424 END IF;
424 425 error_wen_f1 <= one_sample_f1_wen AND one_sample_f1_full;
425 426 END IF;
426 427 END PROCESS;
427 428
428 429 -----------------------------------------------------------------------------
429 430
430 431
431 432 lppFIFOxN_f2 : lppFIFOxN
432 433 GENERIC MAP (
433 434 tech => 0,
434 435 Mem_use => Mem_use,
435 436 Data_sz => 16,
436 437 Addr_sz => 8,
437 438 FifoCnt => 5)
438 439 PORT MAP (
439 440 clk => clk,
440 441 rstn => rstn,
441 442
442 443 ReUse => (OTHERS => '0'),
443 444 run => (OTHERS => '1'),
444 445
445 wen => sample_f2_wen,
446 wen => sample_f2_wen_s,
446 447 wdata => sample_f2_wdata,
447 448 ren => sample_f2_ren,
448 449 rdata => sample_f2_rdata,
449 450 empty => sample_f2_empty,
450 451 full => sample_f2_full,
451 452 almost_full => OPEN);
452 453
453 454
454 455 one_sample_f2_wen <= '0' WHEN sample_f2_wen_s = "11111" ELSE '1';
455 456
456 457 PROCESS (clk, rstn)
457 458 BEGIN -- PROCESS
458 459 IF rstn = '0' THEN -- asynchronous reset (active low)
459 460 one_sample_f2_full <= '0';
460 461 error_wen_f2 <= '0';
461 462 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
462 463 IF sample_f2_full = "00000" THEN
463 464 one_sample_f2_full <= '0';
464 465 ELSE
465 466 one_sample_f2_full <= '1';
466 467 END IF;
467 468 error_wen_f2 <= one_sample_f2_wen AND one_sample_f2_full;
468 469 END IF;
469 470 END PROCESS;
470 471
471 472 -----------------------------------------------------------------------------
472 473 -- FSM SELECT CHANNEL
473 474 -----------------------------------------------------------------------------
474 475 PROCESS (clk, rstn)
475 476 BEGIN
476 477 IF rstn = '0' THEN
477 478 state_fsm_select_channel <= IDLE;
478 479 select_channel <= (OTHERS => '0');
479 480 ELSIF clk'EVENT AND clk = '1' THEN
480 481 CASE state_fsm_select_channel IS
481 482 WHEN IDLE =>
482 483 IF sample_f1_full = "11111" THEN
483 484 state_fsm_select_channel <= SWITCH_F1;
484 485 select_channel <= "10";
485 486 ELSIF sample_f1_almost_full = "00000" THEN
486 487 IF sample_f0_A_full = "11111" THEN
487 488 state_fsm_select_channel <= SWITCH_F0_A;
488 489 select_channel <= "00";
489 490 ELSIF sample_f0_B_full = "11111" THEN
490 491 state_fsm_select_channel <= SWITCH_F0_B;
491 492 select_channel <= "01";
492 493 ELSIF sample_f2_full = "11111" THEN
493 494 state_fsm_select_channel <= SWITCH_F2;
494 495 select_channel <= "11";
495 496 END IF;
496 497 END IF;
497 498
498 499 WHEN SWITCH_F0_A =>
499 500 IF sample_f0_A_empty = "11111" THEN
500 501 state_fsm_select_channel <= IDLE;
501 502 select_channel <= (OTHERS => '0');
502 503 END IF;
503 504 WHEN SWITCH_F0_B =>
504 505 IF sample_f0_B_empty = "11111" THEN
505 506 state_fsm_select_channel <= IDLE;
506 507 select_channel <= (OTHERS => '0');
507 508 END IF;
508 509 WHEN SWITCH_F1 =>
509 510 IF sample_f1_empty = "11111" THEN
510 511 state_fsm_select_channel <= IDLE;
511 512 select_channel <= (OTHERS => '0');
512 513 END IF;
513 514 WHEN SWITCH_F2 =>
514 515 IF sample_f2_empty = "11111" THEN
515 516 state_fsm_select_channel <= IDLE;
516 517 select_channel <= (OTHERS => '0');
517 518 END IF;
518 519 WHEN OTHERS => NULL;
519 520 END CASE;
520 521
521 522 END IF;
522 523 END PROCESS;
523 524
524 525 PROCESS (clk, rstn)
525 526 BEGIN
526 527 IF rstn = '0' THEN
527 528 select_channel_reg <= (OTHERS => '0');
528 529 --pre_state_fsm_select_channel <= IDLE;
529 530 ELSIF clk'EVENT AND clk = '1' THEN
530 531 select_channel_reg <= select_channel;
531 532 --pre_state_fsm_select_channel <= state_fsm_select_channel;
532 533 END IF;
533 534 END PROCESS;
534 535
535 536
536 537 -----------------------------------------------------------------------------
537 538 -- SWITCH SELECT CHANNEL
538 539 -----------------------------------------------------------------------------
539 540 sample_empty <= sample_f0_A_empty WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
540 541 sample_f0_B_empty WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
541 542 sample_f1_empty WHEN state_fsm_select_channel = SWITCH_F1 ELSE
542 543 sample_f2_empty WHEN state_fsm_select_channel = SWITCH_F2 ELSE
543 544 (OTHERS => '1');
544 545
545 546 sample_full <= sample_f0_A_full WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
546 547 sample_f0_B_full WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
547 548 sample_f1_full WHEN state_fsm_select_channel = SWITCH_F1 ELSE
548 549 sample_f2_full WHEN state_fsm_select_channel = SWITCH_F2 ELSE
549 550 (OTHERS => '0');
550 551
551 552 --sample_rdata <= sample_f0_A_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_A ELSE
552 553 -- sample_f0_B_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_B ELSE
553 554 -- sample_f1_rdata WHEN pre_state_fsm_select_channel = SWITCH_F1 ELSE
554 555 -- sample_f2_rdata; -- WHEN state_fsm_select_channel = SWITCH_F2 ELSE
555 556 sample_rdata <= sample_f0_A_rdata WHEN select_channel_reg = "00" ELSE
556 557 sample_f0_B_rdata WHEN select_channel_reg = "01" ELSE
557 558 sample_f1_rdata WHEN select_channel_reg = "10" ELSE
558 559 sample_f2_rdata; -- WHEN state_fsm_select_channel = SWITCH_F2 ELSE
559 560
560 561
561 562 sample_f0_A_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_A ELSE (OTHERS => '1');
562 563 sample_f0_B_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_B ELSE (OTHERS => '1');
563 564 sample_f1_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F1 ELSE (OTHERS => '1');
564 565 sample_f2_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F2 ELSE (OTHERS => '1');
565 566
566 567
567 568 status_channel <= time_reg_f0_A & "00" WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
568 569 time_reg_f0_B & "00" WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
569 570 time_reg_f1 & "01" WHEN state_fsm_select_channel = SWITCH_F1 ELSE
570 571 time_reg_f2 & "10"; -- WHEN state_fsm_select_channel = SWITCH_F2
571 572
572 573 -----------------------------------------------------------------------------
573 574 -- FSM LOAD FFT
574 575 -----------------------------------------------------------------------------
575 576
576 577 sample_ren <= (OTHERS => '1') WHEN fft_ongoing_counter = '1' ELSE
577 578 sample_ren_s WHEN sample_load = '1' ELSE
578 579 (OTHERS => '1');
579 580
580 581 PROCESS (clk, rstn)
581 582 BEGIN
582 583 IF rstn = '0' THEN
583 584 sample_ren_s <= (OTHERS => '1');
584 585 state_fsm_load_FFT <= IDLE;
585 586 status_MS_input <= (OTHERS => '0');
586 587 select_fifo <= "000";
587 588 --next_state_fsm_load_FFT <= IDLE;
588 589 --sample_valid <= '0';
589 590 ELSIF clk'EVENT AND clk = '1' THEN
590 591 CASE state_fsm_load_FFT IS
591 592 WHEN IDLE =>
592 593 --sample_valid <= '0';
593 594 sample_ren_s <= (OTHERS => '1');
594 595 IF sample_full = "11111" AND sample_load = '1' THEN
595 596 state_fsm_load_FFT <= FIFO_1;
596 597 status_MS_input <= status_channel;
597 598 select_fifo <= "000";
598 599 END IF;
599 600
600 601 WHEN FIFO_1 =>
601 602 sample_ren_s <= "1111" & NOT(sample_load);
602 603 IF sample_empty(0) = '1' THEN
603 604 sample_ren_s <= (OTHERS => '1');
604 605 state_fsm_load_FFT <= FIFO_2;
605 606 select_fifo <= "001";
606 607 END IF;
607 608
608 609 WHEN FIFO_2 =>
609 610 sample_ren_s <= "111" & NOT(sample_load) & '1';
610 611 IF sample_empty(1) = '1' THEN
611 612 sample_ren_s <= (OTHERS => '1');
612 613 state_fsm_load_FFT <= FIFO_3;
613 614 select_fifo <= "010";
614 615 END IF;
615 616
616 617 WHEN FIFO_3 =>
617 618 sample_ren_s <= "11" & NOT(sample_load) & "11";
618 619 IF sample_empty(2) = '1' THEN
619 620 sample_ren_s <= (OTHERS => '1');
620 621 state_fsm_load_FFT <= FIFO_4;
621 622 select_fifo <= "011";
622 623 END IF;
623 624
624 625 WHEN FIFO_4 =>
625 626 sample_ren_s <= '1' & NOT(sample_load) & "111";
626 627 IF sample_empty(3) = '1' THEN
627 628 sample_ren_s <= (OTHERS => '1');
628 629 state_fsm_load_FFT <= FIFO_5;
629 630 select_fifo <= "100";
630 631 END IF;
631 632
632 633 WHEN FIFO_5 =>
633 634 sample_ren_s <= NOT(sample_load) & "1111";
634 635 IF sample_empty(4) = '1' THEN
635 636 sample_ren_s <= (OTHERS => '1');
636 637 state_fsm_load_FFT <= IDLE;
637 638 select_fifo <= "000";
638 639 END IF;
639 640 WHEN OTHERS => NULL;
640 641 END CASE;
641 642 END IF;
642 643 END PROCESS;
643 644
644 645 PROCESS (clk, rstn)
645 646 BEGIN
646 647 IF rstn = '0' THEN
647 648 sample_valid_r <= '0';
648 649 select_fifo_reg <= (OTHERS => '0');
649 650 --next_state_fsm_load_FFT <= IDLE;
650 651 ELSIF clk'EVENT AND clk = '1' THEN
651 652 select_fifo_reg <= select_fifo;
652 653 --next_state_fsm_load_FFT <= state_fsm_load_FFT;
653 654 IF sample_ren_s = "11111" THEN
654 655 sample_valid_r <= '0';
655 656 ELSE
656 657 sample_valid_r <= '1';
657 658 END IF;
658 659 END IF;
659 660 END PROCESS;
660 661
661 662 sample_valid <= '0' WHEN fft_ongoing_counter = '1' ELSE sample_valid_r AND sample_load;
662 663
663 664 --sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN next_state_fsm_load_FFT = FIFO_1 ELSE
664 665 -- sample_rdata(16*2-1 DOWNTO 16*1) WHEN next_state_fsm_load_FFT = FIFO_2 ELSE
665 666 -- sample_rdata(16*3-1 DOWNTO 16*2) WHEN next_state_fsm_load_FFT = FIFO_3 ELSE
666 667 -- sample_rdata(16*4-1 DOWNTO 16*3) WHEN next_state_fsm_load_FFT = FIFO_4 ELSE
667 668 -- sample_rdata(16*5-1 DOWNTO 16*4); --WHEN next_state_fsm_load_FFT = FIFO_5 ELSE
668 669 sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN select_fifo_reg = "000" ELSE
669 670 sample_rdata(16*2-1 DOWNTO 16*1) WHEN select_fifo_reg = "001" ELSE
670 671 sample_rdata(16*3-1 DOWNTO 16*2) WHEN select_fifo_reg = "010" ELSE
671 672 sample_rdata(16*4-1 DOWNTO 16*3) WHEN select_fifo_reg = "011" ELSE
672 673 sample_rdata(16*5-1 DOWNTO 16*4); --WHEN next_state_fsm_load_FFT = FIFO_5 ELSE
673 674
674 675 -----------------------------------------------------------------------------
675 676 -- FFT
676 677 -----------------------------------------------------------------------------
677 678 lpp_lfr_ms_FFT_1 : lpp_lfr_ms_FFT
678 679 PORT MAP (
679 680 clk => clk,
680 681 rstn => rstn,
681 682 sample_valid => sample_valid,
682 683 fft_read => fft_read,
683 684 sample_data => sample_data,
684 685 sample_load => sample_load,
685 686 fft_pong => fft_pong,
686 687 fft_data_im => fft_data_im,
687 688 fft_data_re => fft_data_re,
688 689 fft_data_valid => fft_data_valid,
689 690 fft_ready => fft_ready);
691
692 debug_vector(0) <= fft_data_valid;
693 debug_vector(1) <= fft_ready;
694 debug_vector(11 DOWNTO 2) <= (OTHERS => '0');
690 695
696
691 697 -----------------------------------------------------------------------------
692 698 fft_ready_rising_down <= fft_ready_reg AND NOT fft_ready;
693 699 sample_load_rising_down <= sample_load_reg AND NOT sample_load;
694 700
695 701 PROCESS (clk, rstn)
696 702 BEGIN
697 703 IF rstn = '0' THEN
698 704 fft_ready_reg <= '0';
699 705 sample_load_reg <= '0';
700 706
701 707 fft_ongoing_counter <= '0';
702 708 ELSIF clk'event AND clk = '1' THEN
703 709 fft_ready_reg <= fft_ready;
704 710 sample_load_reg <= sample_load;
705 711
706 712 IF fft_ready_rising_down = '1' AND sample_load_rising_down = '0' THEN
707 713 fft_ongoing_counter <= '0';
708 714
709 715 -- CASE fft_ongoing_counter IS
710 716 -- WHEN "01" => fft_ongoing_counter <= "00";
711 717 ---- WHEN "10" => fft_ongoing_counter <= "01";
712 718 -- WHEN OTHERS => NULL;
713 719 -- END CASE;
714 720 ELSIF fft_ready_rising_down = '0' AND sample_load_rising_down = '1' THEN
715 721 fft_ongoing_counter <= '1';
716 722 -- CASE fft_ongoing_counter IS
717 723 -- WHEN "00" => fft_ongoing_counter <= "01";
718 724 ---- WHEN "01" => fft_ongoing_counter <= "10";
719 725 -- WHEN OTHERS => NULL;
720 726 -- END CASE;
721 727 END IF;
722 728
723 729 END IF;
724 730 END PROCESS;
725 731
726 732 -----------------------------------------------------------------------------
727 733 PROCESS (clk, rstn)
728 734 BEGIN
729 735 IF rstn = '0' THEN
730 736 state_fsm_load_MS_memory <= IDLE;
731 737 current_fifo_load <= "00001";
732 738 ELSIF clk'EVENT AND clk = '1' THEN
733 739 CASE state_fsm_load_MS_memory IS
734 740 WHEN IDLE =>
735 741 IF current_fifo_empty = '1' AND fft_ready = '1' AND current_fifo_locked = '0' THEN
736 742 state_fsm_load_MS_memory <= LOAD_FIFO;
737 743 END IF;
738 744 WHEN LOAD_FIFO =>
739 745 IF current_fifo_full = '1' THEN
740 746 state_fsm_load_MS_memory <= TRASH_FFT;
741 747 END IF;
742 748 WHEN TRASH_FFT =>
743 749 IF fft_ready = '0' THEN
744 750 state_fsm_load_MS_memory <= IDLE;
745 751 current_fifo_load <= current_fifo_load(3 DOWNTO 0) & current_fifo_load(4);
746 752 END IF;
747 753 WHEN OTHERS => NULL;
748 754 END CASE;
749 755
750 756 END IF;
751 757 END PROCESS;
752 758
753 759 current_fifo_empty <= MEM_IN_SM_Empty(0) WHEN current_fifo_load(0) = '1' ELSE
754 760 MEM_IN_SM_Empty(1) WHEN current_fifo_load(1) = '1' ELSE
755 761 MEM_IN_SM_Empty(2) WHEN current_fifo_load(2) = '1' ELSE
756 762 MEM_IN_SM_Empty(3) WHEN current_fifo_load(3) = '1' ELSE
757 763 MEM_IN_SM_Empty(4); -- WHEN current_fifo_load(3) = '1' ELSE
758 764
759 765 current_fifo_full <= MEM_IN_SM_Full(0) WHEN current_fifo_load(0) = '1' ELSE
760 766 MEM_IN_SM_Full(1) WHEN current_fifo_load(1) = '1' ELSE
761 767 MEM_IN_SM_Full(2) WHEN current_fifo_load(2) = '1' ELSE
762 768 MEM_IN_SM_Full(3) WHEN current_fifo_load(3) = '1' ELSE
763 769 MEM_IN_SM_Full(4); -- WHEN current_fifo_load(3) = '1' ELSE
764 770
765 771 current_fifo_locked <= MEM_IN_SM_locked(0) WHEN current_fifo_load(0) = '1' ELSE
766 772 MEM_IN_SM_locked(1) WHEN current_fifo_load(1) = '1' ELSE
767 773 MEM_IN_SM_locked(2) WHEN current_fifo_load(2) = '1' ELSE
768 774 MEM_IN_SM_locked(3) WHEN current_fifo_load(3) = '1' ELSE
769 775 MEM_IN_SM_locked(4); -- WHEN current_fifo_load(3) = '1' ELSE
770 776
771 777 fft_read <= '0' WHEN state_fsm_load_MS_memory = IDLE ELSE '1';
772 778
773 779 all_fifo : FOR I IN 4 DOWNTO 0 GENERATE
774 780 MEM_IN_SM_wen_s(I) <= '0' WHEN fft_data_valid = '1'
775 781 AND state_fsm_load_MS_memory = LOAD_FIFO
776 782 AND current_fifo_load(I) = '1'
777 783 ELSE '1';
778 784 END GENERATE all_fifo;
779 785
780 786 PROCESS (clk, rstn)
781 787 BEGIN
782 788 IF rstn = '0' THEN
783 789 MEM_IN_SM_wen <= (OTHERS => '1');
784 790 ELSIF clk'EVENT AND clk = '1' THEN
785 791 MEM_IN_SM_wen <= MEM_IN_SM_wen_s;
786 792 END IF;
787 793 END PROCESS;
788 794
789 795 MEM_IN_SM_wData <= (fft_data_im & fft_data_re) &
790 796 (fft_data_im & fft_data_re) &
791 797 (fft_data_im & fft_data_re) &
792 798 (fft_data_im & fft_data_re) &
793 799 (fft_data_im & fft_data_re);
794 800 -----------------------------------------------------------------------------
795 801
796 802
797 803 -----------------------------------------------------------------------------
798 804 Mem_In_SpectralMatrix : lppFIFOxN
799 805 GENERIC MAP (
800 806 tech => 0,
801 807 Mem_use => Mem_use,
802 808 Data_sz => 32, --16,
803 809 Addr_sz => 7, --8
804 810 FifoCnt => 5)
805 811 PORT MAP (
806 812 clk => clk,
807 813 rstn => rstn,
808 814
809 815 ReUse => MEM_IN_SM_ReUse,
810 816 run => (OTHERS => '1'),
811 817
812 818 wen => MEM_IN_SM_wen,
813 819 wdata => MEM_IN_SM_wData,
814 820
815 821 ren => MEM_IN_SM_ren,
816 822 rdata => MEM_IN_SM_rData,
817 823 full => MEM_IN_SM_Full,
818 824 empty => MEM_IN_SM_Empty,
819 825 almost_full => OPEN);
820 826
821 827
822 828 -----------------------------------------------------------------------------
823 829 MS_control_1 : MS_control
824 830 PORT MAP (
825 831 clk => clk,
826 832 rstn => rstn,
827 833
828 834 current_status_ms => status_MS_input,
829 835
830 836 fifo_in_lock => MEM_IN_SM_locked,
831 837 fifo_in_data => MEM_IN_SM_rdata,
832 838 fifo_in_full => MEM_IN_SM_Full,
833 839 fifo_in_empty => MEM_IN_SM_Empty,
834 840 fifo_in_ren => MEM_IN_SM_ren,
835 841 fifo_in_reuse => MEM_IN_SM_ReUse,
836 842
837 843 fifo_out_data => SM_in_data,
838 844 fifo_out_ren => SM_in_ren,
839 845 fifo_out_empty => SM_in_empty,
840 846
841 847 current_status_component => status_component,
842 848
843 849 correlation_start => SM_correlation_start,
844 850 correlation_auto => SM_correlation_auto,
845 851 correlation_done => SM_correlation_done);
846 852
847 853
848 854 MS_calculation_1 : MS_calculation
849 855 PORT MAP (
850 856 clk => clk,
851 857 rstn => rstn,
852 858
853 859 fifo_in_data => SM_in_data,
854 860 fifo_in_ren => SM_in_ren,
855 861 fifo_in_empty => SM_in_empty,
856 862
857 863 fifo_out_data => MEM_OUT_SM_Data_in_s, -- TODO
858 864 fifo_out_wen => MEM_OUT_SM_Write_s, -- TODO
859 865 fifo_out_full => MEM_OUT_SM_Full_s, -- TODO
860 866
861 867 correlation_start => SM_correlation_start,
862 868 correlation_auto => SM_correlation_auto,
863 869 correlation_begin => SM_correlation_begin,
864 870 correlation_done => SM_correlation_done);
865 871
866 872 -----------------------------------------------------------------------------
867 873 PROCESS (clk, rstn)
868 874 BEGIN -- PROCESS
869 875 IF rstn = '0' THEN -- asynchronous reset (active low)
870 876 current_matrix_write <= '0';
871 877 current_matrix_wait_empty <= '1';
872 878 status_component_fifo_0 <= (OTHERS => '0');
873 879 status_component_fifo_1 <= (OTHERS => '0');
874 880 status_component_fifo_0_end <= '0';
875 881 status_component_fifo_1_end <= '0';
876 882 SM_correlation_done_reg1 <= '0';
877 883 SM_correlation_done_reg2 <= '0';
878 884 SM_correlation_done_reg3 <= '0';
879 885
880 886 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
881 887 SM_correlation_done_reg1 <= SM_correlation_done;
882 888 SM_correlation_done_reg2 <= SM_correlation_done_reg1;
883 889 SM_correlation_done_reg3 <= SM_correlation_done_reg2;
884 890 status_component_fifo_0_end <= '0';
885 891 status_component_fifo_1_end <= '0';
886 892 IF SM_correlation_begin = '1' THEN
887 893 IF current_matrix_write = '0' THEN
888 894 status_component_fifo_0 <= status_component(53 DOWNTO 4);
889 895 ELSE
890 896 status_component_fifo_1 <= status_component(53 DOWNTO 4);
891 897 END IF;
892 898 END IF;
893 899
894 900 IF SM_correlation_done_reg3 = '1' THEN
895 901 IF current_matrix_write = '0' THEN
896 902 status_component_fifo_0_end <= '1';
897 903 ELSE
898 904 status_component_fifo_1_end <= '1';
899 905 END IF;
900 906 current_matrix_wait_empty <= '1';
901 907 current_matrix_write <= NOT current_matrix_write;
902 908 END IF;
903 909
904 910 IF current_matrix_wait_empty <= '1' THEN
905 911 IF current_matrix_write = '0' THEN
906 912 current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(0);
907 913 ELSE
908 914 current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(1);
909 915 END IF;
910 916 END IF;
911 917
912 918 END IF;
913 919 END PROCESS;
914 920
915 921 MEM_OUT_SM_Full_s <= '1' WHEN SM_correlation_done = '1' ELSE
916 922 '1' WHEN SM_correlation_done_reg1 = '1' ELSE
917 923 '1' WHEN SM_correlation_done_reg2 = '1' ELSE
918 924 '1' WHEN SM_correlation_done_reg3 = '1' ELSE
919 925 '1' WHEN current_matrix_wait_empty = '1' ELSE
920 926 MEM_OUT_SM_Full(0) WHEN current_matrix_write = '0' ELSE
921 927 MEM_OUT_SM_Full(1);
922 928
923 929 MEM_OUT_SM_Write(0) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '0' ELSE '1';
924 930 MEM_OUT_SM_Write(1) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '1' ELSE '1';
925 931
926 932 MEM_OUT_SM_Data_in <= MEM_OUT_SM_Data_in_s & MEM_OUT_SM_Data_in_s;
927 933 -----------------------------------------------------------------------------
928 934
929 935 --Mem_Out_SpectralMatrix : lppFIFOxN
930 936 -- GENERIC MAP (
931 937 -- tech => 0,
932 938 -- Mem_use => Mem_use,
933 939 -- Data_sz => 32,
934 940 -- Addr_sz => 8,
935 941 -- FifoCnt => 2)
936 942 -- PORT MAP (
937 943 -- clk => clk,
938 944 -- rstn => rstn,
939 945
940 946 -- ReUse => (OTHERS => '0'),
941 947 -- run => (OTHERS => '1'),
942 948
943 949 -- wen => MEM_OUT_SM_Write,
944 950 -- wdata => MEM_OUT_SM_Data_in,
945 951
946 952 -- ren => MEM_OUT_SM_Read,
947 953 -- rdata => MEM_OUT_SM_Data_out,
948 954
949 955 -- full => MEM_OUT_SM_Full,
950 956 -- empty => MEM_OUT_SM_Empty,
951 957 -- almost_full => OPEN);
952 958
953 959
954 960 all_Mem_Out_SpectralMatrix: FOR I IN 1 DOWNTO 0 GENERATE
955 961 Mem_Out_SpectralMatrix_I: lpp_fifo
956 962 GENERIC MAP (
957 963 tech => 0,
958 964 Mem_use => Mem_use,
959 965 EMPTY_THRESHOLD_LIMIT => 15,
960 966 FULL_THRESHOLD_LIMIT => 1,
961 967 DataSz => 32,
962 968 AddrSz => 8)
963 969 PORT MAP (
964 970 clk => clk,
965 971 rstn => rstn,
966 972 reUse => '0',
967 973 run => run,
968 974
969 975 ren => MEM_OUT_SM_Read(I),
970 976 rdata => MEM_OUT_SM_Data_out(32*(I+1)-1 DOWNTO 32*i),
971 977
972 978 wen => MEM_OUT_SM_Write(I),
973 979 wdata => MEM_OUT_SM_Data_in(32*(I+1)-1 DOWNTO 32*i),
974 980
975 981 empty => MEM_OUT_SM_Empty(I),
976 982 full => MEM_OUT_SM_Full(I),
977 983 full_almost => OPEN,
978 984 empty_threshold => MEM_OUT_SM_Empty_Threshold(I),
979 985
980 986 full_threshold => OPEN);
981 987
982 988 END GENERATE all_Mem_Out_SpectralMatrix;
983 989
984 990 -----------------------------------------------------------------------------
985 991 -- MEM_OUT_SM_Read <= "00";
986 992 PROCESS (clk, rstn)
987 993 BEGIN
988 994 IF rstn = '0' THEN
989 995 fifo_0_ready <= '0';
990 996 fifo_1_ready <= '0';
991 997 fifo_ongoing <= '0';
992 998 ELSIF clk'EVENT AND clk = '1' THEN
993 999 IF fifo_0_ready = '1' AND MEM_OUT_SM_Empty(0) = '1' THEN
994 1000 fifo_ongoing <= '1';
995 1001 fifo_0_ready <= '0';
996 1002 ELSIF status_component_fifo_0_end = '1' THEN
997 1003 fifo_0_ready <= '1';
998 1004 END IF;
999 1005
1000 1006 IF fifo_1_ready = '1' AND MEM_OUT_SM_Empty(1) = '1' THEN
1001 1007 fifo_ongoing <= '0';
1002 1008 fifo_1_ready <= '0';
1003 1009 ELSIF status_component_fifo_1_end = '1' THEN
1004 1010 fifo_1_ready <= '1';
1005 1011 END IF;
1006 1012
1007 1013 END IF;
1008 1014 END PROCESS;
1009 1015
1010 1016 MEM_OUT_SM_Read(0) <= '1' WHEN fifo_ongoing = '1' ELSE
1011 1017 '1' WHEN fifo_0_ready = '0' ELSE
1012 1018 FSM_DMA_fifo_ren;
1013 1019
1014 1020 MEM_OUT_SM_Read(1) <= '1' WHEN fifo_ongoing = '0' ELSE
1015 1021 '1' WHEN fifo_1_ready = '0' ELSE
1016 1022 FSM_DMA_fifo_ren;
1017 1023
1018 1024 FSM_DMA_fifo_empty <= MEM_OUT_SM_Empty(0) WHEN fifo_ongoing = '0' AND fifo_0_ready = '1' ELSE
1019 1025 MEM_OUT_SM_Empty(1) WHEN fifo_ongoing = '1' AND fifo_1_ready = '1' ELSE
1020 1026 '1';
1021 1027
1022 1028 FSM_DMA_fifo_status <= status_component_fifo_0 WHEN fifo_ongoing = '0' ELSE
1023 1029 status_component_fifo_1;
1024 1030
1025 1031 FSM_DMA_fifo_data <= MEM_OUT_SM_Data_out(31 DOWNTO 0) WHEN fifo_ongoing = '0' ELSE
1026 1032 MEM_OUT_SM_Data_out(63 DOWNTO 32);
1027 1033
1028 1034
1029 1035 FSM_DMA_fifo_empty_threshold <= MEM_OUT_SM_Empty_Threshold(0) WHEN fifo_ongoing = '0' AND fifo_0_ready = '1' ELSE
1030 1036 MEM_OUT_SM_Empty_Threshold(1) WHEN fifo_ongoing = '1' AND fifo_1_ready = '1' ELSE
1031 1037 '1';
1032 1038
1033 1039 -----------------------------------------------------------------------------
1034 1040 -- fifo_matrix_type => FSM_DMA_fifo_status(5 DOWNTO 4), --IN
1035 1041 -- fifo_matrix_component => FSM_DMA_fifo_status(3 DOWNTO 0), --IN
1036 1042 -- fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6), --IN
1037 1043 -- fifo_data => FSM_DMA_fifo_data, --IN
1038 1044 -- fifo_empty => FSM_DMA_fifo_empty, --IN
1039 1045 -- fifo_empty_threshold => FSM_DMA_fifo_empty_threshold, --IN
1040 1046 -- fifo_ren => FSM_DMA_fifo_ren, --OUT
1041 1047
1042 1048
1043 1049 lpp_lfr_ms_fsmdma_1: lpp_lfr_ms_fsmdma
1044 1050 PORT MAP (
1045 1051 clk => clk,
1046 1052 rstn => rstn,
1047 1053 run => run,
1048 1054
1049 1055 fifo_matrix_type => FSM_DMA_fifo_status(5 DOWNTO 4),
1050 1056 fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6),
1051 1057 fifo_data => FSM_DMA_fifo_data,
1052 1058 fifo_empty => FSM_DMA_fifo_empty,
1053 1059 fifo_empty_threshold => FSM_DMA_fifo_empty_threshold,
1054 1060 fifo_ren => FSM_DMA_fifo_ren,
1055 1061
1056 1062 dma_fifo_valid_burst => dma_fifo_burst_valid,
1057 1063 dma_fifo_data => dma_fifo_data,
1058 1064 dma_fifo_ren => dma_fifo_ren,
1059 1065 dma_buffer_new => dma_buffer_new,
1060 1066 dma_buffer_addr => dma_buffer_addr,
1061 1067 dma_buffer_length => dma_buffer_length,
1062 1068 dma_buffer_full => dma_buffer_full,
1063 1069 dma_buffer_full_err => dma_buffer_full_err,
1064 1070
1065 1071 status_ready_matrix_f0 => status_ready_matrix_f0,
1066 1072 status_ready_matrix_f1 => status_ready_matrix_f1,
1067 1073 status_ready_matrix_f2 => status_ready_matrix_f2,
1068 1074 addr_matrix_f0 => addr_matrix_f0,
1069 1075 addr_matrix_f1 => addr_matrix_f1,
1070 1076 addr_matrix_f2 => addr_matrix_f2,
1071 1077 length_matrix_f0 => length_matrix_f0,
1072 1078 length_matrix_f1 => length_matrix_f1,
1073 1079 length_matrix_f2 => length_matrix_f2,
1074 1080 ready_matrix_f0 => ready_matrix_f0,
1075 1081 ready_matrix_f1 => ready_matrix_f1,
1076 1082 ready_matrix_f2 => ready_matrix_f2,
1077 1083 matrix_time_f0 => matrix_time_f0,
1078 1084 matrix_time_f1 => matrix_time_f1,
1079 1085 matrix_time_f2 => matrix_time_f2,
1080 1086 error_buffer_full => error_buffer_full);
1081 1087
1082 1088
1083 1089
1084 1090
1085 1091
1086 1092 --dma_fifo_burst_valid: OUT STD_LOGIC; --TODO
1087 1093 --dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --TODO
1088 1094 --dma_fifo_ren : IN STD_LOGIC; --TODO
1089 1095 --dma_buffer_new : OUT STD_LOGIC; --TODO
1090 1096 --dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --TODO
1091 1097 --dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); --TODO
1092 1098 --dma_buffer_full : IN STD_LOGIC; --TODO
1093 1099 --dma_buffer_full_err : IN STD_LOGIC; --TODO
1094 1100
1095 1101 ---- Reg out
1096 1102 --ready_matrix_f0 : OUT STD_LOGIC; -- TODO
1097 1103 --ready_matrix_f1 : OUT STD_LOGIC; -- TODO
1098 1104 --ready_matrix_f2 : OUT STD_LOGIC; -- TODO
1099 1105 --error_bad_component_error : OUT STD_LOGIC; -- TODO
1100 1106 --error_buffer_full : OUT STD_LOGIC; -- TODO
1101 1107
1102 1108 ---- Reg In
1103 1109 --status_ready_matrix_f0 : IN STD_LOGIC; -- TODO
1104 1110 --status_ready_matrix_f1 : IN STD_LOGIC; -- TODO
1105 1111 --status_ready_matrix_f2 : IN STD_LOGIC; -- TODO
1106 1112
1107 1113 --addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
1108 1114 --addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
1109 1115 --addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
1110 1116
1111 1117 --matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
1112 1118 --matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
1113 1119 --matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) -- TODO
1114 1120 -----------------------------------------------------------------------------
1115 1121
1116 1122 -----------------------------------------------------------------------------
1117 1123 --lpp_lfr_ms_fsmdma_1 : lpp_lfr_ms_fsmdma
1118 1124 -- PORT MAP (
1119 1125 -- HCLK => clk,
1120 1126 -- HRESETn => rstn,
1121 1127
1122 1128 -- fifo_matrix_type => FSM_DMA_fifo_status(5 DOWNTO 4),
1123 1129 -- fifo_matrix_component => FSM_DMA_fifo_status(3 DOWNTO 0),
1124 1130 -- fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6),
1125 1131 -- fifo_data => FSM_DMA_fifo_data,
1126 1132 -- fifo_empty => FSM_DMA_fifo_empty,
1127 1133 -- fifo_ren => FSM_DMA_fifo_ren,
1128 1134
1129 1135 -- dma_addr => dma_addr,
1130 1136 -- dma_data => dma_data,
1131 1137 -- dma_valid => dma_valid,
1132 1138 -- dma_valid_burst => dma_valid_burst,
1133 1139 -- dma_ren => dma_ren,
1134 1140 -- dma_done => dma_done,
1135 1141
1136 1142 -- ready_matrix_f0 => ready_matrix_f0,
1137 1143 -- ready_matrix_f1 => ready_matrix_f1,
1138 1144 -- ready_matrix_f2 => ready_matrix_f2,
1139 1145
1140 1146 -- error_bad_component_error => error_bad_component_error,
1141 1147 -- error_buffer_full => error_buffer_full,
1142 1148
1143 1149 -- debug_reg => debug_reg,
1144 1150 -- status_ready_matrix_f0 => status_ready_matrix_f0,
1145 1151 -- status_ready_matrix_f1 => status_ready_matrix_f1,
1146 1152 -- status_ready_matrix_f2 => status_ready_matrix_f2,
1147 1153
1148 1154 -- config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
1149 1155 -- config_active_interruption_onError => config_active_interruption_onError,
1150 1156
1151 1157 -- addr_matrix_f0 => addr_matrix_f0,
1152 1158 -- addr_matrix_f1 => addr_matrix_f1,
1153 1159 -- addr_matrix_f2 => addr_matrix_f2,
1154 1160
1155 1161 -- matrix_time_f0 => matrix_time_f0,
1156 1162 -- matrix_time_f1 => matrix_time_f1,
1157 1163 -- matrix_time_f2 => matrix_time_f2
1158 1164 -- );
1159 1165 -----------------------------------------------------------------------------
1160 1166
1161 1167
1162 1168
1163 1169
1164 1170
1165 1171
1166 1172 -----------------------------------------------------------------------------
1167 1173 -- TIME MANAGMENT
1168 1174 -----------------------------------------------------------------------------
1169 1175 all_time <= coarse_time & fine_time;
1170 1176 --
1171 1177 f_empty(0) <= '1' WHEN sample_f0_A_empty = "11111" ELSE '0';
1172 1178 f_empty(1) <= '1' WHEN sample_f0_B_empty = "11111" ELSE '0';
1173 1179 f_empty(2) <= '1' WHEN sample_f1_empty = "11111" ELSE '0';
1174 1180 f_empty(3) <= '1' WHEN sample_f2_empty = "11111" ELSE '0';
1175 1181
1176 1182 all_time_reg: FOR I IN 0 TO 3 GENERATE
1177 1183
1178 1184 PROCESS (clk, rstn)
1179 1185 BEGIN
1180 1186 IF rstn = '0' THEN
1181 1187 f_empty_reg(I) <= '1';
1182 1188 ELSIF clk'event AND clk = '1' THEN
1183 1189 f_empty_reg(I) <= f_empty(I);
1184 1190 END IF;
1185 1191 END PROCESS;
1186 1192
1187 1193 time_update_f(I) <= '1' WHEN f_empty(I) = '0' AND f_empty_reg(I) = '1' ELSE '0';
1188 1194
1189 1195 s_m_t_m_f0_A : spectral_matrix_time_managment
1190 1196 PORT MAP (
1191 1197 clk => clk,
1192 1198 rstn => rstn,
1193 1199 time_in => all_time,
1194 1200 update_1 => time_update_f(I),
1195 1201 time_out => time_reg_f((I+1)*48-1 DOWNTO I*48)
1196 1202 );
1197 1203
1198 1204 END GENERATE all_time_reg;
1199 1205
1200 1206 time_reg_f0_A <= time_reg_f((0+1)*48-1 DOWNTO 0*48);
1201 1207 time_reg_f0_B <= time_reg_f((1+1)*48-1 DOWNTO 1*48);
1202 1208 time_reg_f1 <= time_reg_f((2+1)*48-1 DOWNTO 2*48);
1203 1209 time_reg_f2 <= time_reg_f((3+1)*48-1 DOWNTO 3*48);
1204 1210
1205 1211 -----------------------------------------------------------------------------
1206 1212
1207 1213 END Behavioral;
Show file before | Show file after | Hide comments
@@ -1,386 +1,390
1 1 LIBRARY ieee;
2 2 USE ieee.std_logic_1164.ALL;
3 3
4 4 LIBRARY grlib;
5 5 USE grlib.amba.ALL;
6 6
7 7 LIBRARY lpp;
8 8 USE lpp.lpp_ad_conv.ALL;
9 9 USE lpp.iir_filter.ALL;
10 10 USE lpp.FILTERcfg.ALL;
11 11 USE lpp.lpp_memory.ALL;
12 12 LIBRARY techmap;
13 13 USE techmap.gencomp.ALL;
14 14
15 15 PACKAGE lpp_lfr_pkg IS
16 16 -----------------------------------------------------------------------------
17 17 -- TEMP
18 18 -----------------------------------------------------------------------------
19 19 COMPONENT lpp_lfr_ms_test
20 20 GENERIC (
21 21 Mem_use : INTEGER);
22 22 PORT (
23 23 clk : IN STD_LOGIC;
24 24 rstn : IN STD_LOGIC;
25 25
26 26 -- TIME
27 27 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
28 28 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
29 29 --
30 30 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
31 31 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
32 32 --
33 33 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
34 34 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
35 35 --
36 36 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
37 37 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
38 38
39 39
40 40
41 41 ---------------------------------------------------------------------------
42 42 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
43 43
44 44 --
45 45 --sample_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
46 46 --sample_full : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
47 47 --sample_empty : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
48 48 --sample_rdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
49 49
50 50 --status_channel : IN STD_LOGIC_VECTOR(49 DOWNTO 0);
51 51
52 52 -- IN
53 53 MEM_IN_SM_locked : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
54 54
55 55 -----------------------------------------------------------------------------
56 56
57 57 status_component : OUT STD_LOGIC_VECTOR(53 DOWNTO 0);
58 58 SM_in_data : OUT STD_LOGIC_VECTOR(32*2-1 DOWNTO 0);
59 59 SM_in_ren : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
60 60 SM_in_empty : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
61 61
62 62 SM_correlation_start : OUT STD_LOGIC;
63 63 SM_correlation_auto : OUT STD_LOGIC;
64 64 SM_correlation_done : IN STD_LOGIC
65 65 );
66 66 END COMPONENT;
67 67
68 68
69 69 -----------------------------------------------------------------------------
70 70 COMPONENT lpp_lfr_ms
71 71 GENERIC (
72 72 Mem_use : INTEGER);
73 73 PORT (
74 74 clk : IN STD_LOGIC;
75 75 rstn : IN STD_LOGIC;
76 76 run : IN STD_LOGIC;
77 77 start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
78 78 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
79 79 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
80 80 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
81 81 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
82 82 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
83 83 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
84 84 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
85 85 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
86 86 dma_fifo_burst_valid : OUT STD_LOGIC;
87 87 dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
88 88 dma_fifo_ren : IN STD_LOGIC;
89 89 dma_buffer_new : OUT STD_LOGIC;
90 90 dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
91 91 dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
92 92 dma_buffer_full : IN STD_LOGIC;
93 93 dma_buffer_full_err : IN STD_LOGIC;
94 94 ready_matrix_f0 : OUT STD_LOGIC;
95 95 ready_matrix_f1 : OUT STD_LOGIC;
96 96 ready_matrix_f2 : OUT STD_LOGIC;
97 97 error_buffer_full : OUT STD_LOGIC;
98 98 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
99 99 status_ready_matrix_f0 : IN STD_LOGIC;
100 100 status_ready_matrix_f1 : IN STD_LOGIC;
101 101 status_ready_matrix_f2 : IN STD_LOGIC;
102 102 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
103 103 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
104 104 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
105 105 length_matrix_f0 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
106 106 length_matrix_f1 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
107 107 length_matrix_f2 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
108 108 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
109 109 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
110 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0));
110 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
111 debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0));
111 112 END COMPONENT;
112 113
113 114 COMPONENT lpp_lfr_ms_fsmdma
114 115 PORT (
115 116 clk : IN STD_ULOGIC;
116 117 rstn : IN STD_ULOGIC;
117 118 run : IN STD_LOGIC;
118 119 fifo_matrix_type : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
119 120 fifo_matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
120 121 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
121 122 fifo_empty : IN STD_LOGIC;
122 123 fifo_empty_threshold : IN STD_LOGIC;
123 124 fifo_ren : OUT STD_LOGIC;
124 125 dma_fifo_valid_burst : OUT STD_LOGIC;
125 126 dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
126 127 dma_fifo_ren : IN STD_LOGIC;
127 128 dma_buffer_new : OUT STD_LOGIC;
128 129 dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
129 130 dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
130 131 dma_buffer_full : IN STD_LOGIC;
131 132 dma_buffer_full_err : IN STD_LOGIC;
132 133 status_ready_matrix_f0 : IN STD_LOGIC;
133 134 status_ready_matrix_f1 : IN STD_LOGIC;
134 135 status_ready_matrix_f2 : IN STD_LOGIC;
135 136 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
136 137 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
137 138 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
138 139 length_matrix_f0 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
139 140 length_matrix_f1 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
140 141 length_matrix_f2 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
141 142 ready_matrix_f0 : OUT STD_LOGIC;
142 143 ready_matrix_f1 : OUT STD_LOGIC;
143 144 ready_matrix_f2 : OUT STD_LOGIC;
144 145 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
145 146 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
146 147 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
147 148 error_buffer_full : OUT STD_LOGIC);
148 149 END COMPONENT;
149 150
150 151 COMPONENT lpp_lfr_ms_FFT
151 152 PORT (
152 153 clk : IN STD_LOGIC;
153 154 rstn : IN STD_LOGIC;
154 155 sample_valid : IN STD_LOGIC;
155 156 fft_read : IN STD_LOGIC;
156 157 sample_data : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
157 158 sample_load : OUT STD_LOGIC;
158 159 fft_pong : OUT STD_LOGIC;
159 160 fft_data_im : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
160 161 fft_data_re : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
161 162 fft_data_valid : OUT STD_LOGIC;
162 163 fft_ready : OUT STD_LOGIC);
163 164 END COMPONENT;
164 165
165 166 COMPONENT lpp_lfr_filter
166 167 GENERIC (
167 168 Mem_use : INTEGER);
168 169 PORT (
169 170 sample : IN Samples(7 DOWNTO 0);
170 171 sample_val : IN STD_LOGIC;
171 172 clk : IN STD_LOGIC;
172 173 rstn : IN STD_LOGIC;
173 174 data_shaping_SP0 : IN STD_LOGIC;
174 175 data_shaping_SP1 : IN STD_LOGIC;
175 176 data_shaping_R0 : IN STD_LOGIC;
176 177 data_shaping_R1 : IN STD_LOGIC;
177 178 data_shaping_R2 : IN STD_LOGIC;
178 179 sample_f0_val : OUT STD_LOGIC;
179 180 sample_f1_val : OUT STD_LOGIC;
180 181 sample_f2_val : OUT STD_LOGIC;
181 182 sample_f3_val : OUT STD_LOGIC;
182 183 sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
183 184 sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
184 185 sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
185 186 sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0));
186 187 END COMPONENT;
187 188
188 189 COMPONENT lpp_lfr
189 190 GENERIC (
190 191 Mem_use : INTEGER;
191 192 nb_data_by_buffer_size : INTEGER;
192 193 -- nb_word_by_buffer_size : INTEGER;
193 194 nb_snapshot_param_size : INTEGER;
194 195 delta_vector_size : INTEGER;
195 196 delta_vector_size_f0_2 : INTEGER;
196 197 pindex : INTEGER;
197 198 paddr : INTEGER;
198 199 pmask : INTEGER;
199 200 pirq_ms : INTEGER;
200 201 pirq_wfp : INTEGER;
201 202 hindex : INTEGER;
202 203 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0)
203 204 );
204 205 PORT (
205 206 clk : IN STD_LOGIC;
206 207 rstn : IN STD_LOGIC;
207 208 sample_B : IN Samples(2 DOWNTO 0);
208 209 sample_E : IN Samples(4 DOWNTO 0);
209 210 sample_val : IN STD_LOGIC;
210 211 apbi : IN apb_slv_in_type;
211 212 apbo : OUT apb_slv_out_type;
212 213 ahbi : IN AHB_Mst_In_Type;
213 214 ahbo : OUT AHB_Mst_Out_Type;
214 215 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
215 216 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
216 data_shaping_BW : OUT STD_LOGIC
217 data_shaping_BW : OUT STD_LOGIC ;
218 debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
219 debug_vector_ms : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
217 220 );
218 221 END COMPONENT;
219 222
220 223 -----------------------------------------------------------------------------
221 224 -- LPP_LFR with only WaveForm Picker (and without Spectral Matrix Sub System)
222 225 -----------------------------------------------------------------------------
223 226 COMPONENT lpp_lfr_WFP_nMS
224 227 GENERIC (
225 228 Mem_use : INTEGER;
226 229 nb_data_by_buffer_size : INTEGER;
227 230 nb_word_by_buffer_size : INTEGER;
228 231 nb_snapshot_param_size : INTEGER;
229 232 delta_vector_size : INTEGER;
230 233 delta_vector_size_f0_2 : INTEGER;
231 234 pindex : INTEGER;
232 235 paddr : INTEGER;
233 236 pmask : INTEGER;
234 237 pirq_ms : INTEGER;
235 238 pirq_wfp : INTEGER;
236 239 hindex : INTEGER;
237 240 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0));
238 241 PORT (
239 242 clk : IN STD_LOGIC;
240 243 rstn : IN STD_LOGIC;
241 244 sample_B : IN Samples(2 DOWNTO 0);
242 245 sample_E : IN Samples(4 DOWNTO 0);
243 246 sample_val : IN STD_LOGIC;
244 247 apbi : IN apb_slv_in_type;
245 248 apbo : OUT apb_slv_out_type;
246 249 ahbi : IN AHB_Mst_In_Type;
247 250 ahbo : OUT AHB_Mst_Out_Type;
248 251 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
249 252 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
250 253 data_shaping_BW : OUT STD_LOGIC;
251 254 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
252 255 END COMPONENT;
253 256 -----------------------------------------------------------------------------
254 257
255 258 COMPONENT lpp_lfr_apbreg
256 259 GENERIC (
257 260 nb_data_by_buffer_size : INTEGER;
258 261 nb_snapshot_param_size : INTEGER;
259 262 delta_vector_size : INTEGER;
260 263 delta_vector_size_f0_2 : INTEGER;
261 264 pindex : INTEGER;
262 265 paddr : INTEGER;
263 266 pmask : INTEGER;
264 267 pirq_ms : INTEGER;
265 268 pirq_wfp : INTEGER;
266 269 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0));
267 270 PORT (
268 271 HCLK : IN STD_ULOGIC;
269 272 HRESETn : IN STD_ULOGIC;
270 273 apbi : IN apb_slv_in_type;
271 274 apbo : OUT apb_slv_out_type;
272 275 run_ms : OUT STD_LOGIC;
273 276 ready_matrix_f0 : IN STD_LOGIC;
274 277 ready_matrix_f1 : IN STD_LOGIC;
275 278 ready_matrix_f2 : IN STD_LOGIC;
276 279 error_buffer_full : IN STD_LOGIC;
277 280 error_input_fifo_write : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
278 281 status_ready_matrix_f0 : OUT STD_LOGIC;
279 282 status_ready_matrix_f1 : OUT STD_LOGIC;
280 283 status_ready_matrix_f2 : OUT STD_LOGIC;
281 284 addr_matrix_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
282 285 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
283 286 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
284 287 length_matrix_f0 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
285 288 length_matrix_f1 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
286 289 length_matrix_f2 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
287 290 matrix_time_f0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
288 291 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
289 292 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
290 293 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
291 294 data_shaping_BW : OUT STD_LOGIC;
292 295 data_shaping_SP0 : OUT STD_LOGIC;
293 296 data_shaping_SP1 : OUT STD_LOGIC;
294 297 data_shaping_R0 : OUT STD_LOGIC;
295 298 data_shaping_R1 : OUT STD_LOGIC;
296 299 data_shaping_R2 : OUT STD_LOGIC;
297 300 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
298 301 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
299 302 delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
300 303 delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
301 304 delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
302 305 nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
303 306 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
304 307 enable_f0 : OUT STD_LOGIC;
305 308 enable_f1 : OUT STD_LOGIC;
306 309 enable_f2 : OUT STD_LOGIC;
307 310 enable_f3 : OUT STD_LOGIC;
308 311 burst_f0 : OUT STD_LOGIC;
309 312 burst_f1 : OUT STD_LOGIC;
310 313 burst_f2 : OUT STD_LOGIC;
311 314 run : OUT STD_LOGIC;
312 315 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
313 316 wfp_status_buffer_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
314 317 wfp_addr_buffer : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
315 318 wfp_length_buffer : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
316 319 wfp_ready_buffer : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
317 320 wfp_buffer_time : IN STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
318 wfp_error_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0));
321 wfp_error_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
322 debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0));
319 323 END COMPONENT;
320 324
321 325 COMPONENT lpp_top_ms
322 326 GENERIC (
323 327 Mem_use : INTEGER;
324 328 nb_burst_available_size : INTEGER;
325 329 nb_snapshot_param_size : INTEGER;
326 330 delta_snapshot_size : INTEGER;
327 331 delta_f2_f0_size : INTEGER;
328 332 delta_f2_f1_size : INTEGER;
329 333 pindex : INTEGER;
330 334 paddr : INTEGER;
331 335 pmask : INTEGER;
332 336 pirq_ms : INTEGER;
333 337 pirq_wfp : INTEGER;
334 338 hindex_wfp : INTEGER;
335 339 hindex_ms : INTEGER);
336 340 PORT (
337 341 clk : IN STD_LOGIC;
338 342 rstn : IN STD_LOGIC;
339 343 sample_B : IN Samples14v(2 DOWNTO 0);
340 344 sample_E : IN Samples14v(4 DOWNTO 0);
341 345 sample_val : IN STD_LOGIC;
342 346 apbi : IN apb_slv_in_type;
343 347 apbo : OUT apb_slv_out_type;
344 348 ahbi_ms : IN AHB_Mst_In_Type;
345 349 ahbo_ms : OUT AHB_Mst_Out_Type;
346 350 data_shaping_BW : OUT STD_LOGIC;
347 351 matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
348 352 matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
349 353 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
350 354 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0)
351 355 );
352 356 END COMPONENT;
353 357
354 358 COMPONENT lpp_apbreg_ms_pointer
355 359 PORT (
356 360 clk : IN STD_LOGIC;
357 361 rstn : IN STD_LOGIC;
358 362 run : IN STD_LOGIC;
359 363 reg0_status_ready_matrix : IN STD_LOGIC;
360 364 reg0_ready_matrix : OUT STD_LOGIC;
361 365 reg0_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
362 366 reg0_matrix_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
363 367 reg1_status_ready_matrix : IN STD_LOGIC;
364 368 reg1_ready_matrix : OUT STD_LOGIC;
365 369 reg1_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
366 370 reg1_matrix_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
367 371 ready_matrix : IN STD_LOGIC;
368 372 status_ready_matrix : OUT STD_LOGIC;
369 373 addr_matrix : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
370 374 matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0));
371 375 END COMPONENT;
372 376
373 377 COMPONENT lpp_lfr_ms_reg_head
374 378 PORT (
375 379 clk : IN STD_LOGIC;
376 380 rstn : IN STD_LOGIC;
377 381 in_wen : IN STD_LOGIC;
378 382 in_data : IN STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
379 383 in_full : IN STD_LOGIC;
380 384 in_empty : IN STD_LOGIC;
381 385 out_wen : OUT STD_LOGIC;
382 386 out_data : OUT STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
383 387 out_full : OUT STD_LOGIC);
384 388 END COMPONENT;
385 389
386 390 END lpp_lfr_pkg;
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