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1 lpp_Header.vhd
2 HeaderBuilder.vhd
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1 VHDLIB=../..
1 VHDLIB=../..
2 SCRIPTSDIR=$(VHDLIB)/scripts/
2 SCRIPTSDIR=$(VHDLIB)/scripts/
3 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
3 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
4 TOP=MINI_LFR_top
4 TOP=MINI_LFR_top
5 BOARD=MINI-LFR
5 BOARD=MINI-LFR
6 include $(VHDLIB)/boards/$(BOARD)/Makefile.inc
6 include $(VHDLIB)/boards/$(BOARD)/Makefile.inc
7 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
7 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
8 UCF=$(VHDLIB)/boards/$(BOARD)/$(TOP).ucf
8 UCF=$(VHDLIB)/boards/$(BOARD)/$(TOP).ucf
9 QSF=$(VHDLIB)/boards/$(BOARD)/$(TOP).qsf
9 QSF=$(VHDLIB)/boards/$(BOARD)/$(TOP).qsf
10 EFFORT=high
10 EFFORT=high
11 XSTOPT=
11 XSTOPT=
12 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
12 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
13 VHDLSYNFILES= MINI_LFR_top.vhd
13 VHDLSYNFILES= MINI_LFR_top.vhd
14 VHDLSIMFILES= testbench.vhd
14 VHDLSIMFILES= testbench.vhd
15 SIMTOP=testbench
15 SIMTOP=testbench
16 PDC=$(VHDLIB)/boards/$(BOARD)/default.pdc
16 PDC=$(VHDLIB)/boards/$(BOARD)/default.pdc
17 ##SDC=$(VHDLIB)/boards/$(BOARD)/default.sdc
17 ##SDC=$(VHDLIB)/boards/$(BOARD)/default.sdc
18 ##SDCFILE=$(VHDLIB)/boards/$(BOARD)/MINI_LFR_synthesis.sdc
18 ##SDCFILE=$(VHDLIB)/boards/$(BOARD)/MINI_LFR_synthesis.sdc
19 SDC=$(VHDLIB)/boards/$(BOARD)/MINI_LFR_place_and_route.sdc
19 SDC=$(VHDLIB)/boards/$(BOARD)/MINI_LFR_place_and_route.sdc
20 BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut
20 BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut
21 CLEAN=soft-clean
21 CLEAN=soft-clean
22
22
23 TECHLIBS = proasic3e
23 TECHLIBS = proasic3e
24
24
25 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
25 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
26 tmtc openchip hynix ihp gleichmann micron usbhc
26 tmtc openchip hynix ihp gleichmann micron usbhc
27
27
28 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
28 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
29 pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
29 pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
30 ./amba_lcd_16x2_ctrlr \
30 ./amba_lcd_16x2_ctrlr \
31 ./general_purpose/lpp_AMR \
31 ./general_purpose/lpp_AMR \
32 ./general_purpose/lpp_balise \
32 ./general_purpose/lpp_balise \
33 ./general_purpose/lpp_delay \
33 ./general_purpose/lpp_delay \
34 ./lpp_bootloader \
34 ./lpp_bootloader \
35 ./lpp_uart \
35 ./lpp_uart \
36 ./lpp_usb \
36 ./lpp_usb \
37 ./dsp/lpp_fft_rtax \
37 ./dsp/lpp_fft_rtax \
38 ./lpp_sim/CY7C1061DV33 \
38 ./lpp_sim/CY7C1061DV33 \
39
39
40 FILESKIP =i2cmst.vhd \
40 FILESKIP =i2cmst.vhd \
41 APB_MULTI_DIODE.vhd \
41 APB_MULTI_DIODE.vhd \
42 APB_SIMPLE_DIODE.vhd \
42 APB_SIMPLE_DIODE.vhd \
43 Top_MatrixSpec.vhd \
43 Top_MatrixSpec.vhd \
44 APB_FFT.vhd \
44 APB_FFT.vhd \
45 CoreFFT_simu.vhd \
45 CoreFFT_simu.vhd \
46 lpp_lfr_apbreg_simu.vhd
46 lpp_lfr_apbreg_simu.vhd \
47 MUXN.vhd
47
48
48 include $(GRLIB)/bin/Makefile
49 include $(GRLIB)/bin/Makefile
49 include $(GRLIB)/software/leon3/Makefile
50 include $(GRLIB)/software/leon3/Makefile
50
51
51 ################## project specific targets ##########################
52 ################## project specific targets ##########################
52
53
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1
1
2 LIBRARY ieee;
2 LIBRARY ieee;
3 USE ieee.std_logic_1164.ALL;
3 USE ieee.std_logic_1164.ALL;
4 USE IEEE.MATH_REAL.ALL;
4 USE IEEE.MATH_REAL.ALL;
5 USE ieee.numeric_std.ALL;
5 USE ieee.numeric_std.ALL;
6
6
7 LIBRARY std;
7 LIBRARY std;
8 use std.textio.all;
8 use std.textio.all;
9
9
10 ENTITY data_write_with_burstCounter IS
10 ENTITY data_write_with_burstCounter IS
11 GENERIC (
11 GENERIC (
12 OUTPUT_FILE_NAME : STRING := "output_data_2.txt";
12 OUTPUT_FILE_NAME : STRING := "output_data_2.txt";
13 NB_CHAR_PER_DATA : INTEGER := 4;
13 NB_CHAR_PER_DATA : INTEGER := 4;
14 BASE_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0)
14 BASE_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0)
15 );
15 );
16 PORT (
16 PORT (
17 clk : IN STD_LOGIC;
17 clk : IN STD_LOGIC;
18 rstn : IN STD_LOGIC;
18 rstn : IN STD_LOGIC;
19
19
20 burst_valid : IN STD_LOGIC;
20 burst_valid : IN STD_LOGIC;
21 burst_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
21 burst_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
22 data_ren : OUT STD_LOGIC;
22 data_ren : OUT STD_LOGIC;
23
23
24 data : IN STD_LOGIC_VECTOR(NB_CHAR_PER_DATA * 4 - 1 DOWNTO 0);
24 data : IN STD_LOGIC_VECTOR(NB_CHAR_PER_DATA * 4 - 1 DOWNTO 0);
25 close_file : IN STD_LOGIC
25 close_file : IN STD_LOGIC
26 );
26 );
27 END;
27 END;
28
28
29 ARCHITECTURE beh OF data_write_with_burstCounter IS
29 ARCHITECTURE beh OF data_write_with_burstCounter IS
30
30
31 COMPONENT data_write
31 COMPONENT data_write
32 GENERIC (
32 GENERIC (
33 OUTPUT_FILE_NAME : STRING;
33 OUTPUT_FILE_NAME : STRING;
34 NB_CHAR_PER_DATA : INTEGER );
34 NB_CHAR_PER_DATA : INTEGER );
35 PORT (
35 PORT (
36 clk : IN STD_LOGIC;
36 clk : IN STD_LOGIC;
37 data_in_val : IN STD_LOGIC;
37 data_in_val : IN STD_LOGIC;
38 data : IN STD_LOGIC_VECTOR(NB_CHAR_PER_DATA * 4 - 1 DOWNTO 0);
38 data : IN STD_LOGIC_VECTOR(NB_CHAR_PER_DATA * 4 - 1 DOWNTO 0);
39 close_file : IN STD_LOGIC);
39 close_file : IN STD_LOGIC);
40 END COMPONENT;
40 END COMPONENT;
41
41
42 SIGNAL ren_counter : INTEGER;
42 SIGNAL ren_counter : INTEGER;
43 SIGNAL data_ren_s : STD_LOGIC;
43 SIGNAL data_ren_s : STD_LOGIC;
44 SIGNAL data_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
44 SIGNAL data_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
45 SIGNAL data_in_val : STD_LOGIC;
45 SIGNAL data_in_val : STD_LOGIC;
46
46
47
47 BEGIN
48 BEGIN
48
49
49 PROCESS (clk, rstn)
50 PROCESS (clk, rstn)
50 BEGIN -- PROCESS
51 BEGIN -- PROCESS
51 IF rstn = '0' THEN -- asynchronous reset (active low)
52 IF rstn = '0' THEN -- asynchronous reset (active low)
52 ren_counter <= 0;
53 ren_counter <= 0;
53 data_ren_s <= '1';
54 data_ren_s <= '1';
54 data_s <= (OTHERS => '0');
55 data_s <= (OTHERS => '0');
56 data_in_val <= '0';
55 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
57 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
56 data_s <= data;
58 data_s <= data;
57 data_ren_s <= '1';
59 data_ren_s <= '1';
58 IF ren_counter = 0 AND burst_valid = '1' AND burst_addr = BASE_ADDR THEN
60 IF ren_counter = 0 AND burst_valid = '1' AND burst_addr = BASE_ADDR THEN
59 ren_counter <= 16;
61 ren_counter <= 16;
60 END IF;
62 END IF;
61 IF ren_counter > 0 THEN
63 IF ren_counter > 0 THEN
62 ren_counter <= ren_counter - 1;
64 ren_counter <= ren_counter - 1;
63 data_ren_s <= '0';
65 data_ren_s <= '0';
64 END IF;
66 END IF;
67 data_in_val <= NOT data_ren_s;
65 END IF;
68 END IF;
66 END PROCESS;
69 END PROCESS;
67
70
68 data_in_val <= NOT data_ren_s;
69 data_ren <= data_ren_s;
71 data_ren <= data_ren_s;
70
72
71 data_write_1: data_write
73 data_write_1: data_write
72 GENERIC MAP (
74 GENERIC MAP (
73 OUTPUT_FILE_NAME => OUTPUT_FILE_NAME,
75 OUTPUT_FILE_NAME => OUTPUT_FILE_NAME,
74 NB_CHAR_PER_DATA => NB_CHAR_PER_DATA)
76 NB_CHAR_PER_DATA => NB_CHAR_PER_DATA)
75 PORT MAP (
77 PORT MAP (
76 clk => clk,
78 clk => clk,
77 data_in_val => data_in_val,
79 data_in_val => data_in_val,
78 data => data_s,
80 data => data,
79 close_file => close_file);
81 close_file => close_file);
80
82
81 END beh;
83 END beh;
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@@ -1,56 +1,57
1 #vsim -c -do "run_nowindow.do" -goutput_file_name="output_data.txt" -ginput_file_name="input_data.txt"
1 #vsim -c -do "run_nowindow.do" -goutput_file_name="output_data.txt" -ginput_file_name="input_data.txt"
2
2
3 quietly set args [ split $argv {\ } ]
3 quietly set args [ split $argv {\ } ]
4 set argc [ llength $args ]
4 set argc [ llength $args ]
5
5
6 set outputfile_f0 "output\_data\_f0\.txt"
6 set outputfile_f0 "output\_data\_f0\.txt"
7 set inputfile_f0 "input\_data\_f0\.txt"
7 set inputfile_f0 "input\_data\_f0\.txt"
8 set outputfile_f1 "output\_data\_f1\.txt"
8 set outputfile_f1 "output\_data\_f1\.txt"
9 set inputfile_f1 "input\_data\_f1\.txt"
9 set inputfile_f1 "input\_data\_f1\.txt"
10 set outputfile_f2 "output\_data\_f2\.txt"
10 set outputfile_f2 "output\_data\_f2\.txt"
11 set inputfile_f2 "input\_data\_f2\.txt"
11 set inputfile_f2 "input\_data\_f2\.txt"
12
12
13 #puts "there are $argc arguments to this script"
13 #puts "there are $argc arguments to this script"
14 #puts "The name of this script is $argv0"
14 #puts "The name of this script is $argv0"
15
15
16 #foreach arg $::argv {puts $arg}
16 #foreach arg $::argv {puts $arg}
17
17
18 #puts [ lindex $args 4 ]
18 #puts [ lindex $args 4 ]
19
19
20 for { set i 0 } { $i < $argc } { incr i 1 } {
20 for { set i 0 } { $i < $argc } { incr i 1 } {
21 puts "$i : [ lindex $args $i ]"
21 puts "$i : [ lindex $args $i ]"
22
22
23 if { [ string match -goutput_file_name_f0=* [ lindex $args $i ] ] } {
23 if { [ string match -goutput_file_name_f0=* [ lindex $args $i ] ] } {
24 set outputfile_f0 [ lindex [ split [ lindex $args $i ] {=} ] 1 ]
24 set outputfile_f0 [ lindex [ split [ lindex $args $i ] {=} ] 1 ]
25 puts "OUTPUT_FILE_f0 : $outputfile_f0"
25 puts "OUTPUT_FILE_f0 : $outputfile_f0"
26 }
26 }
27 if { [ string match -goutput_file_name_f1=* [ lindex $args $i ] ] } {
27 if { [ string match -goutput_file_name_f1=* [ lindex $args $i ] ] } {
28 set outputfile_f1 [ lindex [ split [ lindex $args $i ] {=} ] 1 ]
28 set outputfile_f1 [ lindex [ split [ lindex $args $i ] {=} ] 1 ]
29 puts "OUTPUT_FILE_f1 : $outputfile_f1"
29 puts "OUTPUT_FILE_f1 : $outputfile_f1"
30 }
30 }
31 if { [ string match -goutput_file_name_f2=* [ lindex $args $i ] ] } {
31 if { [ string match -goutput_file_name_f2=* [ lindex $args $i ] ] } {
32 set outputfile_f2 [ lindex [ split [ lindex $args $i ] {=} ] 1 ]
32 set outputfile_f2 [ lindex [ split [ lindex $args $i ] {=} ] 1 ]
33 puts "OUTPUT_FILE_f2 : $outputfile_f2"
33 puts "OUTPUT_FILE_f2 : $outputfile_f2"
34 }
34 }
35
35
36 if { [ string match -ginput_file_name_f0=* [ lindex $args $i ] ] } {
36 if { [ string match -ginput_file_name_f0=* [ lindex $args $i ] ] } {
37 set inputfile_f0 [ lindex [ split [ lindex $args $i ] {=} ] 1 ]
37 set inputfile_f0 [ lindex [ split [ lindex $args $i ] {=} ] 1 ]
38 puts "INPUT_FILE_F0 : $inputfile_f0"
38 puts "INPUT_FILE_F0 : $inputfile_f0"
39 }
39 }
40 if { [ string match -ginput_file_name_f1=* [ lindex $args $i ] ] } {
40 if { [ string match -ginput_file_name_f1=* [ lindex $args $i ] ] } {
41 set inputfile_f1 [ lindex [ split [ lindex $args $i ] {=} ] 1 ]
41 set inputfile_f1 [ lindex [ split [ lindex $args $i ] {=} ] 1 ]
42 puts "INPUT_FILE_F1 : $inputfile_f1"
42 puts "INPUT_FILE_F1 : $inputfile_f1"
43 }
43 }
44 if { [ string match -ginput_file_name_f2=* [ lindex $args $i ] ] } {
44 if { [ string match -ginput_file_name_f2=* [ lindex $args $i ] ] } {
45 set inputfile_f2 [ lindex [ split [ lindex $args $i ] {=} ] 1 ]
45 set inputfile_f2 [ lindex [ split [ lindex $args $i ] {=} ] 1 ]
46 puts "INPUT_FILE_F2 : $inputfile_f2"
46 puts "INPUT_FILE_F2 : $inputfile_f2"
47 }
47 }
48 }
48 }
49
49
50 vsim work.testbench \
50 vsim work.testbench \
51 -goutput_file_name_f0=$outputfile_f0 -ginput_file_name_f0=$inputfile_f0 \
51 -goutput_file_name_f0=$outputfile_f0 -ginput_file_name_f0=$inputfile_f0 \
52 -goutput_file_name_f1=$outputfile_f1 -ginput_file_name_f1=$inputfile_f1 \
52 -goutput_file_name_f1=$outputfile_f1 -ginput_file_name_f1=$inputfile_f1 \
53 -goutput_file_name_f2=$outputfile_f2 -ginput_file_name_f2=$inputfile_f2
53 -goutput_file_name_f2=$outputfile_f2 -ginput_file_name_f2=$inputfile_f2
54 when -label end_of_simulation {end_of_sim == '1'} {echo "End of simulation"; exit ;}
54 when -label end_of_simulation {end_of_sim == '1'} {echo "End of simulation"; exit ;}
55
55 run -all
56 run -all
56 exit
57 exit
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@@ -1,438 +1,448
1
1
2 LIBRARY ieee;
2 LIBRARY ieee;
3 USE ieee.std_logic_1164.ALL;
3 USE ieee.std_logic_1164.ALL;
4 USE IEEE.MATH_REAL.ALL;
4 USE IEEE.MATH_REAL.ALL;
5 USE ieee.numeric_std.ALL;
5 USE ieee.numeric_std.ALL;
6
6
7 LIBRARY std;
7 LIBRARY std;
8 USE std.textio.ALL;
8 USE std.textio.ALL;
9
9
10 LIBRARY lpp;
10 LIBRARY lpp;
11 USE lpp.cic_pkg.ALL;
11 USE lpp.cic_pkg.ALL;
12 USE lpp.chirp_pkg.ALL;
12 USE lpp.chirp_pkg.ALL;
13 USE lpp.lpp_fft.ALL;
13 USE lpp.lpp_fft.ALL;
14 USE lpp.lpp_lfr_pkg.ALL;
14 USE lpp.lpp_lfr_pkg.ALL;
15 USE lpp.iir_filter.ALL;
15 USE lpp.iir_filter.ALL;
16
16
17 ENTITY testbench IS
17 ENTITY testbench IS
18 GENERIC (
18 GENERIC (
19 input_file_name_f0 : STRING := "input_data_f0.txt";
19 input_file_name_f0 : STRING := "input_data_f0.txt";
20 input_file_name_f1 : STRING := "input_data_f1.txt";
20 input_file_name_f1 : STRING := "input_data_f1.txt";
21 input_file_name_f2 : STRING := "input_data_f2.txt";
21 input_file_name_f2 : STRING := "input_data_f2.txt";
22 output_file_name_f0 : STRING := "output_data_f0.txt";
22 output_file_name_f0 : STRING := "output_data_f0.txt";
23 output_file_name_f1 : STRING := "output_data_f1.txt";
23 output_file_name_f1 : STRING := "output_data_f1.txt";
24 output_file_name_f2 : STRING := "output_data_f2.txt");
24 output_file_name_f2 : STRING := "output_data_f2.txt");
25 END;
25 END;
26
26
27 ARCHITECTURE behav OF testbench IS
27 ARCHITECTURE behav OF testbench IS
28
28
29 COMPONENT data_read_with_timer
29 COMPONENT data_read_with_timer
30 GENERIC (
30 GENERIC (
31 input_file_name : STRING;
31 input_file_name : STRING;
32 NB_CHAR_PER_DATA : INTEGER;
32 NB_CHAR_PER_DATA : INTEGER;
33 NB_CYCLE_TIMER : INTEGER);
33 NB_CYCLE_TIMER : INTEGER);
34 PORT (
34 PORT (
35 clk : IN STD_LOGIC;
35 clk : IN STD_LOGIC;
36 rstn : IN STD_LOGIC;
36 rstn : IN STD_LOGIC;
37 end_of_file : OUT STD_LOGIC;
37 end_of_file : OUT STD_LOGIC;
38 data_out_val : OUT STD_LOGIC;
38 data_out_val : OUT STD_LOGIC;
39 data_out : OUT STD_LOGIC_VECTOR(NB_CHAR_PER_DATA * 4 - 1 DOWNTO 0));
39 data_out : OUT STD_LOGIC_VECTOR(NB_CHAR_PER_DATA * 4 - 1 DOWNTO 0));
40 END COMPONENT;
40 END COMPONENT;
41
41
42 COMPONENT data_write_with_burstCounter
42 COMPONENT data_write_with_burstCounter
43 GENERIC (
43 GENERIC (
44 OUTPUT_FILE_NAME : STRING;
44 OUTPUT_FILE_NAME : STRING;
45 NB_CHAR_PER_DATA : INTEGER;
45 NB_CHAR_PER_DATA : INTEGER;
46 BASE_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0));
46 BASE_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0));
47 PORT (
47 PORT (
48 clk : IN STD_LOGIC;
48 clk : IN STD_LOGIC;
49 rstn : IN STD_LOGIC;
49 rstn : IN STD_LOGIC;
50 burst_valid : IN STD_LOGIC;
50 burst_valid : IN STD_LOGIC;
51 burst_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
51 burst_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
52 data_ren : OUT STD_LOGIC;
52 data_ren : OUT STD_LOGIC;
53 data : IN STD_LOGIC_VECTOR(NB_CHAR_PER_DATA * 4 - 1 DOWNTO 0);
53 data : IN STD_LOGIC_VECTOR(NB_CHAR_PER_DATA * 4 - 1 DOWNTO 0);
54 close_file : IN STD_LOGIC);
54 close_file : IN STD_LOGIC);
55 END COMPONENT;
55 END COMPONENT;
56
56
57 SIGNAL clk : STD_LOGIC := '0';
57 SIGNAL clk : STD_LOGIC := '0';
58 SIGNAL rstn : STD_LOGIC;
58 SIGNAL rstn : STD_LOGIC;
59
59
60 SIGNAL start : STD_LOGIC;
60 SIGNAL start : STD_LOGIC;
61
61
62 -- IN
62 -- IN
63 SIGNAL sample_valid : STD_LOGIC;
63 SIGNAL sample_valid : STD_LOGIC;
64 SIGNAL fft_read : STD_LOGIC;
64 SIGNAL fft_read : STD_LOGIC;
65 SIGNAL sample_data : STD_LOGIC_VECTOR(15 DOWNTO 0);
65 SIGNAL sample_data : STD_LOGIC_VECTOR(15 DOWNTO 0);
66 SIGNAL sample_load : STD_LOGIC;
66 SIGNAL sample_load : STD_LOGIC;
67 -- OUT
67 -- OUT
68 SIGNAL fft_pong : STD_LOGIC;
68 SIGNAL fft_pong : STD_LOGIC;
69 SIGNAL fft_data_im : STD_LOGIC_VECTOR(15 DOWNTO 0);
69 SIGNAL fft_data_im : STD_LOGIC_VECTOR(15 DOWNTO 0);
70 SIGNAL fft_data_re : STD_LOGIC_VECTOR(15 DOWNTO 0);
70 SIGNAL fft_data_re : STD_LOGIC_VECTOR(15 DOWNTO 0);
71 SIGNAL fft_data_valid : STD_LOGIC;
71 SIGNAL fft_data_valid : STD_LOGIC;
72 SIGNAL fft_ready : STD_LOGIC;
72 SIGNAL fft_ready : STD_LOGIC;
73 SIGNAL fft_component_number : INTEGER;
73 SIGNAL fft_component_number : INTEGER;
74
74
75 SIGNAL end_of_sim : STD_LOGIC := '0';
75 SIGNAL end_of_sim : STD_LOGIC := '0';
76
76
77 -----------------------------------------------------------------------------
77 -----------------------------------------------------------------------------
78 -- DATA GEN
78 -- DATA GEN
79 -----------------------------------------------------------------------------
79 -----------------------------------------------------------------------------
80 CONSTANT NB_CYCLE_f0 : INTEGER := 1017; -- 25MHz / 24576Hz
80 CONSTANT NB_CYCLE_f0 : INTEGER := 1017; -- 25MHz / 24576Hz
81 CONSTANT NB_CYCLE_f1 : INTEGER := 6103; -- 25MHz / 4096Hz
81 CONSTANT NB_CYCLE_f1 : INTEGER := 6103; -- 25MHz / 4096Hz
82 CONSTANT NB_CYCLE_f2 : INTEGER := 97656; -- 25MHz / 256Hz
82 CONSTANT NB_CYCLE_f2 : INTEGER := 97656; -- 25MHz / 256Hz
83
83
84 SIGNAL data_counter_f0 : INTEGER;
84 SIGNAL data_counter_f0 : INTEGER;
85 SIGNAL data_counter_f1 : INTEGER;
85 SIGNAL data_counter_f1 : INTEGER;
86 SIGNAL data_counter_f2 : INTEGER;
86 SIGNAL data_counter_f2 : INTEGER;
87
87
88 SIGNAL sample_f0_wen : STD_LOGIC;
88 SIGNAL sample_f0_wen : STD_LOGIC;
89 SIGNAL sample_f1_wen : STD_LOGIC;
89 SIGNAL sample_f1_wen : STD_LOGIC;
90 SIGNAL sample_f2_wen : STD_LOGIC;
90 SIGNAL sample_f2_wen : STD_LOGIC;
91
91
92 SIGNAL sample_f0_wen_v : STD_LOGIC_VECTOR(4 DOWNTO 0);
92 SIGNAL sample_f0_wen_v : STD_LOGIC_VECTOR(4 DOWNTO 0);
93 SIGNAL sample_f1_wen_v : STD_LOGIC_VECTOR(4 DOWNTO 0);
93 SIGNAL sample_f1_wen_v : STD_LOGIC_VECTOR(4 DOWNTO 0);
94 SIGNAL sample_f2_wen_v : STD_LOGIC_VECTOR(4 DOWNTO 0);
94 SIGNAL sample_f2_wen_v : STD_LOGIC_VECTOR(4 DOWNTO 0);
95
95
96 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
96 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
97 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
97 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
98 SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
98 SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
99
99
100 -----------------------------------------------------------------------------
100 -----------------------------------------------------------------------------
101 -- TIME
101 -- TIME
102 -----------------------------------------------------------------------------
102 -----------------------------------------------------------------------------
103 SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
103 SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
104 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
104 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
105 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
105 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
106 SIGNAL sample_f0_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
107 SIGNAL sample_f1_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
108 SIGNAL sample_f2_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
106 SIGNAL time_counter : INTEGER;
109 SIGNAL time_counter : INTEGER;
107
110
108 SIGNAL new_fine_time : STD_LOGIC := '0';
111 SIGNAL new_fine_time : STD_LOGIC := '0';
109 SIGNAL new_fine_time_reg : STD_LOGIC := '0';
112 SIGNAL new_fine_time_reg : STD_LOGIC := '0';
110
113
111 -----------------------------------------------------------------------------
114 -----------------------------------------------------------------------------
112 --
115 --
113 -----------------------------------------------------------------------------
116 -----------------------------------------------------------------------------
114 SIGNAL end_of_file : STD_LOGIC_VECTOR(2 DOWNTO 0);
117 SIGNAL end_of_file : STD_LOGIC_VECTOR(2 DOWNTO 0);
115 SIGNAL data_out_val : STD_LOGIC_VECTOR(2 DOWNTO 0);
118 SIGNAL data_out_val : STD_LOGIC_VECTOR(2 DOWNTO 0);
116
119
117 -----------------------------------------------------------------------------
120 -----------------------------------------------------------------------------
118 -----------------------------------------------------------------------------
121 -----------------------------------------------------------------------------
119 SIGNAL dma_fifo_burst_valid : STD_LOGIC; --TODO
122 SIGNAL dma_fifo_burst_valid : STD_LOGIC; --TODO
120 SIGNAL dma_fifo_data : STD_LOGIC_VECTOR(31 DOWNTO 0); --TODO
123 SIGNAL dma_fifo_data : STD_LOGIC_VECTOR(31 DOWNTO 0); --TODO
121 SIGNAL dma_fifo_ren : STD_LOGIC; --TODO
124 SIGNAL dma_fifo_ren : STD_LOGIC; --TODO
122 SIGNAL dma_fifo_ren_f0 : STD_LOGIC; --TODO
125 SIGNAL dma_fifo_ren_f0 : STD_LOGIC; --TODO
123 SIGNAL dma_fifo_ren_f1 : STD_LOGIC; --TODO
126 SIGNAL dma_fifo_ren_f1 : STD_LOGIC; --TODO
124 SIGNAL dma_fifo_ren_f2 : STD_LOGIC; --TODO
127 SIGNAL dma_fifo_ren_f2 : STD_LOGIC; --TODO
125 SIGNAL dma_buffer_new : STD_LOGIC; --TODOx
128 SIGNAL dma_buffer_new : STD_LOGIC; --TODOx
126 SIGNAL dma_buffer_addr : STD_LOGIC_VECTOR(31 DOWNTO 0); --TODO
129 SIGNAL dma_buffer_addr : STD_LOGIC_VECTOR(31 DOWNTO 0); --TODO
127 SIGNAL dma_buffer_length : STD_LOGIC_VECTOR(25 DOWNTO 0); --TODO
130 SIGNAL dma_buffer_length : STD_LOGIC_VECTOR(25 DOWNTO 0); --TODO
128 SIGNAL dma_buffer_full : STD_LOGIC; --TODO
131 SIGNAL dma_buffer_full : STD_LOGIC; --TODO
129 SIGNAL dma_buffer_full_err : STD_LOGIC; --TODO
132 SIGNAL dma_buffer_full_err : STD_LOGIC; --TODO
130 SIGNAL ready_matrix_f0 : STD_LOGIC; -- TODO
133 SIGNAL ready_matrix_f0 : STD_LOGIC; -- TODO
131 SIGNAL ready_matrix_f1 : STD_LOGIC; -- TODO
134 SIGNAL ready_matrix_f1 : STD_LOGIC; -- TODO
132 SIGNAL ready_matrix_f2 : STD_LOGIC; -- TODO
135 SIGNAL ready_matrix_f2 : STD_LOGIC; -- TODO
133 SIGNAL status_ready_matrix_f0 : STD_LOGIC; -- TODO
136 SIGNAL status_ready_matrix_f0 : STD_LOGIC; -- TODO
134 SIGNAL status_ready_matrix_f1 : STD_LOGIC; -- TODO
137 SIGNAL status_ready_matrix_f1 : STD_LOGIC; -- TODO
135 SIGNAL status_ready_matrix_f2 : STD_LOGIC; -- TODO
138 SIGNAL status_ready_matrix_f2 : STD_LOGIC; -- TODO
136 SIGNAL addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
139 SIGNAL addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
137 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
140 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
138 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
141 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
139 SIGNAL length_matrix_f0 : STD_LOGIC_VECTOR(25 DOWNTO 0); -- TODO
142 SIGNAL length_matrix_f0 : STD_LOGIC_VECTOR(25 DOWNTO 0); -- TODO
140 SIGNAL length_matrix_f1 : STD_LOGIC_VECTOR(25 DOWNTO 0); -- TODO
143 SIGNAL length_matrix_f1 : STD_LOGIC_VECTOR(25 DOWNTO 0); -- TODO
141 SIGNAL length_matrix_f2 : STD_LOGIC_VECTOR(25 DOWNTO 0); -- TODO
144 SIGNAL length_matrix_f2 : STD_LOGIC_VECTOR(25 DOWNTO 0); -- TODO
142 SIGNAL matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
145 SIGNAL matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
143 SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
146 SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
144 SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
147 SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
145 -----------------------------------------------------------------------------
148 -----------------------------------------------------------------------------
146 SIGNAL dma_ren_counter : INTEGER;
149 SIGNAL dma_ren_counter : INTEGER;
147 SIGNAL dma_output_counter : INTEGER;
150 SIGNAL dma_output_counter : INTEGER;
148 -----------------------------------------------------------------------------
151 -----------------------------------------------------------------------------
149 CONSTANT BASE_ADDR_F0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"01000000";
152 CONSTANT BASE_ADDR_F0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"01000000";
150 CONSTANT BASE_ADDR_F1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"10000000";
153 CONSTANT BASE_ADDR_F1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"10000000";
151 CONSTANT BASE_ADDR_F2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"11000000";
154 CONSTANT BASE_ADDR_F2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"11000000";
152 -----------------------------------------------------------------------------
155 -----------------------------------------------------------------------------
153 SIGNAL close_file : STD_LOGIC := '0';
156 SIGNAL close_file : STD_LOGIC := '0';
154
157
155 BEGIN
158 BEGIN
156
159
157 -----------------------------------------------------------------------------
160 -----------------------------------------------------------------------------
158
161
159 clk <= NOT clk AFTER 20 ns;
162 clk <= NOT clk AFTER 20 ns;
160 new_fine_time <= NOT new_fine_time AFTER 15258 ns;
163 new_fine_time <= NOT new_fine_time AFTER 15258 ns;
161
164
162 PROCESS
165 PROCESS
163 BEGIN -- PROCESS
166 BEGIN -- PROCESS
164 WAIT UNTIL clk = '1';
167 WAIT UNTIL clk = '1';
165 close_file <= '0';
168 close_file <= '0';
166 rstn <= '0';
169 rstn <= '0';
167 start <= '0';
170 start <= '0';
168 WAIT UNTIL clk = '1';
171 WAIT UNTIL clk = '1';
169 rstn <= '1';
172 rstn <= '1';
170 WAIT UNTIL clk = '1';
173 WAIT UNTIL clk = '1';
171 WAIT UNTIL clk = '1';
174 WAIT UNTIL clk = '1';
172 WAIT UNTIL clk = '1';
175 WAIT UNTIL clk = '1';
173 WAIT UNTIL clk = '1';
176 WAIT UNTIL clk = '1';
174 start <= '1';
177 start <= '1';
175 WHILE NOT (end_of_file = "111") LOOP
178 WHILE NOT (end_of_file = "111") LOOP
176 WAIT UNTIL clk = '1';
179 WAIT UNTIL clk = '1';
177 END LOOP;
180 END LOOP;
178 REPORT "*** END READ FILE ***";-- SEVERITY failure;
181 REPORT "*** END READ FILE ***";-- SEVERITY failure;
179 WAIT FOR 3 ms;
182 WAIT FOR 3 ms;
180 close_file <= '1';
183 close_file <= '1';
181 WAIT UNTIL clk = '1';
184 WAIT UNTIL clk = '1';
182 WAIT UNTIL clk = '1';
185 WAIT UNTIL clk = '1';
183 WAIT UNTIL clk = '1';
186 WAIT UNTIL clk = '1';
184 end_of_sim <= '1';
187 end_of_sim <= '1';
185 WAIT FOR 100 ns;
188 WAIT FOR 100 ns;
186 REPORT "*** END SIMULATION ***" SEVERITY failure;
189 REPORT "*** END SIMULATION ***" SEVERITY failure;
187 WAIT;
190 WAIT;
188 END PROCESS;
191 END PROCESS;
189
192
190 -----------------------------------------------------------------------------
193 -----------------------------------------------------------------------------
191 -- TIME
194 -- TIME
192 -----------------------------------------------------------------------------
195 -----------------------------------------------------------------------------
193 PROCESS (clk, rstn)
196 PROCESS (clk, rstn)
194 BEGIN -- PROCESS
197 BEGIN -- PROCESS
195 IF rstn = '0' THEN -- asynchronous reset (active low)
198 IF rstn = '0' THEN -- asynchronous reset (active low)
196 start_date <= X"0000000" & "001";
199 start_date <= X"0000000" & "001";
197 coarse_time <= (OTHERS => '0');
200 coarse_time <= (OTHERS => '0');
198 fine_time <= (OTHERS => '0');
201 fine_time <= (OTHERS => '0');
199 time_counter <= 0;
202 time_counter <= 0;
200 new_fine_time_reg <= '0';
203 new_fine_time_reg <= '0';
201 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
204 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
202 new_fine_time_reg <= new_fine_time;
205 new_fine_time_reg <= new_fine_time;
203 IF start = '1' THEN
206 IF start = '1' THEN
204 IF coarse_time(30 downto 0) = X"0000000" & "000" THEN
207 IF coarse_time(30 downto 0) = X"0000000" & "000" THEN
205 coarse_time(30 downto 0) <= start_date;
208 coarse_time(30 downto 0) <= start_date;
206 ELSE
209 ELSE
207 IF new_fine_time = NOT new_fine_time_reg THEN
210 IF new_fine_time = NOT new_fine_time_reg THEN
208 IF fine_time = X"FFFF" THEN
211 IF fine_time = X"FFFF" THEN
209 coarse_time <= STD_LOGIC_VECTOR(UNSIGNED(coarse_time) + 1);
212 coarse_time <= STD_LOGIC_VECTOR(UNSIGNED(coarse_time) + 1);
210 fine_time <= (OTHERS => '0');
213 fine_time <= (OTHERS => '0');
211 ELSE
214 ELSE
212 fine_time <= STD_LOGIC_VECTOR(UNSIGNED(fine_time) + 1);
215 fine_time <= STD_LOGIC_VECTOR(UNSIGNED(fine_time) + 1);
213 END IF;
216 END IF;
214 END IF;
217 END IF;
215 END IF;
218 END IF;
216 END IF;
219 END IF;
217 END IF;
220 END IF;
218 END PROCESS;
221 END PROCESS;
219
222
220 -----------------------------------------------------------------------------
223 -----------------------------------------------------------------------------
221 -- DATA IN
224 -- DATA IN
222 -----------------------------------------------------------------------------
225 -----------------------------------------------------------------------------
223 data_read_with_timer_f0 : data_read_with_timer
226 data_read_with_timer_f0 : data_read_with_timer
224 GENERIC MAP (input_file_name_f0, 4*5, NB_CYCLE_f0)
227 GENERIC MAP (input_file_name_f0, 4*5, NB_CYCLE_f0)
225 PORT MAP (clk, rstn, end_of_file(0), data_out_val(0), sample_f0_wdata(16*5-1 downto 0));
228 PORT MAP (clk, rstn, end_of_file(0), data_out_val(0), sample_f0_wdata(16*5-1 downto 0));
226 sample_f0_wen <= NOT data_out_val(0);
229 sample_f0_wen <= NOT data_out_val(0);
227
230
228 data_read_with_timer_f1 : data_read_with_timer
231 data_read_with_timer_f1 : data_read_with_timer
229 GENERIC MAP (input_file_name_f1, 4*5, NB_CYCLE_f1)
232 GENERIC MAP (input_file_name_f1, 4*5, NB_CYCLE_f1)
230 PORT MAP (clk, rstn, end_of_file(1), data_out_val(1), sample_f1_wdata(16*5-1 downto 0));
233 PORT MAP (clk, rstn, end_of_file(1), data_out_val(1), sample_f1_wdata(16*5-1 downto 0));
231 sample_f1_wen <= NOT data_out_val(1);
234 sample_f1_wen <= NOT data_out_val(1);
232
235
233 data_read_with_timer_f2 : data_read_with_timer
236 data_read_with_timer_f2 : data_read_with_timer
234 GENERIC MAP (input_file_name_f2, 4*5, NB_CYCLE_f2)
237 GENERIC MAP (input_file_name_f2, 4*5, NB_CYCLE_f2)
235 PORT MAP (clk, rstn, end_of_file(2), data_out_val(2), sample_f2_wdata(16*5-1 downto 0));
238 PORT MAP (clk, rstn, end_of_file(2), data_out_val(2), sample_f2_wdata(16*5-1 downto 0));
236 sample_f2_wen <= NOT data_out_val(2);
239 sample_f2_wen <= NOT data_out_val(2);
237
240
238 -----------------------------------------------------------------------------
241 -----------------------------------------------------------------------------
239 -- DATA OUT
242 -- DATA OUT
240 -----------------------------------------------------------------------------
243 -----------------------------------------------------------------------------
241 --dma_fifo_burst_valid -- in
244 --dma_fifo_burst_valid -- in
242 --dma_fifo_data -- in
245 --dma_fifo_data -- in
243 --dma_fifo_ren -- OUT
246 --dma_fifo_ren -- OUT
244 --dma_fifo_ren <= '0';
247 --dma_fifo_ren <= '0';
245
248
246 --PROCESS (clk, rstn)
249 --PROCESS (clk, rstn)
247 --BEGIN -- PROCESS
250 --BEGIN -- PROCESS
248 -- IF rstn = '0' THEN -- asynchronous reset (active low)
251 -- IF rstn = '0' THEN -- asynchronous reset (active low)
249 -- dma_ren_counter <= 0;
252 -- dma_ren_counter <= 0;
250 -- dma_fifo_ren <= '1';
253 -- dma_fifo_ren <= '1';
251 -- ELSIF clk'event AND clk = '1' THEN -- rising clock edge
254 -- ELSIF clk'event AND clk = '1' THEN -- rising clock edge
252 -- dma_fifo_ren <= '1';
255 -- dma_fifo_ren <= '1';
253 -- IF dma_ren_counter = 0 AND dma_fifo_burst_valid = '1' THEN
256 -- IF dma_ren_counter = 0 AND dma_fifo_burst_valid = '1' THEN
254 -- dma_ren_counter <= 16;
257 -- dma_ren_counter <= 16;
255 -- END IF;
258 -- END IF;
256 -- IF dma_ren_counter > 0 THEN
259 -- IF dma_ren_counter > 0 THEN
257 -- dma_ren_counter <= dma_ren_counter - 1;
260 -- dma_ren_counter <= dma_ren_counter - 1;
258 -- dma_fifo_ren <= '0';
261 -- dma_fifo_ren <= '0';
259 -- END IF;
262 -- END IF;
260
263
261 -- END IF;
264 -- END IF;
262 --END PROCESS;
265 --END PROCESS;
263
266
264 data_write_with_burstCounter_0: data_write_with_burstCounter
267 data_write_with_burstCounter_0: data_write_with_burstCounter
265 GENERIC MAP (
268 GENERIC MAP (
266 OUTPUT_FILE_NAME => output_file_name_f0,
269 OUTPUT_FILE_NAME => output_file_name_f0,
267 NB_CHAR_PER_DATA => 32/4,
270 NB_CHAR_PER_DATA => 32/4,
268 BASE_ADDR => BASE_ADDR_F0)
271 BASE_ADDR => BASE_ADDR_F0)
269 PORT MAP (
272 PORT MAP (
270 clk => clk,
273 clk => clk,
271 rstn => rstn,
274 rstn => rstn,
272 burst_addr => dma_buffer_addr,
275 burst_addr => dma_buffer_addr,
273 burst_valid => dma_fifo_burst_valid,
276 burst_valid => dma_fifo_burst_valid,
274 data_ren => dma_fifo_ren_f0,
277 data_ren => dma_fifo_ren_f0,
275 data => dma_fifo_data,
278 data => dma_fifo_data,
276 close_file => close_file);
279 close_file => close_file);
277
280
278 data_write_with_burstCounter_1: data_write_with_burstCounter
281 data_write_with_burstCounter_1: data_write_with_burstCounter
279 GENERIC MAP (
282 GENERIC MAP (
280 OUTPUT_FILE_NAME => output_file_name_f1,
283 OUTPUT_FILE_NAME => output_file_name_f1,
281 NB_CHAR_PER_DATA => 32/4,
284 NB_CHAR_PER_DATA => 32/4,
282 BASE_ADDR => BASE_ADDR_F1)
285 BASE_ADDR => BASE_ADDR_F1)
283 PORT MAP (
286 PORT MAP (
284 clk => clk,
287 clk => clk,
285 rstn => rstn,
288 rstn => rstn,
286 burst_addr => dma_buffer_addr,
289 burst_addr => dma_buffer_addr,
287 burst_valid => dma_fifo_burst_valid,
290 burst_valid => dma_fifo_burst_valid,
288 data_ren => dma_fifo_ren_f1,
291 data_ren => dma_fifo_ren_f1,
289 data => dma_fifo_data,
292 data => dma_fifo_data,
290 close_file => close_file);
293 close_file => close_file);
291
294
292 data_write_with_burstCounter_2: data_write_with_burstCounter
295 data_write_with_burstCounter_2: data_write_with_burstCounter
293 GENERIC MAP (
296 GENERIC MAP (
294 OUTPUT_FILE_NAME => output_file_name_f2,
297 OUTPUT_FILE_NAME => output_file_name_f2,
295 NB_CHAR_PER_DATA => 32/4,
298 NB_CHAR_PER_DATA => 32/4,
296 BASE_ADDR => BASE_ADDR_F2)
299 BASE_ADDR => BASE_ADDR_F2)
297 PORT MAP (
300 PORT MAP (
298 clk => clk,
301 clk => clk,
299 rstn => rstn,
302 rstn => rstn,
300 burst_addr => dma_buffer_addr,
303 burst_addr => dma_buffer_addr,
301 burst_valid => dma_fifo_burst_valid,
304 burst_valid => dma_fifo_burst_valid,
302 data_ren => dma_fifo_ren_f2,
305 data_ren => dma_fifo_ren_f2,
303 data => dma_fifo_data,
306 data => dma_fifo_data,
304 close_file => close_file);
307 close_file => close_file);
305
308
306 dma_fifo_ren <= dma_fifo_ren_f0 AND dma_fifo_ren_f1 AND dma_fifo_ren_f2;
309 dma_fifo_ren <= dma_fifo_ren_f0 AND dma_fifo_ren_f1 AND dma_fifo_ren_f2;
307
310
308
311
309 PROCESS (clk, rstn)
312 PROCESS (clk, rstn)
310 BEGIN -- PROCESS
313 BEGIN -- PROCESS
311 IF rstn = '0' THEN -- asynchronous reset (active low)
314 IF rstn = '0' THEN -- asynchronous reset (active low)
312 dma_buffer_full <= '0';
315 dma_buffer_full <= '0';
313 dma_buffer_full_err <= '0';
316 dma_buffer_full_err <= '0';
314 dma_output_counter <= 0;
317 dma_output_counter <= 0;
315 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
318 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
316 dma_buffer_full <= '0';
319 dma_buffer_full <= '0';
317
320
318 IF dma_buffer_new = '1' THEN
321 IF dma_buffer_new = '1' THEN
319 dma_output_counter <= to_integer(UNSIGNED(dma_buffer_length));
322 dma_output_counter <= to_integer(UNSIGNED(dma_buffer_length));
320 END IF;
323 END IF;
321
324
322 IF dma_fifo_ren = '0' THEN
325 IF dma_fifo_ren = '0' THEN
323 IF dma_output_counter = 1 THEN
326 IF dma_output_counter = 1 THEN
324 dma_buffer_full <= '1';
327 dma_buffer_full <= '1';
325 dma_output_counter <= 0;
328 dma_output_counter <= 0;
326 ELSE
329 ELSE
327 dma_output_counter <= dma_output_counter - 1;
330 dma_output_counter <= dma_output_counter - 1;
328 END IF;
331 END IF;
329 END IF;
332 END IF;
330
333
331 END IF;
334 END IF;
332 END PROCESS;
335 END PROCESS;
333
336
334 --dma_buffer_new -- in
337 --dma_buffer_new -- in
335 --dma_buffer_addr -- in
338 --dma_buffer_addr -- in
336 --dma_buffer_length -- in
339 --dma_buffer_length -- in
337 --dma_buffer_full -- out
340 --dma_buffer_full -- out
338 --dma_buffer_full_err -- OUT
341 --dma_buffer_full_err -- OUT
339 -- dma_buffer_full <= '0';
342 -- dma_buffer_full <= '0';
340 -- dma_buffer_full_err <= '0';
343 -- dma_buffer_full_err <= '0';
341
344
342 -----------------------------------------------------------------------------
345 -----------------------------------------------------------------------------
343 -- BUFFER CONFIGURATION and INFORMATION
346 -- BUFFER CONFIGURATION and INFORMATION
344 -----------------------------------------------------------------------------
347 -----------------------------------------------------------------------------
345 PROCESS (clk, rstn)
348 PROCESS (clk, rstn)
346 BEGIN -- PROCESS
349 BEGIN -- PROCESS
347 IF rstn = '0' THEN -- asynchronous reset (active low)
350 IF rstn = '0' THEN -- asynchronous reset (active low)
348 status_ready_matrix_f0 <= '0';
351 status_ready_matrix_f0 <= '0';
349 status_ready_matrix_f1 <= '0';
352 status_ready_matrix_f1 <= '0';
350 status_ready_matrix_f2 <= '0';
353 status_ready_matrix_f2 <= '0';
351 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
354 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
352 status_ready_matrix_f0 <= ready_matrix_f0;
355 status_ready_matrix_f0 <= ready_matrix_f0;
353 status_ready_matrix_f1 <= ready_matrix_f1;
356 status_ready_matrix_f1 <= ready_matrix_f1;
354 status_ready_matrix_f2 <= ready_matrix_f2;
357 status_ready_matrix_f2 <= ready_matrix_f2;
355 END IF;
358 END IF;
356 END PROCESS;
359 END PROCESS;
357
360
358 addr_matrix_f0 <= BASE_ADDR_F0;
361 addr_matrix_f0 <= BASE_ADDR_F0;
359 addr_matrix_f1 <= BASE_ADDR_F1;
362 addr_matrix_f1 <= BASE_ADDR_F1;
360 addr_matrix_f2 <= BASE_ADDR_F2;
363 addr_matrix_f2 <= BASE_ADDR_F2;
361
364
362 length_matrix_f0 <= "00" & X"000C80";
365 length_matrix_f0 <= "00" & X"000C80";
363 length_matrix_f1 <= "00" & X"000C80";
366 length_matrix_f1 <= "00" & X"000C80";
364 length_matrix_f2 <= "00" & X"000C80";
367 length_matrix_f2 <= "00" & X"000C80";
365
368
366 sample_f0_wen_v <= sample_f0_wen & sample_f0_wen & sample_f0_wen & sample_f0_wen & sample_f0_wen;
369 sample_f0_wen_v <= sample_f0_wen & sample_f0_wen & sample_f0_wen & sample_f0_wen & sample_f0_wen;
367 sample_f1_wen_v <= sample_f1_wen & sample_f1_wen & sample_f1_wen & sample_f1_wen & sample_f1_wen;
370 sample_f1_wen_v <= sample_f1_wen & sample_f1_wen & sample_f1_wen & sample_f1_wen & sample_f1_wen;
368 sample_f2_wen_v <= sample_f2_wen & sample_f2_wen & sample_f2_wen & sample_f2_wen & sample_f2_wen;
371 sample_f2_wen_v <= sample_f2_wen & sample_f2_wen & sample_f2_wen & sample_f2_wen & sample_f2_wen;
369
372
373 sample_f0_time <= coarse_time & fine_time;
374 sample_f1_time <= coarse_time & fine_time;
375 sample_f2_time <= coarse_time & fine_time;
376
370 -----------------------------------------------------------------------------
377 -----------------------------------------------------------------------------
371 -- DUT
378 -- DUT
372 -----------------------------------------------------------------------------
379 -----------------------------------------------------------------------------
373 lpp_lfr_ms_1 : lpp_lfr_ms
380 lpp_lfr_ms_1 : lpp_lfr_ms
374 GENERIC MAP (
381 GENERIC MAP (
375 Mem_use => use_RAM)
382 Mem_use => use_RAM)
376 PORT MAP (
383 PORT MAP (
377 clk => clk,
384 clk => clk,
378 rstn => rstn,
385 rstn => rstn,
379 run => '1',
386 run => '1',
380
387
381 -----------------------------------------------------------------------------
388 -----------------------------------------------------------------------------
382 -- TIME
389 -- TIME
383 -----------------------------------------------------------------------------
390 -----------------------------------------------------------------------------
384 start_date => start_date,
391 start_date => start_date,
385 coarse_time => coarse_time,
392 coarse_time => coarse_time,
386 fine_time => fine_time,
393 -- fine_time => fine_time,
387
394
388 -------------------------------------------------------------------------
395 -------------------------------------------------------------------------
389 -- DATA IN
396 -- DATA IN
390 -------------------------------------------------------------------------
397 -------------------------------------------------------------------------
391 sample_f0_wen => sample_f0_wen_v, --
398 sample_f0_wen => sample_f0_wen_v, --
392 sample_f0_wdata => sample_f0_wdata,
399 sample_f0_wdata => sample_f0_wdata,
400 sample_f0_time => sample_f0_time,
393 sample_f1_wen => sample_f1_wen_v,
401 sample_f1_wen => sample_f1_wen_v,
394 sample_f1_wdata => sample_f1_wdata,
402 sample_f1_wdata => sample_f1_wdata,
403 sample_f1_time => sample_f1_time,
395 sample_f2_wen => sample_f2_wen_v,
404 sample_f2_wen => sample_f2_wen_v,
396 sample_f2_wdata => sample_f2_wdata,
405 sample_f2_wdata => sample_f2_wdata,
406 sample_f2_time => sample_f2_time,
397
407
398 -------------------------------------------------------------------------
408 -------------------------------------------------------------------------
399 -- DMA OUT
409 -- DMA OUT
400 -------------------------------------------------------------------------
410 -------------------------------------------------------------------------
401 dma_fifo_burst_valid => dma_fifo_burst_valid, --out
411 dma_fifo_burst_valid => dma_fifo_burst_valid, --out
402 dma_fifo_data => dma_fifo_data, --out
412 dma_fifo_data => dma_fifo_data, --out
403 dma_fifo_ren => dma_fifo_ren, --in
413 dma_fifo_ren => dma_fifo_ren, --in
404 dma_buffer_new => dma_buffer_new, --out
414 dma_buffer_new => dma_buffer_new, --out
405 dma_buffer_addr => dma_buffer_addr, --out
415 dma_buffer_addr => dma_buffer_addr, --out
406 dma_buffer_length => dma_buffer_length, --out
416 dma_buffer_length => dma_buffer_length, --out
407 dma_buffer_full => dma_buffer_full, --in
417 dma_buffer_full => dma_buffer_full, --in
408 dma_buffer_full_err => dma_buffer_full_err, --in
418 dma_buffer_full_err => dma_buffer_full_err, --in
409
419
410 -------------------------------------------------------------------------
420 -------------------------------------------------------------------------
411 -- BUFFER CONFIGURATION and INFORMATION
421 -- BUFFER CONFIGURATION and INFORMATION
412 -------------------------------------------------------------------------
422 -------------------------------------------------------------------------
413 ready_matrix_f0 => ready_matrix_f0, --out
423 ready_matrix_f0 => ready_matrix_f0, --out
414 ready_matrix_f1 => ready_matrix_f1, --out
424 ready_matrix_f1 => ready_matrix_f1, --out
415 ready_matrix_f2 => ready_matrix_f2, --out
425 ready_matrix_f2 => ready_matrix_f2, --out
416
426
417 error_buffer_full => OPEN,
427 error_buffer_full => OPEN,
418 error_input_fifo_write => OPEN,
428 error_input_fifo_write => OPEN,
419
429
420 status_ready_matrix_f0 => status_ready_matrix_f0, --in
430 status_ready_matrix_f0 => status_ready_matrix_f0, --in
421 status_ready_matrix_f1 => status_ready_matrix_f1, --in
431 status_ready_matrix_f1 => status_ready_matrix_f1, --in
422 status_ready_matrix_f2 => status_ready_matrix_f2, --in
432 status_ready_matrix_f2 => status_ready_matrix_f2, --in
423
433
424 addr_matrix_f0 => addr_matrix_f0, --in
434 addr_matrix_f0 => addr_matrix_f0, --in
425 addr_matrix_f1 => addr_matrix_f1, --in
435 addr_matrix_f1 => addr_matrix_f1, --in
426 addr_matrix_f2 => addr_matrix_f2, --in
436 addr_matrix_f2 => addr_matrix_f2, --in
427
437
428 length_matrix_f0 => length_matrix_f0, --in
438 length_matrix_f0 => length_matrix_f0, --in
429 length_matrix_f1 => length_matrix_f1, --in
439 length_matrix_f1 => length_matrix_f1, --in
430 length_matrix_f2 => length_matrix_f2, --in
440 length_matrix_f2 => length_matrix_f2, --in
431
441
432 matrix_time_f0 => matrix_time_f0, --out
442 matrix_time_f0 => matrix_time_f0, --out
433 matrix_time_f1 => matrix_time_f1, --out
443 matrix_time_f1 => matrix_time_f1, --out
434 matrix_time_f2 => matrix_time_f2, --out
444 matrix_time_f2 => matrix_time_f2, --out
435
445
436 debug_vector => OPEN);
446 debug_vector => OPEN);
437
447
438 END;
448 END;
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@@ -1,39 +1,199
1 onerror {resume}
1 onerror {resume}
2 quietly virtual signal -install /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix { /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/rdata(31 downto 0)} data_0
3 quietly virtual signal -install /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix { /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/rdata(63 downto 32)} data_1
4 quietly virtual signal -install /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix { /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/rdata(95 downto 64)} data_2
5 quietly virtual signal -install /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix { /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/rdata(127 downto 96)} data_3
6 quietly virtual signal -install /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix { /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/rdata(159 downto 128)} data_4
7 quietly virtual signal -install /testbench/data_read_with_timer_f0 { /testbench/data_read_with_timer_f0/data_out(15 downto 0)} f0_0
8 quietly virtual signal -install /testbench/data_read_with_timer_f0 { /testbench/data_read_with_timer_f0/data_out(31 downto 16)} f0_1
9 quietly virtual signal -install /testbench/data_read_with_timer_f0 { /testbench/data_read_with_timer_f0/data_out(47 downto 32)} f0_2
10 quietly virtual signal -install /testbench/data_read_with_timer_f0 { /testbench/data_read_with_timer_f0/data_out(63 downto 48)} f0_4
11 quietly virtual signal -install /testbench/data_read_with_timer_f0 { /testbench/data_read_with_timer_f0/data_out(79 downto 64)} f0_4001
2 quietly WaveActivateNextPane {} 0
12 quietly WaveActivateNextPane {} 0
3 add wave -noupdate -expand -group DATA_GEN_F0 /testbench/data_read_with_timer_f0/data_out_val
13 add wave -noupdate -expand -group DATA_GEN_F0 /testbench/data_read_with_timer_f0/data_out_val
4 add wave -noupdate -expand -group DATA_GEN_F0 /testbench/data_read_with_timer_f0/end_of_file
14 add wave -noupdate -expand -group DATA_GEN_F0 /testbench/data_read_with_timer_f0/end_of_file
15 add wave -noupdate -expand -group DATA_GEN_F0 -label f0_0 -radix decimal /testbench/data_read_with_timer_f0/f0_0
16 add wave -noupdate -expand -group DATA_GEN_F0 -label f0_1 -radix decimal /testbench/data_read_with_timer_f0/f0_1
17 add wave -noupdate -expand -group DATA_GEN_F0 -label f0_2 -radix decimal /testbench/data_read_with_timer_f0/f0_2
18 add wave -noupdate -expand -group DATA_GEN_F0 -label f0_3 -radix decimal /testbench/data_read_with_timer_f0/f0_4
19 add wave -noupdate -expand -group DATA_GEN_F0 -label f0_4 -radix decimal /testbench/data_read_with_timer_f0/f0_4001
5 add wave -noupdate -expand -group DATA_GEN_F0 /testbench/data_read_with_timer_f0/data_out
20 add wave -noupdate -expand -group DATA_GEN_F0 /testbench/data_read_with_timer_f0/data_out
6 add wave -noupdate -expand -group DATA_GEN_F1 /testbench/data_read_with_timer_f1/data_out_val
21 add wave -noupdate -expand -group DATA_GEN_F1 /testbench/data_read_with_timer_f1/data_out_val
7 add wave -noupdate -expand -group DATA_GEN_F1 /testbench/data_read_with_timer_f1/end_of_file
22 add wave -noupdate -expand -group DATA_GEN_F1 /testbench/data_read_with_timer_f1/end_of_file
8 add wave -noupdate -expand -group DATA_GEN_F1 /testbench/data_read_with_timer_f1/data_out
23 add wave -noupdate -expand -group DATA_GEN_F1 /testbench/data_read_with_timer_f1/data_out
9 add wave -noupdate -expand -group DATA_GEN_F2 /testbench/data_read_with_timer_f2/data_out_val
24 add wave -noupdate -expand -group DATA_GEN_F2 /testbench/data_read_with_timer_f2/data_out_val
10 add wave -noupdate -expand -group DATA_GEN_F2 /testbench/data_read_with_timer_f2/end_of_file
25 add wave -noupdate -expand -group DATA_GEN_F2 /testbench/data_read_with_timer_f2/end_of_file
11 add wave -noupdate -expand -group DATA_GEN_F2 /testbench/data_read_with_timer_f2/data_out
26 add wave -noupdate -expand -group DATA_GEN_F2 /testbench/data_read_with_timer_f2/data_out
12 add wave -noupdate -expand -group DMA_interface /testbench/lpp_lfr_ms_1/dma_buffer_addr
27 add wave -noupdate -expand -group DMA_interface /testbench/lpp_lfr_ms_1/dma_buffer_addr
13 add wave -noupdate -expand -group DMA_interface /testbench/lpp_lfr_ms_1/dma_buffer_full
28 add wave -noupdate -expand -group DMA_interface /testbench/lpp_lfr_ms_1/dma_buffer_full
14 add wave -noupdate -expand -group DMA_interface /testbench/lpp_lfr_ms_1/dma_buffer_full_err
29 add wave -noupdate -expand -group DMA_interface /testbench/lpp_lfr_ms_1/dma_buffer_full_err
15 add wave -noupdate -expand -group DMA_interface /testbench/lpp_lfr_ms_1/dma_buffer_length
30 add wave -noupdate -expand -group DMA_interface /testbench/lpp_lfr_ms_1/dma_buffer_length
16 add wave -noupdate -expand -group DMA_interface /testbench/lpp_lfr_ms_1/dma_buffer_new
31 add wave -noupdate -expand -group DMA_interface /testbench/lpp_lfr_ms_1/dma_buffer_new
17 add wave -noupdate -expand -group DMA_interface /testbench/lpp_lfr_ms_1/dma_fifo_burst_valid
32 add wave -noupdate -expand -group DMA_interface /testbench/lpp_lfr_ms_1/dma_fifo_burst_valid
18 add wave -noupdate -expand -group DMA_interface /testbench/lpp_lfr_ms_1/dma_fifo_data
33 add wave -noupdate -expand -group DMA_interface /testbench/lpp_lfr_ms_1/dma_fifo_data
19 add wave -noupdate -expand -group DMA_interface /testbench/lpp_lfr_ms_1/dma_fifo_ren
34 add wave -noupdate -expand -group DMA_interface /testbench/lpp_lfr_ms_1/dma_fifo_ren
20 add wave -noupdate /testbench/dma_ren_counter
35 add wave -noupdate /testbench/dma_ren_counter
21 add wave -noupdate /testbench/dma_output_counter
36 add wave -noupdate /testbench/dma_output_counter
37 add wave -noupdate -expand -group MEM_IN_MS -radix hexadecimal -childformat {{/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(0) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(1) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(2) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(3) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(4) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(5) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(6) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(7) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(8) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(9) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(10) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(11) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(12) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(13) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(14) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(15) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(16) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(17) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(18) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(19) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(20) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(21) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(22) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(23) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(24) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(25) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(26) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(27) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(28) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(29) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(30) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(31) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(32) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(33) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(34) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(35) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(36) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(37) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(38) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(39) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(40) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(41) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(42) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(43) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(44) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(45) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(46) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(47) -radix hexadecimal} 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/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(40) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(41) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(42) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(43) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(44) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(45) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(46) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(47) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(48) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(49) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(50) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(51) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(52) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(53) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(54) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(55) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(56) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(57) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(58) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(59) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(60) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(61) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(62) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(63) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(64) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(65) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(66) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(67) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(68) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(69) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(70) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(71) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(72) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(73) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(74) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(75) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(76) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(77) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(78) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(79) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(80) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(81) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(82) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(83) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(84) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(85) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(86) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(87) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(88) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(89) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(90) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(91) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(92) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(93) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(94) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(95) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(96) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(97) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(98) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(99) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(100) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(101) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(102) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(103) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(104) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(105) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(106) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(107) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(108) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(109) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(110) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(111) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(112) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(113) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(114) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(115) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(116) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(117) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(118) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(119) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(120) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(121) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(122) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(123) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(124) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(125) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(126) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(127) {-height 15 -radix hexadecimal}} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd
42 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/data_0
43 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/ren(0)
44 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/wen(0)
45 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/full(0)
46 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/empty(0)
47 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/ReUse(0)
48 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group fif0_1 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/data_1
49 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group fif0_1 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/ren(1)
50 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group fif0_1 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/wen(1)
51 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group fif0_1 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/full(1)
52 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group fif0_1 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/empty(1)
53 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group fif0_1 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/ReUse(1)
54 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_2 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/data_2
55 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_2 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/ren(2)
56 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_2 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/wen(2)
57 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_2 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/full(2)
58 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_2 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/empty(2)
59 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_2 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/ReUse(2)
60 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_3 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/data_3
61 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_3 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/ren(3)
62 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_3 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/wen(3)
63 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_3 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/full(3)
64 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_3 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/empty(3)
65 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_3 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/ReUse(3)
66 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_4 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/data_4
67 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_4 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/ren(4)
68 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_4 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/wen(4)
69 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_4 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/full(4)
70 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_4 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/empty(4)
71 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_4 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/ReUse(4)
72 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(0)/Mem_Out_SpectralMatrix_I/full_threshold
73 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(0)/Mem_Out_SpectralMatrix_I/full
74 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(0)/Mem_Out_SpectralMatrix_I/empty
75 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(0)/Mem_Out_SpectralMatrix_I/full_almost
76 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(0)/Mem_Out_SpectralMatrix_I/empty_threshold
77 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(0)/Mem_Out_SpectralMatrix_I/wen
78 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(0)/Mem_Out_SpectralMatrix_I/wdata
79 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(0)/Mem_Out_SpectralMatrix_I/ren
80 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(0)/Mem_Out_SpectralMatrix_I/rdata
81 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(0)/Mem_Out_SpectralMatrix_I/run
82 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(0)/Mem_Out_SpectralMatrix_I/reUse
83 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_1 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/full_threshold
84 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_1 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/full
85 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_1 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/empty
86 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_1 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/full_almost
87 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_1 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/empty_threshold
88 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_1 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/wen
89 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_1 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/wdata
90 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_1 -radix decimal -childformat {{/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(31) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(30) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(29) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(28) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(27) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(26) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(25) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(24) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(23) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(22) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(21) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(20) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(19) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(18) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(17) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(16) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(15) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(14) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(13) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(12) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(11) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(10) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(9) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(8) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(7) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(6) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(5) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(4) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(3) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(2) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(1) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(0) -radix hexadecimal}} -subitemconfig {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(31) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(30) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(29) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(28) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(27) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(26) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(25) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(24) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(23) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(22) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(21) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(20) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(19) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(18) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(17) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(16) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(15) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(14) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(13) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(12) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(11) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(10) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(9) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(8) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(7) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(6) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(5) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(4) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(3) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(2) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(1) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(0) {-height 15 -radix hexadecimal}} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata
91 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_1 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/ren
92 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_1 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/run
93 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_1 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/reUse
94 add wave -noupdate -radix hexadecimal /testbench/lpp_lfr_ms_1/dma_fifo_data
95 add wave -noupdate -expand -group ALU_MS -radix decimal /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/RES
96 add wave -noupdate -expand -group ALU_MS -radix decimal -childformat {{/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(15) -radix decimal} {/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(14) -radix decimal} {/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(13) -radix decimal} {/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(12) -radix decimal} {/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(11) -radix decimal} {/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(10) -radix decimal} {/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(9) -radix decimal} {/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(8) -radix decimal} {/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(7) -radix decimal} {/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(6) -radix decimal} {/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(5) -radix decimal} {/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(4) -radix decimal} {/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(3) -radix decimal} {/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(2) -radix decimal} {/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(1) -radix decimal} {/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(0) -radix decimal}} -subitemconfig {/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(15) {-height 15 -radix decimal} /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(14) {-height 15 -radix decimal} /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(13) {-height 15 -radix decimal} /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(12) {-height 15 -radix decimal} /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(11) {-height 15 -radix decimal} /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(10) {-height 15 -radix decimal} /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(9) {-height 15 -radix decimal} /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(8) {-height 15 -radix decimal} /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(7) {-height 15 -radix decimal} /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(6) {-height 15 -radix decimal} /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(5) {-height 15 -radix decimal} /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(4) {-height 15 -radix decimal} /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(3) {-height 15 -radix decimal} /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(2) {-height 15 -radix decimal} /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(1) {-height 15 -radix decimal} /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(0) {-height 15 -radix decimal}} /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2
97 add wave -noupdate -expand -group ALU_MS -radix decimal /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP1
98 add wave -noupdate -expand -group ALU_MS -radix hexadecimal /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/comp
99 add wave -noupdate -expand -group ALU_MS -radix hexadecimal /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/ctrl
100 add wave -noupdate /testbench/lpp_lfr_ms_1/MS_control_1/state
101 add wave -noupdate /testbench/lpp_lfr_ms_1/MS_calculation_1/state
102 add wave -noupdate -radix hexadecimal /testbench/lpp_lfr_ms_1/MS_calculation_1/fifo_in_data
103 add wave -noupdate /testbench/lpp_lfr_ms_1/MS_calculation_1/fifo_in_ren
104 add wave -noupdate /testbench/lpp_lfr_ms_1/MEM_OUT_SM_Full
105 add wave -noupdate /testbench/lpp_lfr_ms_1/MEM_OUT_SM_Full_s
106 add wave -noupdate /testbench/lpp_lfr_ms_1/SM_correlation_done
107 add wave -noupdate /testbench/lpp_lfr_ms_1/SM_correlation_done_reg1
108 add wave -noupdate /testbench/lpp_lfr_ms_1/SM_correlation_done_reg2
109 add wave -noupdate /testbench/lpp_lfr_ms_1/SM_correlation_done_reg3
110 add wave -noupdate /testbench/lpp_lfr_ms_1/current_matrix_wait_empty
111 add wave -noupdate /testbench/lpp_lfr_ms_1/current_matrix_write
112 add wave -noupdate /testbench/lpp_lfr_ms_1/MEM_OUT_SM_Empty
113 add wave -noupdate /testbench/lpp_lfr_ms_1/dma_fifo_ren
114 add wave -noupdate /testbench/lpp_lfr_ms_1/addr_matrix_f2
115 add wave -noupdate /testbench/lpp_lfr_ms_1/addr_matrix_f1
116 add wave -noupdate /testbench/lpp_lfr_ms_1/length_matrix_f2
117 add wave -noupdate /testbench/lpp_lfr_ms_1/dma_buffer_full
118 add wave -noupdate /testbench/lpp_lfr_ms_1/dma_buffer_full_err
119 add wave -noupdate /testbench/lpp_lfr_ms_1/addr_matrix_f0
120 add wave -noupdate /testbench/lpp_lfr_ms_1/status_ready_matrix_f2
121 add wave -noupdate /testbench/lpp_lfr_ms_1/status_ready_matrix_f1
122 add wave -noupdate /testbench/lpp_lfr_ms_1/status_ready_matrix_f0
123 add wave -noupdate /testbench/lpp_lfr_ms_1/current_matrix_write
124 add wave -noupdate /testbench/lpp_lfr_ms_1/matrix_time_f2
125 add wave -noupdate /testbench/lpp_lfr_ms_1/matrix_time_f1
126 add wave -noupdate /testbench/lpp_lfr_ms_1/matrix_time_f0
127 add wave -noupdate /testbench/lpp_lfr_ms_1/error_input_fifo_write
128 add wave -noupdate /testbench/lpp_lfr_ms_1/error_buffer_full
129 add wave -noupdate /testbench/lpp_lfr_ms_1/ready_matrix_f2
130 add wave -noupdate /testbench/lpp_lfr_ms_1/ready_matrix_f1
131 add wave -noupdate /testbench/lpp_lfr_ms_1/ready_matrix_f0
132 add wave -noupdate /testbench/lpp_lfr_ms_1/dma_buffer_length
133 add wave -noupdate /testbench/lpp_lfr_ms_1/dma_buffer_addr
134 add wave -noupdate /testbench/lpp_lfr_ms_1/dma_buffer_new
135 add wave -noupdate /testbench/lpp_lfr_ms_1/dma_fifo_data
136 add wave -noupdate /testbench/lpp_lfr_ms_1/dma_fifo_burst_valid
137 add wave -noupdate /testbench/lpp_lfr_ms_1/debug_vector
138 add wave -noupdate /testbench/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/state
139 add wave -noupdate /testbench/lpp_lfr_ms_1/fifo_0_ready
140 add wave -noupdate /testbench/lpp_lfr_ms_1/fifo_1_ready
141 add wave -noupdate /testbench/lpp_lfr_ms_1/fifo_ongoing
142 add wave -noupdate /testbench/lpp_lfr_ms_1/status_component_fifo_0
143 add wave -noupdate /testbench/lpp_lfr_ms_1/status_component_fifo_1
144 add wave -noupdate /testbench/lpp_lfr_ms_1/status_component_fifo_0_end
145 add wave -noupdate /testbench/lpp_lfr_ms_1/status_component_fifo_1_end
146 add wave -noupdate /testbench/lpp_lfr_ms_1/MS_calculation_1/state
147 add wave -noupdate /testbench/lpp_lfr_ms_1/MS_calculation_1/fifo_in_empty
148 add wave -noupdate /testbench/lpp_lfr_ms_1/MS_calculation_1/fifo_in_empty_reg
149 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/start_date
150 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/coarse_time
151 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/sample_f0_wen
152 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/sample_f0_wdata
153 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/sample_f1_wen
154 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/sample_f1_wdata
155 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/sample_f2_wen
156 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/sample_f2_wdata
157 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/length_matrix_f1
158 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/length_matrix_f0
159 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/dma_fifo_ren
160 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/addr_matrix_f2
161 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/addr_matrix_f1
162 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/length_matrix_f2
163 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/dma_buffer_full
164 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/dma_buffer_full_err
165 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/addr_matrix_f0
166 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/status_ready_matrix_f2
167 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/status_ready_matrix_f1
168 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/status_ready_matrix_f0
169 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/matrix_time_f2
170 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/matrix_time_f1
171 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/matrix_time_f0
172 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/error_input_fifo_write
173 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/error_buffer_full
174 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/ready_matrix_f2
175 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/ready_matrix_f1
176 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/ready_matrix_f0
177 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/dma_buffer_length
178 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/dma_buffer_addr
179 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/dma_buffer_new
180 add wave -noupdate -expand -group TOP_IN_OUT -radix decimal /testbench/lpp_lfr_ms_1/dma_fifo_data
181 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/dma_fifo_burst_valid
22 TreeUpdate [SetDefaultTree]
182 TreeUpdate [SetDefaultTree]
23 WaveRestoreCursors {{Cursor 1} {10933060000 ps} 0}
183 WaveRestoreCursors {WDATA_1 {10541340000 ps} 1} {WDATA_2 {10541500000 ps} 1} {WDATA_8 {10542460000 ps} 1} {WDATA_16 {10543740000 ps} 1} {{Cursor 9} {10572740000 ps} 0} {{Cursor 10} {6346220000 ps} 0}
24 quietly wave cursor active 1
184 quietly wave cursor active 6
25 configure wave -namecolwidth 339
185 configure wave -namecolwidth 573
26 configure wave -valuecolwidth 100
186 configure wave -valuecolwidth 108
27 configure wave -justifyvalue left
187 configure wave -justifyvalue left
28 configure wave -signalnamewidth 0
188 configure wave -signalnamewidth 0
29 configure wave -snapdistance 10
189 configure wave -snapdistance 10
30 configure wave -datasetprefix 0
190 configure wave -datasetprefix 0
31 configure wave -rowmargin 4
191 configure wave -rowmargin 4
32 configure wave -childrowmargin 2
192 configure wave -childrowmargin 2
33 configure wave -gridoffset 0
193 configure wave -gridoffset 0
34 configure wave -gridperiod 1
194 configure wave -gridperiod 1
35 configure wave -griddelta 40
195 configure wave -griddelta 40
36 configure wave -timeline 0
196 configure wave -timeline 0
37 configure wave -timelineunits ns
197 configure wave -timelineunits ns
38 update
198 update
39 WaveRestoreZoom {0 ps} {42718685333 ps}
199 WaveRestoreZoom {0 ps} {14085099 ns}
Show file before | Show file after | Hide comments
@@ -1,253 +1,262
1 LIBRARY IEEE;
1 LIBRARY IEEE;
2 USE IEEE.std_logic_1164.ALL;
2 USE IEEE.std_logic_1164.ALL;
3
3
4 LIBRARY lpp;
4 LIBRARY lpp;
5 USE lpp.general_purpose.ALL;
5 USE lpp.general_purpose.ALL;
6
6
7 ENTITY MS_calculation IS
7 ENTITY MS_calculation IS
8 PORT (
8 PORT (
9 clk : IN STD_LOGIC;
9 clk : IN STD_LOGIC;
10 rstn : IN STD_LOGIC;
10 rstn : IN STD_LOGIC;
11 -- IN
11 -- IN
12 fifo_in_data : IN STD_LOGIC_VECTOR(32*2-1 DOWNTO 0);
12 fifo_in_data : IN STD_LOGIC_VECTOR(32*2-1 DOWNTO 0);
13 fifo_in_ren : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
13 fifo_in_ren : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
14 fifo_in_empty : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
14 fifo_in_empty : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
15 -- OUT
15 -- OUT
16 fifo_out_data : OUT STD_LOGIC_VECTOR(32-1 DOWNTO 0);
16 fifo_out_data : OUT STD_LOGIC_VECTOR(32-1 DOWNTO 0);
17 fifo_out_wen : OUT STD_LOGIC;
17 fifo_out_wen : OUT STD_LOGIC;
18 fifo_out_full : IN STD_LOGIC;
18 fifo_out_full : IN STD_LOGIC;
19 --
19 --
20 correlation_start : IN STD_LOGIC;
20 correlation_start : IN STD_LOGIC;
21 correlation_auto : IN STD_LOGIC; -- 1 => auto correlation / 0 => inter correlation
21 correlation_auto : IN STD_LOGIC; -- 1 => auto correlation / 0 => inter correlation
22
22
23 correlation_begin : OUT STD_LOGIC;
23 correlation_begin : OUT STD_LOGIC;
24 correlation_done : OUT STD_LOGIC
24 correlation_done : OUT STD_LOGIC
25 );
25 );
26 END MS_calculation;
26 END MS_calculation;
27
27
28 ARCHITECTURE beh OF MS_calculation IS
28 ARCHITECTURE beh OF MS_calculation IS
29
29
30 TYPE fsm_calculation_MS IS (IDLE, WF, S1, S2, S3, S4, WFa, S1a, S2a);
30 TYPE fsm_calculation_MS IS (IDLE, WF, S1, S2, S3, S4, WFa, S1a, S2a);
31 SIGNAL state : fsm_calculation_MS;
31 SIGNAL state : fsm_calculation_MS;
32
32
33 SIGNAL OP1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
33 SIGNAL OP1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
34 SIGNAL OP2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
34 SIGNAL OP2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
35 SIGNAL RES : STD_LOGIC_VECTOR(31 DOWNTO 0);
35 SIGNAL RES : STD_LOGIC_VECTOR(31 DOWNTO 0);
36
36
37 SIGNAL ALU_CTRL : STD_LOGIC_VECTOR(4 DOWNTO 0);
37 SIGNAL ALU_CTRL : STD_LOGIC_VECTOR(4 DOWNTO 0);
38
38
39
39
40 CONSTANT ALU_CTRL_NOP : STD_LOGIC_VECTOR(4 DOWNTO 0) := "00000";
40 CONSTANT ALU_CTRL_NOP : STD_LOGIC_VECTOR(4 DOWNTO 0) := "00000";
41 CONSTANT ALU_CTRL_MULT : STD_LOGIC_VECTOR(4 DOWNTO 0) := "00010";
41 CONSTANT ALU_CTRL_MULT : STD_LOGIC_VECTOR(4 DOWNTO 0) := "00010";
42 CONSTANT ALU_CTRL_MAC : STD_LOGIC_VECTOR(4 DOWNTO 0) := "00001";
42 CONSTANT ALU_CTRL_MAC : STD_LOGIC_VECTOR(4 DOWNTO 0) := "00001";
43 CONSTANT ALU_CTRL_MACn : STD_LOGIC_VECTOR(4 DOWNTO 0) := "10001";
43 CONSTANT ALU_CTRL_MACn : STD_LOGIC_VECTOR(4 DOWNTO 0) := "10001";
44
44
45 SIGNAL select_ctrl : STD_LOGIC_VECTOR(1 DOWNTO 0);
45 SIGNAL select_ctrl : STD_LOGIC_VECTOR(1 DOWNTO 0);
46 CONSTANT select_ctrl_NOP : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
46 CONSTANT select_ctrl_NOP : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
47 CONSTANT select_ctrl_MULT : STD_LOGIC_VECTOR(1 DOWNTO 0) := "01";
47 CONSTANT select_ctrl_MULT : STD_LOGIC_VECTOR(1 DOWNTO 0) := "01";
48 CONSTANT select_ctrl_MAC : STD_LOGIC_VECTOR(1 DOWNTO 0) := "10";
48 CONSTANT select_ctrl_MAC : STD_LOGIC_VECTOR(1 DOWNTO 0) := "10";
49 CONSTANT select_ctrl_MACn : STD_LOGIC_VECTOR(1 DOWNTO 0) := "11";
49 CONSTANT select_ctrl_MACn : STD_LOGIC_VECTOR(1 DOWNTO 0) := "11";
50
50
51 SIGNAL select_op1 : STD_LOGIC;
51 SIGNAL select_op1 : STD_LOGIC;
52 SIGNAL select_op2 : STD_LOGIC_VECTOR(1 DOWNTO 0) ;
52 SIGNAL select_op2 : STD_LOGIC_VECTOR(1 DOWNTO 0) ;
53
53
54 CONSTANT select_R0 : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
54 CONSTANT select_R0 : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
55 CONSTANT select_I0 : STD_LOGIC_VECTOR(1 DOWNTO 0) := "01";
55 CONSTANT select_I0 : STD_LOGIC_VECTOR(1 DOWNTO 0) := "01";
56 CONSTANT select_R1 : STD_LOGIC_VECTOR(1 DOWNTO 0) := "10";
56 CONSTANT select_R1 : STD_LOGIC_VECTOR(1 DOWNTO 0) := "10";
57 CONSTANT select_I1 : STD_LOGIC_VECTOR(1 DOWNTO 0) := "11";
57 CONSTANT select_I1 : STD_LOGIC_VECTOR(1 DOWNTO 0) := "11";
58
58
59 SIGNAL res_wen : STD_LOGIC;
59 SIGNAL res_wen : STD_LOGIC;
60 SIGNAL res_wen_reg1 : STD_LOGIC;
60 SIGNAL res_wen_reg1 : STD_LOGIC;
61 SIGNAL res_wen_reg2 : STD_LOGIC;
61 SIGNAL res_wen_reg2 : STD_LOGIC;
62 --SIGNAL res_wen_reg3 : STD_LOGIC;
62 --SIGNAL res_wen_reg3 : STD_LOGIC;
63
63
64 SIGNAL fifo_in_ren_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
64 SIGNAL fifo_in_ren_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
65
65
66
67 SIGNAL fifo_in_empty_reg : STD_LOGIC_VECTOR(1 DOWNTO 0);
68
69
66 BEGIN
70 BEGIN
67
71
68
72
69 PROCESS (clk, rstn)
73 --PROCESS (clk, rstn)
70 BEGIN -- PROCESS
74 --BEGIN -- PROCESS
71 IF rstn = '0' THEN -- asynchronous reset (active low)
75 -- IF rstn = '0' THEN -- asynchronous reset (active low)
72 fifo_in_ren <= "11";
76 -- fifo_in_ren <= "11";
73 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
77 -- ELSIF clk'event AND clk = '1' THEN -- rising clock edge
78 -- fifo_in_ren <= fifo_in_ren_s;
79 -- END IF;
80 --END PROCESS;
81
74 fifo_in_ren <= fifo_in_ren_s;
82 fifo_in_ren <= fifo_in_ren_s;
75 END IF;
76 END PROCESS;
77
78
83
79 PROCESS (clk, rstn)
84 PROCESS (clk, rstn)
80 BEGIN
85 BEGIN
81 IF rstn = '0' THEN
86 IF rstn = '0' THEN
82
87
83 correlation_begin <= '0';
88 correlation_begin <= '0';
84 correlation_done <= '0';
89 correlation_done <= '0';
85 state <= IDLE;
90 state <= IDLE;
86 fifo_in_ren_s <= "11";
91 fifo_in_ren_s <= "11";
87 select_ctrl <= select_ctrl_NOP;
92 select_ctrl <= select_ctrl_NOP;
88 --ALU_CTRL <= ALU_CTRL_NOP;
93 --ALU_CTRL <= ALU_CTRL_NOP;
89 select_op1 <= select_R0(0);
94 select_op1 <= select_R0(0);
90 select_op2 <= select_R0;
95 select_op2 <= select_R0;
91 res_wen <= '1';
96 res_wen <= '1';
97 fifo_in_empty_reg <= "11";
92
98
93 ELSIF clk'EVENT AND clk = '1' THEN
99 ELSIF clk'EVENT AND clk = '1' THEN
94 select_ctrl <= select_ctrl_NOP;
100 select_ctrl <= select_ctrl_NOP;
95 --ALU_CTRL <= ALU_CTRL_NOP;
101 --ALU_CTRL <= ALU_CTRL_NOP;
96 correlation_begin <= '0';
102 correlation_begin <= '0';
97 fifo_in_ren_s <= "11";
103 fifo_in_ren_s <= "11";
98 res_wen <= '1';
104 res_wen <= '1';
99 correlation_done <= '0';
105 correlation_done <= '0';
106 fifo_in_empty_reg <= fifo_in_empty;
100 CASE state IS
107 CASE state IS
101 WHEN IDLE =>
108 WHEN IDLE =>
102 IF correlation_start = '1' THEN
109 IF correlation_start = '1' THEN
103 IF correlation_auto = '1' THEN
110 IF correlation_auto = '1' THEN
104 IF fifo_out_full = '1' THEN
111 IF fifo_out_full = '1' THEN
105 state <= WFa;
112 state <= WFa;
106 ELSE
113 ELSE
107 correlation_begin <= '1';
114 correlation_begin <= '1';
108 state <= S1a;
115 state <= S1a;
109 fifo_in_ren_s <= "10";
116 --fifo_in_ren_s <= "10";
110 END IF;
117 END IF;
111 ELSE
118 ELSE
112 IF fifo_out_full = '1' THEN
119 IF fifo_out_full = '1' THEN
113 state <= WF;
120 state <= WF;
114 ELSE
121 ELSE
115 correlation_begin <= '1';
122 correlation_begin <= '1';
116 state <= S1;
123 state <= S1;
117 fifo_in_ren_s <= "00";
124 --fifo_in_ren_s <= "00";
118 END IF;
125 END IF;
119 END IF;
126 END IF;
120 END IF;
127 END IF;
121
128
122 ---------------------------------------------------------------------
129 ---------------------------------------------------------------------
123 -- INTER CORRELATION
130 -- INTER CORRELATION
124 ---------------------------------------------------------------------
131 ---------------------------------------------------------------------
125 WHEN WF =>
132 WHEN WF =>
126 IF fifo_out_full = '0' THEN
133 IF fifo_out_full = '0' THEN
127 correlation_begin <= '1';
134 correlation_begin <= '1';
128 state <= S1;
135 state <= S1;
129 fifo_in_ren_s <= "00";
136 --fifo_in_ren_s <= "00";
130 END IF;
137 END IF;
131 WHEN S1 =>
138 WHEN S1 =>
132 select_ctrl <= select_ctrl_MULT;
139 select_ctrl <= select_ctrl_MULT;
133 --ALU_CTRL <= ALU_CTRL_MULT;
140 --ALU_CTRL <= ALU_CTRL_MULT;
134 select_op1 <= select_R0(0);
141 select_op1 <= select_R0(0);
135 select_op2 <= select_R1;
142 select_op2 <= select_R1;
136 state <= S2;
143 state <= S2;
137 WHEN S2 =>
144 WHEN S2 =>
138 select_ctrl <= select_ctrl_MAC;
145 select_ctrl <= select_ctrl_MAC;
139 --ALU_CTRL <= ALU_CTRL_MAC;
146 --ALU_CTRL <= ALU_CTRL_MAC;
140 select_op1 <= select_I0(0);
147 select_op1 <= select_I0(0);
141 select_op2 <= select_I1;
148 select_op2 <= select_I1;
142 res_wen <= '0';
149 res_wen <= '0';
143 state <= S3;
150 state <= S3;
144 WHEN S3 =>
151 WHEN S3 =>
145 select_ctrl <= select_ctrl_MULT;
152 select_ctrl <= select_ctrl_MULT;
146 --ALU_CTRL <= ALU_CTRL_MULT;
153 --ALU_CTRL <= ALU_CTRL_MULT;
147 select_op1 <= select_I0(0);
154 select_op1 <= select_I0(0);
148 select_op2 <= select_R1;
155 select_op2 <= select_R1;
156 fifo_in_ren_s <= fifo_in_empty;
149 state <= S4;
157 state <= S4;
150 WHEN S4 =>
158 WHEN S4 =>
151 select_ctrl <= select_ctrl_MACn;
159 select_ctrl <= select_ctrl_MACn;
152 --ALU_CTRL <= ALU_CTRL_MACn;
160 --ALU_CTRL <= ALU_CTRL_MACn;
153 select_op1 <= select_R0(0);
161 select_op1 <= select_R0(0);
154 select_op2 <= select_I1;
162 select_op2 <= select_I1;
155 res_wen <= '0';
163 res_wen <= '0';
156 IF fifo_in_empty = "00" THEN
164 IF fifo_in_empty = "00" THEN
157 state <= S1;
165 state <= S1;
158 fifo_in_ren_s <= "00";
166 -- fifo_in_ren_s <= "00";
159 ELSE
167 ELSE
160 correlation_done <= '1';
168 correlation_done <= '1';
161 state <= IDLE;
169 state <= IDLE;
162 END IF;
170 END IF;
163
171
164
172
165
173
166 ---------------------------------------------------------------------
174 ---------------------------------------------------------------------
167 -- AUTO CORRELATION
175 -- AUTO CORRELATION
168 ---------------------------------------------------------------------
176 ---------------------------------------------------------------------
169 WHEN WFa =>
177 WHEN WFa =>
170 IF fifo_out_full = '0' THEN
178 IF fifo_out_full = '0' THEN
171 correlation_begin <= '1';
179 correlation_begin <= '1';
172 state <= S1a;
180 state <= S1a;
173 fifo_in_ren_s <= "10";
181 --fifo_in_ren_s <= "10";
174 END IF;
182 END IF;
175 WHEN S1a =>
183 WHEN S1a =>
176 select_ctrl <= select_ctrl_MULT;
184 select_ctrl <= select_ctrl_MULT;
177 --ALU_CTRL <= ALU_CTRL_MULT;
185 --ALU_CTRL <= ALU_CTRL_MULT;
178 select_op1 <= select_R0(0);
186 select_op1 <= select_R0(0);
179 select_op2 <= select_R0;
187 select_op2 <= select_R0;
188 fifo_in_ren_s(0) <= fifo_in_empty(0);
180 state <= S2a;
189 state <= S2a;
181 WHEN S2a =>
190 WHEN S2a =>
182 select_ctrl <= select_ctrl_MAC;
191 select_ctrl <= select_ctrl_MAC;
183 --ALU_CTRL <= ALU_CTRL_MAC;
192 --ALU_CTRL <= ALU_CTRL_MAC;
184 select_op1 <= select_I0(0);
193 select_op1 <= select_I0(0);
185 select_op2 <= select_I0;
194 select_op2 <= select_I0;
186 res_wen <= '0';
195 res_wen <= '0';
187 IF fifo_in_empty(0) = '0' THEN
196 IF fifo_in_empty(0) = '0' THEN
188 state <= S1a;
197 state <= S1a;
189 fifo_in_ren_s <= "10";
198 --fifo_in_ren_s <= "10";
190 ELSE
199 ELSE
191 correlation_done <= '1';
200 correlation_done <= '1';
192 state <= IDLE;
201 state <= IDLE;
193 END IF;
202 END IF;
194
203
195
204
196 WHEN OTHERS => NULL;
205 WHEN OTHERS => NULL;
197 END CASE;
206 END CASE;
198
207
199 END IF;
208 END IF;
200 END PROCESS;
209 END PROCESS;
201
210
202 ALU_CTRL <= ALU_CTRL_NOP WHEN select_ctrl = select_ctrl_NOP ELSE
211 ALU_CTRL <= ALU_CTRL_NOP WHEN select_ctrl = select_ctrl_NOP ELSE
203 ALU_CTRL_MULT WHEN select_ctrl = select_ctrl_MULT ELSE
212 ALU_CTRL_MULT WHEN select_ctrl = select_ctrl_MULT ELSE
204 ALU_CTRL_MAC WHEN select_ctrl = select_ctrl_MAC ELSE
213 ALU_CTRL_MAC WHEN select_ctrl = select_ctrl_MAC ELSE
205 ALU_CTRL_MACn;
214 ALU_CTRL_MACn;
206
215
207 OP1 <= fifo_in_data(15 DOWNTO 0) WHEN select_op1 = select_R0(0) ELSE
216 OP1 <= fifo_in_data(15 DOWNTO 0) WHEN select_op1 = select_R0(0) ELSE
208 fifo_in_data(31 DOWNTO 16); -- WHEN select_op1 = select_I0(0) ELSE
217 fifo_in_data(31 DOWNTO 16); -- WHEN select_op1 = select_I0(0) ELSE
209
218
210 OP2 <= fifo_in_data(15 DOWNTO 0) WHEN select_op2 = select_R0 ELSE
219 OP2 <= fifo_in_data(15 DOWNTO 0) WHEN select_op2 = select_R0 ELSE
211 fifo_in_data(31 DOWNTO 16) WHEN select_op2 = select_I0 ELSE
220 fifo_in_data(31 DOWNTO 16) WHEN select_op2 = select_I0 ELSE
212 fifo_in_data(47 DOWNTO 32) WHEN select_op2 = select_R1 ELSE
221 fifo_in_data(47 DOWNTO 32) WHEN select_op2 = select_R1 ELSE
213 fifo_in_data(63 DOWNTO 48); -- WHEN select_op2 = select_I1 ELSE
222 fifo_in_data(63 DOWNTO 48); -- WHEN select_op2 = select_I1 ELSE
214
223
215 ALU_MS : ALU
224 ALU_MS : ALU
216 GENERIC MAP (
225 GENERIC MAP (
217 Arith_en => 1,
226 Arith_en => 1,
218 Logic_en => 0,
227 Logic_en => 0,
219 Input_SZ_1 => 16,
228 Input_SZ_1 => 16,
220 Input_SZ_2 => 16,
229 Input_SZ_2 => 16,
221 COMP_EN => 0) -- 0> Enable and 1> Disable
230 COMP_EN => 0) -- 0> Enable and 1> Disable
222 PORT MAP (
231 PORT MAP (
223 clk => clk,
232 clk => clk,
224 reset => rstn,
233 reset => rstn,
225
234
226 ctrl => ALU_CTRL(2 DOWNTO 0),
235 ctrl => ALU_CTRL(2 DOWNTO 0),
227 comp => ALU_CTRL(4 DOWNTO 3),
236 comp => ALU_CTRL(4 DOWNTO 3),
228
237
229 OP1 => OP1,
238 OP1 => OP1,
230 OP2 => OP2,
239 OP2 => OP2,
231
240
232 RES => RES);
241 RES => RES);
233
242
234 fifo_out_data <= RES;
243 fifo_out_data <= RES;
235
244
236
245
237 PROCESS (clk, rstn)
246 PROCESS (clk, rstn)
238 BEGIN
247 BEGIN
239 IF rstn = '0' THEN
248 IF rstn = '0' THEN
240 res_wen_reg1 <= '1';
249 res_wen_reg1 <= '1';
241 res_wen_reg2 <= '1';
250 res_wen_reg2 <= '1';
242 --res_wen_reg3 <= '1';
251 --res_wen_reg3 <= '1';
243 fifo_out_wen <= '1';
252 fifo_out_wen <= '1';
244 ELSIF clk'event AND clk = '1' THEN
253 ELSIF clk'event AND clk = '1' THEN
245 res_wen_reg1 <= res_wen;
254 res_wen_reg1 <= res_wen;
246 res_wen_reg2 <= res_wen_reg1;
255 res_wen_reg2 <= res_wen_reg1;
247 --res_wen_reg3 <= res_wen_reg2;
256 --res_wen_reg3 <= res_wen_reg2;
248 fifo_out_wen <= res_wen_reg2;
257 fifo_out_wen <= res_wen_reg2;
249 END IF;
258 END IF;
250 END PROCESS;
259 END PROCESS;
251
260
252
261
253 END beh;
262 END beh;
Show file before | Show file after | Hide comments
@@ -1,1217 +1,1220
1 LIBRARY ieee;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
2 USE ieee.std_logic_1164.ALL;
3 USE ieee.numeric_std.ALL;
3 USE ieee.numeric_std.ALL;
4
4
5
5
6 LIBRARY lpp;
6 LIBRARY lpp;
7 USE lpp.lpp_memory.ALL;
7 USE lpp.lpp_memory.ALL;
8 USE lpp.iir_filter.ALL;
8 USE lpp.iir_filter.ALL;
9 USE lpp.spectral_matrix_package.ALL;
9 USE lpp.spectral_matrix_package.ALL;
10 USE lpp.lpp_dma_pkg.ALL;
10 USE lpp.lpp_dma_pkg.ALL;
11 USE lpp.lpp_Header.ALL;
11 USE lpp.lpp_Header.ALL;
12 USE lpp.lpp_matrix.ALL;
12 USE lpp.lpp_matrix.ALL;
13 USE lpp.lpp_matrix.ALL;
13 USE lpp.lpp_matrix.ALL;
14 USE lpp.lpp_lfr_pkg.ALL;
14 USE lpp.lpp_lfr_pkg.ALL;
15 USE lpp.lpp_fft.ALL;
15 USE lpp.lpp_fft.ALL;
16 USE lpp.fft_components.ALL;
16 USE lpp.fft_components.ALL;
17
17
18 ENTITY lpp_lfr_ms IS
18 ENTITY lpp_lfr_ms IS
19 GENERIC (
19 GENERIC (
20 Mem_use : INTEGER := use_RAM
20 Mem_use : INTEGER := use_RAM
21 );
21 );
22 PORT (
22 PORT (
23 clk : IN STD_LOGIC;
23 clk : IN STD_LOGIC;
24 rstn : IN STD_LOGIC;
24 rstn : IN STD_LOGIC;
25 run : IN STD_LOGIC;
25 run : IN STD_LOGIC;
26
26
27 ---------------------------------------------------------------------------
27 ---------------------------------------------------------------------------
28 -- DATA INPUT
28 -- DATA INPUT
29 ---------------------------------------------------------------------------
29 ---------------------------------------------------------------------------
30 start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
30 start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
31 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
31 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
32 --fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
32 --fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
33 --
33 --
34 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
34 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
35 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
35 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
36 sample_f0_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
36 sample_f0_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
37 --
37 --
38 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
38 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
39 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
39 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
40 sample_f1_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
40 sample_f1_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
41 --
41 --
42 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
42 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
43 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
43 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
44 sample_f2_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
44 sample_f2_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
45
45
46 ---------------------------------------------------------------------------
46 ---------------------------------------------------------------------------
47 -- DMA
47 -- DMA
48 ---------------------------------------------------------------------------
48 ---------------------------------------------------------------------------
49 dma_fifo_burst_valid: OUT STD_LOGIC; --TODO
49 dma_fifo_burst_valid: OUT STD_LOGIC; --TODO
50 dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --TODO
50 dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --TODO
51 dma_fifo_ren : IN STD_LOGIC; --TODO
51 dma_fifo_ren : IN STD_LOGIC; --TODO
52 dma_buffer_new : OUT STD_LOGIC; --TODOx
52 dma_buffer_new : OUT STD_LOGIC; --TODOx
53 dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --TODO
53 dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --TODO
54 dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); --TODO
54 dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); --TODO
55 dma_buffer_full : IN STD_LOGIC; --TODO
55 dma_buffer_full : IN STD_LOGIC; --TODO
56 dma_buffer_full_err : IN STD_LOGIC; --TODO
56 dma_buffer_full_err : IN STD_LOGIC; --TODO
57
57
58 -- Reg out
58 -- Reg out
59 ready_matrix_f0 : OUT STD_LOGIC; -- TODO
59 ready_matrix_f0 : OUT STD_LOGIC; -- TODO
60 ready_matrix_f1 : OUT STD_LOGIC; -- TODO
60 ready_matrix_f1 : OUT STD_LOGIC; -- TODO
61 ready_matrix_f2 : OUT STD_LOGIC; -- TODO
61 ready_matrix_f2 : OUT STD_LOGIC; -- TODO
62 -- error_bad_component_error : OUT STD_LOGIC; -- TODO
62 -- error_bad_component_error : OUT STD_LOGIC; -- TODO
63 error_buffer_full : OUT STD_LOGIC; -- TODO
63 error_buffer_full : OUT STD_LOGIC; -- TODO
64 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
64 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
65
65
66 -- Reg In
66 -- Reg In
67 status_ready_matrix_f0 : IN STD_LOGIC; -- TODO
67 status_ready_matrix_f0 : IN STD_LOGIC; -- TODO
68 status_ready_matrix_f1 : IN STD_LOGIC; -- TODO
68 status_ready_matrix_f1 : IN STD_LOGIC; -- TODO
69 status_ready_matrix_f2 : IN STD_LOGIC; -- TODO
69 status_ready_matrix_f2 : IN STD_LOGIC; -- TODO
70
70
71 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
71 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
72 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
72 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
73 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
73 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
74
74
75 length_matrix_f0 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); -- TODO
75 length_matrix_f0 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); -- TODO
76 length_matrix_f1 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); -- TODO
76 length_matrix_f1 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); -- TODO
77 length_matrix_f2 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); -- TODO
77 length_matrix_f2 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); -- TODO
78
78
79 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
79 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
80 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
80 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
81 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
81 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
82 ---------------------------------------------------------------------------
82 ---------------------------------------------------------------------------
83 debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
83 debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
84 );
84 );
85 END;
85 END;
86
86
87 ARCHITECTURE Behavioral OF lpp_lfr_ms IS
87 ARCHITECTURE Behavioral OF lpp_lfr_ms IS
88
88
89 SIGNAL sample_f0_A_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
89 SIGNAL sample_f0_A_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
90 SIGNAL sample_f0_A_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
90 SIGNAL sample_f0_A_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
91 SIGNAL sample_f0_A_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
91 SIGNAL sample_f0_A_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
92 SIGNAL sample_f0_A_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
92 SIGNAL sample_f0_A_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
93 SIGNAL sample_f0_A_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
93 SIGNAL sample_f0_A_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
94
94
95 SIGNAL sample_f0_B_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
95 SIGNAL sample_f0_B_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
96 SIGNAL sample_f0_B_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
96 SIGNAL sample_f0_B_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
97 SIGNAL sample_f0_B_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
97 SIGNAL sample_f0_B_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
98 SIGNAL sample_f0_B_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
98 SIGNAL sample_f0_B_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
99 SIGNAL sample_f0_B_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
99 SIGNAL sample_f0_B_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
100
100
101 SIGNAL sample_f1_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
101 SIGNAL sample_f1_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
102 SIGNAL sample_f1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
102 SIGNAL sample_f1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
103 SIGNAL sample_f1_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
103 SIGNAL sample_f1_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
104 SIGNAL sample_f1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
104 SIGNAL sample_f1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
105
105
106 SIGNAL sample_f1_almost_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
106 SIGNAL sample_f1_almost_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
107
107
108 SIGNAL sample_f2_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
108 SIGNAL sample_f2_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
109 SIGNAL sample_f2_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
109 SIGNAL sample_f2_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
110 SIGNAL sample_f2_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
110 SIGNAL sample_f2_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
111 SIGNAL sample_f2_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
111 SIGNAL sample_f2_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
112
112
113 SIGNAL error_wen_f0 : STD_LOGIC;
113 SIGNAL error_wen_f0 : STD_LOGIC;
114 SIGNAL error_wen_f1 : STD_LOGIC;
114 SIGNAL error_wen_f1 : STD_LOGIC;
115 SIGNAL error_wen_f2 : STD_LOGIC;
115 SIGNAL error_wen_f2 : STD_LOGIC;
116
116
117 SIGNAL one_sample_f1_full : STD_LOGIC;
117 SIGNAL one_sample_f1_full : STD_LOGIC;
118 SIGNAL one_sample_f1_wen : STD_LOGIC;
118 SIGNAL one_sample_f1_wen : STD_LOGIC;
119 SIGNAL one_sample_f2_full : STD_LOGIC;
119 SIGNAL one_sample_f2_full : STD_LOGIC;
120 SIGNAL one_sample_f2_wen : STD_LOGIC;
120 SIGNAL one_sample_f2_wen : STD_LOGIC;
121
121
122 -----------------------------------------------------------------------------
122 -----------------------------------------------------------------------------
123 -- FSM / SWITCH SELECT CHANNEL
123 -- FSM / SWITCH SELECT CHANNEL
124 -----------------------------------------------------------------------------
124 -----------------------------------------------------------------------------
125 TYPE fsm_select_channel IS (IDLE, SWITCH_F0_A, SWITCH_F0_B, SWITCH_F1, SWITCH_F2);
125 TYPE fsm_select_channel IS (IDLE, SWITCH_F0_A, SWITCH_F0_B, SWITCH_F1, SWITCH_F2);
126 SIGNAL state_fsm_select_channel : fsm_select_channel;
126 SIGNAL state_fsm_select_channel : fsm_select_channel;
127 -- SIGNAL pre_state_fsm_select_channel : fsm_select_channel;
127 -- SIGNAL pre_state_fsm_select_channel : fsm_select_channel;
128 SIGNAL select_channel : STD_LOGIC_VECTOR(1 DOWNTO 0);
128 SIGNAL select_channel : STD_LOGIC_VECTOR(1 DOWNTO 0);
129 SIGNAL select_channel_reg : STD_LOGIC_VECTOR(1 DOWNTO 0);
129 SIGNAL select_channel_reg : STD_LOGIC_VECTOR(1 DOWNTO 0);
130
130
131 SIGNAL sample_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
131 SIGNAL sample_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
132 SIGNAL sample_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
132 SIGNAL sample_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
133 SIGNAL sample_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
133 SIGNAL sample_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
134 SIGNAL sample_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
134 SIGNAL sample_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
135
135
136 -----------------------------------------------------------------------------
136 -----------------------------------------------------------------------------
137 -- FSM LOAD FFT
137 -- FSM LOAD FFT
138 -----------------------------------------------------------------------------
138 -----------------------------------------------------------------------------
139 TYPE fsm_load_FFT IS (IDLE, FIFO_1, FIFO_2, FIFO_3, FIFO_4, FIFO_5);
139 TYPE fsm_load_FFT IS (IDLE, FIFO_1, FIFO_2, FIFO_3, FIFO_4, FIFO_5);
140 SIGNAL state_fsm_load_FFT : fsm_load_FFT;
140 SIGNAL state_fsm_load_FFT : fsm_load_FFT;
141 -- SIGNAL next_state_fsm_load_FFT : fsm_load_FFT;
141 -- SIGNAL next_state_fsm_load_FFT : fsm_load_FFT;
142 SIGNAL select_fifo : STD_LOGIC_VECTOR(2 DOWNTO 0);
142 SIGNAL select_fifo : STD_LOGIC_VECTOR(2 DOWNTO 0);
143 SIGNAL select_fifo_reg : STD_LOGIC_VECTOR(2 DOWNTO 0);
143 SIGNAL select_fifo_reg : STD_LOGIC_VECTOR(2 DOWNTO 0);
144
144
145 SIGNAL sample_ren_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
145 SIGNAL sample_ren_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
146 SIGNAL sample_load : STD_LOGIC;
146 SIGNAL sample_load : STD_LOGIC;
147 SIGNAL sample_valid : STD_LOGIC;
147 SIGNAL sample_valid : STD_LOGIC;
148 SIGNAL sample_valid_r : STD_LOGIC;
148 SIGNAL sample_valid_r : STD_LOGIC;
149 SIGNAL sample_data : STD_LOGIC_VECTOR(15 DOWNTO 0);
149 SIGNAL sample_data : STD_LOGIC_VECTOR(15 DOWNTO 0);
150
150
151
151
152 -----------------------------------------------------------------------------
152 -----------------------------------------------------------------------------
153 -- FFT
153 -- FFT
154 -----------------------------------------------------------------------------
154 -----------------------------------------------------------------------------
155 SIGNAL fft_read : STD_LOGIC;
155 SIGNAL fft_read : STD_LOGIC;
156 SIGNAL fft_pong : STD_LOGIC;
156 SIGNAL fft_pong : STD_LOGIC;
157 SIGNAL fft_data_im : STD_LOGIC_VECTOR(15 DOWNTO 0);
157 SIGNAL fft_data_im : STD_LOGIC_VECTOR(15 DOWNTO 0);
158 SIGNAL fft_data_re : STD_LOGIC_VECTOR(15 DOWNTO 0);
158 SIGNAL fft_data_re : STD_LOGIC_VECTOR(15 DOWNTO 0);
159 SIGNAL fft_data_valid : STD_LOGIC;
159 SIGNAL fft_data_valid : STD_LOGIC;
160 SIGNAL fft_ready : STD_LOGIC;
160 SIGNAL fft_ready : STD_LOGIC;
161 -----------------------------------------------------------------------------
161 -----------------------------------------------------------------------------
162 -- SIGNAL fft_linker_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
162 -- SIGNAL fft_linker_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
163 -----------------------------------------------------------------------------
163 -----------------------------------------------------------------------------
164 TYPE fsm_load_MS_memory IS (IDLE, LOAD_FIFO, TRASH_FFT);
164 TYPE fsm_load_MS_memory IS (IDLE, LOAD_FIFO, TRASH_FFT);
165 SIGNAL state_fsm_load_MS_memory : fsm_load_MS_memory;
165 SIGNAL state_fsm_load_MS_memory : fsm_load_MS_memory;
166 SIGNAL current_fifo_load : STD_LOGIC_VECTOR(4 DOWNTO 0);
166 SIGNAL current_fifo_load : STD_LOGIC_VECTOR(4 DOWNTO 0);
167 SIGNAL current_fifo_empty : STD_LOGIC;
167 SIGNAL current_fifo_empty : STD_LOGIC;
168 SIGNAL current_fifo_locked : STD_LOGIC;
168 SIGNAL current_fifo_locked : STD_LOGIC;
169 SIGNAL current_fifo_full : STD_LOGIC;
169 SIGNAL current_fifo_full : STD_LOGIC;
170 SIGNAL MEM_IN_SM_locked : STD_LOGIC_VECTOR(4 DOWNTO 0);
170 SIGNAL MEM_IN_SM_locked : STD_LOGIC_VECTOR(4 DOWNTO 0);
171
171
172 -----------------------------------------------------------------------------
172 -----------------------------------------------------------------------------
173 SIGNAL MEM_IN_SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
173 SIGNAL MEM_IN_SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
174 SIGNAL MEM_IN_SM_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
174 SIGNAL MEM_IN_SM_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
175 SIGNAL MEM_IN_SM_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
175 SIGNAL MEM_IN_SM_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
176 SIGNAL MEM_IN_SM_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
176 SIGNAL MEM_IN_SM_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
177 SIGNAL MEM_IN_SM_wData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
177 SIGNAL MEM_IN_SM_wData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
178 SIGNAL MEM_IN_SM_rData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
178 SIGNAL MEM_IN_SM_rData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
179 SIGNAL MEM_IN_SM_Full : STD_LOGIC_VECTOR(4 DOWNTO 0);
179 SIGNAL MEM_IN_SM_Full : STD_LOGIC_VECTOR(4 DOWNTO 0);
180 SIGNAL MEM_IN_SM_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
180 SIGNAL MEM_IN_SM_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
181 -----------------------------------------------------------------------------
181 -----------------------------------------------------------------------------
182 SIGNAL SM_in_data : STD_LOGIC_VECTOR(32*2-1 DOWNTO 0);
182 SIGNAL SM_in_data : STD_LOGIC_VECTOR(32*2-1 DOWNTO 0);
183 SIGNAL SM_in_ren : STD_LOGIC_VECTOR(1 DOWNTO 0);
183 SIGNAL SM_in_ren : STD_LOGIC_VECTOR(1 DOWNTO 0);
184 SIGNAL SM_in_empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
184 SIGNAL SM_in_empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
185
185
186 SIGNAL SM_correlation_start : STD_LOGIC;
186 SIGNAL SM_correlation_start : STD_LOGIC;
187 SIGNAL SM_correlation_auto : STD_LOGIC;
187 SIGNAL SM_correlation_auto : STD_LOGIC;
188 SIGNAL SM_correlation_done : STD_LOGIC;
188 SIGNAL SM_correlation_done : STD_LOGIC;
189 SIGNAL SM_correlation_done_reg1 : STD_LOGIC;
189 SIGNAL SM_correlation_done_reg1 : STD_LOGIC;
190 SIGNAL SM_correlation_done_reg2 : STD_LOGIC;
190 SIGNAL SM_correlation_done_reg2 : STD_LOGIC;
191 SIGNAL SM_correlation_done_reg3 : STD_LOGIC;
191 SIGNAL SM_correlation_done_reg3 : STD_LOGIC;
192 SIGNAL SM_correlation_begin : STD_LOGIC;
192 SIGNAL SM_correlation_begin : STD_LOGIC;
193
193
194 SIGNAL MEM_OUT_SM_Full_s : STD_LOGIC;
194 SIGNAL MEM_OUT_SM_Full_s : STD_LOGIC;
195 SIGNAL MEM_OUT_SM_Data_in_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
195 SIGNAL MEM_OUT_SM_Data_in_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
196 SIGNAL MEM_OUT_SM_Write_s : STD_LOGIC;
196 SIGNAL MEM_OUT_SM_Write_s : STD_LOGIC;
197
197
198 SIGNAL current_matrix_write : STD_LOGIC;
198 SIGNAL current_matrix_write : STD_LOGIC;
199 SIGNAL current_matrix_wait_empty : STD_LOGIC;
199 SIGNAL current_matrix_wait_empty : STD_LOGIC;
200 -----------------------------------------------------------------------------
200 -----------------------------------------------------------------------------
201 SIGNAL fifo_0_ready : STD_LOGIC;
201 SIGNAL fifo_0_ready : STD_LOGIC;
202 SIGNAL fifo_1_ready : STD_LOGIC;
202 SIGNAL fifo_1_ready : STD_LOGIC;
203 SIGNAL fifo_ongoing : STD_LOGIC;
203 SIGNAL fifo_ongoing : STD_LOGIC;
204 SIGNAL fifo_ongoing_reg : STD_LOGIC;
204
205
205 SIGNAL FSM_DMA_fifo_ren : STD_LOGIC;
206 SIGNAL FSM_DMA_fifo_ren : STD_LOGIC;
206 SIGNAL FSM_DMA_fifo_empty : STD_LOGIC;
207 SIGNAL FSM_DMA_fifo_empty : STD_LOGIC;
207 SIGNAL FSM_DMA_fifo_empty_threshold : STD_LOGIC;
208 SIGNAL FSM_DMA_fifo_empty_threshold : STD_LOGIC;
208 SIGNAL FSM_DMA_fifo_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
209 SIGNAL FSM_DMA_fifo_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
209 SIGNAL FSM_DMA_fifo_status : STD_LOGIC_VECTOR(53 DOWNTO 4);
210 SIGNAL FSM_DMA_fifo_status : STD_LOGIC_VECTOR(53 DOWNTO 4);
210 -----------------------------------------------------------------------------
211 -----------------------------------------------------------------------------
211 SIGNAL MEM_OUT_SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0);
212 SIGNAL MEM_OUT_SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0);
212 SIGNAL MEM_OUT_SM_Read : STD_LOGIC_VECTOR(1 DOWNTO 0);
213 SIGNAL MEM_OUT_SM_Read : STD_LOGIC_VECTOR(1 DOWNTO 0);
213 SIGNAL MEM_OUT_SM_Data_in : STD_LOGIC_VECTOR(63 DOWNTO 0);
214 SIGNAL MEM_OUT_SM_Data_in : STD_LOGIC_VECTOR(63 DOWNTO 0);
214 SIGNAL MEM_OUT_SM_Data_out : STD_LOGIC_VECTOR(63 DOWNTO 0);
215 SIGNAL MEM_OUT_SM_Data_out : STD_LOGIC_VECTOR(63 DOWNTO 0);
215 SIGNAL MEM_OUT_SM_Full : STD_LOGIC_VECTOR(1 DOWNTO 0);
216 SIGNAL MEM_OUT_SM_Full : STD_LOGIC_VECTOR(1 DOWNTO 0);
216 SIGNAL MEM_OUT_SM_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
217 SIGNAL MEM_OUT_SM_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
217 SIGNAL MEM_OUT_SM_Empty_Threshold : STD_LOGIC_VECTOR(1 DOWNTO 0);
218 SIGNAL MEM_OUT_SM_Empty_Threshold : STD_LOGIC_VECTOR(1 DOWNTO 0);
218
219
219 -----------------------------------------------------------------------------
220 -----------------------------------------------------------------------------
220 -- TIME REG & INFOs
221 -- TIME REG & INFOs
221 -----------------------------------------------------------------------------
222 -----------------------------------------------------------------------------
222 SIGNAL all_time : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
223 SIGNAL all_time : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
223
224
224 SIGNAL f_empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
225 SIGNAL f_empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
225 SIGNAL f_empty_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
226 SIGNAL f_empty_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
226 SIGNAL time_update_f : STD_LOGIC_VECTOR(3 DOWNTO 0);
227 SIGNAL time_update_f : STD_LOGIC_VECTOR(3 DOWNTO 0);
227 SIGNAL time_reg_f : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
228 SIGNAL time_reg_f : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
228
229
229 SIGNAL time_reg_f0_A : STD_LOGIC_VECTOR(47 DOWNTO 0);
230 SIGNAL time_reg_f0_A : STD_LOGIC_VECTOR(47 DOWNTO 0);
230 SIGNAL time_reg_f0_B : STD_LOGIC_VECTOR(47 DOWNTO 0);
231 SIGNAL time_reg_f0_B : STD_LOGIC_VECTOR(47 DOWNTO 0);
231 SIGNAL time_reg_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
232 SIGNAL time_reg_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
232 SIGNAL time_reg_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
233 SIGNAL time_reg_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
233
234
234 --SIGNAL time_update_f0_A : STD_LOGIC;
235 --SIGNAL time_update_f0_A : STD_LOGIC;
235 --SIGNAL time_update_f0_B : STD_LOGIC;
236 --SIGNAL time_update_f0_B : STD_LOGIC;
236 --SIGNAL time_update_f1 : STD_LOGIC;
237 --SIGNAL time_update_f1 : STD_LOGIC;
237 --SIGNAL time_update_f2 : STD_LOGIC;
238 --SIGNAL time_update_f2 : STD_LOGIC;
238 --
239 --
239 SIGNAL status_channel : STD_LOGIC_VECTOR(49 DOWNTO 0);
240 SIGNAL status_channel : STD_LOGIC_VECTOR(49 DOWNTO 0);
240 SIGNAL status_MS_input : STD_LOGIC_VECTOR(49 DOWNTO 0);
241 SIGNAL status_MS_input : STD_LOGIC_VECTOR(49 DOWNTO 0);
241 SIGNAL status_component : STD_LOGIC_VECTOR(53 DOWNTO 0);
242 SIGNAL status_component : STD_LOGIC_VECTOR(53 DOWNTO 0);
242
243
243 SIGNAL status_component_fifo_0 : STD_LOGIC_VECTOR(53 DOWNTO 4);
244 SIGNAL status_component_fifo_0 : STD_LOGIC_VECTOR(53 DOWNTO 4);
244 SIGNAL status_component_fifo_1 : STD_LOGIC_VECTOR(53 DOWNTO 4);
245 SIGNAL status_component_fifo_1 : STD_LOGIC_VECTOR(53 DOWNTO 4);
245 SIGNAL status_component_fifo_0_end : STD_LOGIC;
246 SIGNAL status_component_fifo_0_end : STD_LOGIC;
246 SIGNAL status_component_fifo_1_end : STD_LOGIC;
247 SIGNAL status_component_fifo_1_end : STD_LOGIC;
247 -----------------------------------------------------------------------------
248 -----------------------------------------------------------------------------
248 SIGNAL fft_ongoing_counter : STD_LOGIC;--_VECTOR(1 DOWNTO 0);
249 SIGNAL fft_ongoing_counter : STD_LOGIC;--_VECTOR(1 DOWNTO 0);
249
250
250 SIGNAL fft_ready_reg : STD_LOGIC;
251 SIGNAL fft_ready_reg : STD_LOGIC;
251 SIGNAL fft_ready_rising_down : STD_LOGIC;
252 SIGNAL fft_ready_rising_down : STD_LOGIC;
252
253
253 SIGNAL sample_load_reg : STD_LOGIC;
254 SIGNAL sample_load_reg : STD_LOGIC;
254 SIGNAL sample_load_rising_down : STD_LOGIC;
255 SIGNAL sample_load_rising_down : STD_LOGIC;
255
256
256 -----------------------------------------------------------------------------
257 -----------------------------------------------------------------------------
257 SIGNAL sample_f1_wen_head : STD_LOGIC_VECTOR(4 DOWNTO 0);
258 SIGNAL sample_f1_wen_head : STD_LOGIC_VECTOR(4 DOWNTO 0);
258 SIGNAL sample_f1_wen_head_in : STD_LOGIC;
259 SIGNAL sample_f1_wen_head_in : STD_LOGIC;
259 SIGNAL sample_f1_wen_head_out : STD_LOGIC;
260 SIGNAL sample_f1_wen_head_out : STD_LOGIC;
260 SIGNAL sample_f1_full_head_in : STD_LOGIC;
261 SIGNAL sample_f1_full_head_in : STD_LOGIC;
261 SIGNAL sample_f1_full_head_out : STD_LOGIC;
262 SIGNAL sample_f1_full_head_out : STD_LOGIC;
262 SIGNAL sample_f1_empty_head_in : STD_LOGIC;
263 SIGNAL sample_f1_empty_head_in : STD_LOGIC;
263
264
264 SIGNAL sample_f1_wdata_head : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
265 SIGNAL sample_f1_wdata_head : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
265 -----------------------------------------------------------------------------
266 -----------------------------------------------------------------------------
266 SIGNAL sample_f0_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
267 SIGNAL sample_f0_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
267 SIGNAL sample_f1_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
268 SIGNAL sample_f1_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
268 SIGNAL sample_f2_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
269 SIGNAL sample_f2_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
269 SIGNAL ongoing : STD_LOGIC;
270 SIGNAL ongoing : STD_LOGIC;
270
271
271 BEGIN
272 BEGIN
272
273
273 PROCESS (clk, rstn)
274 PROCESS (clk, rstn)
274 BEGIN -- PROCESS
275 BEGIN -- PROCESS
275 IF rstn = '0' THEN -- asynchronous reset (active low)
276 IF rstn = '0' THEN -- asynchronous reset (active low)
276 sample_f0_wen_s <= (OTHERS => '1');
277 sample_f0_wen_s <= (OTHERS => '1');
277 sample_f1_wen_s <= (OTHERS => '1');
278 sample_f1_wen_s <= (OTHERS => '1');
278 sample_f2_wen_s <= (OTHERS => '1');
279 sample_f2_wen_s <= (OTHERS => '1');
279 ongoing <= '0';
280 ongoing <= '0';
280 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
281 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
281 IF ongoing = '1' THEN
282 IF ongoing = '1' THEN
282 sample_f0_wen_s <= sample_f0_wen;
283 sample_f0_wen_s <= sample_f0_wen;
283 sample_f1_wen_s <= sample_f1_wen;
284 sample_f1_wen_s <= sample_f1_wen;
284 sample_f2_wen_s <= sample_f2_wen;
285 sample_f2_wen_s <= sample_f2_wen;
285 ELSE
286 ELSE
286 IF start_date = coarse_time(30 DOWNTO 0) THEN
287 IF start_date = coarse_time(30 DOWNTO 0) THEN
287 ongoing <= '1';
288 ongoing <= '1';
288 END IF;
289 END IF;
289 sample_f0_wen_s <= (OTHERS => '1');
290 sample_f0_wen_s <= (OTHERS => '1');
290 sample_f1_wen_s <= (OTHERS => '1');
291 sample_f1_wen_s <= (OTHERS => '1');
291 sample_f2_wen_s <= (OTHERS => '1');
292 sample_f2_wen_s <= (OTHERS => '1');
292 END IF;
293 END IF;
293 END IF;
294 END IF;
294 END PROCESS;
295 END PROCESS;
295
296
296
297
297 error_input_fifo_write <= error_wen_f2 & error_wen_f1 & error_wen_f0;
298 error_input_fifo_write <= error_wen_f2 & error_wen_f1 & error_wen_f0;
298
299
299
300
300 switch_f0_inst : spectral_matrix_switch_f0
301 switch_f0_inst : spectral_matrix_switch_f0
301 PORT MAP (
302 PORT MAP (
302 clk => clk,
303 clk => clk,
303 rstn => rstn,
304 rstn => rstn,
304
305
305 sample_wen => sample_f0_wen_s,
306 sample_wen => sample_f0_wen_s,
306
307
307 fifo_A_empty => sample_f0_A_empty,
308 fifo_A_empty => sample_f0_A_empty,
308 fifo_A_full => sample_f0_A_full,
309 fifo_A_full => sample_f0_A_full,
309 fifo_A_wen => sample_f0_A_wen,
310 fifo_A_wen => sample_f0_A_wen,
310
311
311 fifo_B_empty => sample_f0_B_empty,
312 fifo_B_empty => sample_f0_B_empty,
312 fifo_B_full => sample_f0_B_full,
313 fifo_B_full => sample_f0_B_full,
313 fifo_B_wen => sample_f0_B_wen,
314 fifo_B_wen => sample_f0_B_wen,
314
315
315 error_wen => error_wen_f0); -- TODO
316 error_wen => error_wen_f0); -- TODO
316
317
317 -----------------------------------------------------------------------------
318 -----------------------------------------------------------------------------
318 -- FIFO IN
319 -- FIFO IN
319 -----------------------------------------------------------------------------
320 -----------------------------------------------------------------------------
320 lppFIFOxN_f0_a : lppFIFOxN
321 lppFIFOxN_f0_a : lppFIFOxN
321 GENERIC MAP (
322 GENERIC MAP (
322 tech => 0,
323 tech => 0,
323 Mem_use => Mem_use,
324 Mem_use => Mem_use,
324 Data_sz => 16,
325 Data_sz => 16,
325 Addr_sz => 8,
326 Addr_sz => 8,
326 FifoCnt => 5)
327 FifoCnt => 5)
327 PORT MAP (
328 PORT MAP (
328 clk => clk,
329 clk => clk,
329 rstn => rstn,
330 rstn => rstn,
330
331
331 ReUse => (OTHERS => '0'),
332 ReUse => (OTHERS => '0'),
332
333
333 run => (OTHERS => '1'),
334 run => (OTHERS => '1'),
334
335
335 wen => sample_f0_A_wen,
336 wen => sample_f0_A_wen,
336 wdata => sample_f0_wdata,
337 wdata => sample_f0_wdata,
337
338
338 ren => sample_f0_A_ren,
339 ren => sample_f0_A_ren,
339 rdata => sample_f0_A_rdata,
340 rdata => sample_f0_A_rdata,
340
341
341 empty => sample_f0_A_empty,
342 empty => sample_f0_A_empty,
342 full => sample_f0_A_full,
343 full => sample_f0_A_full,
343 almost_full => OPEN);
344 almost_full => OPEN);
344
345
345 lppFIFOxN_f0_b : lppFIFOxN
346 lppFIFOxN_f0_b : lppFIFOxN
346 GENERIC MAP (
347 GENERIC MAP (
347 tech => 0,
348 tech => 0,
348 Mem_use => Mem_use,
349 Mem_use => Mem_use,
349 Data_sz => 16,
350 Data_sz => 16,
350 Addr_sz => 8,
351 Addr_sz => 8,
351 FifoCnt => 5)
352 FifoCnt => 5)
352 PORT MAP (
353 PORT MAP (
353 clk => clk,
354 clk => clk,
354 rstn => rstn,
355 rstn => rstn,
355
356
356 ReUse => (OTHERS => '0'),
357 ReUse => (OTHERS => '0'),
357 run => (OTHERS => '1'),
358 run => (OTHERS => '1'),
358
359
359 wen => sample_f0_B_wen,
360 wen => sample_f0_B_wen,
360 wdata => sample_f0_wdata,
361 wdata => sample_f0_wdata,
361 ren => sample_f0_B_ren,
362 ren => sample_f0_B_ren,
362 rdata => sample_f0_B_rdata,
363 rdata => sample_f0_B_rdata,
363 empty => sample_f0_B_empty,
364 empty => sample_f0_B_empty,
364 full => sample_f0_B_full,
365 full => sample_f0_B_full,
365 almost_full => OPEN);
366 almost_full => OPEN);
366
367
367 -----------------------------------------------------------------------------
368 -----------------------------------------------------------------------------
368 -- sample_f1_wen in
369 -- sample_f1_wen in
369 -- sample_f1_wdata in
370 -- sample_f1_wdata in
370 -- sample_f1_full OUT
371 -- sample_f1_full OUT
371
372
372 sample_f1_wen_head_in <= '0' WHEN sample_f1_wen_s = "00000" ELSE '1';
373 sample_f1_wen_head_in <= '0' WHEN sample_f1_wen_s = "00000" ELSE '1';
373 sample_f1_full_head_in <= '0' WHEN sample_f1_full = "00000" ELSE '1';
374 sample_f1_full_head_in <= '0' WHEN sample_f1_full = "00000" ELSE '1';
374 sample_f1_empty_head_in <= '1' WHEN sample_f1_empty = "11111" ELSE '0';
375 sample_f1_empty_head_in <= '1' WHEN sample_f1_empty = "11111" ELSE '0';
375
376
376 lpp_lfr_ms_reg_head_1:lpp_lfr_ms_reg_head
377 lpp_lfr_ms_reg_head_1:lpp_lfr_ms_reg_head
377 PORT MAP (
378 PORT MAP (
378 clk => clk,
379 clk => clk,
379 rstn => rstn,
380 rstn => rstn,
380 in_wen => sample_f1_wen_head_in,
381 in_wen => sample_f1_wen_head_in,
381 in_data => sample_f1_wdata,
382 in_data => sample_f1_wdata,
382 in_full => sample_f1_full_head_in,
383 in_full => sample_f1_full_head_in,
383 in_empty => sample_f1_empty_head_in,
384 in_empty => sample_f1_empty_head_in,
384 out_write_error => error_wen_f1,
385 out_write_error => error_wen_f1,
385 out_wen => sample_f1_wen_head_out,
386 out_wen => sample_f1_wen_head_out,
386 out_data => sample_f1_wdata_head,
387 out_data => sample_f1_wdata_head,
387 out_full => sample_f1_full_head_out);
388 out_full => sample_f1_full_head_out);
388
389
389 sample_f1_wen_head <= sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out;
390 sample_f1_wen_head <= sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out;
390
391
391
392
392 lppFIFOxN_f1 : lppFIFOxN
393 lppFIFOxN_f1 : lppFIFOxN
393 GENERIC MAP (
394 GENERIC MAP (
394 tech => 0,
395 tech => 0,
395 Mem_use => Mem_use,
396 Mem_use => Mem_use,
396 Data_sz => 16,
397 Data_sz => 16,
397 Addr_sz => 8,
398 Addr_sz => 8,
398 FifoCnt => 5)
399 FifoCnt => 5)
399 PORT MAP (
400 PORT MAP (
400 clk => clk,
401 clk => clk,
401 rstn => rstn,
402 rstn => rstn,
402
403
403 ReUse => (OTHERS => '0'),
404 ReUse => (OTHERS => '0'),
404 run => (OTHERS => '1'),
405 run => (OTHERS => '1'),
405
406
406 wen => sample_f1_wen_head,
407 wen => sample_f1_wen_head,
407 wdata => sample_f1_wdata_head,
408 wdata => sample_f1_wdata_head,
408 ren => sample_f1_ren,
409 ren => sample_f1_ren,
409 rdata => sample_f1_rdata,
410 rdata => sample_f1_rdata,
410 empty => sample_f1_empty,
411 empty => sample_f1_empty,
411 full => sample_f1_full,
412 full => sample_f1_full,
412 almost_full => sample_f1_almost_full);
413 almost_full => sample_f1_almost_full);
413
414
414
415
415 one_sample_f1_wen <= '0' WHEN sample_f1_wen_head = "11111" ELSE '1';
416 one_sample_f1_wen <= '0' WHEN sample_f1_wen_head = "11111" ELSE '1';
416
417
417 PROCESS (clk, rstn)
418 PROCESS (clk, rstn)
418 BEGIN -- PROCESS
419 BEGIN -- PROCESS
419 IF rstn = '0' THEN -- asynchronous reset (active low)
420 IF rstn = '0' THEN -- asynchronous reset (active low)
420 one_sample_f1_full <= '0';
421 one_sample_f1_full <= '0';
421 --error_wen_f1 <= '0';
422 --error_wen_f1 <= '0';
422 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
423 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
423 IF sample_f1_full_head_out = '0' THEN
424 IF sample_f1_full_head_out = '0' THEN
424 one_sample_f1_full <= '0';
425 one_sample_f1_full <= '0';
425 ELSE
426 ELSE
426 one_sample_f1_full <= '1';
427 one_sample_f1_full <= '1';
427 END IF;
428 END IF;
428 --error_wen_f1 <= one_sample_f1_wen AND one_sample_f1_full;
429 --error_wen_f1 <= one_sample_f1_wen AND one_sample_f1_full;
429 END IF;
430 END IF;
430 END PROCESS;
431 END PROCESS;
431
432
432 -----------------------------------------------------------------------------
433 -----------------------------------------------------------------------------
433
434
434
435
435 lppFIFOxN_f2 : lppFIFOxN
436 lppFIFOxN_f2 : lppFIFOxN
436 GENERIC MAP (
437 GENERIC MAP (
437 tech => 0,
438 tech => 0,
438 Mem_use => Mem_use,
439 Mem_use => Mem_use,
439 Data_sz => 16,
440 Data_sz => 16,
440 Addr_sz => 8,
441 Addr_sz => 8,
441 FifoCnt => 5)
442 FifoCnt => 5)
442 PORT MAP (
443 PORT MAP (
443 clk => clk,
444 clk => clk,
444 rstn => rstn,
445 rstn => rstn,
445
446
446 ReUse => (OTHERS => '0'),
447 ReUse => (OTHERS => '0'),
447 run => (OTHERS => '1'),
448 run => (OTHERS => '1'),
448
449
449 wen => sample_f2_wen_s,
450 wen => sample_f2_wen_s,
450 wdata => sample_f2_wdata,
451 wdata => sample_f2_wdata,
451 ren => sample_f2_ren,
452 ren => sample_f2_ren,
452 rdata => sample_f2_rdata,
453 rdata => sample_f2_rdata,
453 empty => sample_f2_empty,
454 empty => sample_f2_empty,
454 full => sample_f2_full,
455 full => sample_f2_full,
455 almost_full => OPEN);
456 almost_full => OPEN);
456
457
457
458
458 one_sample_f2_wen <= '0' WHEN sample_f2_wen_s = "11111" ELSE '1';
459 one_sample_f2_wen <= '0' WHEN sample_f2_wen_s = "11111" ELSE '1';
459
460
460 PROCESS (clk, rstn)
461 PROCESS (clk, rstn)
461 BEGIN -- PROCESS
462 BEGIN -- PROCESS
462 IF rstn = '0' THEN -- asynchronous reset (active low)
463 IF rstn = '0' THEN -- asynchronous reset (active low)
463 one_sample_f2_full <= '0';
464 one_sample_f2_full <= '0';
464 error_wen_f2 <= '0';
465 error_wen_f2 <= '0';
465 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
466 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
466 IF sample_f2_full = "00000" THEN
467 IF sample_f2_full = "00000" THEN
467 one_sample_f2_full <= '0';
468 one_sample_f2_full <= '0';
468 ELSE
469 ELSE
469 one_sample_f2_full <= '1';
470 one_sample_f2_full <= '1';
470 END IF;
471 END IF;
471 error_wen_f2 <= one_sample_f2_wen AND one_sample_f2_full;
472 error_wen_f2 <= one_sample_f2_wen AND one_sample_f2_full;
472 END IF;
473 END IF;
473 END PROCESS;
474 END PROCESS;
474
475
475 -----------------------------------------------------------------------------
476 -----------------------------------------------------------------------------
476 -- FSM SELECT CHANNEL
477 -- FSM SELECT CHANNEL
477 -----------------------------------------------------------------------------
478 -----------------------------------------------------------------------------
478 PROCESS (clk, rstn)
479 PROCESS (clk, rstn)
479 BEGIN
480 BEGIN
480 IF rstn = '0' THEN
481 IF rstn = '0' THEN
481 state_fsm_select_channel <= IDLE;
482 state_fsm_select_channel <= IDLE;
482 select_channel <= (OTHERS => '0');
483 select_channel <= (OTHERS => '0');
483 ELSIF clk'EVENT AND clk = '1' THEN
484 ELSIF clk'EVENT AND clk = '1' THEN
484 CASE state_fsm_select_channel IS
485 CASE state_fsm_select_channel IS
485 WHEN IDLE =>
486 WHEN IDLE =>
486 IF sample_f1_full = "11111" THEN
487 IF sample_f1_full = "11111" THEN
487 state_fsm_select_channel <= SWITCH_F1;
488 state_fsm_select_channel <= SWITCH_F1;
488 select_channel <= "10";
489 select_channel <= "10";
489 ELSIF sample_f1_almost_full = "00000" THEN
490 ELSIF sample_f1_almost_full = "00000" THEN
490 IF sample_f0_A_full = "11111" THEN
491 IF sample_f0_A_full = "11111" THEN
491 state_fsm_select_channel <= SWITCH_F0_A;
492 state_fsm_select_channel <= SWITCH_F0_A;
492 select_channel <= "00";
493 select_channel <= "00";
493 ELSIF sample_f0_B_full = "11111" THEN
494 ELSIF sample_f0_B_full = "11111" THEN
494 state_fsm_select_channel <= SWITCH_F0_B;
495 state_fsm_select_channel <= SWITCH_F0_B;
495 select_channel <= "01";
496 select_channel <= "01";
496 ELSIF sample_f2_full = "11111" THEN
497 ELSIF sample_f2_full = "11111" THEN
497 state_fsm_select_channel <= SWITCH_F2;
498 state_fsm_select_channel <= SWITCH_F2;
498 select_channel <= "11";
499 select_channel <= "11";
499 END IF;
500 END IF;
500 END IF;
501 END IF;
501
502
502 WHEN SWITCH_F0_A =>
503 WHEN SWITCH_F0_A =>
503 IF sample_f0_A_empty = "11111" THEN
504 IF sample_f0_A_empty = "11111" THEN
504 state_fsm_select_channel <= IDLE;
505 state_fsm_select_channel <= IDLE;
505 select_channel <= (OTHERS => '0');
506 select_channel <= (OTHERS => '0');
506 END IF;
507 END IF;
507 WHEN SWITCH_F0_B =>
508 WHEN SWITCH_F0_B =>
508 IF sample_f0_B_empty = "11111" THEN
509 IF sample_f0_B_empty = "11111" THEN
509 state_fsm_select_channel <= IDLE;
510 state_fsm_select_channel <= IDLE;
510 select_channel <= (OTHERS => '0');
511 select_channel <= (OTHERS => '0');
511 END IF;
512 END IF;
512 WHEN SWITCH_F1 =>
513 WHEN SWITCH_F1 =>
513 IF sample_f1_empty = "11111" THEN
514 IF sample_f1_empty = "11111" THEN
514 state_fsm_select_channel <= IDLE;
515 state_fsm_select_channel <= IDLE;
515 select_channel <= (OTHERS => '0');
516 select_channel <= (OTHERS => '0');
516 END IF;
517 END IF;
517 WHEN SWITCH_F2 =>
518 WHEN SWITCH_F2 =>
518 IF sample_f2_empty = "11111" THEN
519 IF sample_f2_empty = "11111" THEN
519 state_fsm_select_channel <= IDLE;
520 state_fsm_select_channel <= IDLE;
520 select_channel <= (OTHERS => '0');
521 select_channel <= (OTHERS => '0');
521 END IF;
522 END IF;
522 WHEN OTHERS => NULL;
523 WHEN OTHERS => NULL;
523 END CASE;
524 END CASE;
524
525
525 END IF;
526 END IF;
526 END PROCESS;
527 END PROCESS;
527
528
528 PROCESS (clk, rstn)
529 PROCESS (clk, rstn)
529 BEGIN
530 BEGIN
530 IF rstn = '0' THEN
531 IF rstn = '0' THEN
531 select_channel_reg <= (OTHERS => '0');
532 select_channel_reg <= (OTHERS => '0');
532 --pre_state_fsm_select_channel <= IDLE;
533 --pre_state_fsm_select_channel <= IDLE;
533 ELSIF clk'EVENT AND clk = '1' THEN
534 ELSIF clk'EVENT AND clk = '1' THEN
534 select_channel_reg <= select_channel;
535 select_channel_reg <= select_channel;
535 --pre_state_fsm_select_channel <= state_fsm_select_channel;
536 --pre_state_fsm_select_channel <= state_fsm_select_channel;
536 END IF;
537 END IF;
537 END PROCESS;
538 END PROCESS;
538
539
539
540
540 -----------------------------------------------------------------------------
541 -----------------------------------------------------------------------------
541 -- SWITCH SELECT CHANNEL
542 -- SWITCH SELECT CHANNEL
542 -----------------------------------------------------------------------------
543 -----------------------------------------------------------------------------
543 sample_empty <= sample_f0_A_empty WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
544 sample_empty <= sample_f0_A_empty WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
544 sample_f0_B_empty WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
545 sample_f0_B_empty WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
545 sample_f1_empty WHEN state_fsm_select_channel = SWITCH_F1 ELSE
546 sample_f1_empty WHEN state_fsm_select_channel = SWITCH_F1 ELSE
546 sample_f2_empty WHEN state_fsm_select_channel = SWITCH_F2 ELSE
547 sample_f2_empty WHEN state_fsm_select_channel = SWITCH_F2 ELSE
547 (OTHERS => '1');
548 (OTHERS => '1');
548
549
549 sample_full <= sample_f0_A_full WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
550 sample_full <= sample_f0_A_full WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
550 sample_f0_B_full WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
551 sample_f0_B_full WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
551 sample_f1_full WHEN state_fsm_select_channel = SWITCH_F1 ELSE
552 sample_f1_full WHEN state_fsm_select_channel = SWITCH_F1 ELSE
552 sample_f2_full WHEN state_fsm_select_channel = SWITCH_F2 ELSE
553 sample_f2_full WHEN state_fsm_select_channel = SWITCH_F2 ELSE
553 (OTHERS => '0');
554 (OTHERS => '0');
554
555
555 --sample_rdata <= sample_f0_A_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_A ELSE
556 --sample_rdata <= sample_f0_A_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_A ELSE
556 -- sample_f0_B_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_B ELSE
557 -- sample_f0_B_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_B ELSE
557 -- sample_f1_rdata WHEN pre_state_fsm_select_channel = SWITCH_F1 ELSE
558 -- sample_f1_rdata WHEN pre_state_fsm_select_channel = SWITCH_F1 ELSE
558 -- sample_f2_rdata; -- WHEN state_fsm_select_channel = SWITCH_F2 ELSE
559 -- sample_f2_rdata; -- WHEN state_fsm_select_channel = SWITCH_F2 ELSE
559 sample_rdata <= sample_f0_A_rdata WHEN select_channel_reg = "00" ELSE
560 sample_rdata <= sample_f0_A_rdata WHEN select_channel_reg = "00" ELSE
560 sample_f0_B_rdata WHEN select_channel_reg = "01" ELSE
561 sample_f0_B_rdata WHEN select_channel_reg = "01" ELSE
561 sample_f1_rdata WHEN select_channel_reg = "10" ELSE
562 sample_f1_rdata WHEN select_channel_reg = "10" ELSE
562 sample_f2_rdata; -- WHEN state_fsm_select_channel = SWITCH_F2 ELSE
563 sample_f2_rdata; -- WHEN state_fsm_select_channel = SWITCH_F2 ELSE
563
564
564
565
565 sample_f0_A_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_A ELSE (OTHERS => '1');
566 sample_f0_A_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_A ELSE (OTHERS => '1');
566 sample_f0_B_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_B ELSE (OTHERS => '1');
567 sample_f0_B_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_B ELSE (OTHERS => '1');
567 sample_f1_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F1 ELSE (OTHERS => '1');
568 sample_f1_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F1 ELSE (OTHERS => '1');
568 sample_f2_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F2 ELSE (OTHERS => '1');
569 sample_f2_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F2 ELSE (OTHERS => '1');
569
570
570
571
571 status_channel <= time_reg_f0_A & "00" WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
572 status_channel <= time_reg_f0_A & "00" WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
572 time_reg_f0_B & "00" WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
573 time_reg_f0_B & "00" WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
573 time_reg_f1 & "01" WHEN state_fsm_select_channel = SWITCH_F1 ELSE
574 time_reg_f1 & "01" WHEN state_fsm_select_channel = SWITCH_F1 ELSE
574 time_reg_f2 & "10"; -- WHEN state_fsm_select_channel = SWITCH_F2
575 time_reg_f2 & "10"; -- WHEN state_fsm_select_channel = SWITCH_F2
575
576
576 -----------------------------------------------------------------------------
577 -----------------------------------------------------------------------------
577 -- FSM LOAD FFT
578 -- FSM LOAD FFT
578 -----------------------------------------------------------------------------
579 -----------------------------------------------------------------------------
579
580
580 sample_ren <= (OTHERS => '1') WHEN fft_ongoing_counter = '1' ELSE
581 sample_ren <= (OTHERS => '1') WHEN fft_ongoing_counter = '1' ELSE
581 sample_ren_s WHEN sample_load = '1' ELSE
582 sample_ren_s WHEN sample_load = '1' ELSE
582 (OTHERS => '1');
583 (OTHERS => '1');
583
584
584 PROCESS (clk, rstn)
585 PROCESS (clk, rstn)
585 BEGIN
586 BEGIN
586 IF rstn = '0' THEN
587 IF rstn = '0' THEN
587 sample_ren_s <= (OTHERS => '1');
588 sample_ren_s <= (OTHERS => '1');
588 state_fsm_load_FFT <= IDLE;
589 state_fsm_load_FFT <= IDLE;
589 status_MS_input <= (OTHERS => '0');
590 status_MS_input <= (OTHERS => '0');
590 select_fifo <= "000";
591 select_fifo <= "000";
591 --next_state_fsm_load_FFT <= IDLE;
592 --next_state_fsm_load_FFT <= IDLE;
592 --sample_valid <= '0';
593 --sample_valid <= '0';
593 ELSIF clk'EVENT AND clk = '1' THEN
594 ELSIF clk'EVENT AND clk = '1' THEN
594 CASE state_fsm_load_FFT IS
595 CASE state_fsm_load_FFT IS
595 WHEN IDLE =>
596 WHEN IDLE =>
596 --sample_valid <= '0';
597 --sample_valid <= '0';
597 sample_ren_s <= (OTHERS => '1');
598 sample_ren_s <= (OTHERS => '1');
598 IF sample_full = "11111" AND sample_load = '1' THEN
599 IF sample_full = "11111" AND sample_load = '1' THEN
599 state_fsm_load_FFT <= FIFO_1;
600 state_fsm_load_FFT <= FIFO_1;
600 status_MS_input <= status_channel;
601 status_MS_input <= status_channel;
601 select_fifo <= "000";
602 select_fifo <= "000";
602 END IF;
603 END IF;
603
604
604 WHEN FIFO_1 =>
605 WHEN FIFO_1 =>
605 sample_ren_s <= "1111" & NOT(sample_load);
606 sample_ren_s <= "1111" & NOT(sample_load);
606 IF sample_empty(0) = '1' THEN
607 IF sample_empty(0) = '1' THEN
607 sample_ren_s <= (OTHERS => '1');
608 sample_ren_s <= (OTHERS => '1');
608 state_fsm_load_FFT <= FIFO_2;
609 state_fsm_load_FFT <= FIFO_2;
609 select_fifo <= "001";
610 select_fifo <= "001";
610 END IF;
611 END IF;
611
612
612 WHEN FIFO_2 =>
613 WHEN FIFO_2 =>
613 sample_ren_s <= "111" & NOT(sample_load) & '1';
614 sample_ren_s <= "111" & NOT(sample_load) & '1';
614 IF sample_empty(1) = '1' THEN
615 IF sample_empty(1) = '1' THEN
615 sample_ren_s <= (OTHERS => '1');
616 sample_ren_s <= (OTHERS => '1');
616 state_fsm_load_FFT <= FIFO_3;
617 state_fsm_load_FFT <= FIFO_3;
617 select_fifo <= "010";
618 select_fifo <= "010";
618 END IF;
619 END IF;
619
620
620 WHEN FIFO_3 =>
621 WHEN FIFO_3 =>
621 sample_ren_s <= "11" & NOT(sample_load) & "11";
622 sample_ren_s <= "11" & NOT(sample_load) & "11";
622 IF sample_empty(2) = '1' THEN
623 IF sample_empty(2) = '1' THEN
623 sample_ren_s <= (OTHERS => '1');
624 sample_ren_s <= (OTHERS => '1');
624 state_fsm_load_FFT <= FIFO_4;
625 state_fsm_load_FFT <= FIFO_4;
625 select_fifo <= "011";
626 select_fifo <= "011";
626 END IF;
627 END IF;
627
628
628 WHEN FIFO_4 =>
629 WHEN FIFO_4 =>
629 sample_ren_s <= '1' & NOT(sample_load) & "111";
630 sample_ren_s <= '1' & NOT(sample_load) & "111";
630 IF sample_empty(3) = '1' THEN
631 IF sample_empty(3) = '1' THEN
631 sample_ren_s <= (OTHERS => '1');
632 sample_ren_s <= (OTHERS => '1');
632 state_fsm_load_FFT <= FIFO_5;
633 state_fsm_load_FFT <= FIFO_5;
633 select_fifo <= "100";
634 select_fifo <= "100";
634 END IF;
635 END IF;
635
636
636 WHEN FIFO_5 =>
637 WHEN FIFO_5 =>
637 sample_ren_s <= NOT(sample_load) & "1111";
638 sample_ren_s <= NOT(sample_load) & "1111";
638 IF sample_empty(4) = '1' THEN
639 IF sample_empty(4) = '1' THEN
639 sample_ren_s <= (OTHERS => '1');
640 sample_ren_s <= (OTHERS => '1');
640 state_fsm_load_FFT <= IDLE;
641 state_fsm_load_FFT <= IDLE;
641 select_fifo <= "000";
642 select_fifo <= "000";
642 END IF;
643 END IF;
643 WHEN OTHERS => NULL;
644 WHEN OTHERS => NULL;
644 END CASE;
645 END CASE;
645 END IF;
646 END IF;
646 END PROCESS;
647 END PROCESS;
647
648
648 PROCESS (clk, rstn)
649 PROCESS (clk, rstn)
649 BEGIN
650 BEGIN
650 IF rstn = '0' THEN
651 IF rstn = '0' THEN
651 sample_valid_r <= '0';
652 sample_valid_r <= '0';
652 select_fifo_reg <= (OTHERS => '0');
653 select_fifo_reg <= (OTHERS => '0');
653 --next_state_fsm_load_FFT <= IDLE;
654 --next_state_fsm_load_FFT <= IDLE;
654 ELSIF clk'EVENT AND clk = '1' THEN
655 ELSIF clk'EVENT AND clk = '1' THEN
655 select_fifo_reg <= select_fifo;
656 select_fifo_reg <= select_fifo;
656 --next_state_fsm_load_FFT <= state_fsm_load_FFT;
657 --next_state_fsm_load_FFT <= state_fsm_load_FFT;
657 IF sample_ren_s = "11111" THEN
658 IF sample_ren_s = "11111" THEN
658 sample_valid_r <= '0';
659 sample_valid_r <= '0';
659 ELSE
660 ELSE
660 sample_valid_r <= '1';
661 sample_valid_r <= '1';
661 END IF;
662 END IF;
662 END IF;
663 END IF;
663 END PROCESS;
664 END PROCESS;
664
665
665 sample_valid <= '0' WHEN fft_ongoing_counter = '1' ELSE sample_valid_r AND sample_load;
666 sample_valid <= '0' WHEN fft_ongoing_counter = '1' ELSE sample_valid_r AND sample_load;
666
667
667 --sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN next_state_fsm_load_FFT = FIFO_1 ELSE
668 --sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN next_state_fsm_load_FFT = FIFO_1 ELSE
668 -- sample_rdata(16*2-1 DOWNTO 16*1) WHEN next_state_fsm_load_FFT = FIFO_2 ELSE
669 -- sample_rdata(16*2-1 DOWNTO 16*1) WHEN next_state_fsm_load_FFT = FIFO_2 ELSE
669 -- sample_rdata(16*3-1 DOWNTO 16*2) WHEN next_state_fsm_load_FFT = FIFO_3 ELSE
670 -- sample_rdata(16*3-1 DOWNTO 16*2) WHEN next_state_fsm_load_FFT = FIFO_3 ELSE
670 -- sample_rdata(16*4-1 DOWNTO 16*3) WHEN next_state_fsm_load_FFT = FIFO_4 ELSE
671 -- sample_rdata(16*4-1 DOWNTO 16*3) WHEN next_state_fsm_load_FFT = FIFO_4 ELSE
671 -- sample_rdata(16*5-1 DOWNTO 16*4); --WHEN next_state_fsm_load_FFT = FIFO_5 ELSE
672 -- sample_rdata(16*5-1 DOWNTO 16*4); --WHEN next_state_fsm_load_FFT = FIFO_5 ELSE
672 sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN select_fifo_reg = "000" ELSE
673 sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN select_fifo_reg = "000" ELSE
673 sample_rdata(16*2-1 DOWNTO 16*1) WHEN select_fifo_reg = "001" ELSE
674 sample_rdata(16*2-1 DOWNTO 16*1) WHEN select_fifo_reg = "001" ELSE
674 sample_rdata(16*3-1 DOWNTO 16*2) WHEN select_fifo_reg = "010" ELSE
675 sample_rdata(16*3-1 DOWNTO 16*2) WHEN select_fifo_reg = "010" ELSE
675 sample_rdata(16*4-1 DOWNTO 16*3) WHEN select_fifo_reg = "011" ELSE
676 sample_rdata(16*4-1 DOWNTO 16*3) WHEN select_fifo_reg = "011" ELSE
676 sample_rdata(16*5-1 DOWNTO 16*4); --WHEN next_state_fsm_load_FFT = FIFO_5 ELSE
677 sample_rdata(16*5-1 DOWNTO 16*4); --WHEN next_state_fsm_load_FFT = FIFO_5 ELSE
677
678
678 -----------------------------------------------------------------------------
679 -----------------------------------------------------------------------------
679 -- FFT
680 -- FFT
680 -----------------------------------------------------------------------------
681 -----------------------------------------------------------------------------
681 lpp_lfr_ms_FFT_1 : lpp_lfr_ms_FFT
682 lpp_lfr_ms_FFT_1 : lpp_lfr_ms_FFT
682 PORT MAP (
683 PORT MAP (
683 clk => clk,
684 clk => clk,
684 rstn => rstn,
685 rstn => rstn,
685 sample_valid => sample_valid,
686 sample_valid => sample_valid,
686 fft_read => fft_read,
687 fft_read => fft_read,
687 sample_data => sample_data,
688 sample_data => sample_data,
688 sample_load => sample_load,
689 sample_load => sample_load,
689 fft_pong => fft_pong,
690 fft_pong => fft_pong,
690 fft_data_im => fft_data_im,
691 fft_data_im => fft_data_im,
691 fft_data_re => fft_data_re,
692 fft_data_re => fft_data_re,
692 fft_data_valid => fft_data_valid,
693 fft_data_valid => fft_data_valid,
693 fft_ready => fft_ready);
694 fft_ready => fft_ready);
694
695
695 debug_vector(0) <= fft_data_valid;
696 debug_vector(0) <= fft_data_valid;
696 debug_vector(1) <= fft_ready;
697 debug_vector(1) <= fft_ready;
697 debug_vector(11 DOWNTO 2) <= (OTHERS => '0');
698 debug_vector(11 DOWNTO 2) <= (OTHERS => '0');
698
699
699
700
700 -----------------------------------------------------------------------------
701 -----------------------------------------------------------------------------
701 fft_ready_rising_down <= fft_ready_reg AND NOT fft_ready;
702 fft_ready_rising_down <= fft_ready_reg AND NOT fft_ready;
702 sample_load_rising_down <= sample_load_reg AND NOT sample_load;
703 sample_load_rising_down <= sample_load_reg AND NOT sample_load;
703
704
704 PROCESS (clk, rstn)
705 PROCESS (clk, rstn)
705 BEGIN
706 BEGIN
706 IF rstn = '0' THEN
707 IF rstn = '0' THEN
707 fft_ready_reg <= '0';
708 fft_ready_reg <= '0';
708 sample_load_reg <= '0';
709 sample_load_reg <= '0';
709
710
710 fft_ongoing_counter <= '0';
711 fft_ongoing_counter <= '0';
711 ELSIF clk'event AND clk = '1' THEN
712 ELSIF clk'event AND clk = '1' THEN
712 fft_ready_reg <= fft_ready;
713 fft_ready_reg <= fft_ready;
713 sample_load_reg <= sample_load;
714 sample_load_reg <= sample_load;
714
715
715 IF fft_ready_rising_down = '1' AND sample_load_rising_down = '0' THEN
716 IF fft_ready_rising_down = '1' AND sample_load_rising_down = '0' THEN
716 fft_ongoing_counter <= '0';
717 fft_ongoing_counter <= '0';
717
718
718 -- CASE fft_ongoing_counter IS
719 -- CASE fft_ongoing_counter IS
719 -- WHEN "01" => fft_ongoing_counter <= "00";
720 -- WHEN "01" => fft_ongoing_counter <= "00";
720 ---- WHEN "10" => fft_ongoing_counter <= "01";
721 ---- WHEN "10" => fft_ongoing_counter <= "01";
721 -- WHEN OTHERS => NULL;
722 -- WHEN OTHERS => NULL;
722 -- END CASE;
723 -- END CASE;
723 ELSIF fft_ready_rising_down = '0' AND sample_load_rising_down = '1' THEN
724 ELSIF fft_ready_rising_down = '0' AND sample_load_rising_down = '1' THEN
724 fft_ongoing_counter <= '1';
725 fft_ongoing_counter <= '1';
725 -- CASE fft_ongoing_counter IS
726 -- CASE fft_ongoing_counter IS
726 -- WHEN "00" => fft_ongoing_counter <= "01";
727 -- WHEN "00" => fft_ongoing_counter <= "01";
727 ---- WHEN "01" => fft_ongoing_counter <= "10";
728 ---- WHEN "01" => fft_ongoing_counter <= "10";
728 -- WHEN OTHERS => NULL;
729 -- WHEN OTHERS => NULL;
729 -- END CASE;
730 -- END CASE;
730 END IF;
731 END IF;
731
732
732 END IF;
733 END IF;
733 END PROCESS;
734 END PROCESS;
734
735
735 -----------------------------------------------------------------------------
736 -----------------------------------------------------------------------------
736 PROCESS (clk, rstn)
737 PROCESS (clk, rstn)
737 BEGIN
738 BEGIN
738 IF rstn = '0' THEN
739 IF rstn = '0' THEN
739 state_fsm_load_MS_memory <= IDLE;
740 state_fsm_load_MS_memory <= IDLE;
740 current_fifo_load <= "00001";
741 current_fifo_load <= "00001";
741 ELSIF clk'EVENT AND clk = '1' THEN
742 ELSIF clk'EVENT AND clk = '1' THEN
742 CASE state_fsm_load_MS_memory IS
743 CASE state_fsm_load_MS_memory IS
743 WHEN IDLE =>
744 WHEN IDLE =>
744 IF current_fifo_empty = '1' AND fft_ready = '1' AND current_fifo_locked = '0' THEN
745 IF current_fifo_empty = '1' AND fft_ready = '1' AND current_fifo_locked = '0' THEN
745 state_fsm_load_MS_memory <= LOAD_FIFO;
746 state_fsm_load_MS_memory <= LOAD_FIFO;
746 END IF;
747 END IF;
747 WHEN LOAD_FIFO =>
748 WHEN LOAD_FIFO =>
748 IF current_fifo_full = '1' THEN
749 IF current_fifo_full = '1' THEN
749 state_fsm_load_MS_memory <= TRASH_FFT;
750 state_fsm_load_MS_memory <= TRASH_FFT;
750 END IF;
751 END IF;
751 WHEN TRASH_FFT =>
752 WHEN TRASH_FFT =>
752 IF fft_ready = '0' THEN
753 IF fft_ready = '0' THEN
753 state_fsm_load_MS_memory <= IDLE;
754 state_fsm_load_MS_memory <= IDLE;
754 current_fifo_load <= current_fifo_load(3 DOWNTO 0) & current_fifo_load(4);
755 current_fifo_load <= current_fifo_load(3 DOWNTO 0) & current_fifo_load(4);
755 END IF;
756 END IF;
756 WHEN OTHERS => NULL;
757 WHEN OTHERS => NULL;
757 END CASE;
758 END CASE;
758
759
759 END IF;
760 END IF;
760 END PROCESS;
761 END PROCESS;
761
762
762 current_fifo_empty <= MEM_IN_SM_Empty(0) WHEN current_fifo_load(0) = '1' ELSE
763 current_fifo_empty <= MEM_IN_SM_Empty(0) WHEN current_fifo_load(0) = '1' ELSE
763 MEM_IN_SM_Empty(1) WHEN current_fifo_load(1) = '1' ELSE
764 MEM_IN_SM_Empty(1) WHEN current_fifo_load(1) = '1' ELSE
764 MEM_IN_SM_Empty(2) WHEN current_fifo_load(2) = '1' ELSE
765 MEM_IN_SM_Empty(2) WHEN current_fifo_load(2) = '1' ELSE
765 MEM_IN_SM_Empty(3) WHEN current_fifo_load(3) = '1' ELSE
766 MEM_IN_SM_Empty(3) WHEN current_fifo_load(3) = '1' ELSE
766 MEM_IN_SM_Empty(4); -- WHEN current_fifo_load(3) = '1' ELSE
767 MEM_IN_SM_Empty(4); -- WHEN current_fifo_load(3) = '1' ELSE
767
768
768 current_fifo_full <= MEM_IN_SM_Full(0) WHEN current_fifo_load(0) = '1' ELSE
769 current_fifo_full <= MEM_IN_SM_Full(0) WHEN current_fifo_load(0) = '1' ELSE
769 MEM_IN_SM_Full(1) WHEN current_fifo_load(1) = '1' ELSE
770 MEM_IN_SM_Full(1) WHEN current_fifo_load(1) = '1' ELSE
770 MEM_IN_SM_Full(2) WHEN current_fifo_load(2) = '1' ELSE
771 MEM_IN_SM_Full(2) WHEN current_fifo_load(2) = '1' ELSE
771 MEM_IN_SM_Full(3) WHEN current_fifo_load(3) = '1' ELSE
772 MEM_IN_SM_Full(3) WHEN current_fifo_load(3) = '1' ELSE
772 MEM_IN_SM_Full(4); -- WHEN current_fifo_load(3) = '1' ELSE
773 MEM_IN_SM_Full(4); -- WHEN current_fifo_load(3) = '1' ELSE
773
774
774 current_fifo_locked <= MEM_IN_SM_locked(0) WHEN current_fifo_load(0) = '1' ELSE
775 current_fifo_locked <= MEM_IN_SM_locked(0) WHEN current_fifo_load(0) = '1' ELSE
775 MEM_IN_SM_locked(1) WHEN current_fifo_load(1) = '1' ELSE
776 MEM_IN_SM_locked(1) WHEN current_fifo_load(1) = '1' ELSE
776 MEM_IN_SM_locked(2) WHEN current_fifo_load(2) = '1' ELSE
777 MEM_IN_SM_locked(2) WHEN current_fifo_load(2) = '1' ELSE
777 MEM_IN_SM_locked(3) WHEN current_fifo_load(3) = '1' ELSE
778 MEM_IN_SM_locked(3) WHEN current_fifo_load(3) = '1' ELSE
778 MEM_IN_SM_locked(4); -- WHEN current_fifo_load(3) = '1' ELSE
779 MEM_IN_SM_locked(4); -- WHEN current_fifo_load(3) = '1' ELSE
779
780
780 fft_read <= '0' WHEN state_fsm_load_MS_memory = IDLE ELSE '1';
781 fft_read <= '0' WHEN state_fsm_load_MS_memory = IDLE ELSE '1';
781
782
782 all_fifo : FOR I IN 4 DOWNTO 0 GENERATE
783 all_fifo : FOR I IN 4 DOWNTO 0 GENERATE
783 MEM_IN_SM_wen_s(I) <= '0' WHEN fft_data_valid = '1'
784 MEM_IN_SM_wen_s(I) <= '0' WHEN fft_data_valid = '1'
784 AND state_fsm_load_MS_memory = LOAD_FIFO
785 AND state_fsm_load_MS_memory = LOAD_FIFO
785 AND current_fifo_load(I) = '1'
786 AND current_fifo_load(I) = '1'
786 ELSE '1';
787 ELSE '1';
787 END GENERATE all_fifo;
788 END GENERATE all_fifo;
788
789
789 PROCESS (clk, rstn)
790 PROCESS (clk, rstn)
790 BEGIN
791 BEGIN
791 IF rstn = '0' THEN
792 IF rstn = '0' THEN
792 MEM_IN_SM_wen <= (OTHERS => '1');
793 MEM_IN_SM_wen <= (OTHERS => '1');
793 ELSIF clk'EVENT AND clk = '1' THEN
794 ELSIF clk'EVENT AND clk = '1' THEN
794 MEM_IN_SM_wen <= MEM_IN_SM_wen_s;
795 MEM_IN_SM_wen <= MEM_IN_SM_wen_s;
795 END IF;
796 END IF;
796 END PROCESS;
797 END PROCESS;
797
798
798 MEM_IN_SM_wData <= (fft_data_im & fft_data_re) &
799 MEM_IN_SM_wData <= (fft_data_im & fft_data_re) &
799 (fft_data_im & fft_data_re) &
800 (fft_data_im & fft_data_re) &
800 (fft_data_im & fft_data_re) &
801 (fft_data_im & fft_data_re) &
801 (fft_data_im & fft_data_re) &
802 (fft_data_im & fft_data_re) &
802 (fft_data_im & fft_data_re);
803 (fft_data_im & fft_data_re);
803 -----------------------------------------------------------------------------
804 -----------------------------------------------------------------------------
804
805
805
806
806 -----------------------------------------------------------------------------
807 -----------------------------------------------------------------------------
807 Mem_In_SpectralMatrix : lppFIFOxN
808 Mem_In_SpectralMatrix : lppFIFOxN
808 GENERIC MAP (
809 GENERIC MAP (
809 tech => 0,
810 tech => 0,
810 Mem_use => Mem_use,
811 Mem_use => Mem_use,
811 Data_sz => 32, --16,
812 Data_sz => 32, --16,
812 Addr_sz => 7, --8
813 Addr_sz => 7, --8
813 FifoCnt => 5)
814 FifoCnt => 5)
814 PORT MAP (
815 PORT MAP (
815 clk => clk,
816 clk => clk,
816 rstn => rstn,
817 rstn => rstn,
817
818
818 ReUse => MEM_IN_SM_ReUse,
819 ReUse => MEM_IN_SM_ReUse,
819 run => (OTHERS => '1'),
820 run => (OTHERS => '1'),
820
821
821 wen => MEM_IN_SM_wen,
822 wen => MEM_IN_SM_wen,
822 wdata => MEM_IN_SM_wData,
823 wdata => MEM_IN_SM_wData,
823
824
824 ren => MEM_IN_SM_ren,
825 ren => MEM_IN_SM_ren,
825 rdata => MEM_IN_SM_rData,
826 rdata => MEM_IN_SM_rData,
826 full => MEM_IN_SM_Full,
827 full => MEM_IN_SM_Full,
827 empty => MEM_IN_SM_Empty,
828 empty => MEM_IN_SM_Empty,
828 almost_full => OPEN);
829 almost_full => OPEN);
829
830
830
831
831 -----------------------------------------------------------------------------
832 -----------------------------------------------------------------------------
832 MS_control_1 : MS_control
833 MS_control_1 : MS_control
833 PORT MAP (
834 PORT MAP (
834 clk => clk,
835 clk => clk,
835 rstn => rstn,
836 rstn => rstn,
836
837
837 current_status_ms => status_MS_input,
838 current_status_ms => status_MS_input,
838
839
839 fifo_in_lock => MEM_IN_SM_locked,
840 fifo_in_lock => MEM_IN_SM_locked,
840 fifo_in_data => MEM_IN_SM_rdata,
841 fifo_in_data => MEM_IN_SM_rdata,
841 fifo_in_full => MEM_IN_SM_Full,
842 fifo_in_full => MEM_IN_SM_Full,
842 fifo_in_empty => MEM_IN_SM_Empty,
843 fifo_in_empty => MEM_IN_SM_Empty,
843 fifo_in_ren => MEM_IN_SM_ren,
844 fifo_in_ren => MEM_IN_SM_ren,
844 fifo_in_reuse => MEM_IN_SM_ReUse,
845 fifo_in_reuse => MEM_IN_SM_ReUse,
845
846
846 fifo_out_data => SM_in_data,
847 fifo_out_data => SM_in_data,
847 fifo_out_ren => SM_in_ren,
848 fifo_out_ren => SM_in_ren,
848 fifo_out_empty => SM_in_empty,
849 fifo_out_empty => SM_in_empty,
849
850
850 current_status_component => status_component,
851 current_status_component => status_component,
851
852
852 correlation_start => SM_correlation_start,
853 correlation_start => SM_correlation_start,
853 correlation_auto => SM_correlation_auto,
854 correlation_auto => SM_correlation_auto,
854 correlation_done => SM_correlation_done);
855 correlation_done => SM_correlation_done);
855
856
856
857
857 MS_calculation_1 : MS_calculation
858 MS_calculation_1 : MS_calculation
858 PORT MAP (
859 PORT MAP (
859 clk => clk,
860 clk => clk,
860 rstn => rstn,
861 rstn => rstn,
861
862
862 fifo_in_data => SM_in_data,
863 fifo_in_data => SM_in_data,
863 fifo_in_ren => SM_in_ren,
864 fifo_in_ren => SM_in_ren,
864 fifo_in_empty => SM_in_empty,
865 fifo_in_empty => SM_in_empty,
865
866
866 fifo_out_data => MEM_OUT_SM_Data_in_s, -- TODO
867 fifo_out_data => MEM_OUT_SM_Data_in_s, -- TODO
867 fifo_out_wen => MEM_OUT_SM_Write_s, -- TODO
868 fifo_out_wen => MEM_OUT_SM_Write_s, -- TODO
868 fifo_out_full => MEM_OUT_SM_Full_s, -- TODO
869 fifo_out_full => MEM_OUT_SM_Full_s, -- TODO
869
870
870 correlation_start => SM_correlation_start,
871 correlation_start => SM_correlation_start,
871 correlation_auto => SM_correlation_auto,
872 correlation_auto => SM_correlation_auto,
872 correlation_begin => SM_correlation_begin,
873 correlation_begin => SM_correlation_begin,
873 correlation_done => SM_correlation_done);
874 correlation_done => SM_correlation_done);
874
875
875 -----------------------------------------------------------------------------
876 -----------------------------------------------------------------------------
876 PROCESS (clk, rstn)
877 PROCESS (clk, rstn)
877 BEGIN -- PROCESS
878 BEGIN -- PROCESS
878 IF rstn = '0' THEN -- asynchronous reset (active low)
879 IF rstn = '0' THEN -- asynchronous reset (active low)
879 current_matrix_write <= '0';
880 current_matrix_write <= '0';
880 current_matrix_wait_empty <= '1';
881 current_matrix_wait_empty <= '1';
881 status_component_fifo_0 <= (OTHERS => '0');
882 status_component_fifo_0 <= (OTHERS => '0');
882 status_component_fifo_1 <= (OTHERS => '0');
883 status_component_fifo_1 <= (OTHERS => '0');
883 status_component_fifo_0_end <= '0';
884 status_component_fifo_0_end <= '0';
884 status_component_fifo_1_end <= '0';
885 status_component_fifo_1_end <= '0';
885 SM_correlation_done_reg1 <= '0';
886 SM_correlation_done_reg1 <= '0';
886 SM_correlation_done_reg2 <= '0';
887 SM_correlation_done_reg2 <= '0';
887 SM_correlation_done_reg3 <= '0';
888 SM_correlation_done_reg3 <= '0';
888
889
889 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
890 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
890 SM_correlation_done_reg1 <= SM_correlation_done;
891 SM_correlation_done_reg1 <= SM_correlation_done;
891 SM_correlation_done_reg2 <= SM_correlation_done_reg1;
892 SM_correlation_done_reg2 <= SM_correlation_done_reg1;
892 SM_correlation_done_reg3 <= SM_correlation_done_reg2;
893 SM_correlation_done_reg3 <= SM_correlation_done_reg2;
893 status_component_fifo_0_end <= '0';
894 status_component_fifo_0_end <= '0';
894 status_component_fifo_1_end <= '0';
895 status_component_fifo_1_end <= '0';
895 IF SM_correlation_begin = '1' THEN
896 IF SM_correlation_begin = '1' THEN
896 IF current_matrix_write = '0' THEN
897 IF current_matrix_write = '0' THEN
897 status_component_fifo_0 <= status_component(53 DOWNTO 4);
898 status_component_fifo_0 <= status_component(53 DOWNTO 4);
898 ELSE
899 ELSE
899 status_component_fifo_1 <= status_component(53 DOWNTO 4);
900 status_component_fifo_1 <= status_component(53 DOWNTO 4);
900 END IF;
901 END IF;
901 END IF;
902 END IF;
902
903
903 IF SM_correlation_done_reg3 = '1' THEN
904 IF SM_correlation_done_reg3 = '1' THEN
904 IF current_matrix_write = '0' THEN
905 IF current_matrix_write = '0' THEN
905 status_component_fifo_0_end <= '1';
906 status_component_fifo_0_end <= '1';
906 ELSE
907 ELSE
907 status_component_fifo_1_end <= '1';
908 status_component_fifo_1_end <= '1';
908 END IF;
909 END IF;
909 current_matrix_wait_empty <= '1';
910 current_matrix_wait_empty <= '1';
910 current_matrix_write <= NOT current_matrix_write;
911 current_matrix_write <= NOT current_matrix_write;
911 END IF;
912 END IF;
912
913
913 IF current_matrix_wait_empty <= '1' THEN
914 IF current_matrix_wait_empty <= '1' THEN
914 IF current_matrix_write = '0' THEN
915 IF current_matrix_write = '0' THEN
915 current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(0);
916 current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(0);
916 ELSE
917 ELSE
917 current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(1);
918 current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(1);
918 END IF;
919 END IF;
919 END IF;
920 END IF;
920
921
921 END IF;
922 END IF;
922 END PROCESS;
923 END PROCESS;
923
924
924 MEM_OUT_SM_Full_s <= '1' WHEN SM_correlation_done = '1' ELSE
925 MEM_OUT_SM_Full_s <= '1' WHEN SM_correlation_done = '1' ELSE
925 '1' WHEN SM_correlation_done_reg1 = '1' ELSE
926 '1' WHEN SM_correlation_done_reg1 = '1' ELSE
926 '1' WHEN SM_correlation_done_reg2 = '1' ELSE
927 '1' WHEN SM_correlation_done_reg2 = '1' ELSE
927 '1' WHEN SM_correlation_done_reg3 = '1' ELSE
928 '1' WHEN SM_correlation_done_reg3 = '1' ELSE
928 '1' WHEN current_matrix_wait_empty = '1' ELSE
929 '1' WHEN current_matrix_wait_empty = '1' ELSE
929 MEM_OUT_SM_Full(0) WHEN current_matrix_write = '0' ELSE
930 MEM_OUT_SM_Full(0) WHEN current_matrix_write = '0' ELSE
930 MEM_OUT_SM_Full(1);
931 MEM_OUT_SM_Full(1);
931
932
932 MEM_OUT_SM_Write(0) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '0' ELSE '1';
933 MEM_OUT_SM_Write(0) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '0' ELSE '1';
933 MEM_OUT_SM_Write(1) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '1' ELSE '1';
934 MEM_OUT_SM_Write(1) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '1' ELSE '1';
934
935
935 MEM_OUT_SM_Data_in <= MEM_OUT_SM_Data_in_s & MEM_OUT_SM_Data_in_s;
936 MEM_OUT_SM_Data_in <= MEM_OUT_SM_Data_in_s & MEM_OUT_SM_Data_in_s;
936 -----------------------------------------------------------------------------
937 -----------------------------------------------------------------------------
937
938
938 --Mem_Out_SpectralMatrix : lppFIFOxN
939 --Mem_Out_SpectralMatrix : lppFIFOxN
939 -- GENERIC MAP (
940 -- GENERIC MAP (
940 -- tech => 0,
941 -- tech => 0,
941 -- Mem_use => Mem_use,
942 -- Mem_use => Mem_use,
942 -- Data_sz => 32,
943 -- Data_sz => 32,
943 -- Addr_sz => 8,
944 -- Addr_sz => 8,
944 -- FifoCnt => 2)
945 -- FifoCnt => 2)
945 -- PORT MAP (
946 -- PORT MAP (
946 -- clk => clk,
947 -- clk => clk,
947 -- rstn => rstn,
948 -- rstn => rstn,
948
949
949 -- ReUse => (OTHERS => '0'),
950 -- ReUse => (OTHERS => '0'),
950 -- run => (OTHERS => '1'),
951 -- run => (OTHERS => '1'),
951
952
952 -- wen => MEM_OUT_SM_Write,
953 -- wen => MEM_OUT_SM_Write,
953 -- wdata => MEM_OUT_SM_Data_in,
954 -- wdata => MEM_OUT_SM_Data_in,
954
955
955 -- ren => MEM_OUT_SM_Read,
956 -- ren => MEM_OUT_SM_Read,
956 -- rdata => MEM_OUT_SM_Data_out,
957 -- rdata => MEM_OUT_SM_Data_out,
957
958
958 -- full => MEM_OUT_SM_Full,
959 -- full => MEM_OUT_SM_Full,
959 -- empty => MEM_OUT_SM_Empty,
960 -- empty => MEM_OUT_SM_Empty,
960 -- almost_full => OPEN);
961 -- almost_full => OPEN);
961
962
962
963
963 all_Mem_Out_SpectralMatrix: FOR I IN 1 DOWNTO 0 GENERATE
964 all_Mem_Out_SpectralMatrix: FOR I IN 1 DOWNTO 0 GENERATE
964 Mem_Out_SpectralMatrix_I: lpp_fifo
965 Mem_Out_SpectralMatrix_I: lpp_fifo
965 GENERIC MAP (
966 GENERIC MAP (
966 tech => 0,
967 tech => 0,
967 Mem_use => Mem_use,
968 Mem_use => Mem_use,
968 EMPTY_THRESHOLD_LIMIT => 15,
969 EMPTY_THRESHOLD_LIMIT => 15,
969 FULL_THRESHOLD_LIMIT => 1,
970 FULL_THRESHOLD_LIMIT => 1,
970 DataSz => 32,
971 DataSz => 32,
971 AddrSz => 8)
972 AddrSz => 8)
972 PORT MAP (
973 PORT MAP (
973 clk => clk,
974 clk => clk,
974 rstn => rstn,
975 rstn => rstn,
975 reUse => '0',
976 reUse => '0',
976 run => run,
977 run => run,
977
978
978 ren => MEM_OUT_SM_Read(I),
979 ren => MEM_OUT_SM_Read(I),
979 rdata => MEM_OUT_SM_Data_out(32*(I+1)-1 DOWNTO 32*i),
980 rdata => MEM_OUT_SM_Data_out(32*(I+1)-1 DOWNTO 32*i),
980
981
981 wen => MEM_OUT_SM_Write(I),
982 wen => MEM_OUT_SM_Write(I),
982 wdata => MEM_OUT_SM_Data_in(32*(I+1)-1 DOWNTO 32*i),
983 wdata => MEM_OUT_SM_Data_in(32*(I+1)-1 DOWNTO 32*i),
983
984
984 empty => MEM_OUT_SM_Empty(I),
985 empty => MEM_OUT_SM_Empty(I),
985 full => MEM_OUT_SM_Full(I),
986 full => MEM_OUT_SM_Full(I),
986 full_almost => OPEN,
987 full_almost => OPEN,
987 empty_threshold => MEM_OUT_SM_Empty_Threshold(I),
988 empty_threshold => MEM_OUT_SM_Empty_Threshold(I),
988
989
989 full_threshold => OPEN);
990 full_threshold => OPEN);
990
991
991 END GENERATE all_Mem_Out_SpectralMatrix;
992 END GENERATE all_Mem_Out_SpectralMatrix;
992
993
993 -----------------------------------------------------------------------------
994 -----------------------------------------------------------------------------
994 -- MEM_OUT_SM_Read <= "00";
995 -- MEM_OUT_SM_Read <= "00";
995 PROCESS (clk, rstn)
996 PROCESS (clk, rstn)
996 BEGIN
997 BEGIN
997 IF rstn = '0' THEN
998 IF rstn = '0' THEN
998 fifo_0_ready <= '0';
999 fifo_0_ready <= '0';
999 fifo_1_ready <= '0';
1000 fifo_1_ready <= '0';
1000 fifo_ongoing <= '0';
1001 fifo_ongoing <= '0';
1002 fifo_ongoing_reg <= '0';
1001 ELSIF clk'EVENT AND clk = '1' THEN
1003 ELSIF clk'EVENT AND clk = '1' THEN
1004 fifo_ongoing_reg <= fifo_ongoing;
1002 IF fifo_0_ready = '1' AND MEM_OUT_SM_Empty(0) = '1' THEN
1005 IF fifo_0_ready = '1' AND MEM_OUT_SM_Empty(0) = '1' THEN
1003 fifo_ongoing <= '1';
1006 fifo_ongoing <= '1';
1004 fifo_0_ready <= '0';
1007 fifo_0_ready <= '0';
1005 ELSIF status_component_fifo_0_end = '1' THEN
1008 ELSIF status_component_fifo_0_end = '1' THEN
1006 fifo_0_ready <= '1';
1009 fifo_0_ready <= '1';
1007 END IF;
1010 END IF;
1008
1011
1009 IF fifo_1_ready = '1' AND MEM_OUT_SM_Empty(1) = '1' THEN
1012 IF fifo_1_ready = '1' AND MEM_OUT_SM_Empty(1) = '1' THEN
1010 fifo_ongoing <= '0';
1013 fifo_ongoing <= '0';
1011 fifo_1_ready <= '0';
1014 fifo_1_ready <= '0';
1012 ELSIF status_component_fifo_1_end = '1' THEN
1015 ELSIF status_component_fifo_1_end = '1' THEN
1013 fifo_1_ready <= '1';
1016 fifo_1_ready <= '1';
1014 END IF;
1017 END IF;
1015
1018
1016 END IF;
1019 END IF;
1017 END PROCESS;
1020 END PROCESS;
1018
1021
1019 MEM_OUT_SM_Read(0) <= '1' WHEN fifo_ongoing = '1' ELSE
1022 MEM_OUT_SM_Read(0) <= '1' WHEN fifo_ongoing = '1' ELSE
1020 '1' WHEN fifo_0_ready = '0' ELSE
1023 '1' WHEN fifo_0_ready = '0' ELSE
1021 FSM_DMA_fifo_ren;
1024 FSM_DMA_fifo_ren;
1022
1025
1023 MEM_OUT_SM_Read(1) <= '1' WHEN fifo_ongoing = '0' ELSE
1026 MEM_OUT_SM_Read(1) <= '1' WHEN fifo_ongoing = '0' ELSE
1024 '1' WHEN fifo_1_ready = '0' ELSE
1027 '1' WHEN fifo_1_ready = '0' ELSE
1025 FSM_DMA_fifo_ren;
1028 FSM_DMA_fifo_ren;
1026
1029
1027 FSM_DMA_fifo_empty <= MEM_OUT_SM_Empty(0) WHEN fifo_ongoing = '0' AND fifo_0_ready = '1' ELSE
1030 FSM_DMA_fifo_empty <= MEM_OUT_SM_Empty(0) WHEN fifo_ongoing = '0' AND fifo_0_ready = '1' ELSE
1028 MEM_OUT_SM_Empty(1) WHEN fifo_ongoing = '1' AND fifo_1_ready = '1' ELSE
1031 MEM_OUT_SM_Empty(1) WHEN fifo_ongoing = '1' AND fifo_1_ready = '1' ELSE
1029 '1';
1032 '1';
1030
1033
1031 FSM_DMA_fifo_status <= status_component_fifo_0 WHEN fifo_ongoing = '0' ELSE
1034 FSM_DMA_fifo_status <= status_component_fifo_0 WHEN fifo_ongoing = '0' ELSE
1032 status_component_fifo_1;
1035 status_component_fifo_1;
1033
1036
1034 FSM_DMA_fifo_data <= MEM_OUT_SM_Data_out(31 DOWNTO 0) WHEN fifo_ongoing = '0' ELSE
1037 FSM_DMA_fifo_data <= MEM_OUT_SM_Data_out(31 DOWNTO 0) WHEN fifo_ongoing_reg = '0' ELSE
1035 MEM_OUT_SM_Data_out(63 DOWNTO 32);
1038 MEM_OUT_SM_Data_out(63 DOWNTO 32);
1036
1039
1037
1040
1038 FSM_DMA_fifo_empty_threshold <= MEM_OUT_SM_Empty_Threshold(0) WHEN fifo_ongoing = '0' AND fifo_0_ready = '1' ELSE
1041 FSM_DMA_fifo_empty_threshold <= MEM_OUT_SM_Empty_Threshold(0) WHEN fifo_ongoing = '0' AND fifo_0_ready = '1' ELSE
1039 MEM_OUT_SM_Empty_Threshold(1) WHEN fifo_ongoing = '1' AND fifo_1_ready = '1' ELSE
1042 MEM_OUT_SM_Empty_Threshold(1) WHEN fifo_ongoing = '1' AND fifo_1_ready = '1' ELSE
1040 '1';
1043 '1';
1041
1044
1042 -----------------------------------------------------------------------------
1045 -----------------------------------------------------------------------------
1043 -- fifo_matrix_type => FSM_DMA_fifo_status(5 DOWNTO 4), --IN
1046 -- fifo_matrix_type => FSM_DMA_fifo_status(5 DOWNTO 4), --IN
1044 -- fifo_matrix_component => FSM_DMA_fifo_status(3 DOWNTO 0), --IN
1047 -- fifo_matrix_component => FSM_DMA_fifo_status(3 DOWNTO 0), --IN
1045 -- fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6), --IN
1048 -- fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6), --IN
1046 -- fifo_data => FSM_DMA_fifo_data, --IN
1049 -- fifo_data => FSM_DMA_fifo_data, --IN
1047 -- fifo_empty => FSM_DMA_fifo_empty, --IN
1050 -- fifo_empty => FSM_DMA_fifo_empty, --IN
1048 -- fifo_empty_threshold => FSM_DMA_fifo_empty_threshold, --IN
1051 -- fifo_empty_threshold => FSM_DMA_fifo_empty_threshold, --IN
1049 -- fifo_ren => FSM_DMA_fifo_ren, --OUT
1052 -- fifo_ren => FSM_DMA_fifo_ren, --OUT
1050
1053
1051
1054
1052 lpp_lfr_ms_fsmdma_1: lpp_lfr_ms_fsmdma
1055 lpp_lfr_ms_fsmdma_1: lpp_lfr_ms_fsmdma
1053 PORT MAP (
1056 PORT MAP (
1054 clk => clk,
1057 clk => clk,
1055 rstn => rstn,
1058 rstn => rstn,
1056 run => run,
1059 run => run,
1057
1060
1058 fifo_matrix_type => FSM_DMA_fifo_status(5 DOWNTO 4),
1061 fifo_matrix_type => FSM_DMA_fifo_status(5 DOWNTO 4),
1059 fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6),
1062 fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6),
1060 fifo_data => FSM_DMA_fifo_data,
1063 fifo_data => FSM_DMA_fifo_data,
1061 fifo_empty => FSM_DMA_fifo_empty,
1064 fifo_empty => FSM_DMA_fifo_empty,
1062 fifo_empty_threshold => FSM_DMA_fifo_empty_threshold,
1065 fifo_empty_threshold => FSM_DMA_fifo_empty_threshold,
1063 fifo_ren => FSM_DMA_fifo_ren,
1066 fifo_ren => FSM_DMA_fifo_ren,
1064
1067
1065 dma_fifo_valid_burst => dma_fifo_burst_valid,
1068 dma_fifo_valid_burst => dma_fifo_burst_valid,
1066 dma_fifo_data => dma_fifo_data,
1069 dma_fifo_data => dma_fifo_data,
1067 dma_fifo_ren => dma_fifo_ren,
1070 dma_fifo_ren => dma_fifo_ren,
1068 dma_buffer_new => dma_buffer_new,
1071 dma_buffer_new => dma_buffer_new,
1069 dma_buffer_addr => dma_buffer_addr,
1072 dma_buffer_addr => dma_buffer_addr,
1070 dma_buffer_length => dma_buffer_length,
1073 dma_buffer_length => dma_buffer_length,
1071 dma_buffer_full => dma_buffer_full,
1074 dma_buffer_full => dma_buffer_full,
1072 dma_buffer_full_err => dma_buffer_full_err,
1075 dma_buffer_full_err => dma_buffer_full_err,
1073
1076
1074 status_ready_matrix_f0 => status_ready_matrix_f0,
1077 status_ready_matrix_f0 => status_ready_matrix_f0,
1075 status_ready_matrix_f1 => status_ready_matrix_f1,
1078 status_ready_matrix_f1 => status_ready_matrix_f1,
1076 status_ready_matrix_f2 => status_ready_matrix_f2,
1079 status_ready_matrix_f2 => status_ready_matrix_f2,
1077 addr_matrix_f0 => addr_matrix_f0,
1080 addr_matrix_f0 => addr_matrix_f0,
1078 addr_matrix_f1 => addr_matrix_f1,
1081 addr_matrix_f1 => addr_matrix_f1,
1079 addr_matrix_f2 => addr_matrix_f2,
1082 addr_matrix_f2 => addr_matrix_f2,
1080 length_matrix_f0 => length_matrix_f0,
1083 length_matrix_f0 => length_matrix_f0,
1081 length_matrix_f1 => length_matrix_f1,
1084 length_matrix_f1 => length_matrix_f1,
1082 length_matrix_f2 => length_matrix_f2,
1085 length_matrix_f2 => length_matrix_f2,
1083 ready_matrix_f0 => ready_matrix_f0,
1086 ready_matrix_f0 => ready_matrix_f0,
1084 ready_matrix_f1 => ready_matrix_f1,
1087 ready_matrix_f1 => ready_matrix_f1,
1085 ready_matrix_f2 => ready_matrix_f2,
1088 ready_matrix_f2 => ready_matrix_f2,
1086 matrix_time_f0 => matrix_time_f0,
1089 matrix_time_f0 => matrix_time_f0,
1087 matrix_time_f1 => matrix_time_f1,
1090 matrix_time_f1 => matrix_time_f1,
1088 matrix_time_f2 => matrix_time_f2,
1091 matrix_time_f2 => matrix_time_f2,
1089 error_buffer_full => error_buffer_full);
1092 error_buffer_full => error_buffer_full);
1090
1093
1091
1094
1092
1095
1093
1096
1094
1097
1095 --dma_fifo_burst_valid: OUT STD_LOGIC; --TODO
1098 --dma_fifo_burst_valid: OUT STD_LOGIC; --TODO
1096 --dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --TODO
1099 --dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --TODO
1097 --dma_fifo_ren : IN STD_LOGIC; --TODO
1100 --dma_fifo_ren : IN STD_LOGIC; --TODO
1098 --dma_buffer_new : OUT STD_LOGIC; --TODO
1101 --dma_buffer_new : OUT STD_LOGIC; --TODO
1099 --dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --TODO
1102 --dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --TODO
1100 --dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); --TODO
1103 --dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); --TODO
1101 --dma_buffer_full : IN STD_LOGIC; --TODO
1104 --dma_buffer_full : IN STD_LOGIC; --TODO
1102 --dma_buffer_full_err : IN STD_LOGIC; --TODO
1105 --dma_buffer_full_err : IN STD_LOGIC; --TODO
1103
1106
1104 ---- Reg out
1107 ---- Reg out
1105 --ready_matrix_f0 : OUT STD_LOGIC; -- TODO
1108 --ready_matrix_f0 : OUT STD_LOGIC; -- TODO
1106 --ready_matrix_f1 : OUT STD_LOGIC; -- TODO
1109 --ready_matrix_f1 : OUT STD_LOGIC; -- TODO
1107 --ready_matrix_f2 : OUT STD_LOGIC; -- TODO
1110 --ready_matrix_f2 : OUT STD_LOGIC; -- TODO
1108 --error_bad_component_error : OUT STD_LOGIC; -- TODO
1111 --error_bad_component_error : OUT STD_LOGIC; -- TODO
1109 --error_buffer_full : OUT STD_LOGIC; -- TODO
1112 --error_buffer_full : OUT STD_LOGIC; -- TODO
1110
1113
1111 ---- Reg In
1114 ---- Reg In
1112 --status_ready_matrix_f0 : IN STD_LOGIC; -- TODO
1115 --status_ready_matrix_f0 : IN STD_LOGIC; -- TODO
1113 --status_ready_matrix_f1 : IN STD_LOGIC; -- TODO
1116 --status_ready_matrix_f1 : IN STD_LOGIC; -- TODO
1114 --status_ready_matrix_f2 : IN STD_LOGIC; -- TODO
1117 --status_ready_matrix_f2 : IN STD_LOGIC; -- TODO
1115
1118
1116 --addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
1119 --addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
1117 --addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
1120 --addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
1118 --addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
1121 --addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
1119
1122
1120 --matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
1123 --matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
1121 --matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
1124 --matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
1122 --matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) -- TODO
1125 --matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) -- TODO
1123 -----------------------------------------------------------------------------
1126 -----------------------------------------------------------------------------
1124
1127
1125 -----------------------------------------------------------------------------
1128 -----------------------------------------------------------------------------
1126 --lpp_lfr_ms_fsmdma_1 : lpp_lfr_ms_fsmdma
1129 --lpp_lfr_ms_fsmdma_1 : lpp_lfr_ms_fsmdma
1127 -- PORT MAP (
1130 -- PORT MAP (
1128 -- HCLK => clk,
1131 -- HCLK => clk,
1129 -- HRESETn => rstn,
1132 -- HRESETn => rstn,
1130
1133
1131 -- fifo_matrix_type => FSM_DMA_fifo_status(5 DOWNTO 4),
1134 -- fifo_matrix_type => FSM_DMA_fifo_status(5 DOWNTO 4),
1132 -- fifo_matrix_component => FSM_DMA_fifo_status(3 DOWNTO 0),
1135 -- fifo_matrix_component => FSM_DMA_fifo_status(3 DOWNTO 0),
1133 -- fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6),
1136 -- fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6),
1134 -- fifo_data => FSM_DMA_fifo_data,
1137 -- fifo_data => FSM_DMA_fifo_data,
1135 -- fifo_empty => FSM_DMA_fifo_empty,
1138 -- fifo_empty => FSM_DMA_fifo_empty,
1136 -- fifo_ren => FSM_DMA_fifo_ren,
1139 -- fifo_ren => FSM_DMA_fifo_ren,
1137
1140
1138 -- dma_addr => dma_addr,
1141 -- dma_addr => dma_addr,
1139 -- dma_data => dma_data,
1142 -- dma_data => dma_data,
1140 -- dma_valid => dma_valid,
1143 -- dma_valid => dma_valid,
1141 -- dma_valid_burst => dma_valid_burst,
1144 -- dma_valid_burst => dma_valid_burst,
1142 -- dma_ren => dma_ren,
1145 -- dma_ren => dma_ren,
1143 -- dma_done => dma_done,
1146 -- dma_done => dma_done,
1144
1147
1145 -- ready_matrix_f0 => ready_matrix_f0,
1148 -- ready_matrix_f0 => ready_matrix_f0,
1146 -- ready_matrix_f1 => ready_matrix_f1,
1149 -- ready_matrix_f1 => ready_matrix_f1,
1147 -- ready_matrix_f2 => ready_matrix_f2,
1150 -- ready_matrix_f2 => ready_matrix_f2,
1148
1151
1149 -- error_bad_component_error => error_bad_component_error,
1152 -- error_bad_component_error => error_bad_component_error,
1150 -- error_buffer_full => error_buffer_full,
1153 -- error_buffer_full => error_buffer_full,
1151
1154
1152 -- debug_reg => debug_reg,
1155 -- debug_reg => debug_reg,
1153 -- status_ready_matrix_f0 => status_ready_matrix_f0,
1156 -- status_ready_matrix_f0 => status_ready_matrix_f0,
1154 -- status_ready_matrix_f1 => status_ready_matrix_f1,
1157 -- status_ready_matrix_f1 => status_ready_matrix_f1,
1155 -- status_ready_matrix_f2 => status_ready_matrix_f2,
1158 -- status_ready_matrix_f2 => status_ready_matrix_f2,
1156
1159
1157 -- config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
1160 -- config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
1158 -- config_active_interruption_onError => config_active_interruption_onError,
1161 -- config_active_interruption_onError => config_active_interruption_onError,
1159
1162
1160 -- addr_matrix_f0 => addr_matrix_f0,
1163 -- addr_matrix_f0 => addr_matrix_f0,
1161 -- addr_matrix_f1 => addr_matrix_f1,
1164 -- addr_matrix_f1 => addr_matrix_f1,
1162 -- addr_matrix_f2 => addr_matrix_f2,
1165 -- addr_matrix_f2 => addr_matrix_f2,
1163
1166
1164 -- matrix_time_f0 => matrix_time_f0,
1167 -- matrix_time_f0 => matrix_time_f0,
1165 -- matrix_time_f1 => matrix_time_f1,
1168 -- matrix_time_f1 => matrix_time_f1,
1166 -- matrix_time_f2 => matrix_time_f2
1169 -- matrix_time_f2 => matrix_time_f2
1167 -- );
1170 -- );
1168 -----------------------------------------------------------------------------
1171 -----------------------------------------------------------------------------
1169
1172
1170
1173
1171
1174
1172
1175
1173
1176
1174
1177
1175 -----------------------------------------------------------------------------
1178 -----------------------------------------------------------------------------
1176 -- TIME MANAGMENT
1179 -- TIME MANAGMENT
1177 -----------------------------------------------------------------------------
1180 -----------------------------------------------------------------------------
1178 all_time <= sample_f2_time & sample_f1_time & sample_f0_time & sample_f0_time;
1181 all_time <= sample_f2_time & sample_f1_time & sample_f0_time & sample_f0_time;
1179 --all_time <= coarse_time & fine_time;
1182 --all_time <= coarse_time & fine_time;
1180 --
1183 --
1181 f_empty(0) <= '1' WHEN sample_f0_A_empty = "11111" ELSE '0';
1184 f_empty(0) <= '1' WHEN sample_f0_A_empty = "11111" ELSE '0';
1182 f_empty(1) <= '1' WHEN sample_f0_B_empty = "11111" ELSE '0';
1185 f_empty(1) <= '1' WHEN sample_f0_B_empty = "11111" ELSE '0';
1183 f_empty(2) <= '1' WHEN sample_f1_empty = "11111" ELSE '0';
1186 f_empty(2) <= '1' WHEN sample_f1_empty = "11111" ELSE '0';
1184 f_empty(3) <= '1' WHEN sample_f2_empty = "11111" ELSE '0';
1187 f_empty(3) <= '1' WHEN sample_f2_empty = "11111" ELSE '0';
1185
1188
1186 all_time_reg: FOR I IN 0 TO 3 GENERATE
1189 all_time_reg: FOR I IN 0 TO 3 GENERATE
1187
1190
1188 PROCESS (clk, rstn)
1191 PROCESS (clk, rstn)
1189 BEGIN
1192 BEGIN
1190 IF rstn = '0' THEN
1193 IF rstn = '0' THEN
1191 f_empty_reg(I) <= '1';
1194 f_empty_reg(I) <= '1';
1192 ELSIF clk'event AND clk = '1' THEN
1195 ELSIF clk'event AND clk = '1' THEN
1193 f_empty_reg(I) <= f_empty(I);
1196 f_empty_reg(I) <= f_empty(I);
1194 END IF;
1197 END IF;
1195 END PROCESS;
1198 END PROCESS;
1196
1199
1197 time_update_f(I) <= '1' WHEN f_empty(I) = '0' AND f_empty_reg(I) = '1' ELSE '0';
1200 time_update_f(I) <= '1' WHEN f_empty(I) = '0' AND f_empty_reg(I) = '1' ELSE '0';
1198
1201
1199 s_m_t_m_f0_A : spectral_matrix_time_managment
1202 s_m_t_m_f0_A : spectral_matrix_time_managment
1200 PORT MAP (
1203 PORT MAP (
1201 clk => clk,
1204 clk => clk,
1202 rstn => rstn,
1205 rstn => rstn,
1203 time_in => all_time((I+1)*48-1 DOWNTO I*48),
1206 time_in => all_time((I+1)*48-1 DOWNTO I*48),
1204 update_1 => time_update_f(I),
1207 update_1 => time_update_f(I),
1205 time_out => time_reg_f((I+1)*48-1 DOWNTO I*48)
1208 time_out => time_reg_f((I+1)*48-1 DOWNTO I*48)
1206 );
1209 );
1207
1210
1208 END GENERATE all_time_reg;
1211 END GENERATE all_time_reg;
1209
1212
1210 time_reg_f0_A <= time_reg_f((0+1)*48-1 DOWNTO 0*48);
1213 time_reg_f0_A <= time_reg_f((0+1)*48-1 DOWNTO 0*48);
1211 time_reg_f0_B <= time_reg_f((1+1)*48-1 DOWNTO 1*48);
1214 time_reg_f0_B <= time_reg_f((1+1)*48-1 DOWNTO 1*48);
1212 time_reg_f1 <= time_reg_f((2+1)*48-1 DOWNTO 2*48);
1215 time_reg_f1 <= time_reg_f((2+1)*48-1 DOWNTO 2*48);
1213 time_reg_f2 <= time_reg_f((3+1)*48-1 DOWNTO 3*48);
1216 time_reg_f2 <= time_reg_f((3+1)*48-1 DOWNTO 3*48);
1214
1217
1215 -----------------------------------------------------------------------------
1218 -----------------------------------------------------------------------------
1216
1219
1217 END Behavioral;
1220 END Behavioral;
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