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1 lpp_Header.vhd
2 HeaderBuilder.vhd
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1 1 VHDLIB=../..
2 2 SCRIPTSDIR=$(VHDLIB)/scripts/
3 3 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
4 4 TOP=MINI_LFR_top
5 5 BOARD=MINI-LFR
6 6 include $(VHDLIB)/boards/$(BOARD)/Makefile.inc
7 7 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
8 8 UCF=$(VHDLIB)/boards/$(BOARD)/$(TOP).ucf
9 9 QSF=$(VHDLIB)/boards/$(BOARD)/$(TOP).qsf
10 10 EFFORT=high
11 11 XSTOPT=
12 12 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
13 13 VHDLSYNFILES= MINI_LFR_top.vhd
14 14 VHDLSIMFILES= testbench.vhd
15 15 SIMTOP=testbench
16 16 PDC=$(VHDLIB)/boards/$(BOARD)/default.pdc
17 17 ##SDC=$(VHDLIB)/boards/$(BOARD)/default.sdc
18 18 ##SDCFILE=$(VHDLIB)/boards/$(BOARD)/MINI_LFR_synthesis.sdc
19 19 SDC=$(VHDLIB)/boards/$(BOARD)/MINI_LFR_place_and_route.sdc
20 20 BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut
21 21 CLEAN=soft-clean
22 22
23 23 TECHLIBS = proasic3e
24 24
25 25 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
26 26 tmtc openchip hynix ihp gleichmann micron usbhc
27 27
28 28 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
29 29 pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
30 30 ./amba_lcd_16x2_ctrlr \
31 31 ./general_purpose/lpp_AMR \
32 32 ./general_purpose/lpp_balise \
33 33 ./general_purpose/lpp_delay \
34 34 ./lpp_bootloader \
35 35 ./lpp_uart \
36 36 ./lpp_usb \
37 37 ./dsp/lpp_fft_rtax \
38 38 ./lpp_sim/CY7C1061DV33 \
39 39
40 40 FILESKIP =i2cmst.vhd \
41 41 APB_MULTI_DIODE.vhd \
42 42 APB_SIMPLE_DIODE.vhd \
43 43 Top_MatrixSpec.vhd \
44 44 APB_FFT.vhd \
45 45 CoreFFT_simu.vhd \
46 lpp_lfr_apbreg_simu.vhd
46 lpp_lfr_apbreg_simu.vhd \
47 MUXN.vhd
47 48
48 49 include $(GRLIB)/bin/Makefile
49 50 include $(GRLIB)/software/leon3/Makefile
50 51
51 52 ################## project specific targets ##########################
52 53
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1 1
2 2 LIBRARY ieee;
3 3 USE ieee.std_logic_1164.ALL;
4 4 USE IEEE.MATH_REAL.ALL;
5 5 USE ieee.numeric_std.ALL;
6 6
7 7 LIBRARY std;
8 8 use std.textio.all;
9 9
10 10 ENTITY data_write_with_burstCounter IS
11 11 GENERIC (
12 12 OUTPUT_FILE_NAME : STRING := "output_data_2.txt";
13 13 NB_CHAR_PER_DATA : INTEGER := 4;
14 14 BASE_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0)
15 15 );
16 16 PORT (
17 17 clk : IN STD_LOGIC;
18 18 rstn : IN STD_LOGIC;
19 19
20 20 burst_valid : IN STD_LOGIC;
21 21 burst_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
22 22 data_ren : OUT STD_LOGIC;
23 23
24 24 data : IN STD_LOGIC_VECTOR(NB_CHAR_PER_DATA * 4 - 1 DOWNTO 0);
25 25 close_file : IN STD_LOGIC
26 26 );
27 27 END;
28 28
29 29 ARCHITECTURE beh OF data_write_with_burstCounter IS
30 30
31 31 COMPONENT data_write
32 32 GENERIC (
33 33 OUTPUT_FILE_NAME : STRING;
34 34 NB_CHAR_PER_DATA : INTEGER );
35 35 PORT (
36 36 clk : IN STD_LOGIC;
37 37 data_in_val : IN STD_LOGIC;
38 38 data : IN STD_LOGIC_VECTOR(NB_CHAR_PER_DATA * 4 - 1 DOWNTO 0);
39 39 close_file : IN STD_LOGIC);
40 40 END COMPONENT;
41 41
42 42 SIGNAL ren_counter : INTEGER;
43 43 SIGNAL data_ren_s : STD_LOGIC;
44 44 SIGNAL data_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
45 45 SIGNAL data_in_val : STD_LOGIC;
46
46 47
47 48 BEGIN
48 49
49 50 PROCESS (clk, rstn)
50 51 BEGIN -- PROCESS
51 52 IF rstn = '0' THEN -- asynchronous reset (active low)
52 53 ren_counter <= 0;
53 54 data_ren_s <= '1';
54 55 data_s <= (OTHERS => '0');
56 data_in_val <= '0';
55 57 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
56 58 data_s <= data;
57 59 data_ren_s <= '1';
58 60 IF ren_counter = 0 AND burst_valid = '1' AND burst_addr = BASE_ADDR THEN
59 61 ren_counter <= 16;
60 62 END IF;
61 63 IF ren_counter > 0 THEN
62 64 ren_counter <= ren_counter - 1;
63 65 data_ren_s <= '0';
64 END IF;
66 END IF;
67 data_in_val <= NOT data_ren_s;
65 68 END IF;
66 69 END PROCESS;
67 70
68 data_in_val <= NOT data_ren_s;
69 71 data_ren <= data_ren_s;
70 72
71 73 data_write_1: data_write
72 74 GENERIC MAP (
73 75 OUTPUT_FILE_NAME => OUTPUT_FILE_NAME,
74 76 NB_CHAR_PER_DATA => NB_CHAR_PER_DATA)
75 77 PORT MAP (
76 78 clk => clk,
77 79 data_in_val => data_in_val,
78 data => data_s,
80 data => data,
79 81 close_file => close_file);
80 82
81 83 END beh;
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1 1 #vsim -c -do "run_nowindow.do" -goutput_file_name="output_data.txt" -ginput_file_name="input_data.txt"
2 2
3 3 quietly set args [ split $argv {\ } ]
4 4 set argc [ llength $args ]
5 5
6 6 set outputfile_f0 "output\_data\_f0\.txt"
7 7 set inputfile_f0 "input\_data\_f0\.txt"
8 8 set outputfile_f1 "output\_data\_f1\.txt"
9 9 set inputfile_f1 "input\_data\_f1\.txt"
10 10 set outputfile_f2 "output\_data\_f2\.txt"
11 11 set inputfile_f2 "input\_data\_f2\.txt"
12 12
13 13 #puts "there are $argc arguments to this script"
14 14 #puts "The name of this script is $argv0"
15 15
16 16 #foreach arg $::argv {puts $arg}
17 17
18 18 #puts [ lindex $args 4 ]
19 19
20 20 for { set i 0 } { $i < $argc } { incr i 1 } {
21 21 puts "$i : [ lindex $args $i ]"
22 22
23 23 if { [ string match -goutput_file_name_f0=* [ lindex $args $i ] ] } {
24 24 set outputfile_f0 [ lindex [ split [ lindex $args $i ] {=} ] 1 ]
25 25 puts "OUTPUT_FILE_f0 : $outputfile_f0"
26 26 }
27 27 if { [ string match -goutput_file_name_f1=* [ lindex $args $i ] ] } {
28 28 set outputfile_f1 [ lindex [ split [ lindex $args $i ] {=} ] 1 ]
29 29 puts "OUTPUT_FILE_f1 : $outputfile_f1"
30 30 }
31 31 if { [ string match -goutput_file_name_f2=* [ lindex $args $i ] ] } {
32 32 set outputfile_f2 [ lindex [ split [ lindex $args $i ] {=} ] 1 ]
33 33 puts "OUTPUT_FILE_f2 : $outputfile_f2"
34 34 }
35 35
36 36 if { [ string match -ginput_file_name_f0=* [ lindex $args $i ] ] } {
37 37 set inputfile_f0 [ lindex [ split [ lindex $args $i ] {=} ] 1 ]
38 38 puts "INPUT_FILE_F0 : $inputfile_f0"
39 39 }
40 40 if { [ string match -ginput_file_name_f1=* [ lindex $args $i ] ] } {
41 41 set inputfile_f1 [ lindex [ split [ lindex $args $i ] {=} ] 1 ]
42 42 puts "INPUT_FILE_F1 : $inputfile_f1"
43 43 }
44 44 if { [ string match -ginput_file_name_f2=* [ lindex $args $i ] ] } {
45 45 set inputfile_f2 [ lindex [ split [ lindex $args $i ] {=} ] 1 ]
46 46 puts "INPUT_FILE_F2 : $inputfile_f2"
47 47 }
48 48 }
49 49
50 50 vsim work.testbench \
51 51 -goutput_file_name_f0=$outputfile_f0 -ginput_file_name_f0=$inputfile_f0 \
52 52 -goutput_file_name_f1=$outputfile_f1 -ginput_file_name_f1=$inputfile_f1 \
53 53 -goutput_file_name_f2=$outputfile_f2 -ginput_file_name_f2=$inputfile_f2
54 54 when -label end_of_simulation {end_of_sim == '1'} {echo "End of simulation"; exit ;}
55
55 56 run -all
56 57 exit
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1 1
2 2 LIBRARY ieee;
3 3 USE ieee.std_logic_1164.ALL;
4 4 USE IEEE.MATH_REAL.ALL;
5 5 USE ieee.numeric_std.ALL;
6 6
7 7 LIBRARY std;
8 8 USE std.textio.ALL;
9 9
10 10 LIBRARY lpp;
11 11 USE lpp.cic_pkg.ALL;
12 12 USE lpp.chirp_pkg.ALL;
13 13 USE lpp.lpp_fft.ALL;
14 14 USE lpp.lpp_lfr_pkg.ALL;
15 15 USE lpp.iir_filter.ALL;
16 16
17 17 ENTITY testbench IS
18 18 GENERIC (
19 19 input_file_name_f0 : STRING := "input_data_f0.txt";
20 20 input_file_name_f1 : STRING := "input_data_f1.txt";
21 21 input_file_name_f2 : STRING := "input_data_f2.txt";
22 22 output_file_name_f0 : STRING := "output_data_f0.txt";
23 23 output_file_name_f1 : STRING := "output_data_f1.txt";
24 24 output_file_name_f2 : STRING := "output_data_f2.txt");
25 25 END;
26 26
27 27 ARCHITECTURE behav OF testbench IS
28 28
29 29 COMPONENT data_read_with_timer
30 30 GENERIC (
31 31 input_file_name : STRING;
32 32 NB_CHAR_PER_DATA : INTEGER;
33 33 NB_CYCLE_TIMER : INTEGER);
34 34 PORT (
35 35 clk : IN STD_LOGIC;
36 36 rstn : IN STD_LOGIC;
37 37 end_of_file : OUT STD_LOGIC;
38 38 data_out_val : OUT STD_LOGIC;
39 39 data_out : OUT STD_LOGIC_VECTOR(NB_CHAR_PER_DATA * 4 - 1 DOWNTO 0));
40 40 END COMPONENT;
41 41
42 42 COMPONENT data_write_with_burstCounter
43 43 GENERIC (
44 44 OUTPUT_FILE_NAME : STRING;
45 45 NB_CHAR_PER_DATA : INTEGER;
46 46 BASE_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0));
47 47 PORT (
48 48 clk : IN STD_LOGIC;
49 49 rstn : IN STD_LOGIC;
50 50 burst_valid : IN STD_LOGIC;
51 51 burst_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
52 52 data_ren : OUT STD_LOGIC;
53 53 data : IN STD_LOGIC_VECTOR(NB_CHAR_PER_DATA * 4 - 1 DOWNTO 0);
54 54 close_file : IN STD_LOGIC);
55 55 END COMPONENT;
56 56
57 57 SIGNAL clk : STD_LOGIC := '0';
58 58 SIGNAL rstn : STD_LOGIC;
59 59
60 60 SIGNAL start : STD_LOGIC;
61 61
62 62 -- IN
63 63 SIGNAL sample_valid : STD_LOGIC;
64 64 SIGNAL fft_read : STD_LOGIC;
65 65 SIGNAL sample_data : STD_LOGIC_VECTOR(15 DOWNTO 0);
66 66 SIGNAL sample_load : STD_LOGIC;
67 67 -- OUT
68 68 SIGNAL fft_pong : STD_LOGIC;
69 69 SIGNAL fft_data_im : STD_LOGIC_VECTOR(15 DOWNTO 0);
70 70 SIGNAL fft_data_re : STD_LOGIC_VECTOR(15 DOWNTO 0);
71 71 SIGNAL fft_data_valid : STD_LOGIC;
72 72 SIGNAL fft_ready : STD_LOGIC;
73 73 SIGNAL fft_component_number : INTEGER;
74 74
75 75 SIGNAL end_of_sim : STD_LOGIC := '0';
76 76
77 77 -----------------------------------------------------------------------------
78 78 -- DATA GEN
79 79 -----------------------------------------------------------------------------
80 80 CONSTANT NB_CYCLE_f0 : INTEGER := 1017; -- 25MHz / 24576Hz
81 81 CONSTANT NB_CYCLE_f1 : INTEGER := 6103; -- 25MHz / 4096Hz
82 82 CONSTANT NB_CYCLE_f2 : INTEGER := 97656; -- 25MHz / 256Hz
83 83
84 84 SIGNAL data_counter_f0 : INTEGER;
85 85 SIGNAL data_counter_f1 : INTEGER;
86 86 SIGNAL data_counter_f2 : INTEGER;
87 87
88 88 SIGNAL sample_f0_wen : STD_LOGIC;
89 89 SIGNAL sample_f1_wen : STD_LOGIC;
90 90 SIGNAL sample_f2_wen : STD_LOGIC;
91 91
92 92 SIGNAL sample_f0_wen_v : STD_LOGIC_VECTOR(4 DOWNTO 0);
93 93 SIGNAL sample_f1_wen_v : STD_LOGIC_VECTOR(4 DOWNTO 0);
94 94 SIGNAL sample_f2_wen_v : STD_LOGIC_VECTOR(4 DOWNTO 0);
95 95
96 96 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
97 97 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
98 98 SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
99 99
100 100 -----------------------------------------------------------------------------
101 101 -- TIME
102 102 -----------------------------------------------------------------------------
103 103 SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
104 104 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
105 105 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
106 SIGNAL sample_f0_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
107 SIGNAL sample_f1_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
108 SIGNAL sample_f2_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
106 109 SIGNAL time_counter : INTEGER;
107 110
108 111 SIGNAL new_fine_time : STD_LOGIC := '0';
109 112 SIGNAL new_fine_time_reg : STD_LOGIC := '0';
110 113
111 114 -----------------------------------------------------------------------------
112 115 --
113 116 -----------------------------------------------------------------------------
114 117 SIGNAL end_of_file : STD_LOGIC_VECTOR(2 DOWNTO 0);
115 118 SIGNAL data_out_val : STD_LOGIC_VECTOR(2 DOWNTO 0);
116 119
117 120 -----------------------------------------------------------------------------
118 121 -----------------------------------------------------------------------------
119 122 SIGNAL dma_fifo_burst_valid : STD_LOGIC; --TODO
120 123 SIGNAL dma_fifo_data : STD_LOGIC_VECTOR(31 DOWNTO 0); --TODO
121 124 SIGNAL dma_fifo_ren : STD_LOGIC; --TODO
122 125 SIGNAL dma_fifo_ren_f0 : STD_LOGIC; --TODO
123 126 SIGNAL dma_fifo_ren_f1 : STD_LOGIC; --TODO
124 127 SIGNAL dma_fifo_ren_f2 : STD_LOGIC; --TODO
125 128 SIGNAL dma_buffer_new : STD_LOGIC; --TODOx
126 129 SIGNAL dma_buffer_addr : STD_LOGIC_VECTOR(31 DOWNTO 0); --TODO
127 130 SIGNAL dma_buffer_length : STD_LOGIC_VECTOR(25 DOWNTO 0); --TODO
128 131 SIGNAL dma_buffer_full : STD_LOGIC; --TODO
129 132 SIGNAL dma_buffer_full_err : STD_LOGIC; --TODO
130 133 SIGNAL ready_matrix_f0 : STD_LOGIC; -- TODO
131 134 SIGNAL ready_matrix_f1 : STD_LOGIC; -- TODO
132 135 SIGNAL ready_matrix_f2 : STD_LOGIC; -- TODO
133 136 SIGNAL status_ready_matrix_f0 : STD_LOGIC; -- TODO
134 137 SIGNAL status_ready_matrix_f1 : STD_LOGIC; -- TODO
135 138 SIGNAL status_ready_matrix_f2 : STD_LOGIC; -- TODO
136 139 SIGNAL addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
137 140 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
138 141 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
139 142 SIGNAL length_matrix_f0 : STD_LOGIC_VECTOR(25 DOWNTO 0); -- TODO
140 143 SIGNAL length_matrix_f1 : STD_LOGIC_VECTOR(25 DOWNTO 0); -- TODO
141 144 SIGNAL length_matrix_f2 : STD_LOGIC_VECTOR(25 DOWNTO 0); -- TODO
142 145 SIGNAL matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
143 146 SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
144 147 SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
145 148 -----------------------------------------------------------------------------
146 149 SIGNAL dma_ren_counter : INTEGER;
147 150 SIGNAL dma_output_counter : INTEGER;
148 151 -----------------------------------------------------------------------------
149 152 CONSTANT BASE_ADDR_F0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"01000000";
150 153 CONSTANT BASE_ADDR_F1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"10000000";
151 154 CONSTANT BASE_ADDR_F2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"11000000";
152 155 -----------------------------------------------------------------------------
153 156 SIGNAL close_file : STD_LOGIC := '0';
154 157
155 158 BEGIN
156 159
157 160 -----------------------------------------------------------------------------
158 161
159 162 clk <= NOT clk AFTER 20 ns;
160 163 new_fine_time <= NOT new_fine_time AFTER 15258 ns;
161 164
162 165 PROCESS
163 166 BEGIN -- PROCESS
164 167 WAIT UNTIL clk = '1';
165 168 close_file <= '0';
166 169 rstn <= '0';
167 170 start <= '0';
168 171 WAIT UNTIL clk = '1';
169 172 rstn <= '1';
170 173 WAIT UNTIL clk = '1';
171 174 WAIT UNTIL clk = '1';
172 175 WAIT UNTIL clk = '1';
173 176 WAIT UNTIL clk = '1';
174 177 start <= '1';
175 178 WHILE NOT (end_of_file = "111") LOOP
176 179 WAIT UNTIL clk = '1';
177 180 END LOOP;
178 181 REPORT "*** END READ FILE ***";-- SEVERITY failure;
179 182 WAIT FOR 3 ms;
180 183 close_file <= '1';
181 184 WAIT UNTIL clk = '1';
182 185 WAIT UNTIL clk = '1';
183 186 WAIT UNTIL clk = '1';
184 187 end_of_sim <= '1';
185 188 WAIT FOR 100 ns;
186 189 REPORT "*** END SIMULATION ***" SEVERITY failure;
187 190 WAIT;
188 191 END PROCESS;
189 192
190 193 -----------------------------------------------------------------------------
191 194 -- TIME
192 195 -----------------------------------------------------------------------------
193 196 PROCESS (clk, rstn)
194 197 BEGIN -- PROCESS
195 198 IF rstn = '0' THEN -- asynchronous reset (active low)
196 199 start_date <= X"0000000" & "001";
197 200 coarse_time <= (OTHERS => '0');
198 201 fine_time <= (OTHERS => '0');
199 202 time_counter <= 0;
200 203 new_fine_time_reg <= '0';
201 204 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
202 205 new_fine_time_reg <= new_fine_time;
203 206 IF start = '1' THEN
204 207 IF coarse_time(30 downto 0) = X"0000000" & "000" THEN
205 208 coarse_time(30 downto 0) <= start_date;
206 209 ELSE
207 210 IF new_fine_time = NOT new_fine_time_reg THEN
208 211 IF fine_time = X"FFFF" THEN
209 212 coarse_time <= STD_LOGIC_VECTOR(UNSIGNED(coarse_time) + 1);
210 213 fine_time <= (OTHERS => '0');
211 214 ELSE
212 215 fine_time <= STD_LOGIC_VECTOR(UNSIGNED(fine_time) + 1);
213 216 END IF;
214 217 END IF;
215 218 END IF;
216 219 END IF;
217 220 END IF;
218 221 END PROCESS;
219 222
220 223 -----------------------------------------------------------------------------
221 224 -- DATA IN
222 225 -----------------------------------------------------------------------------
223 226 data_read_with_timer_f0 : data_read_with_timer
224 227 GENERIC MAP (input_file_name_f0, 4*5, NB_CYCLE_f0)
225 228 PORT MAP (clk, rstn, end_of_file(0), data_out_val(0), sample_f0_wdata(16*5-1 downto 0));
226 229 sample_f0_wen <= NOT data_out_val(0);
227 230
228 231 data_read_with_timer_f1 : data_read_with_timer
229 232 GENERIC MAP (input_file_name_f1, 4*5, NB_CYCLE_f1)
230 233 PORT MAP (clk, rstn, end_of_file(1), data_out_val(1), sample_f1_wdata(16*5-1 downto 0));
231 234 sample_f1_wen <= NOT data_out_val(1);
232 235
233 236 data_read_with_timer_f2 : data_read_with_timer
234 237 GENERIC MAP (input_file_name_f2, 4*5, NB_CYCLE_f2)
235 238 PORT MAP (clk, rstn, end_of_file(2), data_out_val(2), sample_f2_wdata(16*5-1 downto 0));
236 239 sample_f2_wen <= NOT data_out_val(2);
237 240
238 241 -----------------------------------------------------------------------------
239 242 -- DATA OUT
240 243 -----------------------------------------------------------------------------
241 244 --dma_fifo_burst_valid -- in
242 245 --dma_fifo_data -- in
243 246 --dma_fifo_ren -- OUT
244 247 --dma_fifo_ren <= '0';
245 248
246 249 --PROCESS (clk, rstn)
247 250 --BEGIN -- PROCESS
248 251 -- IF rstn = '0' THEN -- asynchronous reset (active low)
249 252 -- dma_ren_counter <= 0;
250 253 -- dma_fifo_ren <= '1';
251 254 -- ELSIF clk'event AND clk = '1' THEN -- rising clock edge
252 255 -- dma_fifo_ren <= '1';
253 256 -- IF dma_ren_counter = 0 AND dma_fifo_burst_valid = '1' THEN
254 257 -- dma_ren_counter <= 16;
255 258 -- END IF;
256 259 -- IF dma_ren_counter > 0 THEN
257 260 -- dma_ren_counter <= dma_ren_counter - 1;
258 261 -- dma_fifo_ren <= '0';
259 262 -- END IF;
260 263
261 264 -- END IF;
262 265 --END PROCESS;
263 266
264 267 data_write_with_burstCounter_0: data_write_with_burstCounter
265 268 GENERIC MAP (
266 269 OUTPUT_FILE_NAME => output_file_name_f0,
267 270 NB_CHAR_PER_DATA => 32/4,
268 271 BASE_ADDR => BASE_ADDR_F0)
269 272 PORT MAP (
270 273 clk => clk,
271 274 rstn => rstn,
272 275 burst_addr => dma_buffer_addr,
273 276 burst_valid => dma_fifo_burst_valid,
274 277 data_ren => dma_fifo_ren_f0,
275 278 data => dma_fifo_data,
276 279 close_file => close_file);
277 280
278 281 data_write_with_burstCounter_1: data_write_with_burstCounter
279 282 GENERIC MAP (
280 283 OUTPUT_FILE_NAME => output_file_name_f1,
281 284 NB_CHAR_PER_DATA => 32/4,
282 285 BASE_ADDR => BASE_ADDR_F1)
283 286 PORT MAP (
284 287 clk => clk,
285 288 rstn => rstn,
286 289 burst_addr => dma_buffer_addr,
287 290 burst_valid => dma_fifo_burst_valid,
288 291 data_ren => dma_fifo_ren_f1,
289 292 data => dma_fifo_data,
290 293 close_file => close_file);
291 294
292 295 data_write_with_burstCounter_2: data_write_with_burstCounter
293 296 GENERIC MAP (
294 297 OUTPUT_FILE_NAME => output_file_name_f2,
295 298 NB_CHAR_PER_DATA => 32/4,
296 299 BASE_ADDR => BASE_ADDR_F2)
297 300 PORT MAP (
298 301 clk => clk,
299 302 rstn => rstn,
300 303 burst_addr => dma_buffer_addr,
301 304 burst_valid => dma_fifo_burst_valid,
302 305 data_ren => dma_fifo_ren_f2,
303 306 data => dma_fifo_data,
304 307 close_file => close_file);
305 308
306 309 dma_fifo_ren <= dma_fifo_ren_f0 AND dma_fifo_ren_f1 AND dma_fifo_ren_f2;
307 310
308 311
309 312 PROCESS (clk, rstn)
310 313 BEGIN -- PROCESS
311 314 IF rstn = '0' THEN -- asynchronous reset (active low)
312 315 dma_buffer_full <= '0';
313 316 dma_buffer_full_err <= '0';
314 317 dma_output_counter <= 0;
315 318 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
316 319 dma_buffer_full <= '0';
317 320
318 321 IF dma_buffer_new = '1' THEN
319 322 dma_output_counter <= to_integer(UNSIGNED(dma_buffer_length));
320 323 END IF;
321 324
322 325 IF dma_fifo_ren = '0' THEN
323 326 IF dma_output_counter = 1 THEN
324 327 dma_buffer_full <= '1';
325 328 dma_output_counter <= 0;
326 329 ELSE
327 330 dma_output_counter <= dma_output_counter - 1;
328 331 END IF;
329 332 END IF;
330 333
331 334 END IF;
332 335 END PROCESS;
333 336
334 337 --dma_buffer_new -- in
335 338 --dma_buffer_addr -- in
336 339 --dma_buffer_length -- in
337 340 --dma_buffer_full -- out
338 341 --dma_buffer_full_err -- OUT
339 342 -- dma_buffer_full <= '0';
340 343 -- dma_buffer_full_err <= '0';
341 344
342 345 -----------------------------------------------------------------------------
343 346 -- BUFFER CONFIGURATION and INFORMATION
344 347 -----------------------------------------------------------------------------
345 348 PROCESS (clk, rstn)
346 349 BEGIN -- PROCESS
347 350 IF rstn = '0' THEN -- asynchronous reset (active low)
348 351 status_ready_matrix_f0 <= '0';
349 352 status_ready_matrix_f1 <= '0';
350 353 status_ready_matrix_f2 <= '0';
351 354 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
352 355 status_ready_matrix_f0 <= ready_matrix_f0;
353 356 status_ready_matrix_f1 <= ready_matrix_f1;
354 357 status_ready_matrix_f2 <= ready_matrix_f2;
355 358 END IF;
356 359 END PROCESS;
357 360
358 361 addr_matrix_f0 <= BASE_ADDR_F0;
359 362 addr_matrix_f1 <= BASE_ADDR_F1;
360 363 addr_matrix_f2 <= BASE_ADDR_F2;
361 364
362 365 length_matrix_f0 <= "00" & X"000C80";
363 366 length_matrix_f1 <= "00" & X"000C80";
364 367 length_matrix_f2 <= "00" & X"000C80";
365 368
366 369 sample_f0_wen_v <= sample_f0_wen & sample_f0_wen & sample_f0_wen & sample_f0_wen & sample_f0_wen;
367 370 sample_f1_wen_v <= sample_f1_wen & sample_f1_wen & sample_f1_wen & sample_f1_wen & sample_f1_wen;
368 371 sample_f2_wen_v <= sample_f2_wen & sample_f2_wen & sample_f2_wen & sample_f2_wen & sample_f2_wen;
369 372
373 sample_f0_time <= coarse_time & fine_time;
374 sample_f1_time <= coarse_time & fine_time;
375 sample_f2_time <= coarse_time & fine_time;
376
370 377 -----------------------------------------------------------------------------
371 378 -- DUT
372 379 -----------------------------------------------------------------------------
373 380 lpp_lfr_ms_1 : lpp_lfr_ms
374 381 GENERIC MAP (
375 382 Mem_use => use_RAM)
376 383 PORT MAP (
377 384 clk => clk,
378 385 rstn => rstn,
379 386 run => '1',
380 387
381 388 -----------------------------------------------------------------------------
382 389 -- TIME
383 390 -----------------------------------------------------------------------------
384 391 start_date => start_date,
385 392 coarse_time => coarse_time,
386 fine_time => fine_time,
393 -- fine_time => fine_time,
387 394
388 395 -------------------------------------------------------------------------
389 396 -- DATA IN
390 397 -------------------------------------------------------------------------
391 398 sample_f0_wen => sample_f0_wen_v, --
392 399 sample_f0_wdata => sample_f0_wdata,
400 sample_f0_time => sample_f0_time,
393 401 sample_f1_wen => sample_f1_wen_v,
394 402 sample_f1_wdata => sample_f1_wdata,
403 sample_f1_time => sample_f1_time,
395 404 sample_f2_wen => sample_f2_wen_v,
396 405 sample_f2_wdata => sample_f2_wdata,
406 sample_f2_time => sample_f2_time,
397 407
398 408 -------------------------------------------------------------------------
399 409 -- DMA OUT
400 410 -------------------------------------------------------------------------
401 411 dma_fifo_burst_valid => dma_fifo_burst_valid, --out
402 412 dma_fifo_data => dma_fifo_data, --out
403 413 dma_fifo_ren => dma_fifo_ren, --in
404 414 dma_buffer_new => dma_buffer_new, --out
405 415 dma_buffer_addr => dma_buffer_addr, --out
406 416 dma_buffer_length => dma_buffer_length, --out
407 417 dma_buffer_full => dma_buffer_full, --in
408 418 dma_buffer_full_err => dma_buffer_full_err, --in
409 419
410 420 -------------------------------------------------------------------------
411 421 -- BUFFER CONFIGURATION and INFORMATION
412 422 -------------------------------------------------------------------------
413 423 ready_matrix_f0 => ready_matrix_f0, --out
414 424 ready_matrix_f1 => ready_matrix_f1, --out
415 425 ready_matrix_f2 => ready_matrix_f2, --out
416 426
417 427 error_buffer_full => OPEN,
418 428 error_input_fifo_write => OPEN,
419 429
420 430 status_ready_matrix_f0 => status_ready_matrix_f0, --in
421 431 status_ready_matrix_f1 => status_ready_matrix_f1, --in
422 432 status_ready_matrix_f2 => status_ready_matrix_f2, --in
423 433
424 434 addr_matrix_f0 => addr_matrix_f0, --in
425 435 addr_matrix_f1 => addr_matrix_f1, --in
426 436 addr_matrix_f2 => addr_matrix_f2, --in
427 437
428 438 length_matrix_f0 => length_matrix_f0, --in
429 439 length_matrix_f1 => length_matrix_f1, --in
430 440 length_matrix_f2 => length_matrix_f2, --in
431 441
432 442 matrix_time_f0 => matrix_time_f0, --out
433 443 matrix_time_f1 => matrix_time_f1, --out
434 444 matrix_time_f2 => matrix_time_f2, --out
435 445
436 446 debug_vector => OPEN);
437 447
438 448 END;
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1 1 onerror {resume}
2 quietly virtual signal -install /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix { /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/rdata(31 downto 0)} data_0
3 quietly virtual signal -install /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix { /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/rdata(63 downto 32)} data_1
4 quietly virtual signal -install /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix { /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/rdata(95 downto 64)} data_2
5 quietly virtual signal -install /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix { /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/rdata(127 downto 96)} data_3
6 quietly virtual signal -install /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix { /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/rdata(159 downto 128)} data_4
7 quietly virtual signal -install /testbench/data_read_with_timer_f0 { /testbench/data_read_with_timer_f0/data_out(15 downto 0)} f0_0
8 quietly virtual signal -install /testbench/data_read_with_timer_f0 { /testbench/data_read_with_timer_f0/data_out(31 downto 16)} f0_1
9 quietly virtual signal -install /testbench/data_read_with_timer_f0 { /testbench/data_read_with_timer_f0/data_out(47 downto 32)} f0_2
10 quietly virtual signal -install /testbench/data_read_with_timer_f0 { /testbench/data_read_with_timer_f0/data_out(63 downto 48)} f0_4
11 quietly virtual signal -install /testbench/data_read_with_timer_f0 { /testbench/data_read_with_timer_f0/data_out(79 downto 64)} f0_4001
2 12 quietly WaveActivateNextPane {} 0
3 13 add wave -noupdate -expand -group DATA_GEN_F0 /testbench/data_read_with_timer_f0/data_out_val
4 14 add wave -noupdate -expand -group DATA_GEN_F0 /testbench/data_read_with_timer_f0/end_of_file
15 add wave -noupdate -expand -group DATA_GEN_F0 -label f0_0 -radix decimal /testbench/data_read_with_timer_f0/f0_0
16 add wave -noupdate -expand -group DATA_GEN_F0 -label f0_1 -radix decimal /testbench/data_read_with_timer_f0/f0_1
17 add wave -noupdate -expand -group DATA_GEN_F0 -label f0_2 -radix decimal /testbench/data_read_with_timer_f0/f0_2
18 add wave -noupdate -expand -group DATA_GEN_F0 -label f0_3 -radix decimal /testbench/data_read_with_timer_f0/f0_4
19 add wave -noupdate -expand -group DATA_GEN_F0 -label f0_4 -radix decimal /testbench/data_read_with_timer_f0/f0_4001
5 20 add wave -noupdate -expand -group DATA_GEN_F0 /testbench/data_read_with_timer_f0/data_out
6 21 add wave -noupdate -expand -group DATA_GEN_F1 /testbench/data_read_with_timer_f1/data_out_val
7 22 add wave -noupdate -expand -group DATA_GEN_F1 /testbench/data_read_with_timer_f1/end_of_file
8 23 add wave -noupdate -expand -group DATA_GEN_F1 /testbench/data_read_with_timer_f1/data_out
9 24 add wave -noupdate -expand -group DATA_GEN_F2 /testbench/data_read_with_timer_f2/data_out_val
10 25 add wave -noupdate -expand -group DATA_GEN_F2 /testbench/data_read_with_timer_f2/end_of_file
11 26 add wave -noupdate -expand -group DATA_GEN_F2 /testbench/data_read_with_timer_f2/data_out
12 27 add wave -noupdate -expand -group DMA_interface /testbench/lpp_lfr_ms_1/dma_buffer_addr
13 28 add wave -noupdate -expand -group DMA_interface /testbench/lpp_lfr_ms_1/dma_buffer_full
14 29 add wave -noupdate -expand -group DMA_interface /testbench/lpp_lfr_ms_1/dma_buffer_full_err
15 30 add wave -noupdate -expand -group DMA_interface /testbench/lpp_lfr_ms_1/dma_buffer_length
16 31 add wave -noupdate -expand -group DMA_interface /testbench/lpp_lfr_ms_1/dma_buffer_new
17 32 add wave -noupdate -expand -group DMA_interface /testbench/lpp_lfr_ms_1/dma_fifo_burst_valid
18 33 add wave -noupdate -expand -group DMA_interface /testbench/lpp_lfr_ms_1/dma_fifo_data
19 34 add wave -noupdate -expand -group DMA_interface /testbench/lpp_lfr_ms_1/dma_fifo_ren
20 35 add wave -noupdate /testbench/dma_ren_counter
21 36 add wave -noupdate /testbench/dma_output_counter
37 add wave -noupdate -expand -group MEM_IN_MS -radix hexadecimal -childformat {{/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(0) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(1) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(2) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(3) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(4) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(5) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(6) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(7) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(8) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(9) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(10) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(11) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(12) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(13) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(14) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(15) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(16) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(17) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(18) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(19) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(20) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(21) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(22) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(23) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(24) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(25) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(26) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(27) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(28) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(29) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(30) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(31) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(32) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(33) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(34) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(35) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(36) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(37) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(38) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(39) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(40) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(41) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(42) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(43) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(44) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(45) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(46) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(47) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(48) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(49) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(50) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(51) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(52) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(53) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(54) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(55) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(56) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(57) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(58) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(59) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(60) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(61) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(62) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(63) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(64) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(65) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(66) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(67) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(68) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(69) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(70) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(71) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(72) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(73) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(74) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(75) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(76) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(77) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(78) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(79) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(80) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(81) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(82) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(83) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(84) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(85) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(86) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(87) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(88) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(89) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(90) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(91) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(92) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(93) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(94) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(95) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(96) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(97) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(98) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(99) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(100) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(101) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(102) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(103) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(104) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(105) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(106) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(107) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(108) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(109) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(110) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(111) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(112) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(113) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(114) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(115) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(116) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(117) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(118) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(119) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(120) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(121) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(122) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(123) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(124) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(125) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(126) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(127) -radix hexadecimal}} -subitemconfig {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(0) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(1) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(2) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(3) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(4) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(5) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(6) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(7) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(8) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(9) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(10) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(11) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(12) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(13) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(14) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(15) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(16) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(17) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(18) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(19) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(20) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(21) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(22) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(23) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(24) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(25) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(26) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(27) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(28) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(29) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(30) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(31) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(32) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(33) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(34) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(35) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(36) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(37) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(38) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(39) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(40) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(41) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(42) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(43) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(44) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(45) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(46) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(47) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(48) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(49) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(50) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(51) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(52) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(53) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(54) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(55) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(56) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(57) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(58) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(59) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(60) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(61) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(62) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(63) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(64) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(65) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(66) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(67) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(68) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(69) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(70) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(71) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(72) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(73) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(74) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(75) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(76) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(77) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(78) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(79) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(80) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(81) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(82) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(83) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(84) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(85) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(86) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(87) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(88) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(89) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(90) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(91) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(92) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(93) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(94) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(95) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(96) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(97) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(98) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(99) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(100) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(101) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(102) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(103) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(104) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(105) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(106) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(107) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(108) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(109) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(110) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(111) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(112) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(113) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(114) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(115) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(116) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(117) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(118) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(119) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(120) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(121) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(122) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(123) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(124) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(125) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(126) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(127) {-height 15 -radix hexadecimal}} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd
38 add wave -noupdate -expand -group MEM_IN_MS -radix hexadecimal -childformat {{/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(0) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(1) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(2) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(3) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(4) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(5) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(6) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(7) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(8) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(9) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(10) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(11) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(12) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(13) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(14) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(15) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(16) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(17) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(18) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(19) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(20) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(21) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(22) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(23) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(24) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(25) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(26) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(27) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(28) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(29) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(30) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(31) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(32) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(33) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(34) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(35) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(36) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(37) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(38) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(39) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(40) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(41) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(42) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(43) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(44) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(45) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(46) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(47) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(48) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(49) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(50) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(51) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(52) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(53) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(54) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(55) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(56) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(57) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(58) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(59) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(60) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(61) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(62) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(63) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(64) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(65) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(66) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(67) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(68) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(69) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(70) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(71) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(72) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(73) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(74) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(75) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(76) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(77) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(78) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(79) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(80) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(81) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(82) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(83) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(84) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(85) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(86) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(87) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(88) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(89) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(90) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(91) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(92) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(93) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(94) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(95) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(96) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(97) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(98) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(99) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(100) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(101) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(102) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(103) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(104) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(105) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(106) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(107) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(108) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(109) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(110) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(111) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(112) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(113) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(114) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(115) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(116) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(117) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(118) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(119) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(120) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(121) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(122) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(123) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(124) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(125) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(126) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(127) -radix hexadecimal}} -subitemconfig {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(0) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(1) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(2) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(3) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(4) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(5) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(6) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(7) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(8) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(9) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(10) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(11) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(12) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(13) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(14) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(15) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(16) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(17) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(18) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(19) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(20) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(21) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(22) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(23) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(24) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(25) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(26) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(27) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(28) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(29) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(30) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(31) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(32) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(33) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(34) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(35) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(36) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(37) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(38) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(39) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(40) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(41) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(42) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(43) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(44) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(45) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(46) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(47) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(48) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(49) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(50) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(51) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(52) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(53) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(54) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(55) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(56) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(57) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(58) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(59) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(60) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(61) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(62) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(63) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(64) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(65) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(66) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(67) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(68) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(69) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(70) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(71) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(72) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(73) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(74) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(75) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(76) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(77) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(78) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(79) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(80) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(81) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(82) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(83) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(84) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(85) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(86) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(87) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(88) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(89) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(90) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(91) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(92) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(93) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(94) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(95) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(96) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(97) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(98) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(99) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(100) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(101) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(102) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(103) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(104) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(105) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(106) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(107) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(108) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(109) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(110) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(111) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(112) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(113) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(114) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(115) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(116) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(117) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(118) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(119) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(120) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(121) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(122) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(123) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(124) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(125) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(126) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(127) {-height 15 -radix hexadecimal}} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd
39 add wave -noupdate -expand -group MEM_IN_MS -radix hexadecimal -childformat {{/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(0) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(1) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(2) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(3) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(4) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(5) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(6) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(7) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(8) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(9) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(10) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(11) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(12) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(13) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(14) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(15) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(16) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(17) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(18) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(19) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(20) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(21) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(22) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(23) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(24) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(25) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(26) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(27) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(28) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(29) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(30) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(31) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(32) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(33) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(34) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(35) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(36) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(37) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(38) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(39) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(40) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(41) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(42) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(43) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(44) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(45) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(46) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(47) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(48) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(49) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(50) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(51) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(52) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(53) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(54) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(55) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(56) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(57) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(58) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(59) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(60) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(61) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(62) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(63) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(64) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(65) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(66) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(67) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(68) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(69) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(70) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(71) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(72) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(73) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(74) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(75) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(76) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(77) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(78) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(79) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(80) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(81) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(82) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(83) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(84) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(85) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(86) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(87) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(88) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(89) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(90) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(91) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(92) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(93) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(94) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(95) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(96) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(97) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(98) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(99) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(100) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(101) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(102) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(103) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(104) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(105) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(106) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(107) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(108) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(109) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(110) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(111) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(112) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(113) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(114) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(115) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(116) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(117) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(118) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(119) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(120) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(121) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(122) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(123) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(124) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(125) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(126) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(127) -radix hexadecimal}} -subitemconfig {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(0) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(1) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(2) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(3) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(4) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(5) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(6) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(7) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(8) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(9) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(10) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(11) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(12) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(13) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(14) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(15) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(16) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(17) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(18) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(19) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(20) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(21) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(22) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(23) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(24) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(25) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(26) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(27) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(28) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(29) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(30) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(31) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(32) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(33) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(34) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(35) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(36) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(37) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(38) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(39) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(40) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(41) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(42) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(43) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(44) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(45) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(46) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(47) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(48) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(49) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(50) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(51) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(52) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(53) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(54) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(55) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(56) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(57) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(58) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(59) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(60) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(61) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(62) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(63) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(64) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(65) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(66) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(67) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(68) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(69) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(70) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(71) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(72) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(73) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(74) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(75) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(76) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(77) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(78) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(79) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(80) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(81) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(82) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(83) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(84) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(85) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(86) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(87) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(88) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(89) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(90) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(91) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(92) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(93) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(94) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(95) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(96) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(97) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(98) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(99) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(100) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(101) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(102) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(103) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(104) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(105) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(106) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(107) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(108) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(109) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(110) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(111) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(112) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(113) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(114) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(115) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(116) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(117) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(118) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(119) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(120) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(121) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(122) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(123) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(124) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(125) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(126) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(127) {-height 15 -radix hexadecimal}} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd
40 add wave -noupdate -expand -group MEM_IN_MS -radix hexadecimal -childformat {{/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(0) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(1) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(2) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(3) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(4) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(5) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(6) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(7) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(8) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(9) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(10) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(11) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(12) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(13) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(14) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(15) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(16) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(17) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(18) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(19) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(20) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(21) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(22) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(23) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(24) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(25) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(26) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(27) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(28) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(29) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(30) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(31) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(32) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(33) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(34) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(35) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(36) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(37) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(38) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(39) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(40) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(41) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(42) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(43) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(44) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(45) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(46) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(47) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(48) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(49) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(50) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(51) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(52) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(53) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(54) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(55) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(56) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(57) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(58) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(59) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(60) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(61) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(62) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(63) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(64) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(65) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(66) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(67) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(68) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(69) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(70) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(71) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(72) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(73) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(74) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(75) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(76) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(77) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(78) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(79) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(80) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(81) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(82) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(83) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(84) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(85) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(86) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(87) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(88) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(89) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(90) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(91) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(92) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(93) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(94) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(95) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(96) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(97) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(98) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(99) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(100) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(101) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(102) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(103) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(104) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(105) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(106) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(107) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(108) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(109) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(110) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(111) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(112) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(113) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(114) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(115) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(116) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(117) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(118) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(119) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(120) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(121) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(122) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(123) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(124) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(125) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(126) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(127) -radix hexadecimal}} -subitemconfig {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(0) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(1) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(2) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(3) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(4) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(5) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(6) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(7) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(8) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(9) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(10) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(11) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(12) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(13) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(14) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(15) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(16) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(17) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(18) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(19) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(20) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(21) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(22) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(23) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(24) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(25) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(26) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(27) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(28) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(29) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(30) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(31) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(32) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(33) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(34) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(35) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(36) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(37) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(38) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(39) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(40) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(41) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(42) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(43) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(44) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(45) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(46) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(47) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(48) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(49) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(50) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(51) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(52) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(53) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(54) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(55) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(56) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(57) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(58) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(59) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(60) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(61) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(62) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(63) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(64) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(65) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(66) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(67) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(68) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(69) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(70) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(71) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(72) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(73) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(74) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(75) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(76) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(77) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(78) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(79) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(80) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(81) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(82) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(83) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(84) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(85) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(86) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(87) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(88) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(89) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(90) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(91) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(92) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(93) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(94) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(95) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(96) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(97) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(98) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(99) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(100) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(101) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(102) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(103) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(104) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(105) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(106) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(107) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(108) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(109) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(110) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(111) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(112) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(113) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(114) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(115) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(116) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(117) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(118) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(119) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(120) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(121) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(122) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(123) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(124) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(125) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(126) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(127) {-height 15 -radix hexadecimal}} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd
41 add wave -noupdate -expand -group MEM_IN_MS -radix hexadecimal -childformat {{/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(0) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(1) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(2) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(3) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(4) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(5) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(6) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(7) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(8) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(9) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(10) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(11) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(12) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(13) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(14) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(15) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(16) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(17) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(18) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(19) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(20) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(21) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(22) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(23) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(24) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(25) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(26) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(27) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(28) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(29) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(30) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(31) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(32) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(33) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(34) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(35) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(36) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(37) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(38) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(39) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(40) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(41) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(42) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(43) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(44) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(45) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(46) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(47) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(48) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(49) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(50) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(51) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(52) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(53) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(54) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(55) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(56) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(57) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(58) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(59) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(60) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(61) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(62) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(63) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(64) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(65) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(66) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(67) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(68) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(69) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(70) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(71) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(72) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(73) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(74) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(75) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(76) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(77) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(78) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(79) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(80) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(81) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(82) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(83) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(84) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(85) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(86) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(87) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(88) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(89) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(90) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(91) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(92) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(93) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(94) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(95) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(96) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(97) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(98) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(99) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(100) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(101) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(102) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(103) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(104) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(105) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(106) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(107) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(108) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(109) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(110) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(111) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(112) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(113) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(114) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(115) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(116) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(117) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(118) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(119) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(120) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(121) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(122) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(123) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(124) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(125) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(126) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(127) -radix hexadecimal}} -subitemconfig {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(0) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(1) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(2) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(3) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(4) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(5) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(6) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(7) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(8) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(9) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(10) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(11) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(12) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(13) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(14) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(15) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(16) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(17) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(18) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(19) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(20) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(21) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(22) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(23) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(24) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(25) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(26) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(27) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(28) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(29) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(30) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(31) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(32) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(33) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(34) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(35) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(36) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(37) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(38) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(39) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(40) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(41) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(42) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(43) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(44) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(45) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(46) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(47) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(48) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(49) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(50) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(51) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(52) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(53) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(54) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(55) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(56) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(57) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(58) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(59) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(60) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(61) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(62) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(63) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(64) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(65) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(66) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(67) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(68) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(69) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(70) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(71) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(72) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(73) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(74) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(75) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(76) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(77) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(78) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(79) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(80) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(81) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(82) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(83) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(84) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(85) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(86) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(87) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(88) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(89) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(90) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(91) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(92) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(93) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(94) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(95) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(96) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(97) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(98) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(99) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(100) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(101) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(102) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(103) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(104) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(105) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(106) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(107) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(108) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(109) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(110) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(111) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(112) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(113) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(114) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(115) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(116) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(117) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(118) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(119) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(120) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(121) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(122) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(123) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(124) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(125) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(126) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(127) {-height 15 -radix hexadecimal}} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd
42 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/data_0
43 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/ren(0)
44 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/wen(0)
45 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/full(0)
46 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/empty(0)
47 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/ReUse(0)
48 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group fif0_1 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/data_1
49 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group fif0_1 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/ren(1)
50 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group fif0_1 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/wen(1)
51 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group fif0_1 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/full(1)
52 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group fif0_1 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/empty(1)
53 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group fif0_1 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/ReUse(1)
54 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_2 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/data_2
55 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_2 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/ren(2)
56 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_2 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/wen(2)
57 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_2 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/full(2)
58 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_2 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/empty(2)
59 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_2 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/ReUse(2)
60 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_3 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/data_3
61 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_3 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/ren(3)
62 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_3 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/wen(3)
63 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_3 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/full(3)
64 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_3 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/empty(3)
65 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_3 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/ReUse(3)
66 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_4 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/data_4
67 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_4 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/ren(4)
68 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_4 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/wen(4)
69 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_4 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/full(4)
70 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_4 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/empty(4)
71 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_4 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/ReUse(4)
72 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(0)/Mem_Out_SpectralMatrix_I/full_threshold
73 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(0)/Mem_Out_SpectralMatrix_I/full
74 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(0)/Mem_Out_SpectralMatrix_I/empty
75 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(0)/Mem_Out_SpectralMatrix_I/full_almost
76 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(0)/Mem_Out_SpectralMatrix_I/empty_threshold
77 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(0)/Mem_Out_SpectralMatrix_I/wen
78 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(0)/Mem_Out_SpectralMatrix_I/wdata
79 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(0)/Mem_Out_SpectralMatrix_I/ren
80 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(0)/Mem_Out_SpectralMatrix_I/rdata
81 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(0)/Mem_Out_SpectralMatrix_I/run
82 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(0)/Mem_Out_SpectralMatrix_I/reUse
83 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_1 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/full_threshold
84 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_1 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/full
85 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_1 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/empty
86 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_1 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/full_almost
87 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_1 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/empty_threshold
88 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_1 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/wen
89 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_1 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/wdata
90 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_1 -radix decimal -childformat {{/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(31) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(30) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(29) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(28) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(27) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(26) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(25) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(24) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(23) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(22) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(21) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(20) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(19) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(18) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(17) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(16) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(15) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(14) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(13) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(12) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(11) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(10) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(9) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(8) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(7) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(6) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(5) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(4) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(3) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(2) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(1) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(0) -radix hexadecimal}} -subitemconfig {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(31) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(30) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(29) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(28) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(27) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(26) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(25) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(24) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(23) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(22) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(21) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(20) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(19) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(18) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(17) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(16) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(15) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(14) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(13) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(12) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(11) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(10) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(9) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(8) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(7) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(6) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(5) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(4) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(3) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(2) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(1) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(0) {-height 15 -radix hexadecimal}} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata
91 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_1 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/ren
92 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_1 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/run
93 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_1 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/reUse
94 add wave -noupdate -radix hexadecimal /testbench/lpp_lfr_ms_1/dma_fifo_data
95 add wave -noupdate -expand -group ALU_MS -radix decimal /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/RES
96 add wave -noupdate -expand -group ALU_MS -radix decimal -childformat {{/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(15) -radix decimal} {/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(14) -radix decimal} {/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(13) -radix decimal} {/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(12) -radix decimal} {/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(11) -radix decimal} {/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(10) -radix decimal} {/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(9) -radix decimal} {/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(8) -radix decimal} {/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(7) -radix decimal} {/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(6) -radix decimal} {/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(5) -radix decimal} {/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(4) -radix decimal} {/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(3) -radix decimal} {/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(2) -radix decimal} {/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(1) -radix decimal} {/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(0) -radix decimal}} -subitemconfig {/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(15) {-height 15 -radix decimal} /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(14) {-height 15 -radix decimal} /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(13) {-height 15 -radix decimal} /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(12) {-height 15 -radix decimal} /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(11) {-height 15 -radix decimal} /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(10) {-height 15 -radix decimal} /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(9) {-height 15 -radix decimal} /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(8) {-height 15 -radix decimal} /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(7) {-height 15 -radix decimal} /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(6) {-height 15 -radix decimal} /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(5) {-height 15 -radix decimal} /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(4) {-height 15 -radix decimal} /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(3) {-height 15 -radix decimal} /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(2) {-height 15 -radix decimal} /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(1) {-height 15 -radix decimal} /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(0) {-height 15 -radix decimal}} /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2
97 add wave -noupdate -expand -group ALU_MS -radix decimal /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP1
98 add wave -noupdate -expand -group ALU_MS -radix hexadecimal /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/comp
99 add wave -noupdate -expand -group ALU_MS -radix hexadecimal /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/ctrl
100 add wave -noupdate /testbench/lpp_lfr_ms_1/MS_control_1/state
101 add wave -noupdate /testbench/lpp_lfr_ms_1/MS_calculation_1/state
102 add wave -noupdate -radix hexadecimal /testbench/lpp_lfr_ms_1/MS_calculation_1/fifo_in_data
103 add wave -noupdate /testbench/lpp_lfr_ms_1/MS_calculation_1/fifo_in_ren
104 add wave -noupdate /testbench/lpp_lfr_ms_1/MEM_OUT_SM_Full
105 add wave -noupdate /testbench/lpp_lfr_ms_1/MEM_OUT_SM_Full_s
106 add wave -noupdate /testbench/lpp_lfr_ms_1/SM_correlation_done
107 add wave -noupdate /testbench/lpp_lfr_ms_1/SM_correlation_done_reg1
108 add wave -noupdate /testbench/lpp_lfr_ms_1/SM_correlation_done_reg2
109 add wave -noupdate /testbench/lpp_lfr_ms_1/SM_correlation_done_reg3
110 add wave -noupdate /testbench/lpp_lfr_ms_1/current_matrix_wait_empty
111 add wave -noupdate /testbench/lpp_lfr_ms_1/current_matrix_write
112 add wave -noupdate /testbench/lpp_lfr_ms_1/MEM_OUT_SM_Empty
113 add wave -noupdate /testbench/lpp_lfr_ms_1/dma_fifo_ren
114 add wave -noupdate /testbench/lpp_lfr_ms_1/addr_matrix_f2
115 add wave -noupdate /testbench/lpp_lfr_ms_1/addr_matrix_f1
116 add wave -noupdate /testbench/lpp_lfr_ms_1/length_matrix_f2
117 add wave -noupdate /testbench/lpp_lfr_ms_1/dma_buffer_full
118 add wave -noupdate /testbench/lpp_lfr_ms_1/dma_buffer_full_err
119 add wave -noupdate /testbench/lpp_lfr_ms_1/addr_matrix_f0
120 add wave -noupdate /testbench/lpp_lfr_ms_1/status_ready_matrix_f2
121 add wave -noupdate /testbench/lpp_lfr_ms_1/status_ready_matrix_f1
122 add wave -noupdate /testbench/lpp_lfr_ms_1/status_ready_matrix_f0
123 add wave -noupdate /testbench/lpp_lfr_ms_1/current_matrix_write
124 add wave -noupdate /testbench/lpp_lfr_ms_1/matrix_time_f2
125 add wave -noupdate /testbench/lpp_lfr_ms_1/matrix_time_f1
126 add wave -noupdate /testbench/lpp_lfr_ms_1/matrix_time_f0
127 add wave -noupdate /testbench/lpp_lfr_ms_1/error_input_fifo_write
128 add wave -noupdate /testbench/lpp_lfr_ms_1/error_buffer_full
129 add wave -noupdate /testbench/lpp_lfr_ms_1/ready_matrix_f2
130 add wave -noupdate /testbench/lpp_lfr_ms_1/ready_matrix_f1
131 add wave -noupdate /testbench/lpp_lfr_ms_1/ready_matrix_f0
132 add wave -noupdate /testbench/lpp_lfr_ms_1/dma_buffer_length
133 add wave -noupdate /testbench/lpp_lfr_ms_1/dma_buffer_addr
134 add wave -noupdate /testbench/lpp_lfr_ms_1/dma_buffer_new
135 add wave -noupdate /testbench/lpp_lfr_ms_1/dma_fifo_data
136 add wave -noupdate /testbench/lpp_lfr_ms_1/dma_fifo_burst_valid
137 add wave -noupdate /testbench/lpp_lfr_ms_1/debug_vector
138 add wave -noupdate /testbench/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/state
139 add wave -noupdate /testbench/lpp_lfr_ms_1/fifo_0_ready
140 add wave -noupdate /testbench/lpp_lfr_ms_1/fifo_1_ready
141 add wave -noupdate /testbench/lpp_lfr_ms_1/fifo_ongoing
142 add wave -noupdate /testbench/lpp_lfr_ms_1/status_component_fifo_0
143 add wave -noupdate /testbench/lpp_lfr_ms_1/status_component_fifo_1
144 add wave -noupdate /testbench/lpp_lfr_ms_1/status_component_fifo_0_end
145 add wave -noupdate /testbench/lpp_lfr_ms_1/status_component_fifo_1_end
146 add wave -noupdate /testbench/lpp_lfr_ms_1/MS_calculation_1/state
147 add wave -noupdate /testbench/lpp_lfr_ms_1/MS_calculation_1/fifo_in_empty
148 add wave -noupdate /testbench/lpp_lfr_ms_1/MS_calculation_1/fifo_in_empty_reg
149 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/start_date
150 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/coarse_time
151 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/sample_f0_wen
152 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/sample_f0_wdata
153 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/sample_f1_wen
154 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/sample_f1_wdata
155 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/sample_f2_wen
156 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/sample_f2_wdata
157 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/length_matrix_f1
158 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/length_matrix_f0
159 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/dma_fifo_ren
160 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/addr_matrix_f2
161 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/addr_matrix_f1
162 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/length_matrix_f2
163 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/dma_buffer_full
164 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/dma_buffer_full_err
165 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/addr_matrix_f0
166 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/status_ready_matrix_f2
167 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/status_ready_matrix_f1
168 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/status_ready_matrix_f0
169 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/matrix_time_f2
170 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/matrix_time_f1
171 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/matrix_time_f0
172 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/error_input_fifo_write
173 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/error_buffer_full
174 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/ready_matrix_f2
175 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/ready_matrix_f1
176 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/ready_matrix_f0
177 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/dma_buffer_length
178 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/dma_buffer_addr
179 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/dma_buffer_new
180 add wave -noupdate -expand -group TOP_IN_OUT -radix decimal /testbench/lpp_lfr_ms_1/dma_fifo_data
181 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/dma_fifo_burst_valid
22 182 TreeUpdate [SetDefaultTree]
23 WaveRestoreCursors {{Cursor 1} {10933060000 ps} 0}
24 quietly wave cursor active 1
25 configure wave -namecolwidth 339
26 configure wave -valuecolwidth 100
183 WaveRestoreCursors {WDATA_1 {10541340000 ps} 1} {WDATA_2 {10541500000 ps} 1} {WDATA_8 {10542460000 ps} 1} {WDATA_16 {10543740000 ps} 1} {{Cursor 9} {10572740000 ps} 0} {{Cursor 10} {6346220000 ps} 0}
184 quietly wave cursor active 6
185 configure wave -namecolwidth 573
186 configure wave -valuecolwidth 108
27 187 configure wave -justifyvalue left
28 188 configure wave -signalnamewidth 0
29 189 configure wave -snapdistance 10
30 190 configure wave -datasetprefix 0
31 191 configure wave -rowmargin 4
32 192 configure wave -childrowmargin 2
33 193 configure wave -gridoffset 0
34 194 configure wave -gridperiod 1
35 195 configure wave -griddelta 40
36 196 configure wave -timeline 0
37 197 configure wave -timelineunits ns
38 198 update
39 WaveRestoreZoom {0 ps} {42718685333 ps}
199 WaveRestoreZoom {0 ps} {14085099 ns}
Show file before | Show file after | Hide comments
@@ -1,253 +1,262
1 1 LIBRARY IEEE;
2 2 USE IEEE.std_logic_1164.ALL;
3 3
4 4 LIBRARY lpp;
5 5 USE lpp.general_purpose.ALL;
6 6
7 7 ENTITY MS_calculation IS
8 8 PORT (
9 9 clk : IN STD_LOGIC;
10 10 rstn : IN STD_LOGIC;
11 11 -- IN
12 12 fifo_in_data : IN STD_LOGIC_VECTOR(32*2-1 DOWNTO 0);
13 13 fifo_in_ren : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
14 14 fifo_in_empty : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
15 15 -- OUT
16 16 fifo_out_data : OUT STD_LOGIC_VECTOR(32-1 DOWNTO 0);
17 17 fifo_out_wen : OUT STD_LOGIC;
18 18 fifo_out_full : IN STD_LOGIC;
19 19 --
20 20 correlation_start : IN STD_LOGIC;
21 21 correlation_auto : IN STD_LOGIC; -- 1 => auto correlation / 0 => inter correlation
22 22
23 23 correlation_begin : OUT STD_LOGIC;
24 24 correlation_done : OUT STD_LOGIC
25 25 );
26 26 END MS_calculation;
27 27
28 28 ARCHITECTURE beh OF MS_calculation IS
29 29
30 30 TYPE fsm_calculation_MS IS (IDLE, WF, S1, S2, S3, S4, WFa, S1a, S2a);
31 31 SIGNAL state : fsm_calculation_MS;
32 32
33 33 SIGNAL OP1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
34 34 SIGNAL OP2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
35 35 SIGNAL RES : STD_LOGIC_VECTOR(31 DOWNTO 0);
36 36
37 37 SIGNAL ALU_CTRL : STD_LOGIC_VECTOR(4 DOWNTO 0);
38 38
39 39
40 40 CONSTANT ALU_CTRL_NOP : STD_LOGIC_VECTOR(4 DOWNTO 0) := "00000";
41 41 CONSTANT ALU_CTRL_MULT : STD_LOGIC_VECTOR(4 DOWNTO 0) := "00010";
42 42 CONSTANT ALU_CTRL_MAC : STD_LOGIC_VECTOR(4 DOWNTO 0) := "00001";
43 43 CONSTANT ALU_CTRL_MACn : STD_LOGIC_VECTOR(4 DOWNTO 0) := "10001";
44 44
45 45 SIGNAL select_ctrl : STD_LOGIC_VECTOR(1 DOWNTO 0);
46 46 CONSTANT select_ctrl_NOP : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
47 47 CONSTANT select_ctrl_MULT : STD_LOGIC_VECTOR(1 DOWNTO 0) := "01";
48 48 CONSTANT select_ctrl_MAC : STD_LOGIC_VECTOR(1 DOWNTO 0) := "10";
49 49 CONSTANT select_ctrl_MACn : STD_LOGIC_VECTOR(1 DOWNTO 0) := "11";
50 50
51 51 SIGNAL select_op1 : STD_LOGIC;
52 52 SIGNAL select_op2 : STD_LOGIC_VECTOR(1 DOWNTO 0) ;
53 53
54 54 CONSTANT select_R0 : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
55 55 CONSTANT select_I0 : STD_LOGIC_VECTOR(1 DOWNTO 0) := "01";
56 56 CONSTANT select_R1 : STD_LOGIC_VECTOR(1 DOWNTO 0) := "10";
57 57 CONSTANT select_I1 : STD_LOGIC_VECTOR(1 DOWNTO 0) := "11";
58 58
59 59 SIGNAL res_wen : STD_LOGIC;
60 60 SIGNAL res_wen_reg1 : STD_LOGIC;
61 61 SIGNAL res_wen_reg2 : STD_LOGIC;
62 62 --SIGNAL res_wen_reg3 : STD_LOGIC;
63 63
64 64 SIGNAL fifo_in_ren_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
65
66
67 SIGNAL fifo_in_empty_reg : STD_LOGIC_VECTOR(1 DOWNTO 0);
68
65 69
66 70 BEGIN
67 71
68 72
69 PROCESS (clk, rstn)
70 BEGIN -- PROCESS
71 IF rstn = '0' THEN -- asynchronous reset (active low)
72 fifo_in_ren <= "11";
73 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
74 fifo_in_ren <= fifo_in_ren_s;
75 END IF;
76 END PROCESS;
73 --PROCESS (clk, rstn)
74 --BEGIN -- PROCESS
75 -- IF rstn = '0' THEN -- asynchronous reset (active low)
76 -- fifo_in_ren <= "11";
77 -- ELSIF clk'event AND clk = '1' THEN -- rising clock edge
78 -- fifo_in_ren <= fifo_in_ren_s;
79 -- END IF;
80 --END PROCESS;
77 81
82 fifo_in_ren <= fifo_in_ren_s;
78 83
79 84 PROCESS (clk, rstn)
80 85 BEGIN
81 86 IF rstn = '0' THEN
82 87
83 88 correlation_begin <= '0';
84 89 correlation_done <= '0';
85 90 state <= IDLE;
86 91 fifo_in_ren_s <= "11";
87 92 select_ctrl <= select_ctrl_NOP;
88 93 --ALU_CTRL <= ALU_CTRL_NOP;
89 94 select_op1 <= select_R0(0);
90 95 select_op2 <= select_R0;
91 96 res_wen <= '1';
97 fifo_in_empty_reg <= "11";
92 98
93 99 ELSIF clk'EVENT AND clk = '1' THEN
94 100 select_ctrl <= select_ctrl_NOP;
95 101 --ALU_CTRL <= ALU_CTRL_NOP;
96 102 correlation_begin <= '0';
97 103 fifo_in_ren_s <= "11";
98 104 res_wen <= '1';
99 105 correlation_done <= '0';
106 fifo_in_empty_reg <= fifo_in_empty;
100 107 CASE state IS
101 108 WHEN IDLE =>
102 109 IF correlation_start = '1' THEN
103 110 IF correlation_auto = '1' THEN
104 111 IF fifo_out_full = '1' THEN
105 112 state <= WFa;
106 113 ELSE
107 114 correlation_begin <= '1';
108 115 state <= S1a;
109 fifo_in_ren_s <= "10";
116 --fifo_in_ren_s <= "10";
110 117 END IF;
111 118 ELSE
112 119 IF fifo_out_full = '1' THEN
113 120 state <= WF;
114 121 ELSE
115 122 correlation_begin <= '1';
116 123 state <= S1;
117 fifo_in_ren_s <= "00";
124 --fifo_in_ren_s <= "00";
118 125 END IF;
119 126 END IF;
120 127 END IF;
121 128
122 129 ---------------------------------------------------------------------
123 130 -- INTER CORRELATION
124 131 ---------------------------------------------------------------------
125 132 WHEN WF =>
126 133 IF fifo_out_full = '0' THEN
127 134 correlation_begin <= '1';
128 135 state <= S1;
129 fifo_in_ren_s <= "00";
136 --fifo_in_ren_s <= "00";
130 137 END IF;
131 138 WHEN S1 =>
132 139 select_ctrl <= select_ctrl_MULT;
133 140 --ALU_CTRL <= ALU_CTRL_MULT;
134 141 select_op1 <= select_R0(0);
135 142 select_op2 <= select_R1;
136 143 state <= S2;
137 144 WHEN S2 =>
138 145 select_ctrl <= select_ctrl_MAC;
139 146 --ALU_CTRL <= ALU_CTRL_MAC;
140 147 select_op1 <= select_I0(0);
141 148 select_op2 <= select_I1;
142 149 res_wen <= '0';
143 150 state <= S3;
144 151 WHEN S3 =>
145 152 select_ctrl <= select_ctrl_MULT;
146 153 --ALU_CTRL <= ALU_CTRL_MULT;
147 select_op1 <= select_I0(0);
148 select_op2 <= select_R1;
154 select_op1 <= select_I0(0);
155 select_op2 <= select_R1;
156 fifo_in_ren_s <= fifo_in_empty;
149 157 state <= S4;
150 158 WHEN S4 =>
151 159 select_ctrl <= select_ctrl_MACn;
152 160 --ALU_CTRL <= ALU_CTRL_MACn;
153 161 select_op1 <= select_R0(0);
154 162 select_op2 <= select_I1;
155 163 res_wen <= '0';
156 164 IF fifo_in_empty = "00" THEN
157 165 state <= S1;
158 fifo_in_ren_s <= "00";
166 -- fifo_in_ren_s <= "00";
159 167 ELSE
160 168 correlation_done <= '1';
161 169 state <= IDLE;
162 170 END IF;
163 171
164 172
165 173
166 174 ---------------------------------------------------------------------
167 175 -- AUTO CORRELATION
168 176 ---------------------------------------------------------------------
169 177 WHEN WFa =>
170 178 IF fifo_out_full = '0' THEN
171 179 correlation_begin <= '1';
172 180 state <= S1a;
173 fifo_in_ren_s <= "10";
181 --fifo_in_ren_s <= "10";
174 182 END IF;
175 183 WHEN S1a =>
176 184 select_ctrl <= select_ctrl_MULT;
177 185 --ALU_CTRL <= ALU_CTRL_MULT;
178 186 select_op1 <= select_R0(0);
179 187 select_op2 <= select_R0;
188 fifo_in_ren_s(0) <= fifo_in_empty(0);
180 189 state <= S2a;
181 190 WHEN S2a =>
182 191 select_ctrl <= select_ctrl_MAC;
183 192 --ALU_CTRL <= ALU_CTRL_MAC;
184 193 select_op1 <= select_I0(0);
185 194 select_op2 <= select_I0;
186 195 res_wen <= '0';
187 196 IF fifo_in_empty(0) = '0' THEN
188 197 state <= S1a;
189 fifo_in_ren_s <= "10";
198 --fifo_in_ren_s <= "10";
190 199 ELSE
191 200 correlation_done <= '1';
192 201 state <= IDLE;
193 202 END IF;
194 203
195 204
196 205 WHEN OTHERS => NULL;
197 206 END CASE;
198 207
199 208 END IF;
200 209 END PROCESS;
201 210
202 211 ALU_CTRL <= ALU_CTRL_NOP WHEN select_ctrl = select_ctrl_NOP ELSE
203 212 ALU_CTRL_MULT WHEN select_ctrl = select_ctrl_MULT ELSE
204 213 ALU_CTRL_MAC WHEN select_ctrl = select_ctrl_MAC ELSE
205 214 ALU_CTRL_MACn;
206 215
207 216 OP1 <= fifo_in_data(15 DOWNTO 0) WHEN select_op1 = select_R0(0) ELSE
208 217 fifo_in_data(31 DOWNTO 16); -- WHEN select_op1 = select_I0(0) ELSE
209 218
210 219 OP2 <= fifo_in_data(15 DOWNTO 0) WHEN select_op2 = select_R0 ELSE
211 220 fifo_in_data(31 DOWNTO 16) WHEN select_op2 = select_I0 ELSE
212 221 fifo_in_data(47 DOWNTO 32) WHEN select_op2 = select_R1 ELSE
213 222 fifo_in_data(63 DOWNTO 48); -- WHEN select_op2 = select_I1 ELSE
214 223
215 224 ALU_MS : ALU
216 225 GENERIC MAP (
217 226 Arith_en => 1,
218 227 Logic_en => 0,
219 228 Input_SZ_1 => 16,
220 229 Input_SZ_2 => 16,
221 230 COMP_EN => 0) -- 0> Enable and 1> Disable
222 231 PORT MAP (
223 232 clk => clk,
224 233 reset => rstn,
225 234
226 235 ctrl => ALU_CTRL(2 DOWNTO 0),
227 236 comp => ALU_CTRL(4 DOWNTO 3),
228 237
229 238 OP1 => OP1,
230 239 OP2 => OP2,
231 240
232 241 RES => RES);
233 242
234 243 fifo_out_data <= RES;
235 244
236 245
237 246 PROCESS (clk, rstn)
238 247 BEGIN
239 248 IF rstn = '0' THEN
240 249 res_wen_reg1 <= '1';
241 250 res_wen_reg2 <= '1';
242 251 --res_wen_reg3 <= '1';
243 252 fifo_out_wen <= '1';
244 253 ELSIF clk'event AND clk = '1' THEN
245 254 res_wen_reg1 <= res_wen;
246 255 res_wen_reg2 <= res_wen_reg1;
247 256 --res_wen_reg3 <= res_wen_reg2;
248 257 fifo_out_wen <= res_wen_reg2;
249 258 END IF;
250 259 END PROCESS;
251 260
252 261
253 262 END beh;
Show file before | Show file after | Hide comments
@@ -1,1217 +1,1220
1 1 LIBRARY ieee;
2 2 USE ieee.std_logic_1164.ALL;
3 3 USE ieee.numeric_std.ALL;
4 4
5 5
6 6 LIBRARY lpp;
7 7 USE lpp.lpp_memory.ALL;
8 8 USE lpp.iir_filter.ALL;
9 9 USE lpp.spectral_matrix_package.ALL;
10 10 USE lpp.lpp_dma_pkg.ALL;
11 11 USE lpp.lpp_Header.ALL;
12 12 USE lpp.lpp_matrix.ALL;
13 13 USE lpp.lpp_matrix.ALL;
14 14 USE lpp.lpp_lfr_pkg.ALL;
15 15 USE lpp.lpp_fft.ALL;
16 16 USE lpp.fft_components.ALL;
17 17
18 18 ENTITY lpp_lfr_ms IS
19 19 GENERIC (
20 20 Mem_use : INTEGER := use_RAM
21 21 );
22 22 PORT (
23 23 clk : IN STD_LOGIC;
24 24 rstn : IN STD_LOGIC;
25 25 run : IN STD_LOGIC;
26 26
27 27 ---------------------------------------------------------------------------
28 28 -- DATA INPUT
29 29 ---------------------------------------------------------------------------
30 30 start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
31 31 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
32 32 --fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
33 33 --
34 34 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
35 35 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
36 36 sample_f0_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
37 37 --
38 38 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
39 39 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
40 40 sample_f1_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
41 41 --
42 42 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
43 43 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
44 sample_f2_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
44 sample_f2_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
45 45
46 46 ---------------------------------------------------------------------------
47 47 -- DMA
48 48 ---------------------------------------------------------------------------
49 49 dma_fifo_burst_valid: OUT STD_LOGIC; --TODO
50 50 dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --TODO
51 51 dma_fifo_ren : IN STD_LOGIC; --TODO
52 52 dma_buffer_new : OUT STD_LOGIC; --TODOx
53 53 dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --TODO
54 54 dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); --TODO
55 55 dma_buffer_full : IN STD_LOGIC; --TODO
56 56 dma_buffer_full_err : IN STD_LOGIC; --TODO
57 57
58 58 -- Reg out
59 59 ready_matrix_f0 : OUT STD_LOGIC; -- TODO
60 60 ready_matrix_f1 : OUT STD_LOGIC; -- TODO
61 61 ready_matrix_f2 : OUT STD_LOGIC; -- TODO
62 62 -- error_bad_component_error : OUT STD_LOGIC; -- TODO
63 63 error_buffer_full : OUT STD_LOGIC; -- TODO
64 64 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
65 65
66 66 -- Reg In
67 67 status_ready_matrix_f0 : IN STD_LOGIC; -- TODO
68 68 status_ready_matrix_f1 : IN STD_LOGIC; -- TODO
69 69 status_ready_matrix_f2 : IN STD_LOGIC; -- TODO
70 70
71 71 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
72 72 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
73 73 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
74 74
75 75 length_matrix_f0 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); -- TODO
76 76 length_matrix_f1 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); -- TODO
77 77 length_matrix_f2 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); -- TODO
78 78
79 79 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
80 80 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
81 81 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
82 82 ---------------------------------------------------------------------------
83 83 debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
84 84 );
85 85 END;
86 86
87 87 ARCHITECTURE Behavioral OF lpp_lfr_ms IS
88 88
89 89 SIGNAL sample_f0_A_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
90 90 SIGNAL sample_f0_A_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
91 91 SIGNAL sample_f0_A_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
92 92 SIGNAL sample_f0_A_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
93 93 SIGNAL sample_f0_A_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
94 94
95 95 SIGNAL sample_f0_B_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
96 96 SIGNAL sample_f0_B_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
97 97 SIGNAL sample_f0_B_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
98 98 SIGNAL sample_f0_B_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
99 99 SIGNAL sample_f0_B_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
100 100
101 101 SIGNAL sample_f1_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
102 102 SIGNAL sample_f1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
103 103 SIGNAL sample_f1_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
104 104 SIGNAL sample_f1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
105 105
106 106 SIGNAL sample_f1_almost_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
107 107
108 108 SIGNAL sample_f2_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
109 109 SIGNAL sample_f2_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
110 110 SIGNAL sample_f2_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
111 111 SIGNAL sample_f2_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
112 112
113 113 SIGNAL error_wen_f0 : STD_LOGIC;
114 114 SIGNAL error_wen_f1 : STD_LOGIC;
115 115 SIGNAL error_wen_f2 : STD_LOGIC;
116 116
117 117 SIGNAL one_sample_f1_full : STD_LOGIC;
118 118 SIGNAL one_sample_f1_wen : STD_LOGIC;
119 119 SIGNAL one_sample_f2_full : STD_LOGIC;
120 120 SIGNAL one_sample_f2_wen : STD_LOGIC;
121 121
122 122 -----------------------------------------------------------------------------
123 123 -- FSM / SWITCH SELECT CHANNEL
124 124 -----------------------------------------------------------------------------
125 125 TYPE fsm_select_channel IS (IDLE, SWITCH_F0_A, SWITCH_F0_B, SWITCH_F1, SWITCH_F2);
126 126 SIGNAL state_fsm_select_channel : fsm_select_channel;
127 127 -- SIGNAL pre_state_fsm_select_channel : fsm_select_channel;
128 128 SIGNAL select_channel : STD_LOGIC_VECTOR(1 DOWNTO 0);
129 129 SIGNAL select_channel_reg : STD_LOGIC_VECTOR(1 DOWNTO 0);
130 130
131 131 SIGNAL sample_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
132 132 SIGNAL sample_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
133 133 SIGNAL sample_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
134 134 SIGNAL sample_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
135 135
136 136 -----------------------------------------------------------------------------
137 137 -- FSM LOAD FFT
138 138 -----------------------------------------------------------------------------
139 139 TYPE fsm_load_FFT IS (IDLE, FIFO_1, FIFO_2, FIFO_3, FIFO_4, FIFO_5);
140 140 SIGNAL state_fsm_load_FFT : fsm_load_FFT;
141 141 -- SIGNAL next_state_fsm_load_FFT : fsm_load_FFT;
142 142 SIGNAL select_fifo : STD_LOGIC_VECTOR(2 DOWNTO 0);
143 143 SIGNAL select_fifo_reg : STD_LOGIC_VECTOR(2 DOWNTO 0);
144 144
145 145 SIGNAL sample_ren_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
146 146 SIGNAL sample_load : STD_LOGIC;
147 147 SIGNAL sample_valid : STD_LOGIC;
148 148 SIGNAL sample_valid_r : STD_LOGIC;
149 149 SIGNAL sample_data : STD_LOGIC_VECTOR(15 DOWNTO 0);
150 150
151 151
152 152 -----------------------------------------------------------------------------
153 153 -- FFT
154 154 -----------------------------------------------------------------------------
155 155 SIGNAL fft_read : STD_LOGIC;
156 156 SIGNAL fft_pong : STD_LOGIC;
157 157 SIGNAL fft_data_im : STD_LOGIC_VECTOR(15 DOWNTO 0);
158 158 SIGNAL fft_data_re : STD_LOGIC_VECTOR(15 DOWNTO 0);
159 159 SIGNAL fft_data_valid : STD_LOGIC;
160 160 SIGNAL fft_ready : STD_LOGIC;
161 161 -----------------------------------------------------------------------------
162 162 -- SIGNAL fft_linker_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
163 163 -----------------------------------------------------------------------------
164 164 TYPE fsm_load_MS_memory IS (IDLE, LOAD_FIFO, TRASH_FFT);
165 165 SIGNAL state_fsm_load_MS_memory : fsm_load_MS_memory;
166 166 SIGNAL current_fifo_load : STD_LOGIC_VECTOR(4 DOWNTO 0);
167 167 SIGNAL current_fifo_empty : STD_LOGIC;
168 168 SIGNAL current_fifo_locked : STD_LOGIC;
169 169 SIGNAL current_fifo_full : STD_LOGIC;
170 170 SIGNAL MEM_IN_SM_locked : STD_LOGIC_VECTOR(4 DOWNTO 0);
171 171
172 172 -----------------------------------------------------------------------------
173 173 SIGNAL MEM_IN_SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
174 174 SIGNAL MEM_IN_SM_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
175 175 SIGNAL MEM_IN_SM_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
176 176 SIGNAL MEM_IN_SM_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
177 177 SIGNAL MEM_IN_SM_wData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
178 178 SIGNAL MEM_IN_SM_rData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
179 179 SIGNAL MEM_IN_SM_Full : STD_LOGIC_VECTOR(4 DOWNTO 0);
180 180 SIGNAL MEM_IN_SM_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
181 181 -----------------------------------------------------------------------------
182 182 SIGNAL SM_in_data : STD_LOGIC_VECTOR(32*2-1 DOWNTO 0);
183 183 SIGNAL SM_in_ren : STD_LOGIC_VECTOR(1 DOWNTO 0);
184 184 SIGNAL SM_in_empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
185 185
186 186 SIGNAL SM_correlation_start : STD_LOGIC;
187 187 SIGNAL SM_correlation_auto : STD_LOGIC;
188 188 SIGNAL SM_correlation_done : STD_LOGIC;
189 189 SIGNAL SM_correlation_done_reg1 : STD_LOGIC;
190 190 SIGNAL SM_correlation_done_reg2 : STD_LOGIC;
191 191 SIGNAL SM_correlation_done_reg3 : STD_LOGIC;
192 192 SIGNAL SM_correlation_begin : STD_LOGIC;
193 193
194 194 SIGNAL MEM_OUT_SM_Full_s : STD_LOGIC;
195 195 SIGNAL MEM_OUT_SM_Data_in_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
196 196 SIGNAL MEM_OUT_SM_Write_s : STD_LOGIC;
197 197
198 198 SIGNAL current_matrix_write : STD_LOGIC;
199 199 SIGNAL current_matrix_wait_empty : STD_LOGIC;
200 200 -----------------------------------------------------------------------------
201 201 SIGNAL fifo_0_ready : STD_LOGIC;
202 202 SIGNAL fifo_1_ready : STD_LOGIC;
203 203 SIGNAL fifo_ongoing : STD_LOGIC;
204 SIGNAL fifo_ongoing_reg : STD_LOGIC;
204 205
205 206 SIGNAL FSM_DMA_fifo_ren : STD_LOGIC;
206 207 SIGNAL FSM_DMA_fifo_empty : STD_LOGIC;
207 208 SIGNAL FSM_DMA_fifo_empty_threshold : STD_LOGIC;
208 209 SIGNAL FSM_DMA_fifo_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
209 210 SIGNAL FSM_DMA_fifo_status : STD_LOGIC_VECTOR(53 DOWNTO 4);
210 211 -----------------------------------------------------------------------------
211 212 SIGNAL MEM_OUT_SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0);
212 213 SIGNAL MEM_OUT_SM_Read : STD_LOGIC_VECTOR(1 DOWNTO 0);
213 214 SIGNAL MEM_OUT_SM_Data_in : STD_LOGIC_VECTOR(63 DOWNTO 0);
214 215 SIGNAL MEM_OUT_SM_Data_out : STD_LOGIC_VECTOR(63 DOWNTO 0);
215 216 SIGNAL MEM_OUT_SM_Full : STD_LOGIC_VECTOR(1 DOWNTO 0);
216 217 SIGNAL MEM_OUT_SM_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
217 218 SIGNAL MEM_OUT_SM_Empty_Threshold : STD_LOGIC_VECTOR(1 DOWNTO 0);
218 219
219 220 -----------------------------------------------------------------------------
220 221 -- TIME REG & INFOs
221 222 -----------------------------------------------------------------------------
222 223 SIGNAL all_time : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
223 224
224 225 SIGNAL f_empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
225 226 SIGNAL f_empty_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
226 227 SIGNAL time_update_f : STD_LOGIC_VECTOR(3 DOWNTO 0);
227 228 SIGNAL time_reg_f : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
228 229
229 230 SIGNAL time_reg_f0_A : STD_LOGIC_VECTOR(47 DOWNTO 0);
230 231 SIGNAL time_reg_f0_B : STD_LOGIC_VECTOR(47 DOWNTO 0);
231 232 SIGNAL time_reg_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
232 233 SIGNAL time_reg_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
233 234
234 235 --SIGNAL time_update_f0_A : STD_LOGIC;
235 236 --SIGNAL time_update_f0_B : STD_LOGIC;
236 237 --SIGNAL time_update_f1 : STD_LOGIC;
237 238 --SIGNAL time_update_f2 : STD_LOGIC;
238 239 --
239 240 SIGNAL status_channel : STD_LOGIC_VECTOR(49 DOWNTO 0);
240 241 SIGNAL status_MS_input : STD_LOGIC_VECTOR(49 DOWNTO 0);
241 242 SIGNAL status_component : STD_LOGIC_VECTOR(53 DOWNTO 0);
242 243
243 244 SIGNAL status_component_fifo_0 : STD_LOGIC_VECTOR(53 DOWNTO 4);
244 245 SIGNAL status_component_fifo_1 : STD_LOGIC_VECTOR(53 DOWNTO 4);
245 246 SIGNAL status_component_fifo_0_end : STD_LOGIC;
246 247 SIGNAL status_component_fifo_1_end : STD_LOGIC;
247 248 -----------------------------------------------------------------------------
248 249 SIGNAL fft_ongoing_counter : STD_LOGIC;--_VECTOR(1 DOWNTO 0);
249 250
250 251 SIGNAL fft_ready_reg : STD_LOGIC;
251 252 SIGNAL fft_ready_rising_down : STD_LOGIC;
252 253
253 254 SIGNAL sample_load_reg : STD_LOGIC;
254 255 SIGNAL sample_load_rising_down : STD_LOGIC;
255 256
256 257 -----------------------------------------------------------------------------
257 258 SIGNAL sample_f1_wen_head : STD_LOGIC_VECTOR(4 DOWNTO 0);
258 259 SIGNAL sample_f1_wen_head_in : STD_LOGIC;
259 260 SIGNAL sample_f1_wen_head_out : STD_LOGIC;
260 261 SIGNAL sample_f1_full_head_in : STD_LOGIC;
261 262 SIGNAL sample_f1_full_head_out : STD_LOGIC;
262 263 SIGNAL sample_f1_empty_head_in : STD_LOGIC;
263 264
264 265 SIGNAL sample_f1_wdata_head : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
265 266 -----------------------------------------------------------------------------
266 267 SIGNAL sample_f0_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
267 268 SIGNAL sample_f1_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
268 269 SIGNAL sample_f2_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
269 270 SIGNAL ongoing : STD_LOGIC;
270 271
271 272 BEGIN
272 273
273 274 PROCESS (clk, rstn)
274 275 BEGIN -- PROCESS
275 276 IF rstn = '0' THEN -- asynchronous reset (active low)
276 277 sample_f0_wen_s <= (OTHERS => '1');
277 278 sample_f1_wen_s <= (OTHERS => '1');
278 279 sample_f2_wen_s <= (OTHERS => '1');
279 280 ongoing <= '0';
280 281 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
281 282 IF ongoing = '1' THEN
282 283 sample_f0_wen_s <= sample_f0_wen;
283 284 sample_f1_wen_s <= sample_f1_wen;
284 285 sample_f2_wen_s <= sample_f2_wen;
285 286 ELSE
286 287 IF start_date = coarse_time(30 DOWNTO 0) THEN
287 288 ongoing <= '1';
288 289 END IF;
289 290 sample_f0_wen_s <= (OTHERS => '1');
290 291 sample_f1_wen_s <= (OTHERS => '1');
291 292 sample_f2_wen_s <= (OTHERS => '1');
292 293 END IF;
293 294 END IF;
294 295 END PROCESS;
295 296
296 297
297 298 error_input_fifo_write <= error_wen_f2 & error_wen_f1 & error_wen_f0;
298 299
299 300
300 301 switch_f0_inst : spectral_matrix_switch_f0
301 302 PORT MAP (
302 303 clk => clk,
303 304 rstn => rstn,
304 305
305 306 sample_wen => sample_f0_wen_s,
306 307
307 308 fifo_A_empty => sample_f0_A_empty,
308 309 fifo_A_full => sample_f0_A_full,
309 310 fifo_A_wen => sample_f0_A_wen,
310 311
311 312 fifo_B_empty => sample_f0_B_empty,
312 313 fifo_B_full => sample_f0_B_full,
313 314 fifo_B_wen => sample_f0_B_wen,
314 315
315 316 error_wen => error_wen_f0); -- TODO
316 317
317 318 -----------------------------------------------------------------------------
318 319 -- FIFO IN
319 320 -----------------------------------------------------------------------------
320 321 lppFIFOxN_f0_a : lppFIFOxN
321 322 GENERIC MAP (
322 323 tech => 0,
323 324 Mem_use => Mem_use,
324 325 Data_sz => 16,
325 326 Addr_sz => 8,
326 327 FifoCnt => 5)
327 328 PORT MAP (
328 329 clk => clk,
329 330 rstn => rstn,
330 331
331 332 ReUse => (OTHERS => '0'),
332 333
333 334 run => (OTHERS => '1'),
334 335
335 336 wen => sample_f0_A_wen,
336 337 wdata => sample_f0_wdata,
337 338
338 339 ren => sample_f0_A_ren,
339 340 rdata => sample_f0_A_rdata,
340 341
341 342 empty => sample_f0_A_empty,
342 343 full => sample_f0_A_full,
343 344 almost_full => OPEN);
344 345
345 346 lppFIFOxN_f0_b : lppFIFOxN
346 347 GENERIC MAP (
347 348 tech => 0,
348 349 Mem_use => Mem_use,
349 350 Data_sz => 16,
350 351 Addr_sz => 8,
351 352 FifoCnt => 5)
352 353 PORT MAP (
353 354 clk => clk,
354 355 rstn => rstn,
355 356
356 357 ReUse => (OTHERS => '0'),
357 358 run => (OTHERS => '1'),
358 359
359 360 wen => sample_f0_B_wen,
360 361 wdata => sample_f0_wdata,
361 362 ren => sample_f0_B_ren,
362 363 rdata => sample_f0_B_rdata,
363 364 empty => sample_f0_B_empty,
364 365 full => sample_f0_B_full,
365 366 almost_full => OPEN);
366 367
367 368 -----------------------------------------------------------------------------
368 369 -- sample_f1_wen in
369 370 -- sample_f1_wdata in
370 371 -- sample_f1_full OUT
371 372
372 373 sample_f1_wen_head_in <= '0' WHEN sample_f1_wen_s = "00000" ELSE '1';
373 374 sample_f1_full_head_in <= '0' WHEN sample_f1_full = "00000" ELSE '1';
374 375 sample_f1_empty_head_in <= '1' WHEN sample_f1_empty = "11111" ELSE '0';
375 376
376 377 lpp_lfr_ms_reg_head_1:lpp_lfr_ms_reg_head
377 378 PORT MAP (
378 379 clk => clk,
379 380 rstn => rstn,
380 381 in_wen => sample_f1_wen_head_in,
381 382 in_data => sample_f1_wdata,
382 383 in_full => sample_f1_full_head_in,
383 384 in_empty => sample_f1_empty_head_in,
384 385 out_write_error => error_wen_f1,
385 386 out_wen => sample_f1_wen_head_out,
386 387 out_data => sample_f1_wdata_head,
387 388 out_full => sample_f1_full_head_out);
388 389
389 390 sample_f1_wen_head <= sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out;
390 391
391 392
392 393 lppFIFOxN_f1 : lppFIFOxN
393 394 GENERIC MAP (
394 395 tech => 0,
395 396 Mem_use => Mem_use,
396 397 Data_sz => 16,
397 398 Addr_sz => 8,
398 399 FifoCnt => 5)
399 400 PORT MAP (
400 401 clk => clk,
401 402 rstn => rstn,
402 403
403 404 ReUse => (OTHERS => '0'),
404 405 run => (OTHERS => '1'),
405 406
406 407 wen => sample_f1_wen_head,
407 408 wdata => sample_f1_wdata_head,
408 409 ren => sample_f1_ren,
409 410 rdata => sample_f1_rdata,
410 411 empty => sample_f1_empty,
411 412 full => sample_f1_full,
412 413 almost_full => sample_f1_almost_full);
413 414
414 415
415 416 one_sample_f1_wen <= '0' WHEN sample_f1_wen_head = "11111" ELSE '1';
416 417
417 418 PROCESS (clk, rstn)
418 419 BEGIN -- PROCESS
419 420 IF rstn = '0' THEN -- asynchronous reset (active low)
420 421 one_sample_f1_full <= '0';
421 422 --error_wen_f1 <= '0';
422 423 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
423 424 IF sample_f1_full_head_out = '0' THEN
424 425 one_sample_f1_full <= '0';
425 426 ELSE
426 427 one_sample_f1_full <= '1';
427 428 END IF;
428 429 --error_wen_f1 <= one_sample_f1_wen AND one_sample_f1_full;
429 430 END IF;
430 431 END PROCESS;
431 432
432 433 -----------------------------------------------------------------------------
433 434
434 435
435 436 lppFIFOxN_f2 : lppFIFOxN
436 437 GENERIC MAP (
437 438 tech => 0,
438 439 Mem_use => Mem_use,
439 440 Data_sz => 16,
440 441 Addr_sz => 8,
441 442 FifoCnt => 5)
442 443 PORT MAP (
443 444 clk => clk,
444 445 rstn => rstn,
445 446
446 447 ReUse => (OTHERS => '0'),
447 448 run => (OTHERS => '1'),
448 449
449 450 wen => sample_f2_wen_s,
450 451 wdata => sample_f2_wdata,
451 452 ren => sample_f2_ren,
452 453 rdata => sample_f2_rdata,
453 454 empty => sample_f2_empty,
454 455 full => sample_f2_full,
455 456 almost_full => OPEN);
456 457
457 458
458 459 one_sample_f2_wen <= '0' WHEN sample_f2_wen_s = "11111" ELSE '1';
459 460
460 461 PROCESS (clk, rstn)
461 462 BEGIN -- PROCESS
462 463 IF rstn = '0' THEN -- asynchronous reset (active low)
463 464 one_sample_f2_full <= '0';
464 465 error_wen_f2 <= '0';
465 466 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
466 467 IF sample_f2_full = "00000" THEN
467 468 one_sample_f2_full <= '0';
468 469 ELSE
469 470 one_sample_f2_full <= '1';
470 471 END IF;
471 472 error_wen_f2 <= one_sample_f2_wen AND one_sample_f2_full;
472 473 END IF;
473 474 END PROCESS;
474 475
475 476 -----------------------------------------------------------------------------
476 477 -- FSM SELECT CHANNEL
477 478 -----------------------------------------------------------------------------
478 479 PROCESS (clk, rstn)
479 480 BEGIN
480 481 IF rstn = '0' THEN
481 482 state_fsm_select_channel <= IDLE;
482 483 select_channel <= (OTHERS => '0');
483 484 ELSIF clk'EVENT AND clk = '1' THEN
484 485 CASE state_fsm_select_channel IS
485 486 WHEN IDLE =>
486 487 IF sample_f1_full = "11111" THEN
487 488 state_fsm_select_channel <= SWITCH_F1;
488 489 select_channel <= "10";
489 490 ELSIF sample_f1_almost_full = "00000" THEN
490 491 IF sample_f0_A_full = "11111" THEN
491 492 state_fsm_select_channel <= SWITCH_F0_A;
492 493 select_channel <= "00";
493 494 ELSIF sample_f0_B_full = "11111" THEN
494 495 state_fsm_select_channel <= SWITCH_F0_B;
495 496 select_channel <= "01";
496 497 ELSIF sample_f2_full = "11111" THEN
497 498 state_fsm_select_channel <= SWITCH_F2;
498 499 select_channel <= "11";
499 500 END IF;
500 501 END IF;
501 502
502 503 WHEN SWITCH_F0_A =>
503 504 IF sample_f0_A_empty = "11111" THEN
504 505 state_fsm_select_channel <= IDLE;
505 506 select_channel <= (OTHERS => '0');
506 507 END IF;
507 508 WHEN SWITCH_F0_B =>
508 509 IF sample_f0_B_empty = "11111" THEN
509 510 state_fsm_select_channel <= IDLE;
510 511 select_channel <= (OTHERS => '0');
511 512 END IF;
512 513 WHEN SWITCH_F1 =>
513 514 IF sample_f1_empty = "11111" THEN
514 515 state_fsm_select_channel <= IDLE;
515 516 select_channel <= (OTHERS => '0');
516 517 END IF;
517 518 WHEN SWITCH_F2 =>
518 519 IF sample_f2_empty = "11111" THEN
519 520 state_fsm_select_channel <= IDLE;
520 521 select_channel <= (OTHERS => '0');
521 522 END IF;
522 523 WHEN OTHERS => NULL;
523 524 END CASE;
524 525
525 526 END IF;
526 527 END PROCESS;
527 528
528 529 PROCESS (clk, rstn)
529 530 BEGIN
530 531 IF rstn = '0' THEN
531 532 select_channel_reg <= (OTHERS => '0');
532 533 --pre_state_fsm_select_channel <= IDLE;
533 534 ELSIF clk'EVENT AND clk = '1' THEN
534 535 select_channel_reg <= select_channel;
535 536 --pre_state_fsm_select_channel <= state_fsm_select_channel;
536 537 END IF;
537 538 END PROCESS;
538 539
539 540
540 541 -----------------------------------------------------------------------------
541 542 -- SWITCH SELECT CHANNEL
542 543 -----------------------------------------------------------------------------
543 544 sample_empty <= sample_f0_A_empty WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
544 545 sample_f0_B_empty WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
545 546 sample_f1_empty WHEN state_fsm_select_channel = SWITCH_F1 ELSE
546 547 sample_f2_empty WHEN state_fsm_select_channel = SWITCH_F2 ELSE
547 548 (OTHERS => '1');
548 549
549 550 sample_full <= sample_f0_A_full WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
550 551 sample_f0_B_full WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
551 552 sample_f1_full WHEN state_fsm_select_channel = SWITCH_F1 ELSE
552 553 sample_f2_full WHEN state_fsm_select_channel = SWITCH_F2 ELSE
553 554 (OTHERS => '0');
554 555
555 556 --sample_rdata <= sample_f0_A_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_A ELSE
556 557 -- sample_f0_B_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_B ELSE
557 558 -- sample_f1_rdata WHEN pre_state_fsm_select_channel = SWITCH_F1 ELSE
558 559 -- sample_f2_rdata; -- WHEN state_fsm_select_channel = SWITCH_F2 ELSE
559 560 sample_rdata <= sample_f0_A_rdata WHEN select_channel_reg = "00" ELSE
560 561 sample_f0_B_rdata WHEN select_channel_reg = "01" ELSE
561 562 sample_f1_rdata WHEN select_channel_reg = "10" ELSE
562 563 sample_f2_rdata; -- WHEN state_fsm_select_channel = SWITCH_F2 ELSE
563 564
564 565
565 566 sample_f0_A_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_A ELSE (OTHERS => '1');
566 567 sample_f0_B_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_B ELSE (OTHERS => '1');
567 568 sample_f1_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F1 ELSE (OTHERS => '1');
568 569 sample_f2_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F2 ELSE (OTHERS => '1');
569 570
570 571
571 572 status_channel <= time_reg_f0_A & "00" WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
572 573 time_reg_f0_B & "00" WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
573 574 time_reg_f1 & "01" WHEN state_fsm_select_channel = SWITCH_F1 ELSE
574 575 time_reg_f2 & "10"; -- WHEN state_fsm_select_channel = SWITCH_F2
575 576
576 577 -----------------------------------------------------------------------------
577 578 -- FSM LOAD FFT
578 579 -----------------------------------------------------------------------------
579 580
580 581 sample_ren <= (OTHERS => '1') WHEN fft_ongoing_counter = '1' ELSE
581 582 sample_ren_s WHEN sample_load = '1' ELSE
582 583 (OTHERS => '1');
583 584
584 585 PROCESS (clk, rstn)
585 586 BEGIN
586 587 IF rstn = '0' THEN
587 588 sample_ren_s <= (OTHERS => '1');
588 589 state_fsm_load_FFT <= IDLE;
589 590 status_MS_input <= (OTHERS => '0');
590 591 select_fifo <= "000";
591 592 --next_state_fsm_load_FFT <= IDLE;
592 593 --sample_valid <= '0';
593 594 ELSIF clk'EVENT AND clk = '1' THEN
594 595 CASE state_fsm_load_FFT IS
595 596 WHEN IDLE =>
596 597 --sample_valid <= '0';
597 598 sample_ren_s <= (OTHERS => '1');
598 599 IF sample_full = "11111" AND sample_load = '1' THEN
599 600 state_fsm_load_FFT <= FIFO_1;
600 601 status_MS_input <= status_channel;
601 602 select_fifo <= "000";
602 603 END IF;
603 604
604 605 WHEN FIFO_1 =>
605 606 sample_ren_s <= "1111" & NOT(sample_load);
606 607 IF sample_empty(0) = '1' THEN
607 608 sample_ren_s <= (OTHERS => '1');
608 609 state_fsm_load_FFT <= FIFO_2;
609 610 select_fifo <= "001";
610 611 END IF;
611 612
612 613 WHEN FIFO_2 =>
613 614 sample_ren_s <= "111" & NOT(sample_load) & '1';
614 615 IF sample_empty(1) = '1' THEN
615 616 sample_ren_s <= (OTHERS => '1');
616 617 state_fsm_load_FFT <= FIFO_3;
617 618 select_fifo <= "010";
618 619 END IF;
619 620
620 621 WHEN FIFO_3 =>
621 622 sample_ren_s <= "11" & NOT(sample_load) & "11";
622 623 IF sample_empty(2) = '1' THEN
623 624 sample_ren_s <= (OTHERS => '1');
624 625 state_fsm_load_FFT <= FIFO_4;
625 626 select_fifo <= "011";
626 627 END IF;
627 628
628 629 WHEN FIFO_4 =>
629 630 sample_ren_s <= '1' & NOT(sample_load) & "111";
630 631 IF sample_empty(3) = '1' THEN
631 632 sample_ren_s <= (OTHERS => '1');
632 633 state_fsm_load_FFT <= FIFO_5;
633 634 select_fifo <= "100";
634 635 END IF;
635 636
636 637 WHEN FIFO_5 =>
637 638 sample_ren_s <= NOT(sample_load) & "1111";
638 639 IF sample_empty(4) = '1' THEN
639 640 sample_ren_s <= (OTHERS => '1');
640 641 state_fsm_load_FFT <= IDLE;
641 642 select_fifo <= "000";
642 643 END IF;
643 644 WHEN OTHERS => NULL;
644 645 END CASE;
645 646 END IF;
646 647 END PROCESS;
647 648
648 649 PROCESS (clk, rstn)
649 650 BEGIN
650 651 IF rstn = '0' THEN
651 652 sample_valid_r <= '0';
652 653 select_fifo_reg <= (OTHERS => '0');
653 654 --next_state_fsm_load_FFT <= IDLE;
654 655 ELSIF clk'EVENT AND clk = '1' THEN
655 656 select_fifo_reg <= select_fifo;
656 657 --next_state_fsm_load_FFT <= state_fsm_load_FFT;
657 658 IF sample_ren_s = "11111" THEN
658 659 sample_valid_r <= '0';
659 660 ELSE
660 661 sample_valid_r <= '1';
661 662 END IF;
662 663 END IF;
663 664 END PROCESS;
664 665
665 666 sample_valid <= '0' WHEN fft_ongoing_counter = '1' ELSE sample_valid_r AND sample_load;
666 667
667 668 --sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN next_state_fsm_load_FFT = FIFO_1 ELSE
668 669 -- sample_rdata(16*2-1 DOWNTO 16*1) WHEN next_state_fsm_load_FFT = FIFO_2 ELSE
669 670 -- sample_rdata(16*3-1 DOWNTO 16*2) WHEN next_state_fsm_load_FFT = FIFO_3 ELSE
670 671 -- sample_rdata(16*4-1 DOWNTO 16*3) WHEN next_state_fsm_load_FFT = FIFO_4 ELSE
671 672 -- sample_rdata(16*5-1 DOWNTO 16*4); --WHEN next_state_fsm_load_FFT = FIFO_5 ELSE
672 673 sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN select_fifo_reg = "000" ELSE
673 674 sample_rdata(16*2-1 DOWNTO 16*1) WHEN select_fifo_reg = "001" ELSE
674 675 sample_rdata(16*3-1 DOWNTO 16*2) WHEN select_fifo_reg = "010" ELSE
675 676 sample_rdata(16*4-1 DOWNTO 16*3) WHEN select_fifo_reg = "011" ELSE
676 677 sample_rdata(16*5-1 DOWNTO 16*4); --WHEN next_state_fsm_load_FFT = FIFO_5 ELSE
677 678
678 679 -----------------------------------------------------------------------------
679 680 -- FFT
680 681 -----------------------------------------------------------------------------
681 682 lpp_lfr_ms_FFT_1 : lpp_lfr_ms_FFT
682 683 PORT MAP (
683 684 clk => clk,
684 685 rstn => rstn,
685 686 sample_valid => sample_valid,
686 687 fft_read => fft_read,
687 688 sample_data => sample_data,
688 689 sample_load => sample_load,
689 690 fft_pong => fft_pong,
690 691 fft_data_im => fft_data_im,
691 692 fft_data_re => fft_data_re,
692 693 fft_data_valid => fft_data_valid,
693 694 fft_ready => fft_ready);
694 695
695 696 debug_vector(0) <= fft_data_valid;
696 697 debug_vector(1) <= fft_ready;
697 698 debug_vector(11 DOWNTO 2) <= (OTHERS => '0');
698 699
699 700
700 701 -----------------------------------------------------------------------------
701 702 fft_ready_rising_down <= fft_ready_reg AND NOT fft_ready;
702 703 sample_load_rising_down <= sample_load_reg AND NOT sample_load;
703 704
704 705 PROCESS (clk, rstn)
705 706 BEGIN
706 707 IF rstn = '0' THEN
707 708 fft_ready_reg <= '0';
708 709 sample_load_reg <= '0';
709 710
710 711 fft_ongoing_counter <= '0';
711 712 ELSIF clk'event AND clk = '1' THEN
712 713 fft_ready_reg <= fft_ready;
713 714 sample_load_reg <= sample_load;
714 715
715 716 IF fft_ready_rising_down = '1' AND sample_load_rising_down = '0' THEN
716 717 fft_ongoing_counter <= '0';
717 718
718 719 -- CASE fft_ongoing_counter IS
719 720 -- WHEN "01" => fft_ongoing_counter <= "00";
720 721 ---- WHEN "10" => fft_ongoing_counter <= "01";
721 722 -- WHEN OTHERS => NULL;
722 723 -- END CASE;
723 724 ELSIF fft_ready_rising_down = '0' AND sample_load_rising_down = '1' THEN
724 725 fft_ongoing_counter <= '1';
725 726 -- CASE fft_ongoing_counter IS
726 727 -- WHEN "00" => fft_ongoing_counter <= "01";
727 728 ---- WHEN "01" => fft_ongoing_counter <= "10";
728 729 -- WHEN OTHERS => NULL;
729 730 -- END CASE;
730 731 END IF;
731 732
732 733 END IF;
733 734 END PROCESS;
734 735
735 736 -----------------------------------------------------------------------------
736 737 PROCESS (clk, rstn)
737 738 BEGIN
738 739 IF rstn = '0' THEN
739 740 state_fsm_load_MS_memory <= IDLE;
740 741 current_fifo_load <= "00001";
741 742 ELSIF clk'EVENT AND clk = '1' THEN
742 743 CASE state_fsm_load_MS_memory IS
743 744 WHEN IDLE =>
744 745 IF current_fifo_empty = '1' AND fft_ready = '1' AND current_fifo_locked = '0' THEN
745 746 state_fsm_load_MS_memory <= LOAD_FIFO;
746 747 END IF;
747 748 WHEN LOAD_FIFO =>
748 749 IF current_fifo_full = '1' THEN
749 750 state_fsm_load_MS_memory <= TRASH_FFT;
750 751 END IF;
751 752 WHEN TRASH_FFT =>
752 753 IF fft_ready = '0' THEN
753 754 state_fsm_load_MS_memory <= IDLE;
754 755 current_fifo_load <= current_fifo_load(3 DOWNTO 0) & current_fifo_load(4);
755 756 END IF;
756 757 WHEN OTHERS => NULL;
757 758 END CASE;
758 759
759 760 END IF;
760 761 END PROCESS;
761 762
762 763 current_fifo_empty <= MEM_IN_SM_Empty(0) WHEN current_fifo_load(0) = '1' ELSE
763 764 MEM_IN_SM_Empty(1) WHEN current_fifo_load(1) = '1' ELSE
764 765 MEM_IN_SM_Empty(2) WHEN current_fifo_load(2) = '1' ELSE
765 766 MEM_IN_SM_Empty(3) WHEN current_fifo_load(3) = '1' ELSE
766 767 MEM_IN_SM_Empty(4); -- WHEN current_fifo_load(3) = '1' ELSE
767 768
768 769 current_fifo_full <= MEM_IN_SM_Full(0) WHEN current_fifo_load(0) = '1' ELSE
769 770 MEM_IN_SM_Full(1) WHEN current_fifo_load(1) = '1' ELSE
770 771 MEM_IN_SM_Full(2) WHEN current_fifo_load(2) = '1' ELSE
771 772 MEM_IN_SM_Full(3) WHEN current_fifo_load(3) = '1' ELSE
772 773 MEM_IN_SM_Full(4); -- WHEN current_fifo_load(3) = '1' ELSE
773 774
774 775 current_fifo_locked <= MEM_IN_SM_locked(0) WHEN current_fifo_load(0) = '1' ELSE
775 776 MEM_IN_SM_locked(1) WHEN current_fifo_load(1) = '1' ELSE
776 777 MEM_IN_SM_locked(2) WHEN current_fifo_load(2) = '1' ELSE
777 778 MEM_IN_SM_locked(3) WHEN current_fifo_load(3) = '1' ELSE
778 779 MEM_IN_SM_locked(4); -- WHEN current_fifo_load(3) = '1' ELSE
779 780
780 781 fft_read <= '0' WHEN state_fsm_load_MS_memory = IDLE ELSE '1';
781 782
782 783 all_fifo : FOR I IN 4 DOWNTO 0 GENERATE
783 784 MEM_IN_SM_wen_s(I) <= '0' WHEN fft_data_valid = '1'
784 785 AND state_fsm_load_MS_memory = LOAD_FIFO
785 786 AND current_fifo_load(I) = '1'
786 787 ELSE '1';
787 788 END GENERATE all_fifo;
788 789
789 790 PROCESS (clk, rstn)
790 791 BEGIN
791 792 IF rstn = '0' THEN
792 793 MEM_IN_SM_wen <= (OTHERS => '1');
793 794 ELSIF clk'EVENT AND clk = '1' THEN
794 795 MEM_IN_SM_wen <= MEM_IN_SM_wen_s;
795 796 END IF;
796 797 END PROCESS;
797 798
798 799 MEM_IN_SM_wData <= (fft_data_im & fft_data_re) &
799 800 (fft_data_im & fft_data_re) &
800 801 (fft_data_im & fft_data_re) &
801 802 (fft_data_im & fft_data_re) &
802 803 (fft_data_im & fft_data_re);
803 804 -----------------------------------------------------------------------------
804 805
805 806
806 807 -----------------------------------------------------------------------------
807 808 Mem_In_SpectralMatrix : lppFIFOxN
808 809 GENERIC MAP (
809 810 tech => 0,
810 811 Mem_use => Mem_use,
811 812 Data_sz => 32, --16,
812 813 Addr_sz => 7, --8
813 814 FifoCnt => 5)
814 815 PORT MAP (
815 816 clk => clk,
816 817 rstn => rstn,
817 818
818 819 ReUse => MEM_IN_SM_ReUse,
819 820 run => (OTHERS => '1'),
820 821
821 822 wen => MEM_IN_SM_wen,
822 823 wdata => MEM_IN_SM_wData,
823 824
824 825 ren => MEM_IN_SM_ren,
825 826 rdata => MEM_IN_SM_rData,
826 827 full => MEM_IN_SM_Full,
827 828 empty => MEM_IN_SM_Empty,
828 829 almost_full => OPEN);
829 830
830 831
831 832 -----------------------------------------------------------------------------
832 833 MS_control_1 : MS_control
833 834 PORT MAP (
834 835 clk => clk,
835 836 rstn => rstn,
836 837
837 838 current_status_ms => status_MS_input,
838 839
839 840 fifo_in_lock => MEM_IN_SM_locked,
840 841 fifo_in_data => MEM_IN_SM_rdata,
841 842 fifo_in_full => MEM_IN_SM_Full,
842 843 fifo_in_empty => MEM_IN_SM_Empty,
843 844 fifo_in_ren => MEM_IN_SM_ren,
844 845 fifo_in_reuse => MEM_IN_SM_ReUse,
845 846
846 847 fifo_out_data => SM_in_data,
847 848 fifo_out_ren => SM_in_ren,
848 849 fifo_out_empty => SM_in_empty,
849 850
850 851 current_status_component => status_component,
851 852
852 853 correlation_start => SM_correlation_start,
853 854 correlation_auto => SM_correlation_auto,
854 855 correlation_done => SM_correlation_done);
855 856
856 857
857 858 MS_calculation_1 : MS_calculation
858 859 PORT MAP (
859 860 clk => clk,
860 861 rstn => rstn,
861 862
862 863 fifo_in_data => SM_in_data,
863 864 fifo_in_ren => SM_in_ren,
864 865 fifo_in_empty => SM_in_empty,
865 866
866 867 fifo_out_data => MEM_OUT_SM_Data_in_s, -- TODO
867 868 fifo_out_wen => MEM_OUT_SM_Write_s, -- TODO
868 869 fifo_out_full => MEM_OUT_SM_Full_s, -- TODO
869 870
870 871 correlation_start => SM_correlation_start,
871 872 correlation_auto => SM_correlation_auto,
872 873 correlation_begin => SM_correlation_begin,
873 874 correlation_done => SM_correlation_done);
874 875
875 876 -----------------------------------------------------------------------------
876 877 PROCESS (clk, rstn)
877 878 BEGIN -- PROCESS
878 879 IF rstn = '0' THEN -- asynchronous reset (active low)
879 880 current_matrix_write <= '0';
880 881 current_matrix_wait_empty <= '1';
881 882 status_component_fifo_0 <= (OTHERS => '0');
882 883 status_component_fifo_1 <= (OTHERS => '0');
883 884 status_component_fifo_0_end <= '0';
884 885 status_component_fifo_1_end <= '0';
885 886 SM_correlation_done_reg1 <= '0';
886 887 SM_correlation_done_reg2 <= '0';
887 888 SM_correlation_done_reg3 <= '0';
888 889
889 890 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
890 891 SM_correlation_done_reg1 <= SM_correlation_done;
891 892 SM_correlation_done_reg2 <= SM_correlation_done_reg1;
892 893 SM_correlation_done_reg3 <= SM_correlation_done_reg2;
893 894 status_component_fifo_0_end <= '0';
894 895 status_component_fifo_1_end <= '0';
895 896 IF SM_correlation_begin = '1' THEN
896 897 IF current_matrix_write = '0' THEN
897 898 status_component_fifo_0 <= status_component(53 DOWNTO 4);
898 899 ELSE
899 900 status_component_fifo_1 <= status_component(53 DOWNTO 4);
900 901 END IF;
901 902 END IF;
902 903
903 904 IF SM_correlation_done_reg3 = '1' THEN
904 905 IF current_matrix_write = '0' THEN
905 906 status_component_fifo_0_end <= '1';
906 907 ELSE
907 908 status_component_fifo_1_end <= '1';
908 909 END IF;
909 910 current_matrix_wait_empty <= '1';
910 911 current_matrix_write <= NOT current_matrix_write;
911 912 END IF;
912 913
913 914 IF current_matrix_wait_empty <= '1' THEN
914 915 IF current_matrix_write = '0' THEN
915 916 current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(0);
916 917 ELSE
917 918 current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(1);
918 919 END IF;
919 920 END IF;
920 921
921 922 END IF;
922 923 END PROCESS;
923 924
924 925 MEM_OUT_SM_Full_s <= '1' WHEN SM_correlation_done = '1' ELSE
925 926 '1' WHEN SM_correlation_done_reg1 = '1' ELSE
926 927 '1' WHEN SM_correlation_done_reg2 = '1' ELSE
927 928 '1' WHEN SM_correlation_done_reg3 = '1' ELSE
928 929 '1' WHEN current_matrix_wait_empty = '1' ELSE
929 930 MEM_OUT_SM_Full(0) WHEN current_matrix_write = '0' ELSE
930 931 MEM_OUT_SM_Full(1);
931 932
932 933 MEM_OUT_SM_Write(0) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '0' ELSE '1';
933 934 MEM_OUT_SM_Write(1) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '1' ELSE '1';
934 935
935 936 MEM_OUT_SM_Data_in <= MEM_OUT_SM_Data_in_s & MEM_OUT_SM_Data_in_s;
936 937 -----------------------------------------------------------------------------
937 938
938 939 --Mem_Out_SpectralMatrix : lppFIFOxN
939 940 -- GENERIC MAP (
940 941 -- tech => 0,
941 942 -- Mem_use => Mem_use,
942 943 -- Data_sz => 32,
943 944 -- Addr_sz => 8,
944 945 -- FifoCnt => 2)
945 946 -- PORT MAP (
946 947 -- clk => clk,
947 948 -- rstn => rstn,
948 949
949 950 -- ReUse => (OTHERS => '0'),
950 951 -- run => (OTHERS => '1'),
951 952
952 953 -- wen => MEM_OUT_SM_Write,
953 954 -- wdata => MEM_OUT_SM_Data_in,
954 955
955 956 -- ren => MEM_OUT_SM_Read,
956 957 -- rdata => MEM_OUT_SM_Data_out,
957 958
958 959 -- full => MEM_OUT_SM_Full,
959 960 -- empty => MEM_OUT_SM_Empty,
960 961 -- almost_full => OPEN);
961 962
962 963
963 964 all_Mem_Out_SpectralMatrix: FOR I IN 1 DOWNTO 0 GENERATE
964 965 Mem_Out_SpectralMatrix_I: lpp_fifo
965 966 GENERIC MAP (
966 967 tech => 0,
967 968 Mem_use => Mem_use,
968 969 EMPTY_THRESHOLD_LIMIT => 15,
969 970 FULL_THRESHOLD_LIMIT => 1,
970 971 DataSz => 32,
971 972 AddrSz => 8)
972 973 PORT MAP (
973 974 clk => clk,
974 975 rstn => rstn,
975 976 reUse => '0',
976 977 run => run,
977 978
978 979 ren => MEM_OUT_SM_Read(I),
979 980 rdata => MEM_OUT_SM_Data_out(32*(I+1)-1 DOWNTO 32*i),
980 981
981 982 wen => MEM_OUT_SM_Write(I),
982 983 wdata => MEM_OUT_SM_Data_in(32*(I+1)-1 DOWNTO 32*i),
983 984
984 985 empty => MEM_OUT_SM_Empty(I),
985 986 full => MEM_OUT_SM_Full(I),
986 987 full_almost => OPEN,
987 988 empty_threshold => MEM_OUT_SM_Empty_Threshold(I),
988 989
989 990 full_threshold => OPEN);
990 991
991 992 END GENERATE all_Mem_Out_SpectralMatrix;
992 993
993 994 -----------------------------------------------------------------------------
994 995 -- MEM_OUT_SM_Read <= "00";
995 996 PROCESS (clk, rstn)
996 997 BEGIN
997 998 IF rstn = '0' THEN
998 999 fifo_0_ready <= '0';
999 1000 fifo_1_ready <= '0';
1000 1001 fifo_ongoing <= '0';
1002 fifo_ongoing_reg <= '0';
1001 1003 ELSIF clk'EVENT AND clk = '1' THEN
1004 fifo_ongoing_reg <= fifo_ongoing;
1002 1005 IF fifo_0_ready = '1' AND MEM_OUT_SM_Empty(0) = '1' THEN
1003 1006 fifo_ongoing <= '1';
1004 1007 fifo_0_ready <= '0';
1005 1008 ELSIF status_component_fifo_0_end = '1' THEN
1006 1009 fifo_0_ready <= '1';
1007 1010 END IF;
1008 1011
1009 1012 IF fifo_1_ready = '1' AND MEM_OUT_SM_Empty(1) = '1' THEN
1010 1013 fifo_ongoing <= '0';
1011 1014 fifo_1_ready <= '0';
1012 1015 ELSIF status_component_fifo_1_end = '1' THEN
1013 1016 fifo_1_ready <= '1';
1014 1017 END IF;
1015 1018
1016 1019 END IF;
1017 1020 END PROCESS;
1018 1021
1019 1022 MEM_OUT_SM_Read(0) <= '1' WHEN fifo_ongoing = '1' ELSE
1020 1023 '1' WHEN fifo_0_ready = '0' ELSE
1021 1024 FSM_DMA_fifo_ren;
1022 1025
1023 1026 MEM_OUT_SM_Read(1) <= '1' WHEN fifo_ongoing = '0' ELSE
1024 1027 '1' WHEN fifo_1_ready = '0' ELSE
1025 1028 FSM_DMA_fifo_ren;
1026 1029
1027 1030 FSM_DMA_fifo_empty <= MEM_OUT_SM_Empty(0) WHEN fifo_ongoing = '0' AND fifo_0_ready = '1' ELSE
1028 1031 MEM_OUT_SM_Empty(1) WHEN fifo_ongoing = '1' AND fifo_1_ready = '1' ELSE
1029 1032 '1';
1030 1033
1031 1034 FSM_DMA_fifo_status <= status_component_fifo_0 WHEN fifo_ongoing = '0' ELSE
1032 1035 status_component_fifo_1;
1033 1036
1034 FSM_DMA_fifo_data <= MEM_OUT_SM_Data_out(31 DOWNTO 0) WHEN fifo_ongoing = '0' ELSE
1037 FSM_DMA_fifo_data <= MEM_OUT_SM_Data_out(31 DOWNTO 0) WHEN fifo_ongoing_reg = '0' ELSE
1035 1038 MEM_OUT_SM_Data_out(63 DOWNTO 32);
1036 1039
1037 1040
1038 1041 FSM_DMA_fifo_empty_threshold <= MEM_OUT_SM_Empty_Threshold(0) WHEN fifo_ongoing = '0' AND fifo_0_ready = '1' ELSE
1039 1042 MEM_OUT_SM_Empty_Threshold(1) WHEN fifo_ongoing = '1' AND fifo_1_ready = '1' ELSE
1040 1043 '1';
1041 1044
1042 1045 -----------------------------------------------------------------------------
1043 1046 -- fifo_matrix_type => FSM_DMA_fifo_status(5 DOWNTO 4), --IN
1044 1047 -- fifo_matrix_component => FSM_DMA_fifo_status(3 DOWNTO 0), --IN
1045 1048 -- fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6), --IN
1046 1049 -- fifo_data => FSM_DMA_fifo_data, --IN
1047 1050 -- fifo_empty => FSM_DMA_fifo_empty, --IN
1048 1051 -- fifo_empty_threshold => FSM_DMA_fifo_empty_threshold, --IN
1049 1052 -- fifo_ren => FSM_DMA_fifo_ren, --OUT
1050 1053
1051 1054
1052 1055 lpp_lfr_ms_fsmdma_1: lpp_lfr_ms_fsmdma
1053 1056 PORT MAP (
1054 1057 clk => clk,
1055 1058 rstn => rstn,
1056 1059 run => run,
1057 1060
1058 1061 fifo_matrix_type => FSM_DMA_fifo_status(5 DOWNTO 4),
1059 1062 fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6),
1060 1063 fifo_data => FSM_DMA_fifo_data,
1061 1064 fifo_empty => FSM_DMA_fifo_empty,
1062 1065 fifo_empty_threshold => FSM_DMA_fifo_empty_threshold,
1063 1066 fifo_ren => FSM_DMA_fifo_ren,
1064 1067
1065 1068 dma_fifo_valid_burst => dma_fifo_burst_valid,
1066 1069 dma_fifo_data => dma_fifo_data,
1067 1070 dma_fifo_ren => dma_fifo_ren,
1068 1071 dma_buffer_new => dma_buffer_new,
1069 1072 dma_buffer_addr => dma_buffer_addr,
1070 1073 dma_buffer_length => dma_buffer_length,
1071 1074 dma_buffer_full => dma_buffer_full,
1072 1075 dma_buffer_full_err => dma_buffer_full_err,
1073 1076
1074 1077 status_ready_matrix_f0 => status_ready_matrix_f0,
1075 1078 status_ready_matrix_f1 => status_ready_matrix_f1,
1076 1079 status_ready_matrix_f2 => status_ready_matrix_f2,
1077 1080 addr_matrix_f0 => addr_matrix_f0,
1078 1081 addr_matrix_f1 => addr_matrix_f1,
1079 1082 addr_matrix_f2 => addr_matrix_f2,
1080 1083 length_matrix_f0 => length_matrix_f0,
1081 1084 length_matrix_f1 => length_matrix_f1,
1082 1085 length_matrix_f2 => length_matrix_f2,
1083 1086 ready_matrix_f0 => ready_matrix_f0,
1084 1087 ready_matrix_f1 => ready_matrix_f1,
1085 1088 ready_matrix_f2 => ready_matrix_f2,
1086 1089 matrix_time_f0 => matrix_time_f0,
1087 1090 matrix_time_f1 => matrix_time_f1,
1088 1091 matrix_time_f2 => matrix_time_f2,
1089 1092 error_buffer_full => error_buffer_full);
1090 1093
1091 1094
1092 1095
1093 1096
1094 1097
1095 1098 --dma_fifo_burst_valid: OUT STD_LOGIC; --TODO
1096 1099 --dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --TODO
1097 1100 --dma_fifo_ren : IN STD_LOGIC; --TODO
1098 1101 --dma_buffer_new : OUT STD_LOGIC; --TODO
1099 1102 --dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --TODO
1100 1103 --dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); --TODO
1101 1104 --dma_buffer_full : IN STD_LOGIC; --TODO
1102 1105 --dma_buffer_full_err : IN STD_LOGIC; --TODO
1103 1106
1104 1107 ---- Reg out
1105 1108 --ready_matrix_f0 : OUT STD_LOGIC; -- TODO
1106 1109 --ready_matrix_f1 : OUT STD_LOGIC; -- TODO
1107 1110 --ready_matrix_f2 : OUT STD_LOGIC; -- TODO
1108 1111 --error_bad_component_error : OUT STD_LOGIC; -- TODO
1109 1112 --error_buffer_full : OUT STD_LOGIC; -- TODO
1110 1113
1111 1114 ---- Reg In
1112 1115 --status_ready_matrix_f0 : IN STD_LOGIC; -- TODO
1113 1116 --status_ready_matrix_f1 : IN STD_LOGIC; -- TODO
1114 1117 --status_ready_matrix_f2 : IN STD_LOGIC; -- TODO
1115 1118
1116 1119 --addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
1117 1120 --addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
1118 1121 --addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
1119 1122
1120 1123 --matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
1121 1124 --matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
1122 1125 --matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) -- TODO
1123 1126 -----------------------------------------------------------------------------
1124 1127
1125 1128 -----------------------------------------------------------------------------
1126 1129 --lpp_lfr_ms_fsmdma_1 : lpp_lfr_ms_fsmdma
1127 1130 -- PORT MAP (
1128 1131 -- HCLK => clk,
1129 1132 -- HRESETn => rstn,
1130 1133
1131 1134 -- fifo_matrix_type => FSM_DMA_fifo_status(5 DOWNTO 4),
1132 1135 -- fifo_matrix_component => FSM_DMA_fifo_status(3 DOWNTO 0),
1133 1136 -- fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6),
1134 1137 -- fifo_data => FSM_DMA_fifo_data,
1135 1138 -- fifo_empty => FSM_DMA_fifo_empty,
1136 1139 -- fifo_ren => FSM_DMA_fifo_ren,
1137 1140
1138 1141 -- dma_addr => dma_addr,
1139 1142 -- dma_data => dma_data,
1140 1143 -- dma_valid => dma_valid,
1141 1144 -- dma_valid_burst => dma_valid_burst,
1142 1145 -- dma_ren => dma_ren,
1143 1146 -- dma_done => dma_done,
1144 1147
1145 1148 -- ready_matrix_f0 => ready_matrix_f0,
1146 1149 -- ready_matrix_f1 => ready_matrix_f1,
1147 1150 -- ready_matrix_f2 => ready_matrix_f2,
1148 1151
1149 1152 -- error_bad_component_error => error_bad_component_error,
1150 1153 -- error_buffer_full => error_buffer_full,
1151 1154
1152 1155 -- debug_reg => debug_reg,
1153 1156 -- status_ready_matrix_f0 => status_ready_matrix_f0,
1154 1157 -- status_ready_matrix_f1 => status_ready_matrix_f1,
1155 1158 -- status_ready_matrix_f2 => status_ready_matrix_f2,
1156 1159
1157 1160 -- config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
1158 1161 -- config_active_interruption_onError => config_active_interruption_onError,
1159 1162
1160 1163 -- addr_matrix_f0 => addr_matrix_f0,
1161 1164 -- addr_matrix_f1 => addr_matrix_f1,
1162 1165 -- addr_matrix_f2 => addr_matrix_f2,
1163 1166
1164 1167 -- matrix_time_f0 => matrix_time_f0,
1165 1168 -- matrix_time_f1 => matrix_time_f1,
1166 1169 -- matrix_time_f2 => matrix_time_f2
1167 1170 -- );
1168 1171 -----------------------------------------------------------------------------
1169 1172
1170 1173
1171 1174
1172 1175
1173 1176
1174 1177
1175 1178 -----------------------------------------------------------------------------
1176 1179 -- TIME MANAGMENT
1177 1180 -----------------------------------------------------------------------------
1178 1181 all_time <= sample_f2_time & sample_f1_time & sample_f0_time & sample_f0_time;
1179 1182 --all_time <= coarse_time & fine_time;
1180 1183 --
1181 1184 f_empty(0) <= '1' WHEN sample_f0_A_empty = "11111" ELSE '0';
1182 1185 f_empty(1) <= '1' WHEN sample_f0_B_empty = "11111" ELSE '0';
1183 1186 f_empty(2) <= '1' WHEN sample_f1_empty = "11111" ELSE '0';
1184 1187 f_empty(3) <= '1' WHEN sample_f2_empty = "11111" ELSE '0';
1185 1188
1186 1189 all_time_reg: FOR I IN 0 TO 3 GENERATE
1187 1190
1188 1191 PROCESS (clk, rstn)
1189 1192 BEGIN
1190 1193 IF rstn = '0' THEN
1191 1194 f_empty_reg(I) <= '1';
1192 1195 ELSIF clk'event AND clk = '1' THEN
1193 1196 f_empty_reg(I) <= f_empty(I);
1194 1197 END IF;
1195 1198 END PROCESS;
1196 1199
1197 1200 time_update_f(I) <= '1' WHEN f_empty(I) = '0' AND f_empty_reg(I) = '1' ELSE '0';
1198 1201
1199 1202 s_m_t_m_f0_A : spectral_matrix_time_managment
1200 1203 PORT MAP (
1201 1204 clk => clk,
1202 1205 rstn => rstn,
1203 1206 time_in => all_time((I+1)*48-1 DOWNTO I*48),
1204 1207 update_1 => time_update_f(I),
1205 1208 time_out => time_reg_f((I+1)*48-1 DOWNTO I*48)
1206 1209 );
1207 1210
1208 1211 END GENERATE all_time_reg;
1209 1212
1210 1213 time_reg_f0_A <= time_reg_f((0+1)*48-1 DOWNTO 0*48);
1211 1214 time_reg_f0_B <= time_reg_f((1+1)*48-1 DOWNTO 1*48);
1212 1215 time_reg_f1 <= time_reg_f((2+1)*48-1 DOWNTO 2*48);
1213 1216 time_reg_f2 <= time_reg_f((3+1)*48-1 DOWNTO 3*48);
1214 1217
1215 1218 -----------------------------------------------------------------------------
1216 1219
1217 1220 END Behavioral;
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