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MS (first version, ok in simulation but whitout data integrity)
pellion -
r360:8846562be00d JC
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@@ -1,129 +1,148
1 LIBRARY IEEE;
1 LIBRARY IEEE;
2 USE IEEE.std_logic_1164.ALL;
2 USE IEEE.std_logic_1164.ALL;
3 USE IEEE.numeric_std.ALL;
3 USE IEEE.numeric_std.ALL;
4
4
5 ENTITY MS_control IS
5 ENTITY MS_control IS
6 PORT (
6 PORT (
7 clk : IN STD_LOGIC;
7 clk : IN STD_LOGIC;
8 rstn : IN STD_LOGIC;
8 rstn : IN STD_LOGIC;
9
9 -- IN
10 current_status_ms : IN STD_LOGIC_VECTOR(49 DOWNTO 0); -- TIME(47 .. 0) & Matrix_type(1..0)
11
10 -- IN
12 -- IN
11 fifo_in_lock : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
13 fifo_in_lock : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
12 fifo_in_data : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
14 fifo_in_data : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
13 fifo_in_full : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
15 fifo_in_full : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
14 fifo_in_empty : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
16 fifo_in_empty : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
15 fifo_in_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
17 fifo_in_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
16 fifo_in_reuse : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
18 fifo_in_reuse : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
17 -- OUT
19 -- OUT
18 fifo_out_data : OUT STD_LOGIC_VECTOR(32*2-1 DOWNTO 0);
20 fifo_out_data : OUT STD_LOGIC_VECTOR(32*2-1 DOWNTO 0);
19 fifo_out_ren : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
21 fifo_out_ren : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
20 fifo_out_empty : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
22 fifo_out_empty : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
21 -- OUT
23 -- OUT
24 current_status_component : OUT STD_LOGIC_VECTOR(53 DOWNTO 0); -- TIME(47 .. 0) &
25 -- Matrix_type (1..0)
26 -- ComponentType (3..0)
22 correlation_start : OUT STD_LOGIC;
27 correlation_start : OUT STD_LOGIC;
23 correlation_auto : OUT STD_LOGIC; -- 1 => auto correlation / 0 => inter correlation
28 correlation_auto : OUT STD_LOGIC; -- 1 => auto correlation / 0 => inter correlation
24 correlation_done : IN STD_LOGIC
29 correlation_done : IN STD_LOGIC
25 );
30 );
26 END MS_control;
31 END MS_control;
27
32
28 ARCHITECTURE beh OF MS_control IS
33 ARCHITECTURE beh OF MS_control IS
29
34
30 TYPE fsm_control_MS IS (WAIT_DATA, CORRELATION_ONGOING);
35 TYPE fsm_control_MS IS (WAIT_DATA, CORRELATION_ONGOING);
31 SIGNAL state : fsm_control_MS;
36 SIGNAL state : fsm_control_MS;
32
37
33 SUBTYPE fifo_pointer IS RANGE 0 TO 4;
38 SUBTYPE fifo_pointer IS INTEGER RANGE 0 TO 4;
34 SIGNAL fifo_1 : fifo_pointer;
39 SIGNAL fifo_1 : fifo_pointer;
35 SIGNAL fifo_2 : fifo_pointer;
40 SIGNAL fifo_2 : fifo_pointer;
36
41
37 SIGNAL fifo_in_lock_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
42 SIGNAL fifo_in_lock_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
38 SIGNAL fifo_in_reuse_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
43 SIGNAL fifo_in_reuse_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
39
44
40 BEGIN -- beh
45 BEGIN -- beh
41
46
42 fifo_in_lock <= fifo_in_lock_s;
47 fifo_in_lock <= fifo_in_lock_s;
43 fifo_in_reuse <= fifo_in_reuse_s;
48 fifo_in_reuse <= fifo_in_reuse_s;
44
49
45 PROCESS (clk, rstn)
50 PROCESS (clk, rstn)
46 BEGIN
51 BEGIN
47 IF rstn = '0' THEN
52 IF rstn = '0' THEN
48 state <= WAIT_DATA;
53 state <= WAIT_DATA;
49 fifo_1 <= 0;
54 fifo_1 <= 0;
50 fifo_2 <= 0;
55 fifo_2 <= 0;
51 fifo_in_lock_s <= (OTHERS => '0');
56 fifo_in_lock_s <= (OTHERS => '0');
52 fifo_in_reuse_s <= (OTHERS => '0');
57 fifo_in_reuse_s <= (OTHERS => '0');
53 correlation_start <= '0';
58 correlation_start <= '0';
54 correlation_auto <= '0';
59 correlation_auto <= '0';
60 current_status_component <= (OTHERS => '0');
55 ELSIF clk'event AND clk = '1' THEN
61 ELSIF clk'event AND clk = '1' THEN
56 CASE state IS
62 CASE state IS
63
57 WHEN WAIT_DATA =>
64 WHEN WAIT_DATA =>
58 fifo_in_reuse_s <= (OTHERS => '0');
65 fifo_in_reuse_s <= (OTHERS => '0');
59 IF fifo_in_full[fifo_1] = '1' AND fifo_in_full[fifo_2] = '1' THEN
66 IF fifo_in_full(fifo_1) = '1' AND fifo_in_full(fifo_2) = '1' THEN
60 fifo_in_lock_s(fifo_1) <= '1';
67 fifo_in_lock_s(fifo_1) <= '1';
61 fifo_in_lock_s(fifo_2) <= '1';
68 fifo_in_lock_s(fifo_2) <= '1';
62 correlation_start <= '1';
69 correlation_start <= '1';
63 IF fifo_1 = fifo_2 THEN
70 IF fifo_1 = fifo_2 THEN
64 correlation_auto <= '1';
71 correlation_auto <= '1';
65 END IF;
72 END IF;
66 state <= CORRELATION_ONGOING;
73 state <= CORRELATION_ONGOING;
74 IF fifo_1 = 0 AND fifo_2 = 0 THEN
75 current_status_component(53 DOWNTO 4) <= current_status_ms;
76 END IF;
77 CASE fifo_1 IS
78 WHEN 0 => current_status_component(3 DOWNTO 0) <= STD_LOGIC_VECTOR(to_unsigned( fifo_2,4));
79 WHEN 1 => current_status_component(3 DOWNTO 0) <= STD_LOGIC_VECTOR(to_unsigned(4+fifo_2,4));
80 WHEN 2 => current_status_component(3 DOWNTO 0) <= STD_LOGIC_VECTOR(to_unsigned(7+fifo_2,4));
81 WHEN 3 => current_status_component(3 DOWNTO 0) <= STD_LOGIC_VECTOR(to_unsigned(9+fifo_2,4));
82 WHEN 4 => current_status_component(3 DOWNTO 0) <= STD_LOGIC_VECTOR(to_unsigned(14 ,4));
83 WHEN OTHERS => NULL;
84 END CASE;
85 --current_status_component(3 DOWNTO 0) <= STD_LOGIC_VECTOR(to_unsigned(fifo_1*5+fifo_2,4));
67 END IF;
86 END IF;
68
87
69 WHEN CORRELATION_ONGOING =>
88 WHEN CORRELATION_ONGOING =>
70 correlation_start <= '0';
89 correlation_start <= '0';
71 correlation_auto <= '0';
90 correlation_auto <= '0';
72 IF correlation_done = '1' THEN
91 IF correlation_done = '1' THEN
73 state <= WAIT_DATA;
92 state <= WAIT_DATA;
74 IF fifo_2 = 4 THEN
93 IF fifo_2 = 4 THEN
75 fifo_in_lock_s(fifo_1) <= '0';
94 fifo_in_lock_s(fifo_1) <= '0';
76 IF fifo_1 = 4 THEN
95 IF fifo_1 = 4 THEN
77 fifo_1 <= 0;
96 fifo_1 <= 0;
78 fifo_2 <= 0;
97 fifo_2 <= 0;
79 ELSE
98 ELSE
80 fifo_in_reuse_s(fifo_2) <= '1';
99 fifo_in_reuse_s(fifo_2) <= '1';
81 fifo_1 <= fifo_1 + 1;
100 fifo_1 <= fifo_1 + 1;
82 fifo_2 <= fifo_1 + 1;
101 fifo_2 <= fifo_1 + 1;
83 END IF;
102 END IF;
84 ELSE
103 ELSE
85 fifo_in_reuse_s(fifo_2) <= '1';
104 fifo_in_reuse_s(fifo_2) <= '1';
86 fifo_in_reuse_s(fifo_1) <= '1';
105 fifo_in_reuse_s(fifo_1) <= '1';
87 fifo_2 <= fifo_2 + 1;
106 fifo_2 <= fifo_2 + 1;
88 END IF;
107 END IF;
89 END IF;
108 END IF;
90
109
91 WHEN OTHERS => NULL;
110 WHEN OTHERS => NULL;
92 END CASE;
111 END CASE;
93 END IF;
112 END IF;
94 END PROCESS;
113 END PROCESS;
95
114
96
115
97 fifo_out_data(31 DOWNTO 0) <= fifo_in_data(31*1-1 DOWNTO 32*0) WHEN fifo_1 = 0 ELSE
116 fifo_out_data(31 DOWNTO 0) <= fifo_in_data(32*1-1 DOWNTO 32*0) WHEN fifo_1 = 0 ELSE
98 fifo_in_data(32*2-1 DOWNTO 32*1) WHEN fifo_1 = 1 ELSE
117 fifo_in_data(32*2-1 DOWNTO 32*1) WHEN fifo_1 = 1 ELSE
99 fifo_in_data(32*3-1 DOWNTO 32*2) WHEN fifo_1 = 2 ELSE
118 fifo_in_data(32*3-1 DOWNTO 32*2) WHEN fifo_1 = 2 ELSE
100 fifo_in_data(32*4-1 DOWNTO 32*3) WHEN fifo_1 = 3 ELSE
119 fifo_in_data(32*4-1 DOWNTO 32*3) WHEN fifo_1 = 3 ELSE
101 fifo_in_data(32*5-1 DOWNTO 32*4);-- WHEN fifo_1 = 4
120 fifo_in_data(32*5-1 DOWNTO 32*4);-- WHEN fifo_1 = 4
102
121
103
122
104 fifo_out_data(63 DOWNTO 32) <= fifo_in_data(31*1-1 DOWNTO 32*0) WHEN fifo_2 = 0 ELSE
123 fifo_out_data(63 DOWNTO 32) <= fifo_in_data(32*1-1 DOWNTO 32*0) WHEN fifo_2 = 0 ELSE
105 fifo_in_data(32*2-1 DOWNTO 32*1) WHEN fifo_2 = 1 ELSE
124 fifo_in_data(32*2-1 DOWNTO 32*1) WHEN fifo_2 = 1 ELSE
106 fifo_in_data(32*3-1 DOWNTO 32*2) WHEN fifo_2 = 2 ELSE
125 fifo_in_data(32*3-1 DOWNTO 32*2) WHEN fifo_2 = 2 ELSE
107 fifo_in_data(32*4-1 DOWNTO 32*3) WHEN fifo_2 = 3 ELSE
126 fifo_in_data(32*4-1 DOWNTO 32*3) WHEN fifo_2 = 3 ELSE
108 fifo_in_data(32*5-1 DOWNTO 32*4);-- WHEN fifo_2 = 4
127 fifo_in_data(32*5-1 DOWNTO 32*4);-- WHEN fifo_2 = 4
109
128
110 fifo_out_empty(0) <= fifo_in_empty(0) WHEN fifo_1 = 0 ELSE
129 fifo_out_empty(0) <= fifo_in_empty(0) WHEN fifo_1 = 0 ELSE
111 fifo_in_empty(1) WHEN fifo_1 = 1 ELSE
130 fifo_in_empty(1) WHEN fifo_1 = 1 ELSE
112 fifo_in_empty(2) WHEN fifo_1 = 2 ELSE
131 fifo_in_empty(2) WHEN fifo_1 = 2 ELSE
113 fifo_in_empty(3) WHEN fifo_1 = 3 ELSE
132 fifo_in_empty(3) WHEN fifo_1 = 3 ELSE
114 fifo_in_empty(4);
133 fifo_in_empty(4);
115
134
116 fifo_out_empty(1) <= fifo_in_empty(0) WHEN fifo_2 = 0 ELSE
135 fifo_out_empty(1) <= fifo_in_empty(0) WHEN fifo_2 = 0 ELSE
117 fifo_in_empty(1) WHEN fifo_2 = 1 ELSE
136 fifo_in_empty(1) WHEN fifo_2 = 1 ELSE
118 fifo_in_empty(2) WHEN fifo_2 = 2 ELSE
137 fifo_in_empty(2) WHEN fifo_2 = 2 ELSE
119 fifo_in_empty(3) WHEN fifo_2 = 3 ELSE
138 fifo_in_empty(3) WHEN fifo_2 = 3 ELSE
120 fifo_in_empty(4);
139 fifo_in_empty(4);
121
140
122
141
123 all_fifo: FOR I IN 0 TO 4 GENERATE
142 all_fifo: FOR I IN 0 TO 4 GENERATE
124 fifo_in_ren(I) <= fifo_out_ren(I) WHEN fifo_1 = I ELSE
143 fifo_in_ren(I) <= fifo_out_ren(0) WHEN fifo_1 = I ELSE
125 fifo_out_ren(I) WHEN fifo_2 = I ELSE
144 fifo_out_ren(1) WHEN fifo_2 = I ELSE
126 '1';
145 '1';
127 END GENERATE all_fifo;
146 END GENERATE all_fifo;
128
147
129 END beh;
148 END beh;
Show file before | Show file after | Hide comments
@@ -1,430 +1,432
1 VHDLIB=../..
1 VHDLIB=../..
2 SCRIPTSDIR=$(VHDLIB)/scripts/
2 SCRIPTSDIR=$(VHDLIB)/scripts/
3
3
4 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
4 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
5 TOP=TB
5 TOP=TB
6
6
7 CMD_VLIB=vlib
7 CMD_VLIB=vlib
8 CMD_VMAP=vmap
8 CMD_VMAP=vmap
9 CMD_VCOM=@vcom -quiet -93 -work
9 CMD_VCOM=@vcom -quiet -93 -work
10
10
11 ################## project specific targets ##########################
11 ################## project specific targets ##########################
12
12
13 all:
13 all:
14 @echo "make vsim"
14 @echo "make vsim"
15 @echo "make libs"
15 @echo "make libs"
16 @echo "make clean"
16 @echo "make clean"
17 @echo "make vcom_grlib vcom_lpp vcom_tb"
17 @echo "make vcom_grlib vcom_lpp vcom_tb"
18
18
19 run:
19 run:
20 @vsim work.TB -do run.do
20 @vsim work.TB -do run.do
21 # @vsim work.TB
21 # @vsim work.TB
22 # @vsim lpp.lpp_lfr_ms
22 # @vsim lpp.lpp_lfr_ms
23
23
24 vsim: libs vcom run
24 vsim: libs vcom run
25
25
26 libs:
26 libs:
27 @$(CMD_VLIB) modelsim
27 @$(CMD_VLIB) modelsim
28 @$(CMD_VMAP) modelsim modelsim
28 @$(CMD_VMAP) modelsim modelsim
29 @$(CMD_VLIB) modelsim/techmap
29 @$(CMD_VLIB) modelsim/techmap
30 @$(CMD_VMAP) techmap modelsim/techmap
30 @$(CMD_VMAP) techmap modelsim/techmap
31 @$(CMD_VLIB) modelsim/grlib
31 @$(CMD_VLIB) modelsim/grlib
32 @$(CMD_VMAP) grlib modelsim/grlib
32 @$(CMD_VMAP) grlib modelsim/grlib
33 @$(CMD_VLIB) modelsim/gaisler
33 @$(CMD_VLIB) modelsim/gaisler
34 @$(CMD_VMAP) gaisler modelsim/gaisler
34 @$(CMD_VMAP) gaisler modelsim/gaisler
35 @$(CMD_VLIB) modelsim/work
35 @$(CMD_VLIB) modelsim/work
36 @$(CMD_VMAP) work modelsim/work
36 @$(CMD_VMAP) work modelsim/work
37 @$(CMD_VLIB) modelsim/lpp
37 @$(CMD_VLIB) modelsim/lpp
38 @$(CMD_VMAP) lpp modelsim/lpp
38 @$(CMD_VMAP) lpp modelsim/lpp
39 @echo "libs done"
39 @echo "libs done"
40
40
41
41
42 clean:
42 clean:
43 @rm -Rf modelsim
43 @rm -Rf modelsim
44 @rm -Rf modelsim.ini
44 @rm -Rf modelsim.ini
45 @rm -Rf *~
45 @rm -Rf *~
46 @rm -Rf transcript
46 @rm -Rf transcript
47 @rm -Rf wlft*
47 @rm -Rf wlft*
48 @rm -Rf *.wlf
48 @rm -Rf *.wlf
49 @rm -Rf vish_stacktrace.vstf
49 @rm -Rf vish_stacktrace.vstf
50 @rm -Rf libs.do
50 @rm -Rf libs.do
51
51
52 vcom: vcom_grlib vcom_techmap vcom_gaisler vcom_lpp vcom_tb
52 vcom: vcom_grlib vcom_techmap vcom_gaisler vcom_lpp vcom_tb
53
53
54
54
55 vcom_tb:
55 vcom_tb:
56 $(CMD_VCOM) lpp lpp_memory.vhd
56 $(CMD_VCOM) lpp lpp_memory.vhd
57 $(CMD_VCOM) lpp lppFIFOxN.vhd
57 $(CMD_VCOM) lpp lppFIFOxN.vhd
58 $(CMD_VCOM) lpp lpp_FIFO.vhd
58 $(CMD_VCOM) lpp lpp_FIFO.vhd
59 $(CMD_VCOM) lpp spectral_matrix_package.vhd
59 $(CMD_VCOM) lpp spectral_matrix_package.vhd
60 $(CMD_VCOM) lpp spectral_matrix_switch_f0.vhd
60 $(CMD_VCOM) lpp spectral_matrix_switch_f0.vhd
61 $(CMD_VCOM) lpp spectral_matrix_time_managment.vhd
61 $(CMD_VCOM) lpp spectral_matrix_time_managment.vhd
62 $(CMD_VCOM) lpp MS_control.vhd
63 $(CMD_VCOM) lpp MS_calculation.vhd
62 $(CMD_VCOM) lpp lpp_lfr_ms.vhd
64 $(CMD_VCOM) lpp lpp_lfr_ms.vhd
63 $(CMD_VCOM) work TB.vhd
65 $(CMD_VCOM) work TB.vhd
64 @echo "vcom done"
66 @echo "vcom done"
65
67
66 vcom_grlib:
68 vcom_grlib:
67 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/version.vhd
69 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/version.vhd
68 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/config_types.vhd
70 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/config_types.vhd
69 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/config.vhd
71 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/config.vhd
70 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/stdlib.vhd
72 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/stdlib.vhd
71 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/stdio.vhd
73 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/stdio.vhd
72 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/testlib.vhd
74 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/testlib.vhd
73 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/ftlib/mtie_ftlib.vhd
75 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/ftlib/mtie_ftlib.vhd
74 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/util/util.vhd
76 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/util/util.vhd
75 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/sparc/sparc.vhd
77 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/sparc/sparc.vhd
76 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/sparc/sparc_disas.vhd
78 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/sparc/sparc_disas.vhd
77 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/sparc/cpu_disas.vhd
79 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/sparc/cpu_disas.vhd
78 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/modgen/multlib.vhd
80 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/modgen/multlib.vhd
79 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/modgen/leaves.vhd
81 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/modgen/leaves.vhd
80 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/amba.vhd
82 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/amba.vhd
81 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/devices.vhd
83 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/devices.vhd
82 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/defmst.vhd
84 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/defmst.vhd
83 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/apbctrl.vhd
85 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/apbctrl.vhd
84 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ahbctrl.vhd
86 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ahbctrl.vhd
85 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/dma2ahb_pkg.vhd
87 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/dma2ahb_pkg.vhd
86 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/dma2ahb.vhd
88 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/dma2ahb.vhd
87 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ahbmst.vhd
89 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ahbmst.vhd
88 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ahbmon.vhd
90 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ahbmon.vhd
89 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/apbmon.vhd
91 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/apbmon.vhd
90 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ambamon.vhd
92 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ambamon.vhd
91 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/dma2ahb_tp.vhd
93 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/dma2ahb_tp.vhd
92 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/amba_tp.vhd
94 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/amba_tp.vhd
93 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_pkg.vhd
95 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_pkg.vhd
94 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_mst_pkg.vhd
96 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_mst_pkg.vhd
95 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_slv_pkg.vhd
97 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_slv_pkg.vhd
96 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_util.vhd
98 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_util.vhd
97 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_mst.vhd
99 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_mst.vhd
98 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_slv.vhd
100 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_slv.vhd
99 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahbs.vhd
101 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahbs.vhd
100 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_ctrl.vhd
102 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_ctrl.vhd
101 @echo "vcom grlib done"
103 @echo "vcom grlib done"
102
104
103 vcom_gaisler:
105 vcom_gaisler:
104 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/arith/arith.vhd
106 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/arith/arith.vhd
105 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/arith/mul32.vhd
107 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/arith/mul32.vhd
106 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/arith/div32.vhd
108 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/arith/div32.vhd
107 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/memctrl.vhd
109 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/memctrl.vhd
108 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/sdctrl.vhd
110 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/sdctrl.vhd
109 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/sdctrl64.vhd
111 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/sdctrl64.vhd
110 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/sdmctrl.vhd
112 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/sdmctrl.vhd
111 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/srctrl.vhd
113 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/srctrl.vhd
112 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ssrctrl.vhd
114 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ssrctrl.vhd
113 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsrctrlc.vhd
115 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsrctrlc.vhd
114 # # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsrctrl.vhd
116 # # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsrctrl.vhd
115 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdctrl.vhd
117 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdctrl.vhd
116 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdmctrl.vhd
118 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdmctrl.vhd
117 # # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftmctrlc.vhd
119 # # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftmctrlc.vhd
118 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsrctrl8.vhd
120 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsrctrl8.vhd
119 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdmctrlx.vhd
121 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdmctrlx.vhd
120 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftmctrlcx.vhd
122 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftmctrlcx.vhd
121 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftmctrl.vhd
123 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftmctrl.vhd
122 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdctrl64.vhd
124 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdctrl64.vhd
123 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/grlfpu/mtie_grlfpu.vhd
125 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/grlfpu/mtie_grlfpu.vhd
124 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/grlfpc/mtie_grlfpc.vhd
126 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/grlfpc/mtie_grlfpc.vhd
125 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/grlfpcft/mtie_grlfpcft.vhd
127 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/grlfpcft/mtie_grlfpcft.vhd
126 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmuconf# ig.vhd
128 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmuconf# ig.vhd
127 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmuiface.vhd
129 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmuiface.vhd
128 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/libmmu.vhd
130 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/libmmu.vhd
129 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmutlbcam.vhd
131 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmutlbcam.vhd
130 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmulrue.vhd
132 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmulrue.vhd
131 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmulru.vhd
133 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmulru.vhd
132 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmutlb.vhd
134 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmutlb.vhd
133 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmutw.vhd
135 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmutw.vhd
134 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmu.vhd
136 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmu.vhd
135 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/leon3.vhd
137 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/leon3.vhd
136 # # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/libiu.vhd
138 # # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/libiu.vhd
137 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/libcache.vhd
139 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/libcache.vhd
138 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/tbufmem.vhd
140 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/tbufmem.vhd
139 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/dsu3x.vhd
141 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/dsu3x.vhd
140 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/dsu3.vhd
142 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/dsu3.vhd
141 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/dsu3_2x.vhd
143 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/dsu3_2x.vhd
142 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/clk2xsync.vhd
144 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/clk2xsync.vhd
143 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/clk2xqual.vhd
145 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/clk2xqual.vhd
144 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/grfpushwx.vhd
146 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/grfpushwx.vhd
145 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/libproc3.vhd
147 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/libproc3.vhd
146 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/cachemem.vhd
148 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/cachemem.vhd
147 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_icache.vhd
149 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_icache.vhd
148 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_dcache.vhd
150 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_dcache.vhd
149 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_acache.vhd
151 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_acache.vhd
150 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_cache.vhd
152 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_cache.vhd
151 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/iu3.vhd
153 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/iu3.vhd
152 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/grfpwx.vhd
154 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/grfpwx.vhd
153 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mfpwx.vhd
155 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mfpwx.vhd
154 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/grlfpwx.vhd
156 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/grlfpwx.vhd
155 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/proc3.vhd
157 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/proc3.vhd
156 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3s2x.vhd
158 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3s2x.vhd
157 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3s.vhd
159 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3s.vhd
158 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3cg.vhd
160 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3cg.vhd
159 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/grfpwxsh.vhd
161 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/grfpwxsh.vhd
160 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3sh.vhd
162 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3sh.vhd
161 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3ftv2/mtie_leon3ftv2.vhd
163 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3ftv2/mtie_leon3ftv2.vhd
162 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqmp2x.vhd
164 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqmp2x.vhd
163 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqmp.vhd
165 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqmp.vhd
164 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqamp.vhd
166 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqamp.vhd
165 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqamp2x.vhd
167 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqamp2x.vhd
166 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can.vhd
168 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can.vhd
167 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_mod.vhd
169 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_mod.vhd
168 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_oc.vhd
170 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_oc.vhd
169 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_mc.vhd
171 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_mc.vhd
170 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/canmux.vhd
172 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/canmux.vhd
171 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_rd.vhd
173 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_rd.vhd
172 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_oc_core.vhd
174 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_oc_core.vhd
173 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/grcan.vhd
175 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/grcan.vhd
174 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/misc.vhd
176 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/misc.vhd
175 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/rstgen.vhd
177 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/rstgen.vhd
176 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/gptimer.vhd
178 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/gptimer.vhd
177 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbram.vhd
179 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbram.vhd
178 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbdpram.vhd
180 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbdpram.vhd
179 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbtrace.vhd
181 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbtrace.vhd
180 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbtrace_mb.vhd
182 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbtrace_mb.vhd
181 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbtrace_mmb.vhd
183 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbtrace_mmb.vhd
182 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grgpio.vhd
184 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grgpio.vhd
183 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ftahbram.vhd
185 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ftahbram.vhd
184 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ftahbram2.vhd
186 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ftahbram2.vhd
185 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbstat.vhd
187 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbstat.vhd
186 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/logan.vhd
188 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/logan.vhd
187 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/apbps2.vhd
189 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/apbps2.vhd
188 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/charrom_package.vhd
190 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/charrom_package.vhd
189 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/charrom.vhd
191 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/charrom.vhd
190 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/apbvga.vhd
192 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/apbvga.vhd
191 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahb2ahb.vhd
193 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahb2ahb.vhd
192 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbbridge.vhd
194 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbbridge.vhd
193 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/svgactrl.vhd
195 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/svgactrl.vhd
194 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grfifo.vhd
196 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grfifo.vhd
195 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/gradcdac.vhd
197 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/gradcdac.vhd
196 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grsysmon.vhd
198 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grsysmon.vhd
197 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/gracectrl.vhd
199 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/gracectrl.vhd
198 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grgpreg.vhd
200 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grgpreg.vhd
199 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbmst2.vhd
201 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbmst2.vhd
200 ## $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/memscrub.vhd
202 ## $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/memscrub.vhd
201 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahb_mst_iface.vhd
203 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahb_mst_iface.vhd
202 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grgprbank.vhd
204 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grgprbank.vhd
203 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grclkgate.vhd
205 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grclkgate.vhd
204 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grclkgate2x.vhd
206 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grclkgate2x.vhd
205 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grtimer.vhd
207 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grtimer.vhd
206 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grpulse.vhd
208 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grpulse.vhd
207 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grversion.vhd
209 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grversion.vhd
208 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbfrom.vhd
210 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbfrom.vhd
209 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/ambatest/ahbtbp.vhd
211 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/ambatest/ahbtbp.vhd
210 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/ambatest/ahbtbm.vhd
212 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/ambatest/ahbtbm.vhd
211 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/net/net.vhd
213 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/net/net.vhd
212 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/uart.vhd
214 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/uart.vhd
213 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/libdcom.vhd
215 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/libdcom.vhd
214 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/apbuart.vhd
216 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/apbuart.vhd
215 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/dcom.vhd
217 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/dcom.vhd
216 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/dcom_uart.vhd
218 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/dcom_uart.vhd
217 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/ahbuart.vhd
219 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/ahbuart.vhd
218 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sim.vhd
220 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sim.vhd
219 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sram.vhd
221 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sram.vhd
220 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sramft.vhd
222 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sramft.vhd
221 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sram16.vhd
223 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sram16.vhd
222 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/phy.vhd
224 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/phy.vhd
223 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/ahbrep.vhd
225 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/ahbrep.vhd
224 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/delay_wire.vhd
226 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/delay_wire.vhd
225 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/pwm_check.vhd
227 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/pwm_check.vhd
226 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/ramback.vhd
228 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/ramback.vhd
227 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/zbtssram.vhd
229 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/zbtssram.vhd
228 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/slavecheck.vhd
230 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/slavecheck.vhd
229 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/jtag.vhd
231 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/jtag.vhd
230 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/libjtagcom.vhd
232 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/libjtagcom.vhd
231 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/jtagcom.vhd
233 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/jtagcom.vhd
232 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/ahbjtag.vhd
234 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/ahbjtag.vhd
233 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/ahbjtag_bsd.vhd
235 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/ahbjtag_bsd.vhd
234 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/bscanctrl.vhd
236 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/bscanctrl.vhd
235 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/bscanregs.vhd
237 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/bscanregs.vhd
236 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/bscanregsbd.vhd
238 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/bscanregsbd.vhd
237 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/jtagtst.vhd
239 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/jtagtst.vhd
238 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/ethernet_mac.vhd
240 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/ethernet_mac.vhd
239 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth.vhd
241 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth.vhd
240 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth_mb.vhd
242 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth_mb.vhd
241 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth_gbit.vhd
243 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth_gbit.vhd
242 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth_gbit_mb.vhd
244 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth_gbit_mb.vhd
243 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/grethm.vhd
245 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/grethm.vhd
244 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/rgmii.vhd
246 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/rgmii.vhd
245 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/spacewire.vhd
247 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/spacewire.vhd
246 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw.vhd
248 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw.vhd
247 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw2.vhd
249 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw2.vhd
248 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspwm.vhd
250 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspwm.vhd
249 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw2_phy.vhd
251 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw2_phy.vhd
250 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw_phy.vhd
252 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw_phy.vhd
251 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/gr1553b/gr1553b_pkg.vhd
253 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/gr1553b/gr1553b_pkg.vhd
252 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/gr1553b/gr1553b_pads.vhd
254 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/gr1553b/gr1553b_pads.vhd
253 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/gr1553b/simtrans1553.vhd
255 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/gr1553b/simtrans1553.vhd
254 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/nand/nandpkg.vhd
256 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/nand/nandpkg.vhd
255 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/nand/nandfctrlx.vhd
257 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/nand/nandfctrlx.vhd
256 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/nand/nandfctrl.vhd
258 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/nand/nandfctrl.vhd
257 @echo "vcom gaisler done"
259 @echo "vcom gaisler done"
258
260
259 vcom_techmap:
261 vcom_techmap:
260 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/gencomp/gencomp.vhd
262 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/gencomp/gencomp.vhd
261 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/gencomp/netcomp.vhd
263 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/gencomp/netcomp.vhd
262 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/memory_inferred.vhd
264 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/memory_inferred.vhd
263 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/tap_inferred.vhd
265 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/tap_inferred.vhd
264 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/ddr_inferred.vhd
266 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/ddr_inferred.vhd
265 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/mul_inferred.vhd
267 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/mul_inferred.vhd
266 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/ddr_phy_inferred.vhd
268 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/ddr_phy_inferred.vhd
267 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/ddrphy_datapath.vhd
269 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/ddrphy_datapath.vhd
268 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/sim_pll.vhd
270 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/sim_pll.vhd
269 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/buffer_apa3e.vhd
271 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/buffer_apa3e.vhd
270 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/clkgen_proasic3e.vhd
272 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/clkgen_proasic3e.vhd
271 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/ddr_proasic3e.vhd
273 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/ddr_proasic3e.vhd
272 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/memory_apa3e.vhd
274 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/memory_apa3e.vhd
273 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/pads_apa3e.vhd
275 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/pads_apa3e.vhd
274 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/tap_proasic3e.vhd
276 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/tap_proasic3e.vhd
275 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allclkgen.vhd
277 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allclkgen.vhd
276 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allddr.vhd
278 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allddr.vhd
277 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allmem.vhd
279 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allmem.vhd
278 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allmul.vhd
280 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allmul.vhd
279 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allpads.vhd
281 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allpads.vhd
280 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/alltap.vhd
282 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/alltap.vhd
281 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkgen.vhd
283 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkgen.vhd
282 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkmux.vhd
284 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkmux.vhd
283 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkand.vhd
285 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkand.vhd
284 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ddr_ireg.vhd
286 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ddr_ireg.vhd
285 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ddr_oreg.vhd
287 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ddr_oreg.vhd
286 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ddrphy.vhd
288 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ddrphy.vhd
287 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram.vhd
289 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram.vhd
288 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram64.vhd
290 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram64.vhd
289 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram_2p.vhd
291 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram_2p.vhd
290 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram_dp.vhd
292 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram_dp.vhd
291 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncfifo.vhd
293 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncfifo.vhd
292 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/regfile_3p.vhd
294 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/regfile_3p.vhd
293 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/tap.vhd
295 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/tap.vhd
294 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/techbuf.vhd
296 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/techbuf.vhd
295 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/nandtree.vhd
297 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/nandtree.vhd
296 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkpad.vhd
298 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkpad.vhd
297 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkpad_ds.vhd
299 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkpad_ds.vhd
298 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/inpad.vhd
300 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/inpad.vhd
299 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/inpad_ds.vhd
301 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/inpad_ds.vhd
300 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iodpad.vhd
302 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iodpad.vhd
301 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iopad.vhd
303 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iopad.vhd
302 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iopad_ds.vhd
304 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iopad_ds.vhd
303 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/lvds_combo.vhd
305 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/lvds_combo.vhd
304 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/odpad.vhd
306 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/odpad.vhd
305 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/outpad.vhd
307 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/outpad.vhd
306 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/outpad_ds.vhd
308 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/outpad_ds.vhd
307 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/toutpad.vhd
309 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/toutpad.vhd
308 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/skew_outpad.vhd
310 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/skew_outpad.vhd
309 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grspwc_net.vhd
311 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grspwc_net.vhd
310 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grspwc2_net.vhd
312 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grspwc2_net.vhd
311 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grlfpw_net.vhd
313 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grlfpw_net.vhd
312 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grlfpw4_net.vhd
314 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grlfpw4_net.vhd
313 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grfpw_net.vhd
315 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grfpw_net.vhd
314 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grfpw4_net.vhd
316 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grfpw4_net.vhd
315 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/leon4_net.vhd
317 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/leon4_net.vhd
316 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/mul_61x61.vhd
318 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/mul_61x61.vhd
317 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/cpu_disas_net.vhd
319 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/cpu_disas_net.vhd
318 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ringosc.vhd
320 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ringosc.vhd
319 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/corepcif_net.vhd
321 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/corepcif_net.vhd
320 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/pci_arb_net.vhd
322 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/pci_arb_net.vhd
321 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grpci2_phy_net.vhd
323 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grpci2_phy_net.vhd
322 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/system_monitor.vhd
324 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/system_monitor.vhd
323 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grgates.vhd
325 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grgates.vhd
324 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/inpad_ddr.vhd
326 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/inpad_ddr.vhd
325 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/outpad_ddr.vhd
327 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/outpad_ddr.vhd
326 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iopad_ddr.vhd
328 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iopad_ddr.vhd
327 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram128bw.vhd
329 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram128bw.vhd
328 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram256bw.vhd
330 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram256bw.vhd
329 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram128.vhd
331 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram128.vhd
330 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram156bw.vhd
332 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram156bw.vhd
331 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/techmult.vhd
333 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/techmult.vhd
332 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/spictrl_net.vhd
334 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/spictrl_net.vhd
333 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/scanreg.vhd
335 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/scanreg.vhd
334 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncrambw.vhd
336 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncrambw.vhd
335 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram_2pbw.vhd
337 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram_2pbw.vhd
336 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/obt1553_net.vhd
338 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/obt1553_net.vhd
337 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/sdram_phy.vhd
339 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/sdram_phy.vhd
338 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/from.vhd
340 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/from.vhd
339 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/mtie_maps.vhd
341 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/mtie_maps.vhd
340 @echo "vcom techmap done"
342 @echo "vcom techmap done"
341
343
342 vcom_lpp:
344 vcom_lpp:
343 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_amba/lpp_amba.vhd
345 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_amba/lpp_amba.vhd
344 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/iir_filter/iir_filter.vhd
346 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/iir_filter/iir_filter.vhd
345 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/iir_filter/RAM_CEL.vhd
347 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/iir_filter/RAM_CEL.vhd
346 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/fft_components.vhd
348 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/fft_components.vhd
347 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/lpp_fft.vhd
349 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/lpp_fft.vhd
348 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/Linker_FFT.vhd
350 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/Linker_FFT.vhd
349 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_purpose.vhd
351 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_purpose.vhd
350 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ADDRcntr.vhd
352 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ADDRcntr.vhd
351 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ALU.vhd
353 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ALU.vhd
352 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Adder.vhd
354 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Adder.vhd
353 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_Divider2.vhd
355 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_Divider2.vhd
354 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_divider.vhd
356 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_divider.vhd
355 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC.vhd
357 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC.vhd
356 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_CONTROLER.vhd
358 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_CONTROLER.vhd
357 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX.vhd
359 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX.vhd
358 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX2.vhd
360 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX2.vhd
359 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_REG.vhd
361 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_REG.vhd
360 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUX2.vhd
362 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUX2.vhd
361 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUXN.vhd
363 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUXN.vhd
362 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Multiplier.vhd
364 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Multiplier.vhd
363 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/REG.vhd
365 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/REG.vhd
364 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_FF.vhd
366 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_FF.vhd
365 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Shifter.vhd
367 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Shifter.vhd
366 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/TwoComplementer.vhd
368 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/TwoComplementer.vhd
367 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clock_Divider.vhd
369 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clock_Divider.vhd
368 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_to_level.vhd
370 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_to_level.vhd
369 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_detection.vhd
371 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_detection.vhd
370 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_positive_detection.vhd
372 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_positive_detection.vhd
371 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_VALID_BIT.vhd
373 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_VALID_BIT.vhd
372 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/RR_Arbiter_4.vhd
374 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/RR_Arbiter_4.vhd
373 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_counter.vhd
375 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_counter.vhd
374 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_ad_Conv/lpp_ad_Conv.vhd
376 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_ad_Conv/lpp_ad_Conv.vhd
375 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/dsp/iir_filter/FILTERcfg.vhd
377 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/dsp/iir_filter/FILTERcfg.vhd
376 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_amba/apb_devices_list.vhd
378 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_amba/apb_devices_list.vhd
377 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_dma/lpp_dma_pkg.vhd
379 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_dma/lpp_dma_pkg.vhd
378 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/lpp_matrix.vhd
380 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/lpp_matrix.vhd
379 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/MatriceSpectrale.vhd
381 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/MatriceSpectrale.vhd
380 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/ALU_Driver.vhd
382 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/ALU_Driver.vhd
381 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/ReUse_CTRLR.vhd
383 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/ReUse_CTRLR.vhd
382 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/Dispatch.vhd
384 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/Dispatch.vhd
383 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/DriveInputs.vhd
385 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/DriveInputs.vhd
384 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/GetResult.vhd
386 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/GetResult.vhd
385 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/MatriceSpectrale.vhd
387 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/MatriceSpectrale.vhd
386 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/Matrix.vhd
388 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/Matrix.vhd
387 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/TopSpecMatrix.vhd
389 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/TopSpecMatrix.vhd
388 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/SpectralMatrix.vhd
390 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/SpectralMatrix.vhd
389 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_Header/lpp_Header.vhd
391 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_Header/lpp_Header.vhd
390 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_Header/HeaderBuilder.vhd
392 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_Header/HeaderBuilder.vhd
391 $(CMD_VCOM) lpp lpp_memory.vhd
393 $(CMD_VCOM) lpp lpp_memory.vhd
392 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/CoreFFT_simu.vhd
394 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/CoreFFT_simu.vhd
393 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd
395 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd
394 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd
396 $(CMD_VCOM) lpp lpp_lfr_ms_fsmdma.vhd
395 @echo "vcom lpp done"
397 @echo "vcom lpp done"
396
398
397 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_amba/apb_devices_list.vhd
399 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_amba/apb_devices_list.vhd
398 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_purpose.vhd
400 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_purpose.vhd
399 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ADDRcntr.vhd
401 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ADDRcntr.vhd
400 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ALU.vhd
402 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ALU.vhd
401 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Adder.vhd
403 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Adder.vhd
402 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_Divider2.vhd
404 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_Divider2.vhd
403 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_divider.vhd
405 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_divider.vhd
404 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC.vhd
406 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC.vhd
405 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_CONTROLER.vhd
407 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_CONTROLER.vhd
406 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX.vhd
408 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX.vhd
407 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX2.vhd
409 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX2.vhd
408 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_REG.vhd
410 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_REG.vhd
409 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUX2.vhd
411 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUX2.vhd
410 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUXN.vhd
412 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUXN.vhd
411 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Multiplier.vhd
413 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Multiplier.vhd
412 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/REG.vhd
414 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/REG.vhd
413 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_FF.vhd
415 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_FF.vhd
414 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Shifter.vhd
416 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Shifter.vhd
415 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/TwoComplementer.vhd
417 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/TwoComplementer.vhd
416 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clock_Divider.vhd
418 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clock_Divider.vhd
417 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_to_level.vhd
419 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_to_level.vhd
418 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_detection.vhd
420 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_detection.vhd
419 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_positive_detection.vhd
421 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_positive_detection.vhd
420 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_VALID_BIT.vhd
422 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_VALID_BIT.vhd
421 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/RR_Arbiter_4.vhd
423 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/RR_Arbiter_4.vhd
422 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_counter.vhd
424 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_counter.vhd
423 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/lpp_lfr_time_management.vhd
425 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/lpp_lfr_time_management.vhd
424 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/apb_lfr_time_management.vhd
426 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/apb_lfr_time_management.vhd
425 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/lfr_time_management.vhd
427 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/lfr_time_management.vhd
426 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/fine_time_counter.vhd
428 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/fine_time_counter.vhd
427 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/coarse_time_counter.vhd
429 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/coarse_time_counter.vhd
428 # @echo "vcom lpp done"
430 # @echo "vcom lpp done"
429
431
430 #include Makefile_vcom_lpp
432 #include Makefile_vcom_lpp
Show file before | Show file after | Hide comments
@@ -1,313 +1,321
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22
22
23 LIBRARY IEEE;
23 LIBRARY IEEE;
24 USE IEEE.STD_LOGIC_1164.ALL;
24 USE IEEE.STD_LOGIC_1164.ALL;
25 USE IEEE.NUMERIC_STD.ALL;
25 USE IEEE.NUMERIC_STD.ALL;
26
26
27 LIBRARY lpp;
27 LIBRARY lpp;
28 USE lpp.lpp_lfr_pkg.ALL;
28 USE lpp.lpp_memory.ALL;
29 USE lpp.lpp_memory.ALL;
29 USE lpp.iir_filter.ALL;
30 USE lpp.iir_filter.ALL;
30 USE lpp.spectral_matrix_package.ALL;
31 USE lpp.spectral_matrix_package.ALL;
31 use lpp.lpp_fft.all;
32 use lpp.lpp_fft.all;
32 use lpp.fft_components.all;
33 use lpp.fft_components.all;
33
34
34 ENTITY TB IS
35 ENTITY TB IS
35
36
36
37
37 END TB;
38 END TB;
38
39
39
40
40 ARCHITECTURE beh OF TB IS
41 ARCHITECTURE beh OF TB IS
41
42 COMPONENT lpp_lfr_ms
43 GENERIC (
44 Mem_use : INTEGER);
45 PORT (
46 clk : IN STD_LOGIC;
47 rstn : IN STD_LOGIC;
48 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
49 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
50 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
51 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
52 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
53 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
54 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
55 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
56 dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
57 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
58 dma_valid : OUT STD_LOGIC;
59 dma_valid_burst : OUT STD_LOGIC;
60 dma_ren : IN STD_LOGIC;
61 dma_done : IN STD_LOGIC;
62 ready_matrix_f0_0 : OUT STD_LOGIC;
63 ready_matrix_f0_1 : OUT STD_LOGIC;
64 ready_matrix_f1 : OUT STD_LOGIC;
65 ready_matrix_f2 : OUT STD_LOGIC;
66 error_anticipating_empty_fifo : OUT STD_LOGIC;
67 error_bad_component_error : OUT STD_LOGIC;
68 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
69 status_ready_matrix_f0_0 : IN STD_LOGIC;
70 status_ready_matrix_f0_1 : IN STD_LOGIC;
71 status_ready_matrix_f1 : IN STD_LOGIC;
72 status_ready_matrix_f2 : IN STD_LOGIC;
73 status_error_anticipating_empty_fifo : IN STD_LOGIC;
74 status_error_bad_component_error : IN STD_LOGIC;
75 config_active_interruption_onNewMatrix : IN STD_LOGIC;
76 config_active_interruption_onError : IN STD_LOGIC;
77 addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
78 addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
79 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
80 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
81 matrix_time_f0_0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
82 matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
83 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
84 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0));
85 END COMPONENT;
86
42
87 -----------------------------------------------------------------------------
43 -----------------------------------------------------------------------------
88 SIGNAL clk25MHz : STD_LOGIC := '0';
44 SIGNAL clk25MHz : STD_LOGIC := '0';
89 SIGNAL rstn : STD_LOGIC := '0';
45 SIGNAL rstn : STD_LOGIC := '0';
90
46
91 -----------------------------------------------------------------------------
47 -----------------------------------------------------------------------------
92 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
48 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
93 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
49 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
94 SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
50 SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
95 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
51 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
96 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
52 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
97 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
53 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
98 SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
54 SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
99 SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
55 SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
100 SIGNAL dma_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
56 SIGNAL dma_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
101 SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
57 SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
102 SIGNAL dma_valid : STD_LOGIC;
58 SIGNAL dma_valid : STD_LOGIC;
103 SIGNAL dma_valid_burst : STD_LOGIC;
59 SIGNAL dma_valid_burst : STD_LOGIC;
104 SIGNAL dma_ren : STD_LOGIC;
60 SIGNAL dma_ren : STD_LOGIC;
105 SIGNAL dma_done : STD_LOGIC;
61 SIGNAL dma_done : STD_LOGIC;
106 SIGNAL ready_matrix_f0_0 : STD_LOGIC;
62 SIGNAL ready_matrix_f0 : STD_LOGIC;
107 SIGNAL ready_matrix_f0_1 : STD_LOGIC;
63 -- SIGNAL ready_matrix_f0_1 : STD_LOGIC;
108 SIGNAL ready_matrix_f1 : STD_LOGIC;
64 SIGNAL ready_matrix_f1 : STD_LOGIC;
109 SIGNAL ready_matrix_f2 : STD_LOGIC;
65 SIGNAL ready_matrix_f2 : STD_LOGIC;
110 SIGNAL error_anticipating_empty_fifo : STD_LOGIC;
66 -- SIGNAL error_anticipating_empty_fifo : STD_LOGIC;
111 SIGNAL error_bad_component_error : STD_LOGIC;
67 SIGNAL error_bad_component_error : STD_LOGIC;
112 SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
68 SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
113 SIGNAL status_ready_matrix_f0_0 : STD_LOGIC;
69 SIGNAL status_ready_matrix_f0 : STD_LOGIC;
114 SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
70 -- SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
115 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
71 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
116 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
72 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
117 SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC;
73 -- SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC;
118 SIGNAL status_error_bad_component_error : STD_LOGIC;
74 -- SIGNAL status_error_bad_component_error : STD_LOGIC;
119 SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
75 SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
120 SIGNAL config_active_interruption_onError : STD_LOGIC;
76 SIGNAL config_active_interruption_onError : STD_LOGIC;
121 SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
77 SIGNAL addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
122 SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
78 -- SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
123 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
79 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
124 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
80 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
125 SIGNAL matrix_time_f0_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
81 SIGNAL matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
126 SIGNAL matrix_time_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
82 -- SIGNAL matrix_time_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
127 SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
83 SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
128 SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
84 SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
129
85
130 -----------------------------------------------------------------------------
86 -----------------------------------------------------------------------------
131 SIGNAL clk49_152MHz : STD_LOGIC := '0';
87 SIGNAL clk49_152MHz : STD_LOGIC := '0';
132 SIGNAL sample_counter_24k : INTEGER;
88 SIGNAL sample_counter_24k : INTEGER;
133 SIGNAL s_24576Hz : STD_LOGIC;
89 SIGNAL s_24576Hz : STD_LOGIC;
134
90
135 SIGNAL s_24_sync_reg_0 : STD_LOGIC;
91 SIGNAL s_24_sync_reg_0 : STD_LOGIC;
136 SIGNAL s_24_sync_reg_1 : STD_LOGIC;
92 SIGNAL s_24_sync_reg_1 : STD_LOGIC;
137
93
138 SIGNAL s_24576Hz_sync : STD_LOGIC;
94 SIGNAL s_24576Hz_sync : STD_LOGIC;
139
95
140 SIGNAL sample_counter_f1 : INTEGER;
96 SIGNAL sample_counter_f1 : INTEGER;
141 SIGNAL sample_counter_f2 : INTEGER;
97 SIGNAL sample_counter_f2 : INTEGER;
142 --
98 --
143 SIGNAL sample_f0_val : STD_LOGIC;
99 SIGNAL sample_f0_val : STD_LOGIC;
144 SIGNAL sample_f1_val : STD_LOGIC;
100 SIGNAL sample_f1_val : STD_LOGIC;
145 SIGNAL sample_f2_val : STD_LOGIC;
101 SIGNAL sample_f2_val : STD_LOGIC;
102
103 -----------------------------------------------------------------------------
104 SIGNAL ren_counter : INTEGER;
146
105
147 BEGIN -- beh
106 BEGIN -- beh
148
107
149 clk25MHz <= NOT clk25MHz AFTER 20 ns;
108 clk25MHz <= NOT clk25MHz AFTER 20 ns;
150 clk25MHz <= NOT clk25MHz AFTER 20 ns;
109 clk25MHz <= NOT clk25MHz AFTER 20 ns;
151 clk49_152MHz <= NOT clk49_152MHz AFTER 10173 ps; -- 49.152/2 MHz
110 clk49_152MHz <= NOT clk49_152MHz AFTER 10173 ps; -- 49.152/2 MHz
152
111
153 PROCESS
112 PROCESS
154 BEGIN -- PROCESS
113 BEGIN -- PROCESS
155 WAIT UNTIL clk25MHz = '1';
114 WAIT UNTIL clk25MHz = '1';
156 WAIT UNTIL clk25MHz = '1';
115 WAIT UNTIL clk25MHz = '1';
157 WAIT UNTIL clk25MHz = '1';
116 WAIT UNTIL clk25MHz = '1';
158 rstn <= '1';
117 rstn <= '1';
159 WAIT UNTIL clk25MHz = '1';
118 WAIT UNTIL clk25MHz = '1';
160
119
161
120
162 WAIT FOR 100 ms;
121 WAIT FOR 100 ms;
163
122
164 REPORT "*** END simulation ***" SEVERITY failure;
123 REPORT "*** END simulation ***" SEVERITY failure;
165 WAIT;
124 WAIT;
166
125
167 END PROCESS;
126 END PROCESS;
168
127
169
128
170 -----------------------------------------------------------------------------
129 -----------------------------------------------------------------------------
171 PROCESS (clk49_152MHz, rstn)
130 PROCESS (clk49_152MHz, rstn)
172 BEGIN -- PROCESS
131 BEGIN -- PROCESS
173 IF rstn = '0' THEN -- asynchronous reset (active low)
132 IF rstn = '0' THEN -- asynchronous reset (active low)
174 sample_counter_24k <= 0;
133 sample_counter_24k <= 0;
175 s_24576Hz <= '0';
134 s_24576Hz <= '0';
176 ELSIF clk49_152MHz'event AND clk49_152MHz = '1' THEN -- rising clock edge
135 ELSIF clk49_152MHz'event AND clk49_152MHz = '1' THEN -- rising clock edge
177 IF sample_counter_24k = 0 THEN
136 IF sample_counter_24k = 0 THEN
178 sample_counter_24k <= 2000;
137 sample_counter_24k <= 2000;
179 s_24576Hz <= NOT s_24576Hz;
138 s_24576Hz <= NOT s_24576Hz;
180 ELSE
139 ELSE
181 sample_counter_24k <= sample_counter_24k - 1;
140 sample_counter_24k <= sample_counter_24k - 1;
182 END IF;
141 END IF;
183 END IF;
142 END IF;
184 END PROCESS;
143 END PROCESS;
185
144
186 PROCESS (clk25MHz, rstn)
145 PROCESS (clk25MHz, rstn)
187 BEGIN -- PROCESS
146 BEGIN -- PROCESS
188 IF rstn = '0' THEN -- asynchronous reset (active low)
147 IF rstn = '0' THEN -- asynchronous reset (active low)
189 s_24_sync_reg_0 <= '0';
148 s_24_sync_reg_0 <= '0';
190 s_24_sync_reg_1 <= '0';
149 s_24_sync_reg_1 <= '0';
191 s_24576Hz_sync <= '0';
150 s_24576Hz_sync <= '0';
192 ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge
151 ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge
193 s_24_sync_reg_0 <= s_24576Hz;
152 s_24_sync_reg_0 <= s_24576Hz;
194 s_24_sync_reg_1 <= s_24_sync_reg_0;
153 s_24_sync_reg_1 <= s_24_sync_reg_0;
195 s_24576Hz_sync <= s_24_sync_reg_0 XOR s_24_sync_reg_1;
154 s_24576Hz_sync <= s_24_sync_reg_0 XOR s_24_sync_reg_1;
196 END IF;
155 END IF;
197 END PROCESS;
156 END PROCESS;
198
157
199 PROCESS (clk25MHz, rstn)
158 PROCESS (clk25MHz, rstn)
200 BEGIN -- PROCESS
159 BEGIN -- PROCESS
201 IF rstn = '0' THEN -- asynchronous reset (active low)
160 IF rstn = '0' THEN -- asynchronous reset (active low)
202 sample_f0_val <= '0';
161 sample_f0_val <= '0';
203 sample_f1_val <= '0';
162 sample_f1_val <= '0';
204 sample_f2_val <= '0';
163 sample_f2_val <= '0';
205
164
206 sample_counter_f1 <= 0;
165 sample_counter_f1 <= 0;
207 sample_counter_f2 <= 0;
166 sample_counter_f2 <= 0;
208 ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge
167 ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge
209 IF s_24576Hz_sync = '1' THEN
168 IF s_24576Hz_sync = '1' THEN
210 sample_f0_val <= '1';
169 sample_f0_val <= '1';
211 IF sample_counter_f1 = 0 THEN
170 IF sample_counter_f1 = 0 THEN
212 sample_f1_val <= '1';
171 sample_f1_val <= '1';
213 sample_counter_f1 <= 5;
172 sample_counter_f1 <= 5;
214 ELSE
173 ELSE
215 sample_f1_val <= '0';
174 sample_f1_val <= '0';
216 sample_counter_f1 <= sample_counter_f1 -1;
175 sample_counter_f1 <= sample_counter_f1 -1;
217 END IF;
176 END IF;
218 IF sample_counter_f2 = 0 THEN
177 IF sample_counter_f2 = 0 THEN
219 sample_f2_val <= '1';
178 sample_f2_val <= '1';
220 sample_counter_f2 <= 95;
179 sample_counter_f2 <= 95;
221 ELSE
180 ELSE
222 sample_f2_val <= '0';
181 sample_f2_val <= '0';
223 sample_counter_f2 <= sample_counter_f2 -1;
182 sample_counter_f2 <= sample_counter_f2 -1;
224 END IF;
183 END IF;
225 ELSE
184 ELSE
226 sample_f0_val <= '0';
185 sample_f0_val <= '0';
227 sample_f1_val <= '0';
186 sample_f1_val <= '0';
228 sample_f2_val <= '0';
187 sample_f2_val <= '0';
229 END IF;
188 END IF;
230 END IF;
189 END IF;
231 END PROCESS;
190 END PROCESS;
232
191
233
192
234
193
235 -----------------------------------------------------------------------------
194 -----------------------------------------------------------------------------
236 coarse_time <= (OTHERS => '0');
195 coarse_time <= (OTHERS => '0');
237 fine_time <= (OTHERS => '0');
196 fine_time <= (OTHERS => '0');
238
197
239 sample_f0_wdata <= X"A000" & X"A111" & X"A222" & X"A333" & X"A444";
198 sample_f0_wdata <= X"A000" & X"A111" & X"A222" & X"A333" & X"A444";
240 sample_f1_wdata <= X"B000" & X"B111" & X"B222" & X"B333" & X"B444";
199 sample_f1_wdata <= X"B000" & X"B111" & X"B222" & X"B333" & X"B444";
241 sample_f2_wdata <= X"C000" & X"C111" & X"C222" & X"C333" & X"C444";
200 sample_f2_wdata <= X"C000" & X"C111" & X"C222" & X"C333" & X"C444";
242
201
243 sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val);
202 sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val);
244 sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val);
203 sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val);
245 sample_f2_wen <= NOT(sample_f2_val) & NOT(sample_f2_val) & NOT(sample_f2_val) & NOT(sample_f2_val) & NOT(sample_f2_val);
204 sample_f2_wen <= NOT(sample_f2_val) & NOT(sample_f2_val) & NOT(sample_f2_val) & NOT(sample_f2_val) & NOT(sample_f2_val);
246 -----------------------------------------------------------------------------
205 -----------------------------------------------------------------------------
247
206
248 lpp_lfr_ms_1: ENTITY lpp.lpp_lfr_ms
207 lpp_lfr_ms_1: lpp_lfr_ms
249 GENERIC MAP (
208 GENERIC MAP (
250 Mem_use => use_CEL)
209 Mem_use => use_CEL)
251 PORT MAP (
210 PORT MAP (
252 clk => clk25MHz,
211 clk => clk25MHz,
253 rstn => rstn,
212 rstn => rstn,
254 --
213 --
255 coarse_time => coarse_time,
214 coarse_time => coarse_time,
256 fine_time => fine_time,
215 fine_time => fine_time,
257 --
216 --
258 sample_f0_wen => sample_f0_wen,
217 sample_f0_wen => sample_f0_wen,
259 sample_f0_wdata => sample_f0_wdata,
218 sample_f0_wdata => sample_f0_wdata,
260 sample_f1_wen => sample_f1_wen,
219 sample_f1_wen => sample_f1_wen,
261 sample_f1_wdata => sample_f1_wdata,
220 sample_f1_wdata => sample_f1_wdata,
262 sample_f2_wen => sample_f2_wen,
221 sample_f2_wen => sample_f2_wen,
263 sample_f2_wdata => sample_f2_wdata,
222 sample_f2_wdata => sample_f2_wdata,
264 --
223 --
265 dma_addr => dma_addr,
224 dma_addr => dma_addr,
266 dma_data => dma_data,
225 dma_data => dma_data,
267 dma_valid => dma_valid,
226 dma_valid => dma_valid,
268 dma_valid_burst => dma_valid_burst,
227 dma_valid_burst => dma_valid_burst,
269 dma_ren => dma_ren,
228 dma_ren => dma_ren,
270 dma_done => dma_done,
229 dma_done => dma_done,
271 ready_matrix_f0_0 => ready_matrix_f0_0,
230
272 ready_matrix_f0_1 => ready_matrix_f0_1,
231 ready_matrix_f0 => ready_matrix_f0,
232 -- ready_matrix_f0_1 => ready_matrix_f0_1,
273 ready_matrix_f1 => ready_matrix_f1,
233 ready_matrix_f1 => ready_matrix_f1,
274 ready_matrix_f2 => ready_matrix_f2,
234 ready_matrix_f2 => ready_matrix_f2,
275 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
235 -- error_anticipating_empty_fifo => error_anticipating_empty_fifo,
276 error_bad_component_error => error_bad_component_error,
236 error_bad_component_error => error_bad_component_error,
237 error_buffer_full => OPEN,
238 error_input_fifo_write => OPEN,
239
277 debug_reg => debug_reg,
240 debug_reg => debug_reg,
278 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
241 status_ready_matrix_f0 => status_ready_matrix_f0,
279 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
242 -- status_ready_matrix_f0 => status_ready_matrix_f0_1,
280 status_ready_matrix_f1 => status_ready_matrix_f1,
243 status_ready_matrix_f1 => status_ready_matrix_f1,
281 status_ready_matrix_f2 => status_ready_matrix_f2,
244 status_ready_matrix_f2 => status_ready_matrix_f2,
282 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
245 -- status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
283 status_error_bad_component_error => status_error_bad_component_error,
246 -- status_error_bad_component_error => status_error_bad_component_error,
284 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
247 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
285 config_active_interruption_onError => config_active_interruption_onError,
248 config_active_interruption_onError => config_active_interruption_onError,
286 addr_matrix_f0_0 => addr_matrix_f0_0,
249 addr_matrix_f0 => addr_matrix_f0,
287 addr_matrix_f0_1 => addr_matrix_f0_1,
250 -- addr_matrix_f0_1 => addr_matrix_f0_1,
288 addr_matrix_f1 => addr_matrix_f1,
251 addr_matrix_f1 => addr_matrix_f1,
289 addr_matrix_f2 => addr_matrix_f2,
252 addr_matrix_f2 => addr_matrix_f2,
290 matrix_time_f0_0 => matrix_time_f0_0,
253 matrix_time_f0 => matrix_time_f0,
291 matrix_time_f0_1 => matrix_time_f0_1,
254 -- matrix_time_f0_1 => matrix_time_f0_1,
292 matrix_time_f1 => matrix_time_f1,
255 matrix_time_f1 => matrix_time_f1,
293 matrix_time_f2 => matrix_time_f2);
256 matrix_time_f2 => matrix_time_f2);
294
257
295 dma_ren <= '0';
258
296 dma_done <= '0';
259
260
297
261
298 status_ready_matrix_f0_0 <= '0';
262 PROCESS (clk25MHz, rstn)
299 status_ready_matrix_f0_1 <= '0';
263 BEGIN -- PROCESS
300 status_ready_matrix_f1 <= '0';
264 IF rstn = '0' THEN -- asynchronous reset (active low)
301 status_ready_matrix_f2 <= '0';
265 status_ready_matrix_f0 <= '0';
302 status_error_anticipating_empty_fifo <= '0';
266 -- status_ready_matrix_f0_1 <= '0';
303 status_error_bad_component_error <= '0';
267 status_ready_matrix_f1 <= '0';
268 status_ready_matrix_f2 <= '0';
269 ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge
270 status_ready_matrix_f0 <= status_ready_matrix_f0 OR ready_matrix_f0;
271 -- status_ready_matrix_f0_1 <= status_ready_matrix_f0_1 OR ready_matrix_f0_1;
272 status_ready_matrix_f1 <= status_ready_matrix_f1 OR ready_matrix_f1;
273 status_ready_matrix_f2 <= status_ready_matrix_f2 OR ready_matrix_f2;
274 END IF;
275 END PROCESS;
276
277
278
279
280 -- status_error_anticipating_empty_fifo <= '0';
281 -- status_error_bad_component_error <= '0';
304
282
305 config_active_interruption_onNewMatrix <= '0';
283 config_active_interruption_onNewMatrix <= '0';
306 config_active_interruption_onError <= '0';
284 config_active_interruption_onError <= '0';
307 addr_matrix_f0_0 <= (OTHERS => '0');
285 addr_matrix_f0 <= (OTHERS => '0');
308 addr_matrix_f0_1 <= (OTHERS => '0');
286 -- addr_matrix_f0_1 <= (OTHERS => '0');
309 addr_matrix_f1 <= (OTHERS => '0');
287 addr_matrix_f1 <= (OTHERS => '0');
310 addr_matrix_f2 <= (OTHERS => '0');
288 addr_matrix_f2 <= (OTHERS => '0');
289
290
291 PROCESS (clk25MHz, rstn)
292 BEGIN -- PROCESS
293 IF rstn = '0' THEN -- asynchronous reset (active low)
294
295 dma_ren <= '1';
296 dma_done <= '0';
297 ren_counter <= 0;
298 ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge
299 dma_ren <= '1';
300 dma_done <= '0';
301
302 IF dma_valid_burst = '1' THEN
303 ren_counter <= 17;
304 END IF;
305
306 IF ren_counter > 1 THEN
307 ren_counter <= ren_counter - 1;
308 dma_ren <= '0';
309 END IF;
310
311 IF ren_counter = 1 THEN
312 ren_counter <= 0;
313 dma_done <= '1';
314 END IF;
315
316 END IF;
317 END PROCESS;
318
311
319
312 END beh;
320 END beh;
313
321
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@@ -1,82 +1,84
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.std_logic_1164.ALL;
23 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.numeric_std.ALL;
24 USE IEEE.numeric_std.ALL;
25 LIBRARY lpp;
25 LIBRARY lpp;
26 USE lpp.lpp_memory.ALL;
26 USE lpp.lpp_memory.ALL;
27 USE lpp.iir_filter.ALL;
27 USE lpp.iir_filter.ALL;
28 LIBRARY techmap;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
29 USE techmap.gencomp.ALL;
30
30
31 ENTITY lppFIFOxN IS
31 ENTITY lppFIFOxN IS
32 GENERIC(
32 GENERIC(
33 tech : INTEGER := 0;
33 tech : INTEGER := 0;
34 Mem_use : INTEGER := use_RAM;
34 Mem_use : INTEGER := use_RAM;
35 Data_sz : INTEGER RANGE 1 TO 32 := 8;
35 Data_sz : INTEGER RANGE 1 TO 32 := 8;
36 Addr_sz : INTEGER RANGE 2 TO 12 := 8;
36 Addr_sz : INTEGER RANGE 2 TO 12 := 8;
37 FifoCnt : INTEGER := 1
37 FifoCnt : INTEGER := 1
38 );
38 );
39 PORT(
39 PORT(
40 clk : IN STD_LOGIC;
40 clk : IN STD_LOGIC;
41 rstn : IN STD_LOGIC;
41 rstn : IN STD_LOGIC;
42
42
43 ReUse : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
43 ReUse : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
44
44
45 wen : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
45 wen : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
46 wdata : IN STD_LOGIC_VECTOR((FifoCnt*Data_sz)-1 DOWNTO 0);
46 wdata : IN STD_LOGIC_VECTOR((FifoCnt*Data_sz)-1 DOWNTO 0);
47
47
48 ren : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
48 ren : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
49 rdata : OUT STD_LOGIC_VECTOR((FifoCnt*Data_sz)-1 DOWNTO 0);
49 rdata : OUT STD_LOGIC_VECTOR((FifoCnt*Data_sz)-1 DOWNTO 0);
50
50
51 empty : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
51 empty : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
52 full : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
52 full : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
53 almost_full : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0)
53 almost_full : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
54 more_16Data : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0)
54 );
55 );
55 END ENTITY;
56 END ENTITY;
56
57
57
58
58 ARCHITECTURE ar_lppFIFOxN OF lppFIFOxN IS
59 ARCHITECTURE ar_lppFIFOxN OF lppFIFOxN IS
59
60
60 BEGIN
61 BEGIN
61
62
62 fifos : FOR i IN 0 TO FifoCnt-1 GENERATE
63 fifos : FOR i IN 0 TO FifoCnt-1 GENERATE
63 lpp_fifo_1: lpp_fifo
64 lpp_fifo_1: lpp_fifo
64 GENERIC MAP (
65 GENERIC MAP (
65 tech => tech,
66 tech => tech,
66 Mem_use => Mem_use,
67 Mem_use => Mem_use,
67 DataSz => Data_sz,
68 DataSz => Data_sz,
68 AddrSz => Addr_sz)
69 AddrSz => Addr_sz)
69 PORT MAP (
70 PORT MAP (
70 clk => clk,
71 clk => clk,
71 rstn => rstn,
72 rstn => rstn,
72 reUse => reUse(I),
73 reUse => reUse(I),
73 ren => ren(I),
74 ren => ren(I),
74 rdata => rdata( ((I+1)*Data_sz)-1 DOWNTO (I*Data_sz) ),
75 rdata => rdata( ((I+1)*Data_sz)-1 DOWNTO (I*Data_sz) ),
75 wen => wen(I),
76 wen => wen(I),
76 wdata => wdata(((I+1)*Data_sz)-1 DOWNTO (I*Data_sz)),
77 wdata => wdata(((I+1)*Data_sz)-1 DOWNTO (I*Data_sz)),
77 empty => empty(I),
78 empty => empty(I),
78 full => full(I),
79 full => full(I),
79 almost_full => almost_full(I));
80 almost_full => almost_full(I),
81 more_16Data => more_16Data(I));
80 END GENERATE;
82 END GENERATE;
81
83
82 END ARCHITECTURE;
84 END ARCHITECTURE;
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@@ -1,188 +1,198
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.std_logic_1164.ALL;
23 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.numeric_std.ALL;
24 USE IEEE.numeric_std.ALL;
25 LIBRARY lpp;
25 LIBRARY lpp;
26 USE lpp.lpp_memory.ALL;
26 USE lpp.lpp_memory.ALL;
27 USE lpp.iir_filter.ALL;
27 USE lpp.iir_filter.ALL;
28 LIBRARY techmap;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
29 USE techmap.gencomp.ALL;
30
30
31 ENTITY lpp_fifo IS
31 ENTITY lpp_fifo IS
32 GENERIC(
32 GENERIC(
33 tech : INTEGER := 0;
33 tech : INTEGER := 0;
34 Mem_use : INTEGER := use_RAM;
34 Mem_use : INTEGER := use_RAM;
35 DataSz : INTEGER RANGE 1 TO 32 := 8;
35 DataSz : INTEGER RANGE 1 TO 32 := 8;
36 AddrSz : INTEGER RANGE 2 TO 12 := 8
36 AddrSz : INTEGER RANGE 2 TO 12 := 8
37 );
37 );
38 PORT(
38 PORT(
39 clk : IN STD_LOGIC;
39 clk : IN STD_LOGIC;
40 rstn : IN STD_LOGIC;
40 rstn : IN STD_LOGIC;
41 --
41 --
42 reUse : IN STD_LOGIC;
42 reUse : IN STD_LOGIC;
43
43
44 --IN
44 --IN
45 ren : IN STD_LOGIC;
45 ren : IN STD_LOGIC;
46 rdata : OUT STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
46 rdata : OUT STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
47
47
48 --OUT
48 --OUT
49 wen : IN STD_LOGIC;
49 wen : IN STD_LOGIC;
50 wdata : IN STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
50 wdata : IN STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
51
51
52 empty : OUT STD_LOGIC;
52 empty : OUT STD_LOGIC;
53 full : OUT STD_LOGIC;
53 full : OUT STD_LOGIC;
54 almost_full : OUT STD_LOGIC
54 almost_full : OUT STD_LOGIC;
55 more_16Data : OUT STD_LOGIC
55 );
56 );
56 END ENTITY;
57 END ENTITY;
57
58
58
59
59 ARCHITECTURE ar_lpp_fifo OF lpp_fifo IS
60 ARCHITECTURE ar_lpp_fifo OF lpp_fifo IS
60
61
61 SIGNAL sFull : STD_LOGIC;
62 SIGNAL sFull : STD_LOGIC;
62 SIGNAL sFull_s : STD_LOGIC;
63 SIGNAL sFull_s : STD_LOGIC;
63 SIGNAL sEmpty_s : STD_LOGIC;
64 SIGNAL sEmpty_s : STD_LOGIC;
64
65
65 SIGNAL sEmpty : STD_LOGIC;
66 SIGNAL sEmpty : STD_LOGIC;
66 SIGNAL sREN : STD_LOGIC;
67 SIGNAL sREN : STD_LOGIC;
67 SIGNAL sWEN : STD_LOGIC;
68 SIGNAL sWEN : STD_LOGIC;
68 SIGNAL sRE : STD_LOGIC;
69 SIGNAL sRE : STD_LOGIC;
69 SIGNAL sWE : STD_LOGIC;
70 SIGNAL sWE : STD_LOGIC;
70
71
71 SIGNAL Waddr_vect : STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0) := (OTHERS => '0');
72 SIGNAL Waddr_vect : STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0) := (OTHERS => '0');
72 SIGNAL Raddr_vect : STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0) := (OTHERS => '0');
73 SIGNAL Raddr_vect : STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0) := (OTHERS => '0');
73 SIGNAL Waddr_vect_s : STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0) := (OTHERS => '0');
74 SIGNAL Waddr_vect_s : STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0) := (OTHERS => '0');
74 SIGNAL Raddr_vect_s : STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0) := (OTHERS => '0');
75 SIGNAL Raddr_vect_s : STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0) := (OTHERS => '0');
75
76
76 SIGNAL almost_full_s : STD_LOGIC;
77 SIGNAL almost_full_s : STD_LOGIC;
77 SIGNAL almost_full_r : STD_LOGIC;
78 SIGNAL almost_full_r : STD_LOGIC;
78 BEGIN
79 BEGIN
79
80
80 --==================================================================================
81 --==================================================================================
81 -- /!\ syncram_2p Write et Read actif a l'οΏ½tat haut /!\
82 -- /!\ syncram_2p Write et Read actif a l'οΏ½tat haut /!\
82 -- A l'inverse de RAM_CEL !!!
83 -- A l'inverse de RAM_CEL !!!
83 --==================================================================================
84 --==================================================================================
84 memRAM : IF Mem_use = use_RAM GENERATE
85 memRAM : IF Mem_use = use_RAM GENERATE
85 SRAM : syncram_2p
86 SRAM : syncram_2p
86 GENERIC MAP(tech, AddrSz, DataSz)
87 GENERIC MAP(tech, AddrSz, DataSz)
87 PORT MAP(CLK, sRE, Raddr_vect, rdata, CLK, sWE, Waddr_vect, wdata);
88 PORT MAP(CLK, sRE, Raddr_vect, rdata, CLK, sWE, Waddr_vect, wdata);
88 END GENERATE;
89 END GENERATE;
89 --==================================================================================
90 --==================================================================================
90 memCEL : IF Mem_use = use_CEL GENERATE
91 memCEL : IF Mem_use = use_CEL GENERATE
91 CRAM : RAM_CEL
92 CRAM : RAM_CEL
92 GENERIC MAP(DataSz, AddrSz)
93 GENERIC MAP(DataSz, AddrSz)
93 PORT MAP(wdata, rdata, sWEN, sREN, Waddr_vect, Raddr_vect, CLK, rstn);
94 PORT MAP(wdata, rdata, sWEN, sREN, Waddr_vect, Raddr_vect, CLK, rstn);
94 END GENERATE;
95 END GENERATE;
95 --==================================================================================
96 --==================================================================================
96
97
97 --=============================
98 --=============================
98 -- Read section
99 -- Read section
99 --=============================
100 --=============================
100 sREN <= REN OR sEmpty;
101 sREN <= REN OR sEmpty;
101 sRE <= NOT sREN;
102 sRE <= NOT sREN;
102
103
103 sEmpty_s <= '0' WHEN ReUse = '1' else
104 sEmpty_s <= '0' WHEN ReUse = '1' else
104 '1' WHEN sEmpty = '1' AND Wen = '1' ELSE
105 '1' WHEN sEmpty = '1' AND Wen = '1' ELSE
105 '1' WHEN sEmpty = '0' AND (Wen = '1' AND Ren = '0' AND Raddr_vect_s = Waddr_vect) ELSE
106 '1' WHEN sEmpty = '0' AND (Wen = '1' AND Ren = '0' AND Raddr_vect_s = Waddr_vect) ELSE
106 '0';
107 '0';
107
108
108 Raddr_vect_s <= STD_LOGIC_VECTOR(UNSIGNED(Raddr_vect) +1);
109 Raddr_vect_s <= STD_LOGIC_VECTOR(UNSIGNED(Raddr_vect) +1);
109
110
110 PROCESS (clk, rstn)
111 PROCESS (clk, rstn)
111 BEGIN
112 BEGIN
112 IF(rstn = '0')then
113 IF(rstn = '0')then
113 Raddr_vect <= (OTHERS => '0');
114 Raddr_vect <= (OTHERS => '0');
114 sempty <= '1';
115 sempty <= '1';
115 ELSIF(clk'EVENT AND clk = '1')then
116 ELSIF(clk'EVENT AND clk = '1')then
116 sEmpty <= sempty_s;
117 sEmpty <= sempty_s;
117
118
118 IF(sREN = '0' and sempty = '0')then
119 IF(sREN = '0' and sempty = '0')then
119 Raddr_vect <= Raddr_vect_s;
120 Raddr_vect <= Raddr_vect_s;
120 END IF;
121 END IF;
121
122
122 END IF;
123 END IF;
123 END PROCESS;
124 END PROCESS;
124
125
125 --=============================
126 --=============================
126 -- Write section
127 -- Write section
127 --=============================
128 --=============================
128 sWEN <= WEN OR sFull;
129 sWEN <= WEN OR sFull;
129 sWE <= NOT sWEN;
130 sWE <= NOT sWEN;
130
131
131 sFull_s <= '1' WHEN ReUse = '1' else
132 sFull_s <= '1' WHEN ReUse = '1' else
132 '1' WHEN Waddr_vect_s = Raddr_vect AND REN = '1' AND WEN = '0' ELSE
133 '1' WHEN Waddr_vect_s = Raddr_vect AND REN = '1' AND WEN = '0' ELSE
133 '1' WHEN sFull = '1' AND REN = '1' ELSE
134 '1' WHEN sFull = '1' AND REN = '1' ELSE
134 '0';
135 '0';
135
136
136 almost_full_s <= '1' WHEN STD_LOGIC_VECTOR(UNSIGNED(Waddr_vect) +2) = Raddr_vect AND REN = '1' AND WEN = '0' ELSE
137 almost_full_s <= '1' WHEN STD_LOGIC_VECTOR(UNSIGNED(Waddr_vect) +2) = Raddr_vect AND REN = '1' AND WEN = '0' ELSE
137 '1' WHEN almost_full_r = '1' AND WEN = REN ELSE
138 '1' WHEN almost_full_r = '1' AND WEN = REN ELSE
138 '0';
139 '0';
139
140
140 Waddr_vect_s <= STD_LOGIC_VECTOR(UNSIGNED(Waddr_vect) +1);
141 Waddr_vect_s <= STD_LOGIC_VECTOR(UNSIGNED(Waddr_vect) +1);
141
142
142 PROCESS (clk, rstn)
143 PROCESS (clk, rstn)
143 BEGIN
144 BEGIN
144 IF(rstn = '0')then
145 IF(rstn = '0')then
145 Waddr_vect <= (OTHERS => '0');
146 Waddr_vect <= (OTHERS => '0');
146 sfull <= '0';
147 sfull <= '0';
147 almost_full_r <= '0';
148 almost_full_r <= '0';
148 ELSIF(clk'EVENT AND clk = '1')then
149 ELSIF(clk'EVENT AND clk = '1')then
149 sfull <= sfull_s;
150 sfull <= sfull_s;
150 almost_full_r <= almost_full_s;
151 almost_full_r <= almost_full_s;
151
152
152 IF(sWEN = '0' and sfull = '0')THEN
153 IF(sWEN = '0' and sfull = '0')THEN
153 Waddr_vect <= Waddr_vect_s;
154 Waddr_vect <= Waddr_vect_s;
154 END IF;
155 END IF;
155
156
156 END IF;
157 END IF;
157 END PROCESS;
158 END PROCESS;
158
159
159 almost_full <= almost_full_s;
160 almost_full <= almost_full_s;
160 full <= sFull_s;
161 full <= sFull_s;
161 empty <= sEmpty_s;
162 empty <= sEmpty_s;
162
163
164
165 more_16Data <= '1' WHEN ReUse = '1' ELSE
166 '1' WHEN sFull = '1' ELSE
167 '1' WHEN UNSIGNED(Waddr_vect) > UNSIGNED(Raddr_vect) AND UNSIGNED(Waddr_vect) > UNSIGNED(Raddr_vect) + 15 ELSE
168 '1' WHEN UNSIGNED(Waddr_vect) < UNSIGNED(Raddr_vect) AND 2**AddrSz - UNSIGNED(Raddr_vect) + UNSIGNED(Waddr_vect) > 15 ELSE
169 '0';
170
171
172
163 END ARCHITECTURE;
173 END ARCHITECTURE;
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Show file before | Show file after | Hide comments
@@ -1,899 +1,1078
1 LIBRARY ieee;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
2 USE ieee.std_logic_1164.ALL;
3
3
4
4
5 LIBRARY lpp;
5 LIBRARY lpp;
6 USE lpp.lpp_memory.ALL;
6 USE lpp.lpp_memory.ALL;
7 USE lpp.iir_filter.ALL;
7 USE lpp.iir_filter.ALL;
8 USE lpp.spectral_matrix_package.ALL;
8 USE lpp.spectral_matrix_package.ALL;
9 USE lpp.lpp_dma_pkg.ALL;
9 USE lpp.lpp_dma_pkg.ALL;
10 USE lpp.lpp_Header.ALL;
10 USE lpp.lpp_Header.ALL;
11 USE lpp.lpp_matrix.ALL;
11 USE lpp.lpp_matrix.ALL;
12 USE lpp.lpp_matrix.ALL;
12 USE lpp.lpp_matrix.ALL;
13 USE lpp.lpp_lfr_pkg.ALL;
13 USE lpp.lpp_lfr_pkg.ALL;
14 USE lpp.lpp_fft.ALL;
14 USE lpp.lpp_fft.ALL;
15 USE lpp.fft_components.ALL;
15 USE lpp.fft_components.ALL;
16
16
17 ENTITY lpp_lfr_ms IS
17 ENTITY lpp_lfr_ms IS
18 GENERIC (
18 GENERIC (
19 Mem_use : INTEGER := use_RAM
19 Mem_use : INTEGER := use_RAM
20 );
20 );
21 PORT (
21 PORT (
22 clk : IN STD_LOGIC;
22 clk : IN STD_LOGIC;
23 rstn : IN STD_LOGIC;
23 rstn : IN STD_LOGIC;
24
24
25 ---------------------------------------------------------------------------
25 ---------------------------------------------------------------------------
26 -- DATA INPUT
26 -- DATA INPUT
27 ---------------------------------------------------------------------------
27 ---------------------------------------------------------------------------
28 -- TIME
28 -- TIME
29 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
29 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
30 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
30 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
31 --
31 --
32 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
32 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
33 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
33 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
34 --
34 --
35 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
35 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
36 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
36 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
37 --
37 --
38 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
38 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
39 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
39 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
40
40
41 ---------------------------------------------------------------------------
41 ---------------------------------------------------------------------------
42 -- DMA
42 -- DMA
43 ---------------------------------------------------------------------------
43 ---------------------------------------------------------------------------
44 dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
44 dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
45 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
45 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
46 dma_valid : OUT STD_LOGIC;
46 dma_valid : OUT STD_LOGIC;
47 dma_valid_burst : OUT STD_LOGIC;
47 dma_valid_burst : OUT STD_LOGIC;
48 dma_ren : IN STD_LOGIC;
48 dma_ren : IN STD_LOGIC;
49 dma_done : IN STD_LOGIC;
49 dma_done : IN STD_LOGIC;
50
50
51 -- Reg out
51 -- Reg out
52 ready_matrix_f0_0 : OUT STD_LOGIC;
52 ready_matrix_f0 : OUT STD_LOGIC;
53 ready_matrix_f0_1 : OUT STD_LOGIC;
53 -- ready_matrix_f0 : OUT STD_LOGIC;
54 ready_matrix_f1 : OUT STD_LOGIC;
54 ready_matrix_f1 : OUT STD_LOGIC;
55 ready_matrix_f2 : OUT STD_LOGIC;
55 ready_matrix_f2 : OUT STD_LOGIC;
56 error_anticipating_empty_fifo : OUT STD_LOGIC;
56 --error_anticipating_empty_fifo : OUT STD_LOGIC;
57 error_bad_component_error : OUT STD_LOGIC;
57 error_bad_component_error : OUT STD_LOGIC;
58 error_buffer_full : OUT STD_LOGIC;
59 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
60
58 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
61 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
59
62
60 -- Reg In
63 -- Reg In
61 status_ready_matrix_f0_0 : IN STD_LOGIC;
64 status_ready_matrix_f0 : IN STD_LOGIC;
62 status_ready_matrix_f0_1 : IN STD_LOGIC;
65 -- status_ready_matrix_f0_1 : IN STD_LOGIC;
63 status_ready_matrix_f1 : IN STD_LOGIC;
66 status_ready_matrix_f1 : IN STD_LOGIC;
64 status_ready_matrix_f2 : IN STD_LOGIC;
67 status_ready_matrix_f2 : IN STD_LOGIC;
65 status_error_anticipating_empty_fifo : IN STD_LOGIC;
68 -- status_error_anticipating_empty_fifo : IN STD_LOGIC;
66 status_error_bad_component_error : IN STD_LOGIC;
69 -- status_error_bad_component_error : IN STD_LOGIC;
70 -- status_error_buffer_full : IN STD_LOGIC;
67
71
68 config_active_interruption_onNewMatrix : IN STD_LOGIC;
72 config_active_interruption_onNewMatrix : IN STD_LOGIC;
69 config_active_interruption_onError : IN STD_LOGIC;
73 config_active_interruption_onError : IN STD_LOGIC;
70 addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
74 -- addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
71 addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
75 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
72 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
76 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
73 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
77 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
74
78
75 matrix_time_f0_0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
79 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
76 matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
80 -- matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
77 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
81 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
78 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
82 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
79
83
80 );
84 );
81 END;
85 END;
82
86
83 ARCHITECTURE Behavioral OF lpp_lfr_ms IS
87 ARCHITECTURE Behavioral OF lpp_lfr_ms IS
84
88
85 SIGNAL sample_f0_A_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
89 SIGNAL sample_f0_A_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
86 SIGNAL sample_f0_A_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
90 SIGNAL sample_f0_A_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
87 SIGNAL sample_f0_A_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
91 SIGNAL sample_f0_A_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
88 SIGNAL sample_f0_A_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
92 SIGNAL sample_f0_A_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
89 SIGNAL sample_f0_A_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
93 SIGNAL sample_f0_A_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
90
94
91 SIGNAL sample_f0_B_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
95 SIGNAL sample_f0_B_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
92 SIGNAL sample_f0_B_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
96 SIGNAL sample_f0_B_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
93 SIGNAL sample_f0_B_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
97 SIGNAL sample_f0_B_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
94 SIGNAL sample_f0_B_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
98 SIGNAL sample_f0_B_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
95 SIGNAL sample_f0_B_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
99 SIGNAL sample_f0_B_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
96
100
97 SIGNAL sample_f1_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
101 SIGNAL sample_f1_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
98 SIGNAL sample_f1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
102 SIGNAL sample_f1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
99 SIGNAL sample_f1_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
103 SIGNAL sample_f1_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
100 SIGNAL sample_f1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
104 SIGNAL sample_f1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
101
105
102 SIGNAL sample_f1_almost_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
106 SIGNAL sample_f1_almost_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
103
107
104 SIGNAL sample_f2_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
108 SIGNAL sample_f2_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
105 SIGNAL sample_f2_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
109 SIGNAL sample_f2_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
106 SIGNAL sample_f2_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
110 SIGNAL sample_f2_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
107 SIGNAL sample_f2_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
111 SIGNAL sample_f2_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
108
112
109 SIGNAL error_wen_f0 : STD_LOGIC;
113 SIGNAL error_wen_f0 : STD_LOGIC;
110 SIGNAL error_wen_f1 : STD_LOGIC;
114 SIGNAL error_wen_f1 : STD_LOGIC;
111 SIGNAL error_wen_f2 : STD_LOGIC;
115 SIGNAL error_wen_f2 : STD_LOGIC;
112
116
113 SIGNAL one_sample_f1_full : STD_LOGIC;
117 SIGNAL one_sample_f1_full : STD_LOGIC;
114 SIGNAL one_sample_f1_wen : STD_LOGIC;
118 SIGNAL one_sample_f1_wen : STD_LOGIC;
115 SIGNAL one_sample_f2_full : STD_LOGIC;
119 SIGNAL one_sample_f2_full : STD_LOGIC;
116 SIGNAL one_sample_f2_wen : STD_LOGIC;
120 SIGNAL one_sample_f2_wen : STD_LOGIC;
117
121
118 -----------------------------------------------------------------------------
122 -----------------------------------------------------------------------------
119 -- FSM / SWITCH SELECT CHANNEL
123 -- FSM / SWITCH SELECT CHANNEL
120 -----------------------------------------------------------------------------
124 -----------------------------------------------------------------------------
121 TYPE fsm_select_channel IS (IDLE, SWITCH_F0_A, SWITCH_F0_B, SWITCH_F1, SWITCH_F2);
125 TYPE fsm_select_channel IS (IDLE, SWITCH_F0_A, SWITCH_F0_B, SWITCH_F1, SWITCH_F2);
122 SIGNAL state_fsm_select_channel : fsm_select_channel;
126 SIGNAL state_fsm_select_channel : fsm_select_channel;
123 SIGNAL pre_state_fsm_select_channel : fsm_select_channel;
127 SIGNAL pre_state_fsm_select_channel : fsm_select_channel;
124
128
125 SIGNAL sample_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
129 SIGNAL sample_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
126 SIGNAL sample_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
130 SIGNAL sample_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
127 SIGNAL sample_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
131 SIGNAL sample_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
128 SIGNAL sample_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
132 SIGNAL sample_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
129
133
130 -----------------------------------------------------------------------------
134 -----------------------------------------------------------------------------
131 -- FSM LOAD FFT
135 -- FSM LOAD FFT
132 -----------------------------------------------------------------------------
136 -----------------------------------------------------------------------------
133 TYPE fsm_load_FFT IS (IDLE, FIFO_1, FIFO_2, FIFO_3, FIFO_4, FIFO_5);
137 TYPE fsm_load_FFT IS (IDLE, FIFO_1, FIFO_2, FIFO_3, FIFO_4, FIFO_5);
134 SIGNAL state_fsm_load_FFT : fsm_load_FFT;
138 SIGNAL state_fsm_load_FFT : fsm_load_FFT;
135 SIGNAL next_state_fsm_load_FFT : fsm_load_FFT;
139 SIGNAL next_state_fsm_load_FFT : fsm_load_FFT;
136
140
137 SIGNAL sample_ren_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
141 SIGNAL sample_ren_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
138 SIGNAL sample_load : STD_LOGIC;
142 SIGNAL sample_load : STD_LOGIC;
139 SIGNAL sample_valid : STD_LOGIC;
143 SIGNAL sample_valid : STD_LOGIC;
140 SIGNAL sample_valid_r : STD_LOGIC;
144 SIGNAL sample_valid_r : STD_LOGIC;
141 SIGNAL sample_data : STD_LOGIC_VECTOR(15 DOWNTO 0);
145 SIGNAL sample_data : STD_LOGIC_VECTOR(15 DOWNTO 0);
142
146
143
147
144 -----------------------------------------------------------------------------
148 -----------------------------------------------------------------------------
145 -- FFT
149 -- FFT
146 -----------------------------------------------------------------------------
150 -----------------------------------------------------------------------------
147 SIGNAL fft_read : STD_LOGIC;
151 SIGNAL fft_read : STD_LOGIC;
148 SIGNAL fft_pong : STD_LOGIC;
152 SIGNAL fft_pong : STD_LOGIC;
149 SIGNAL fft_data_im : STD_LOGIC_VECTOR(15 DOWNTO 0);
153 SIGNAL fft_data_im : STD_LOGIC_VECTOR(15 DOWNTO 0);
150 SIGNAL fft_data_re : STD_LOGIC_VECTOR(15 DOWNTO 0);
154 SIGNAL fft_data_re : STD_LOGIC_VECTOR(15 DOWNTO 0);
151 SIGNAL fft_data_valid : STD_LOGIC;
155 SIGNAL fft_data_valid : STD_LOGIC;
152 SIGNAL fft_ready : STD_LOGIC;
156 SIGNAL fft_ready : STD_LOGIC;
153 -----------------------------------------------------------------------------
157 -----------------------------------------------------------------------------
154 SIGNAL fft_linker_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
158 SIGNAL fft_linker_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
155 -----------------------------------------------------------------------------
159 -----------------------------------------------------------------------------
156 TYPE fsm_load_MS_memory IS (IDLE, LOAD_FIFO, TRASH_FFT);
160 TYPE fsm_load_MS_memory IS (IDLE, LOAD_FIFO, TRASH_FFT);
157 SIGNAL state_fsm_load_MS_memory : fsm_load_MS_memory;
161 SIGNAL state_fsm_load_MS_memory : fsm_load_MS_memory;
158 SIGNAL current_fifo_load : STD_LOGIC_VECTOR(4 DOWNTO 0);
162 SIGNAL current_fifo_load : STD_LOGIC_VECTOR(4 DOWNTO 0);
159 SIGNAL current_fifo_empty : STD_LOGIC;
163 SIGNAL current_fifo_empty : STD_LOGIC;
160 SIGNAL current_fifo_locked : STD_LOGIC;
164 SIGNAL current_fifo_locked : STD_LOGIC;
161 SIGNAL current_fifo_full : STD_LOGIC;
165 SIGNAL current_fifo_full : STD_LOGIC;
162 SIGNAL MEM_IN_SM_locked : STD_LOGIC_VECTOR(4 DOWNTO 0);
166 SIGNAL MEM_IN_SM_locked : STD_LOGIC_VECTOR(4 DOWNTO 0);
163
167
164 -----------------------------------------------------------------------------
168 -----------------------------------------------------------------------------
165 SIGNAL MEM_IN_SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
169 SIGNAL MEM_IN_SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
166 SIGNAL MEM_IN_SM_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
170 SIGNAL MEM_IN_SM_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
167 SIGNAL MEM_IN_SM_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
171 SIGNAL MEM_IN_SM_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
168 SIGNAL MEM_IN_SM_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
172 SIGNAL MEM_IN_SM_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
169 SIGNAL MEM_IN_SM_wData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
173 SIGNAL MEM_IN_SM_wData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
170 SIGNAL MEM_IN_SM_rData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
174 SIGNAL MEM_IN_SM_rData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
171 SIGNAL MEM_IN_SM_Full : STD_LOGIC_VECTOR(4 DOWNTO 0);
175 SIGNAL MEM_IN_SM_Full : STD_LOGIC_VECTOR(4 DOWNTO 0);
172 SIGNAL MEM_IN_SM_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
176 SIGNAL MEM_IN_SM_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
173 -----------------------------------------------------------------------------
177 -----------------------------------------------------------------------------
178 SIGNAL SM_in_data : STD_LOGIC_VECTOR(32*2-1 DOWNTO 0);
179 SIGNAL SM_in_ren : STD_LOGIC_VECTOR(1 DOWNTO 0);
180 SIGNAL SM_in_empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
181
182 SIGNAL SM_correlation_start : STD_LOGIC;
183 SIGNAL SM_correlation_auto : STD_LOGIC;
184 SIGNAL SM_correlation_done : STD_LOGIC;
185 SIGNAL SM_correlation_done_reg1 : STD_LOGIC;
186 SIGNAL SM_correlation_done_reg2 : STD_LOGIC;
187 SIGNAL SM_correlation_begin : STD_LOGIC;
188
189 SIGNAL temp_ongoing : STD_LOGIC;
190 SIGNAL temp_auto : STD_LOGIC;
191
192 SIGNAL MEM_OUT_SM_Full_s : STD_LOGIC;
193 SIGNAL MEM_OUT_SM_Data_in_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
194 SIGNAL MEM_OUT_SM_Write_s : STD_LOGIC;
195
196 SIGNAL current_matrix_write : STD_LOGIC;
197 SIGNAL current_matrix_wait_empty : STD_LOGIC;
198
199 --SIGNAL MEM_OUT_SM_BURST_available : STD_LOGIC_VECTOR(1 DOWNTO 0);
200
201 -----------------------------------------------------------------------------
202 SIGNAL fifo_0_ready : STD_LOGIC;
203 SIGNAL fifo_1_ready : STD_LOGIC;
204 SIGNAL fifo_ongoing : STD_LOGIC;
205
206 SIGNAL FSM_DMA_fifo_ren : STD_LOGIC;
207 SIGNAL FSM_DMA_fifo_empty : STD_LOGIC;
208 SIGNAL FSM_DMA_fifo_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
209 SIGNAL FSM_DMA_fifo_status : STD_LOGIC_VECTOR(53 DOWNTO 0);
210
211 -----------------------------------------------------------------------------
174 SIGNAL HEAD_SM_Param : STD_LOGIC_VECTOR(3 DOWNTO 0);
212 SIGNAL HEAD_SM_Param : STD_LOGIC_VECTOR(3 DOWNTO 0);
175 SIGNAL HEAD_WorkFreq : STD_LOGIC_VECTOR(1 DOWNTO 0);
213 SIGNAL HEAD_WorkFreq : STD_LOGIC_VECTOR(1 DOWNTO 0);
176 SIGNAL HEAD_SM_Wen : STD_LOGIC;
214 SIGNAL HEAD_SM_Wen : STD_LOGIC;
177 SIGNAL HEAD_Valid : STD_LOGIC;
215 SIGNAL HEAD_Valid : STD_LOGIC;
178 SIGNAL HEAD_Data : STD_LOGIC_VECTOR(31 DOWNTO 0);
216 SIGNAL HEAD_Data : STD_LOGIC_VECTOR(31 DOWNTO 0);
179 SIGNAL HEAD_Empty : STD_LOGIC;
217 SIGNAL HEAD_Empty : STD_LOGIC;
180 SIGNAL HEAD_Read : STD_LOGIC;
218 SIGNAL HEAD_Read : STD_LOGIC;
181 -----------------------------------------------------------------------------
219 -----------------------------------------------------------------------------
182 SIGNAL MEM_OUT_SM_ReUse : STD_LOGIC_VECTOR(1 DOWNTO 0);
220 SIGNAL MEM_OUT_SM_ReUse : STD_LOGIC_VECTOR(1 DOWNTO 0);
183 SIGNAL MEM_OUT_SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0);
221 SIGNAL MEM_OUT_SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0);
184 SIGNAL MEM_OUT_SM_Read : STD_LOGIC_VECTOR(1 DOWNTO 0);
222 SIGNAL MEM_OUT_SM_Read : STD_LOGIC_VECTOR(1 DOWNTO 0);
185 SIGNAL MEM_OUT_SM_Data_in : STD_LOGIC_VECTOR(63 DOWNTO 0);
223 SIGNAL MEM_OUT_SM_Data_in : STD_LOGIC_VECTOR(63 DOWNTO 0);
186 SIGNAL MEM_OUT_SM_Data_out : STD_LOGIC_VECTOR(63 DOWNTO 0);
224 SIGNAL MEM_OUT_SM_Data_out : STD_LOGIC_VECTOR(63 DOWNTO 0);
187 SIGNAL MEM_OUT_SM_Full : STD_LOGIC_VECTOR(1 DOWNTO 0);
225 SIGNAL MEM_OUT_SM_Full : STD_LOGIC_VECTOR(1 DOWNTO 0);
188 SIGNAL MEM_OUT_SM_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
226 SIGNAL MEM_OUT_SM_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
189 -----------------------------------------------------------------------------
227 -----------------------------------------------------------------------------
190 SIGNAL DMA_Header : STD_LOGIC_VECTOR(31 DOWNTO 0);
228 SIGNAL DMA_Header : STD_LOGIC_VECTOR(31 DOWNTO 0);
191 SIGNAL DMA_Header_Val : STD_LOGIC;
229 SIGNAL DMA_Header_Val : STD_LOGIC;
192 SIGNAL DMA_Header_Ack : STD_LOGIC;
230 SIGNAL DMA_Header_Ack : STD_LOGIC;
193
231
194 -----------------------------------------------------------------------------
232 -----------------------------------------------------------------------------
195 -- TIME REG & INFOs
233 -- TIME REG & INFOs
196 -----------------------------------------------------------------------------
234 -----------------------------------------------------------------------------
197 SIGNAL all_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
235 SIGNAL all_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
198
236
199 SIGNAL time_reg_f0_A : STD_LOGIC_VECTOR(47 DOWNTO 0);
237 SIGNAL time_reg_f0_A : STD_LOGIC_VECTOR(47 DOWNTO 0);
200 SIGNAL time_reg_f0_B : STD_LOGIC_VECTOR(47 DOWNTO 0);
238 SIGNAL time_reg_f0_B : STD_LOGIC_VECTOR(47 DOWNTO 0);
201 SIGNAL time_reg_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
239 SIGNAL time_reg_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
202 SIGNAL time_reg_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
240 SIGNAL time_reg_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
203
241
204 SIGNAL time_update_f0_A : STD_LOGIC;
242 SIGNAL time_update_f0_A : STD_LOGIC;
205 SIGNAL time_update_f0_B : STD_LOGIC;
243 SIGNAL time_update_f0_B : STD_LOGIC;
206 SIGNAL time_update_f1 : STD_LOGIC;
244 SIGNAL time_update_f1 : STD_LOGIC;
207 SIGNAL time_update_f2 : STD_LOGIC;
245 SIGNAL time_update_f2 : STD_LOGIC;
208 --
246 --
209 SIGNAL status_channel : STD_LOGIC_VECTOR(49 DOWNTO 0);
247 SIGNAL status_channel : STD_LOGIC_VECTOR(49 DOWNTO 0);
248 SIGNAL status_MS_input : STD_LOGIC_VECTOR(49 DOWNTO 0);
249 SIGNAL status_component : STD_LOGIC_VECTOR(53 DOWNTO 0);
250
251 SIGNAL status_component_fifo_0 : STD_LOGIC_VECTOR(53 DOWNTO 0);
252 SIGNAL status_component_fifo_1 : STD_LOGIC_VECTOR(53 DOWNTO 0);
253 SIGNAL status_component_fifo_0_new : STD_LOGIC;
254 SIGNAL status_component_fifo_1_new : STD_LOGIC;
255 SIGNAL status_component_fifo_0_end : STD_LOGIC;
256 SIGNAL status_component_fifo_1_end : STD_LOGIC;
210
257
211 SIGNAL dma_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
258 SIGNAL dma_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
212 -----------------------------------------------------------------------------
259 -----------------------------------------------------------------------------
213
260
214 BEGIN
261 BEGIN
215
262
263
264 error_input_fifo_write <= error_wen_f2 & error_wen_f1 & error_wen_f0;
265
266
216 switch_f0_inst : spectral_matrix_switch_f0
267 switch_f0_inst : spectral_matrix_switch_f0
217 PORT MAP (
268 PORT MAP (
218 clk => clk,
269 clk => clk,
219 rstn => rstn,
270 rstn => rstn,
220
271
221 sample_wen => sample_f0_wen,
272 sample_wen => sample_f0_wen,
222
273
223 fifo_A_empty => sample_f0_A_empty,
274 fifo_A_empty => sample_f0_A_empty,
224 fifo_A_full => sample_f0_A_full,
275 fifo_A_full => sample_f0_A_full,
225 fifo_A_wen => sample_f0_A_wen,
276 fifo_A_wen => sample_f0_A_wen,
226
277
227 fifo_B_empty => sample_f0_B_empty,
278 fifo_B_empty => sample_f0_B_empty,
228 fifo_B_full => sample_f0_B_full,
279 fifo_B_full => sample_f0_B_full,
229 fifo_B_wen => sample_f0_B_wen,
280 fifo_B_wen => sample_f0_B_wen,
230
281
231 error_wen => error_wen_f0); -- TODO
282 error_wen => error_wen_f0); -- TODO
232
283
233 -----------------------------------------------------------------------------
284 -----------------------------------------------------------------------------
234 -- FIFO IN
285 -- FIFO IN
235 -----------------------------------------------------------------------------
286 -----------------------------------------------------------------------------
236 lppFIFOxN_f0_a : lppFIFOxN
287 lppFIFOxN_f0_a : lppFIFOxN
237 GENERIC MAP (
288 GENERIC MAP (
238 tech => 0,
289 tech => 0,
239 Mem_use => Mem_use,
290 Mem_use => Mem_use,
240 Data_sz => 16,
291 Data_sz => 16,
241 Addr_sz => 8,
292 Addr_sz => 8,
242 FifoCnt => 5)
293 FifoCnt => 5)
243 PORT MAP (
294 PORT MAP (
244 clk => clk,
295 clk => clk,
245 rstn => rstn,
296 rstn => rstn,
246
297
247 ReUse => (OTHERS => '0'),
298 ReUse => (OTHERS => '0'),
248
299
249 wen => sample_f0_A_wen,
300 wen => sample_f0_A_wen,
250 wdata => sample_f0_wdata,
301 wdata => sample_f0_wdata,
251
302
252 ren => sample_f0_A_ren,
303 ren => sample_f0_A_ren,
253 rdata => sample_f0_A_rdata,
304 rdata => sample_f0_A_rdata,
254
305
255 empty => sample_f0_A_empty,
306 empty => sample_f0_A_empty,
256 full => sample_f0_A_full,
307 full => sample_f0_A_full,
257 almost_full => OPEN);
308 almost_full => OPEN);
258
309
259 lppFIFOxN_f0_b : lppFIFOxN
310 lppFIFOxN_f0_b : lppFIFOxN
260 GENERIC MAP (
311 GENERIC MAP (
261 tech => 0,
312 tech => 0,
262 Mem_use => Mem_use,
313 Mem_use => Mem_use,
263 Data_sz => 16,
314 Data_sz => 16,
264 Addr_sz => 8,
315 Addr_sz => 8,
265 FifoCnt => 5)
316 FifoCnt => 5)
266 PORT MAP (
317 PORT MAP (
267 clk => clk,
318 clk => clk,
268 rstn => rstn,
319 rstn => rstn,
269
320
270 ReUse => (OTHERS => '0'),
321 ReUse => (OTHERS => '0'),
271
322
272 wen => sample_f0_B_wen,
323 wen => sample_f0_B_wen,
273 wdata => sample_f0_wdata,
324 wdata => sample_f0_wdata,
274 ren => sample_f0_B_ren,
325 ren => sample_f0_B_ren,
275 rdata => sample_f0_B_rdata,
326 rdata => sample_f0_B_rdata,
276 empty => sample_f0_B_empty,
327 empty => sample_f0_B_empty,
277 full => sample_f0_B_full,
328 full => sample_f0_B_full,
278 almost_full => OPEN);
329 almost_full => OPEN);
279
330
280 lppFIFOxN_f1 : lppFIFOxN
331 lppFIFOxN_f1 : lppFIFOxN
281 GENERIC MAP (
332 GENERIC MAP (
282 tech => 0,
333 tech => 0,
283 Mem_use => Mem_use,
334 Mem_use => Mem_use,
284 Data_sz => 16,
335 Data_sz => 16,
285 Addr_sz => 8,
336 Addr_sz => 8,
286 FifoCnt => 5)
337 FifoCnt => 5)
287 PORT MAP (
338 PORT MAP (
288 clk => clk,
339 clk => clk,
289 rstn => rstn,
340 rstn => rstn,
290
341
291 ReUse => (OTHERS => '0'),
342 ReUse => (OTHERS => '0'),
292
343
293 wen => sample_f1_wen,
344 wen => sample_f1_wen,
294 wdata => sample_f1_wdata,
345 wdata => sample_f1_wdata,
295 ren => sample_f1_ren,
346 ren => sample_f1_ren,
296 rdata => sample_f1_rdata,
347 rdata => sample_f1_rdata,
297 empty => sample_f1_empty,
348 empty => sample_f1_empty,
298 full => sample_f1_full,
349 full => sample_f1_full,
299 almost_full => sample_f1_almost_full);
350 almost_full => sample_f1_almost_full);
300
351
301
352
302 one_sample_f1_wen <= '0' WHEN sample_f1_wen = "11111" ELSE '1';
353 one_sample_f1_wen <= '0' WHEN sample_f1_wen = "11111" ELSE '1';
303
354
304 PROCESS (clk, rstn)
355 PROCESS (clk, rstn)
305 BEGIN -- PROCESS
356 BEGIN -- PROCESS
306 IF rstn = '0' THEN -- asynchronous reset (active low)
357 IF rstn = '0' THEN -- asynchronous reset (active low)
307 one_sample_f1_full <= '0';
358 one_sample_f1_full <= '0';
308 error_wen_f1 <= '0';
359 error_wen_f1 <= '0';
309 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
360 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
310 IF sample_f1_full = "00000" THEN
361 IF sample_f1_full = "00000" THEN
311 one_sample_f1_full <= '0';
362 one_sample_f1_full <= '0';
312 ELSE
363 ELSE
313 one_sample_f1_full <= '1';
364 one_sample_f1_full <= '1';
314 END IF;
365 END IF;
315 error_wen_f1 <= one_sample_f1_wen AND one_sample_f1_full;
366 error_wen_f1 <= one_sample_f1_wen AND one_sample_f1_full;
316 END IF;
367 END IF;
317 END PROCESS;
368 END PROCESS;
318
369
319
370
320 lppFIFOxN_f2 : lppFIFOxN
371 lppFIFOxN_f2 : lppFIFOxN
321 GENERIC MAP (
372 GENERIC MAP (
322 tech => 0,
373 tech => 0,
323 Mem_use => Mem_use,
374 Mem_use => Mem_use,
324 Data_sz => 16,
375 Data_sz => 16,
325 Addr_sz => 8,
376 Addr_sz => 8,
326 FifoCnt => 5)
377 FifoCnt => 5)
327 PORT MAP (
378 PORT MAP (
328 clk => clk,
379 clk => clk,
329 rstn => rstn,
380 rstn => rstn,
330
381
331 ReUse => (OTHERS => '0'),
382 ReUse => (OTHERS => '0'),
332
383
333 wen => sample_f2_wen,
384 wen => sample_f2_wen,
334 wdata => sample_f2_wdata,
385 wdata => sample_f2_wdata,
335 ren => sample_f2_ren,
386 ren => sample_f2_ren,
336 rdata => sample_f2_rdata,
387 rdata => sample_f2_rdata,
337 empty => sample_f2_empty,
388 empty => sample_f2_empty,
338 full => sample_f2_full,
389 full => sample_f2_full,
339 almost_full => OPEN);
390 almost_full => OPEN);
340
391
341
392
342 one_sample_f2_wen <= '0' WHEN sample_f2_wen = "11111" ELSE '1';
393 one_sample_f2_wen <= '0' WHEN sample_f2_wen = "11111" ELSE '1';
343
394
344 PROCESS (clk, rstn)
395 PROCESS (clk, rstn)
345 BEGIN -- PROCESS
396 BEGIN -- PROCESS
346 IF rstn = '0' THEN -- asynchronous reset (active low)
397 IF rstn = '0' THEN -- asynchronous reset (active low)
347 one_sample_f2_full <= '0';
398 one_sample_f2_full <= '0';
348 error_wen_f2 <= '0';
399 error_wen_f2 <= '0';
349 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
400 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
350 IF sample_f2_full = "00000" THEN
401 IF sample_f2_full = "00000" THEN
351 one_sample_f2_full <= '0';
402 one_sample_f2_full <= '0';
352 ELSE
403 ELSE
353 one_sample_f2_full <= '1';
404 one_sample_f2_full <= '1';
354 END IF;
405 END IF;
355 error_wen_f2 <= one_sample_f2_wen AND one_sample_f2_full;
406 error_wen_f2 <= one_sample_f2_wen AND one_sample_f2_full;
356 END IF;
407 END IF;
357 END PROCESS;
408 END PROCESS;
358
409
359 -----------------------------------------------------------------------------
410 -----------------------------------------------------------------------------
360 -- FSM SELECT CHANNEL
411 -- FSM SELECT CHANNEL
361 -----------------------------------------------------------------------------
412 -----------------------------------------------------------------------------
362 PROCESS (clk, rstn)
413 PROCESS (clk, rstn)
363 BEGIN
414 BEGIN
364 IF rstn = '0' THEN
415 IF rstn = '0' THEN
365 state_fsm_select_channel <= IDLE;
416 state_fsm_select_channel <= IDLE;
366 ELSIF clk'EVENT AND clk = '1' THEN
417 ELSIF clk'EVENT AND clk = '1' THEN
367 CASE state_fsm_select_channel IS
418 CASE state_fsm_select_channel IS
368 WHEN IDLE =>
419 WHEN IDLE =>
369 IF sample_f1_full = "11111" THEN
420 IF sample_f1_full = "11111" THEN
370 state_fsm_select_channel <= SWITCH_F1;
421 state_fsm_select_channel <= SWITCH_F1;
371 ELSIF sample_f1_almost_full = "00000" THEN
422 ELSIF sample_f1_almost_full = "00000" THEN
372 IF sample_f0_A_full = "11111" THEN
423 IF sample_f0_A_full = "11111" THEN
373 state_fsm_select_channel <= SWITCH_F0_A;
424 state_fsm_select_channel <= SWITCH_F0_A;
374 ELSIF sample_f0_B_full = "11111" THEN
425 ELSIF sample_f0_B_full = "11111" THEN
375 state_fsm_select_channel <= SWITCH_F0_B;
426 state_fsm_select_channel <= SWITCH_F0_B;
376 ELSIF sample_f2_full = "11111" THEN
427 ELSIF sample_f2_full = "11111" THEN
377 state_fsm_select_channel <= SWITCH_F2;
428 state_fsm_select_channel <= SWITCH_F2;
378 END IF;
429 END IF;
379 END IF;
430 END IF;
380
431
381 WHEN SWITCH_F0_A =>
432 WHEN SWITCH_F0_A =>
382 IF sample_f0_A_empty = "11111" THEN
433 IF sample_f0_A_empty = "11111" THEN
383 state_fsm_select_channel <= IDLE;
434 state_fsm_select_channel <= IDLE;
384 END IF;
435 END IF;
385 WHEN SWITCH_F0_B =>
436 WHEN SWITCH_F0_B =>
386 IF sample_f0_B_empty = "11111" THEN
437 IF sample_f0_B_empty = "11111" THEN
387 state_fsm_select_channel <= IDLE;
438 state_fsm_select_channel <= IDLE;
388 END IF;
439 END IF;
389 WHEN SWITCH_F1 =>
440 WHEN SWITCH_F1 =>
390 IF sample_f1_empty = "11111" THEN
441 IF sample_f1_empty = "11111" THEN
391 state_fsm_select_channel <= IDLE;
442 state_fsm_select_channel <= IDLE;
392 END IF;
443 END IF;
393 WHEN SWITCH_F2 =>
444 WHEN SWITCH_F2 =>
394 IF sample_f2_empty = "11111" THEN
445 IF sample_f2_empty = "11111" THEN
395 state_fsm_select_channel <= IDLE;
446 state_fsm_select_channel <= IDLE;
396 END IF;
447 END IF;
397 WHEN OTHERS => NULL;
448 WHEN OTHERS => NULL;
398 END CASE;
449 END CASE;
399
450
400 END IF;
451 END IF;
401 END PROCESS;
452 END PROCESS;
402
453
403 PROCESS (clk, rstn)
454 PROCESS (clk, rstn)
404 BEGIN
455 BEGIN
405 IF rstn = '0' THEN
456 IF rstn = '0' THEN
406 pre_state_fsm_select_channel <= IDLE;
457 pre_state_fsm_select_channel <= IDLE;
407 ELSIF clk'EVENT AND clk = '1' THEN
458 ELSIF clk'EVENT AND clk = '1' THEN
408 pre_state_fsm_select_channel <= state_fsm_select_channel;
459 pre_state_fsm_select_channel <= state_fsm_select_channel;
409 END IF;
460 END IF;
410 END PROCESS;
461 END PROCESS;
411
462
412
463
413 -----------------------------------------------------------------------------
464 -----------------------------------------------------------------------------
414 -- SWITCH SELECT CHANNEL
465 -- SWITCH SELECT CHANNEL
415 -----------------------------------------------------------------------------
466 -----------------------------------------------------------------------------
416 sample_empty <= sample_f0_A_empty WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
467 sample_empty <= sample_f0_A_empty WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
417 sample_f0_B_empty WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
468 sample_f0_B_empty WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
418 sample_f1_empty WHEN state_fsm_select_channel = SWITCH_F1 ELSE
469 sample_f1_empty WHEN state_fsm_select_channel = SWITCH_F1 ELSE
419 sample_f2_empty WHEN state_fsm_select_channel = SWITCH_F2 ELSE
470 sample_f2_empty WHEN state_fsm_select_channel = SWITCH_F2 ELSE
420 (OTHERS => '1');
471 (OTHERS => '1');
421
472
422 sample_full <= sample_f0_A_full WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
473 sample_full <= sample_f0_A_full WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
423 sample_f0_B_full WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
474 sample_f0_B_full WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
424 sample_f1_full WHEN state_fsm_select_channel = SWITCH_F1 ELSE
475 sample_f1_full WHEN state_fsm_select_channel = SWITCH_F1 ELSE
425 sample_f2_full WHEN state_fsm_select_channel = SWITCH_F2 ELSE
476 sample_f2_full WHEN state_fsm_select_channel = SWITCH_F2 ELSE
426 (OTHERS => '0');
477 (OTHERS => '0');
427
478
428 sample_rdata <= sample_f0_A_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_A ELSE
479 sample_rdata <= sample_f0_A_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_A ELSE
429 sample_f0_B_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_B ELSE
480 sample_f0_B_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_B ELSE
430 sample_f1_rdata WHEN pre_state_fsm_select_channel = SWITCH_F1 ELSE
481 sample_f1_rdata WHEN pre_state_fsm_select_channel = SWITCH_F1 ELSE
431 sample_f2_rdata; -- WHEN state_fsm_select_channel = SWITCH_F2 ELSE
482 sample_f2_rdata; -- WHEN state_fsm_select_channel = SWITCH_F2 ELSE
432
483
433
484
434 sample_f0_A_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_A ELSE (OTHERS => '1');
485 sample_f0_A_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_A ELSE (OTHERS => '1');
435 sample_f0_B_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_B ELSE (OTHERS => '1');
486 sample_f0_B_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_B ELSE (OTHERS => '1');
436 sample_f1_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F1 ELSE (OTHERS => '1');
487 sample_f1_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F1 ELSE (OTHERS => '1');
437 sample_f2_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F2 ELSE (OTHERS => '1');
488 sample_f2_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F2 ELSE (OTHERS => '1');
438
489
439
490
440 status_channel <= time_reg_f0_A & "00" WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
491 status_channel <= time_reg_f0_A & "00" WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
441 time_reg_f0_B & "00" WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
492 time_reg_f0_B & "00" WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
442 time_reg_f1 & "01" WHEN state_fsm_select_channel = SWITCH_F1 ELSE
493 time_reg_f1 & "01" WHEN state_fsm_select_channel = SWITCH_F1 ELSE
443 time_reg_f2 & "10"; -- WHEN state_fsm_select_channel = SWITCH_F2
494 time_reg_f2 & "10"; -- WHEN state_fsm_select_channel = SWITCH_F2
444
495
445 -----------------------------------------------------------------------------
496 -----------------------------------------------------------------------------
446 -- FSM LOAD FFT
497 -- FSM LOAD FFT
447 -----------------------------------------------------------------------------
498 -----------------------------------------------------------------------------
448
499
449 sample_ren <= sample_ren_s WHEN sample_load = '1' ELSE (OTHERS => '1');
500 sample_ren <= sample_ren_s WHEN sample_load = '1' ELSE (OTHERS => '1');
450
501
451 PROCESS (clk, rstn)
502 PROCESS (clk, rstn)
452 BEGIN
503 BEGIN
453 IF rstn = '0' THEN
504 IF rstn = '0' THEN
454 sample_ren_s <= (OTHERS => '1');
505 sample_ren_s <= (OTHERS => '1');
455 state_fsm_load_FFT <= IDLE;
506 state_fsm_load_FFT <= IDLE;
507 status_MS_input <= (OTHERS => '0');
456 --next_state_fsm_load_FFT <= IDLE;
508 --next_state_fsm_load_FFT <= IDLE;
457 --sample_valid <= '0';
509 --sample_valid <= '0';
458 ELSIF clk'EVENT AND clk = '1' THEN
510 ELSIF clk'EVENT AND clk = '1' THEN
459 CASE state_fsm_load_FFT IS
511 CASE state_fsm_load_FFT IS
460 WHEN IDLE =>
512 WHEN IDLE =>
461 --sample_valid <= '0';
513 --sample_valid <= '0';
462 sample_ren_s <= (OTHERS => '1');
514 sample_ren_s <= (OTHERS => '1');
463 IF sample_full = "11111" AND sample_load = '1' THEN
515 IF sample_full = "11111" AND sample_load = '1' THEN
464 state_fsm_load_FFT <= FIFO_1;
516 state_fsm_load_FFT <= FIFO_1;
517 status_MS_input <= status_channel;
465 END IF;
518 END IF;
466
519
467 WHEN FIFO_1 =>
520 WHEN FIFO_1 =>
468 sample_ren_s <= "1111" & NOT(sample_load);
521 sample_ren_s <= "1111" & NOT(sample_load);
469 IF sample_empty(0) = '1' THEN
522 IF sample_empty(0) = '1' THEN
470 sample_ren_s <= (OTHERS => '1');
523 sample_ren_s <= (OTHERS => '1');
471 state_fsm_load_FFT <= FIFO_2;
524 state_fsm_load_FFT <= FIFO_2;
472 END IF;
525 END IF;
473
526
474 WHEN FIFO_2 =>
527 WHEN FIFO_2 =>
475 sample_ren_s <= "111" & NOT(sample_load) & '1';
528 sample_ren_s <= "111" & NOT(sample_load) & '1';
476 IF sample_empty(1) = '1' THEN
529 IF sample_empty(1) = '1' THEN
477 sample_ren_s <= (OTHERS => '1');
530 sample_ren_s <= (OTHERS => '1');
478 state_fsm_load_FFT <= FIFO_3;
531 state_fsm_load_FFT <= FIFO_3;
479 END IF;
532 END IF;
480
533
481 WHEN FIFO_3 =>
534 WHEN FIFO_3 =>
482 sample_ren_s <= "11" & NOT(sample_load) & "11";
535 sample_ren_s <= "11" & NOT(sample_load) & "11";
483 IF sample_empty(2) = '1' THEN
536 IF sample_empty(2) = '1' THEN
484 sample_ren_s <= (OTHERS => '1');
537 sample_ren_s <= (OTHERS => '1');
485 state_fsm_load_FFT <= FIFO_4;
538 state_fsm_load_FFT <= FIFO_4;
486 END IF;
539 END IF;
487
540
488 WHEN FIFO_4 =>
541 WHEN FIFO_4 =>
489 sample_ren_s <= '1' & NOT(sample_load) & "111";
542 sample_ren_s <= '1' & NOT(sample_load) & "111";
490 IF sample_empty(3) = '1' THEN
543 IF sample_empty(3) = '1' THEN
491 sample_ren_s <= (OTHERS => '1');
544 sample_ren_s <= (OTHERS => '1');
492 state_fsm_load_FFT <= FIFO_5;
545 state_fsm_load_FFT <= FIFO_5;
493 END IF;
546 END IF;
494
547
495 WHEN FIFO_5 =>
548 WHEN FIFO_5 =>
496 sample_ren_s <= NOT(sample_load) & "1111";
549 sample_ren_s <= NOT(sample_load) & "1111";
497 IF sample_empty(4) = '1' THEN
550 IF sample_empty(4) = '1' THEN
498 sample_ren_s <= (OTHERS => '1');
551 sample_ren_s <= (OTHERS => '1');
499 state_fsm_load_FFT <= IDLE;
552 state_fsm_load_FFT <= IDLE;
500 END IF;
553 END IF;
501 WHEN OTHERS => NULL;
554 WHEN OTHERS => NULL;
502 END CASE;
555 END CASE;
503 END IF;
556 END IF;
504 END PROCESS;
557 END PROCESS;
505
558
506 PROCESS (clk, rstn)
559 PROCESS (clk, rstn)
507 BEGIN
560 BEGIN
508 IF rstn = '0' THEN
561 IF rstn = '0' THEN
509 sample_valid_r <= '0';
562 sample_valid_r <= '0';
510 next_state_fsm_load_FFT <= IDLE;
563 next_state_fsm_load_FFT <= IDLE;
511 ELSIF clk'EVENT AND clk = '1' THEN
564 ELSIF clk'EVENT AND clk = '1' THEN
512 next_state_fsm_load_FFT <= state_fsm_load_FFT;
565 next_state_fsm_load_FFT <= state_fsm_load_FFT;
513 IF sample_ren_s = "11111" THEN
566 IF sample_ren_s = "11111" THEN
514 sample_valid_r <= '0';
567 sample_valid_r <= '0';
515 ELSE
568 ELSE
516 sample_valid_r <= '1';
569 sample_valid_r <= '1';
517 END IF;
570 END IF;
518 END IF;
571 END IF;
519 END PROCESS;
572 END PROCESS;
520
573
521 sample_valid <= sample_valid_r AND sample_load;
574 sample_valid <= sample_valid_r AND sample_load;
522
575
523 sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN next_state_fsm_load_FFT = FIFO_1 ELSE
576 sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN next_state_fsm_load_FFT = FIFO_1 ELSE
524 sample_rdata(16*2-1 DOWNTO 16*1) WHEN next_state_fsm_load_FFT = FIFO_2 ELSE
577 sample_rdata(16*2-1 DOWNTO 16*1) WHEN next_state_fsm_load_FFT = FIFO_2 ELSE
525 sample_rdata(16*3-1 DOWNTO 16*2) WHEN next_state_fsm_load_FFT = FIFO_3 ELSE
578 sample_rdata(16*3-1 DOWNTO 16*2) WHEN next_state_fsm_load_FFT = FIFO_3 ELSE
526 sample_rdata(16*4-1 DOWNTO 16*3) WHEN next_state_fsm_load_FFT = FIFO_4 ELSE
579 sample_rdata(16*4-1 DOWNTO 16*3) WHEN next_state_fsm_load_FFT = FIFO_4 ELSE
527 sample_rdata(16*5-1 DOWNTO 16*4); --WHEN next_state_fsm_load_FFT = FIFO_5 ELSE
580 sample_rdata(16*5-1 DOWNTO 16*4); --WHEN next_state_fsm_load_FFT = FIFO_5 ELSE
528
581
529 -----------------------------------------------------------------------------
582 -----------------------------------------------------------------------------
530 -- FFT
583 -- FFT
531 -----------------------------------------------------------------------------
584 -----------------------------------------------------------------------------
532 CoreFFT_1 : CoreFFT
585 CoreFFT_1 : CoreFFT
533 GENERIC MAP (
586 GENERIC MAP (
534 LOGPTS => gLOGPTS,
587 LOGPTS => gLOGPTS,
535 LOGLOGPTS => gLOGLOGPTS,
588 LOGLOGPTS => gLOGLOGPTS,
536 WSIZE => gWSIZE,
589 WSIZE => gWSIZE,
537 TWIDTH => gTWIDTH,
590 TWIDTH => gTWIDTH,
538 DWIDTH => gDWIDTH,
591 DWIDTH => gDWIDTH,
539 TDWIDTH => gTDWIDTH,
592 TDWIDTH => gTDWIDTH,
540 RND_MODE => gRND_MODE,
593 RND_MODE => gRND_MODE,
541 SCALE_MODE => gSCALE_MODE,
594 SCALE_MODE => gSCALE_MODE,
542 PTS => gPTS,
595 PTS => gPTS,
543 HALFPTS => gHALFPTS,
596 HALFPTS => gHALFPTS,
544 inBuf_RWDLY => gInBuf_RWDLY)
597 inBuf_RWDLY => gInBuf_RWDLY)
545 PORT MAP (
598 PORT MAP (
546 clk => clk,
599 clk => clk,
547 ifiStart => '1',
600 ifiStart => '1',
548 ifiNreset => rstn,
601 ifiNreset => rstn,
549
602
550 ifiD_valid => sample_valid, -- IN
603 ifiD_valid => sample_valid, -- IN
551 ifiRead_y => fft_read,
604 ifiRead_y => fft_read,
552 ifiD_im => (OTHERS => '0'), -- IN
605 ifiD_im => (OTHERS => '0'), -- IN
553 ifiD_re => sample_data, -- IN
606 ifiD_re => sample_data, -- IN
554 ifoLoad => sample_load, -- IN
607 ifoLoad => sample_load, -- IN
555
608
556 ifoPong => fft_pong,
609 ifoPong => fft_pong,
557 ifoY_im => fft_data_im,
610 ifoY_im => fft_data_im,
558 ifoY_re => fft_data_re,
611 ifoY_re => fft_data_re,
559 ifoY_valid => fft_data_valid,
612 ifoY_valid => fft_data_valid,
560 ifoY_rdy => fft_ready);
613 ifoY_rdy => fft_ready);
561
614
562 -----------------------------------------------------------------------------
615 -----------------------------------------------------------------------------
563 -- in fft_data_im & fft_data_re
616 -- in fft_data_im & fft_data_re
564 -- in fft_data_valid
617 -- in fft_data_valid
565 -- in fft_ready
618 -- in fft_ready
566 -- out fft_read
619 -- out fft_read
567 PROCESS (clk, rstn)
620 PROCESS (clk, rstn)
568 BEGIN
621 BEGIN
569 IF rstn = '0' THEN
622 IF rstn = '0' THEN
570 state_fsm_load_MS_memory <= IDLE;
623 state_fsm_load_MS_memory <= IDLE;
571 current_fifo_load <= "00001";
624 current_fifo_load <= "00001";
572 ELSIF clk'event AND clk = '1' THEN
625 ELSIF clk'event AND clk = '1' THEN
573 CASE state_fsm_load_MS_memory IS
626 CASE state_fsm_load_MS_memory IS
574 WHEN IDLE =>
627 WHEN IDLE =>
575 IF current_fifo_empty = '1' AND fft_ready = '1' AND current_fifo_locked = '0' THEN
628 IF current_fifo_empty = '1' AND fft_ready = '1' AND current_fifo_locked = '0' THEN
576 state_fsm_load_MS_memory <= LOAD_FIFO;
629 state_fsm_load_MS_memory <= LOAD_FIFO;
577 END IF;
630 END IF;
578 WHEN LOAD_FIFO =>
631 WHEN LOAD_FIFO =>
579 IF current_fifo_full = '1' THEN
632 IF current_fifo_full = '1' THEN
580 state_fsm_load_MS_memory <= TRASH_FFT;
633 state_fsm_load_MS_memory <= TRASH_FFT;
581 END IF;
634 END IF;
582 WHEN TRASH_FFT =>
635 WHEN TRASH_FFT =>
583 IF fft_ready = '0' THEN
636 IF fft_ready = '0' THEN
584 state_fsm_load_MS_memory <= IDLE;
637 state_fsm_load_MS_memory <= IDLE;
585 current_fifo_load <= current_fifo_load(3 DOWNTO 0) & current_fifo_load(4);
638 current_fifo_load <= current_fifo_load(3 DOWNTO 0) & current_fifo_load(4);
586 END IF;
639 END IF;
587 WHEN OTHERS => NULL;
640 WHEN OTHERS => NULL;
588 END CASE;
641 END CASE;
589
642
590 END IF;
643 END IF;
591 END PROCESS;
644 END PROCESS;
592
645
593 current_fifo_empty <= MEM_IN_SM_Empty(0) WHEN current_fifo_load(0) = '1' ELSE
646 current_fifo_empty <= MEM_IN_SM_Empty(0) WHEN current_fifo_load(0) = '1' ELSE
594 MEM_IN_SM_Empty(1) WHEN current_fifo_load(1) = '1' ELSE
647 MEM_IN_SM_Empty(1) WHEN current_fifo_load(1) = '1' ELSE
595 MEM_IN_SM_Empty(2) WHEN current_fifo_load(2) = '1' ELSE
648 MEM_IN_SM_Empty(2) WHEN current_fifo_load(2) = '1' ELSE
596 MEM_IN_SM_Empty(3) WHEN current_fifo_load(3) = '1' ELSE
649 MEM_IN_SM_Empty(3) WHEN current_fifo_load(3) = '1' ELSE
597 MEM_IN_SM_Empty(4);-- WHEN current_fifo_load(3) = '1' ELSE
650 MEM_IN_SM_Empty(4);-- WHEN current_fifo_load(3) = '1' ELSE
598
651
599 current_fifo_full <= MEM_IN_SM_Full(0) WHEN current_fifo_load(0) = '1' ELSE
652 current_fifo_full <= MEM_IN_SM_Full(0) WHEN current_fifo_load(0) = '1' ELSE
600 MEM_IN_SM_Full(1) WHEN current_fifo_load(1) = '1' ELSE
653 MEM_IN_SM_Full(1) WHEN current_fifo_load(1) = '1' ELSE
601 MEM_IN_SM_Full(2) WHEN current_fifo_load(2) = '1' ELSE
654 MEM_IN_SM_Full(2) WHEN current_fifo_load(2) = '1' ELSE
602 MEM_IN_SM_Full(3) WHEN current_fifo_load(3) = '1' ELSE
655 MEM_IN_SM_Full(3) WHEN current_fifo_load(3) = '1' ELSE
603 MEM_IN_SM_Full(4);-- WHEN current_fifo_load(3) = '1' ELSE
656 MEM_IN_SM_Full(4);-- WHEN current_fifo_load(3) = '1' ELSE
604
657
605 current_fifo_locked <= MEM_IN_SM_locked(0) WHEN current_fifo_load(0) = '1' ELSE
658 current_fifo_locked <= MEM_IN_SM_locked(0) WHEN current_fifo_load(0) = '1' ELSE
606 MEM_IN_SM_locked(1) WHEN current_fifo_load(1) = '1' ELSE
659 MEM_IN_SM_locked(1) WHEN current_fifo_load(1) = '1' ELSE
607 MEM_IN_SM_locked(2) WHEN current_fifo_load(2) = '1' ELSE
660 MEM_IN_SM_locked(2) WHEN current_fifo_load(2) = '1' ELSE
608 MEM_IN_SM_locked(3) WHEN current_fifo_load(3) = '1' ELSE
661 MEM_IN_SM_locked(3) WHEN current_fifo_load(3) = '1' ELSE
609 MEM_IN_SM_locked(4);-- WHEN current_fifo_load(3) = '1' ELSE
662 MEM_IN_SM_locked(4);-- WHEN current_fifo_load(3) = '1' ELSE
610
663
611 fft_read <= '0' WHEN state_fsm_load_MS_memory = IDLE ELSE '1';
664 fft_read <= '0' WHEN state_fsm_load_MS_memory = IDLE ELSE '1';
612
665
613 all_fifo: FOR I IN 4 DOWNTO 0 GENERATE
666 all_fifo: FOR I IN 4 DOWNTO 0 GENERATE
614 MEM_IN_SM_wen_s(I) <= '0' WHEN fft_data_valid = '1'
667 MEM_IN_SM_wen_s(I) <= '0' WHEN fft_data_valid = '1'
615 AND state_fsm_load_MS_memory = LOAD_FIFO
668 AND state_fsm_load_MS_memory = LOAD_FIFO
616 AND current_fifo_load(I) = '1'
669 AND current_fifo_load(I) = '1'
617 ELSE '1';
670 ELSE '1';
618 END GENERATE all_fifo;
671 END GENERATE all_fifo;
619
672
620 PROCESS (clk, rstn)
673 PROCESS (clk, rstn)
621 BEGIN
674 BEGIN
622 IF rstn = '0' THEN
675 IF rstn = '0' THEN
623 MEM_IN_SM_wen <= (OTHERS => '1');
676 MEM_IN_SM_wen <= (OTHERS => '1');
624 ELSIF clk'event AND clk = '1' THEN
677 ELSIF clk'event AND clk = '1' THEN
625 MEM_IN_SM_wen <= MEM_IN_SM_wen_s;
678 MEM_IN_SM_wen <= MEM_IN_SM_wen_s;
626 END IF;
679 END IF;
627 END PROCESS;
680 END PROCESS;
628
681
629 MEM_IN_SM_wData <= (fft_data_im & fft_data_re) &
682 MEM_IN_SM_wData <= (fft_data_im & fft_data_re) &
630 (fft_data_im & fft_data_re) &
683 (fft_data_im & fft_data_re) &
631 (fft_data_im & fft_data_re) &
684 (fft_data_im & fft_data_re) &
632 (fft_data_im & fft_data_re) &
685 (fft_data_im & fft_data_re) &
633 (fft_data_im & fft_data_re);
686 (fft_data_im & fft_data_re);
634
687
635
688
636 -- out SM_MEM_IN_wData
689 -- out SM_MEM_IN_wData
637 -- out SM_MEM_IN_wen
690 -- out SM_MEM_IN_wen
638 -- out SM_MEM_IN_Full
691 -- out SM_MEM_IN_Full
639
692
640 -- out SM_MEM_IN_locked
693 -- out SM_MEM_IN_locked
641 -----------------------------------------------------------------------------
694 -----------------------------------------------------------------------------
642 -----------------------------------------------------------------------------
695 -----------------------------------------------------------------------------
643 -----------------------------------------------------------------------------
696 -----------------------------------------------------------------------------
644 -----------------------------------------------------------------------------
697 -----------------------------------------------------------------------------
645 --Linker_FFT_1 : Linker_FFT
698 --Linker_FFT_1 : Linker_FFT
646 -- GENERIC MAP (
699 -- GENERIC MAP (
647 -- Data_sz => 16,
700 -- Data_sz => 16,
648 -- NbData => 256)
701 -- NbData => 256)
649 -- PORT MAP (
702 -- PORT MAP (
650 -- clk => clk,
703 -- clk => clk,
651 -- rstn => rstn,
704 -- rstn => rstn,
652
705
653 -- Ready => fft_ready,
706 -- Ready => fft_ready,
654 -- Valid => fft_data_valid,
707 -- Valid => fft_data_valid,
655
708
656 -- Full => MEM_IN_SM_Full,
709 -- Full => MEM_IN_SM_Full,
657
710
658 -- Data_re => fft_data_re,
711 -- Data_re => fft_data_re,
659 -- Data_im => fft_data_im,
712 -- Data_im => fft_data_im,
660 -- Read => fft_read,
713 -- Read => fft_read,
661
714
662 -- Write => MEM_IN_SM_wen,
715 -- Write => MEM_IN_SM_wen,
663 -- ReUse => fft_linker_ReUse,
716 -- ReUse => fft_linker_ReUse,
664 -- DATA => MEM_IN_SM_wData);
717 -- DATA => MEM_IN_SM_wData);
665
718
666 -----------------------------------------------------------------------------
719 -----------------------------------------------------------------------------
667 Mem_In_SpectralMatrix : lppFIFOxN
720 Mem_In_SpectralMatrix : lppFIFOxN
668 GENERIC MAP (
721 GENERIC MAP (
669 tech => 0,
722 tech => 0,
670 Mem_use => Mem_use,
723 Mem_use => Mem_use,
671 Data_sz => 32, --16,
724 Data_sz => 32, --16,
672 Addr_sz => 7, --8
725 Addr_sz => 7, --8
673 FifoCnt => 5)
726 FifoCnt => 5)
674 PORT MAP (
727 PORT MAP (
675 clk => clk,
728 clk => clk,
676 rstn => rstn,
729 rstn => rstn,
677
730
678 ReUse => MEM_IN_SM_ReUse,
731 ReUse => MEM_IN_SM_ReUse,
679
732
680 wen => MEM_IN_SM_wen,
733 wen => MEM_IN_SM_wen,
681 wdata => MEM_IN_SM_wData,
734 wdata => MEM_IN_SM_wData,
682
735
683 ren => MEM_IN_SM_ren,
736 ren => MEM_IN_SM_ren,
684 rdata => MEM_IN_SM_rData,
737 rdata => MEM_IN_SM_rData,
685 full => MEM_IN_SM_Full,
738 full => MEM_IN_SM_Full,
686 empty => MEM_IN_SM_Empty);
739 empty => MEM_IN_SM_Empty);
687
740
688
741
689 all_lock: FOR I IN 4 DOWNTO 0 GENERATE
742 --all_lock: FOR I IN 4 DOWNTO 0 GENERATE
690 PROCESS (clk, rstn)
743 -- PROCESS (clk, rstn)
691 BEGIN
744 -- BEGIN
692 IF rstn = '0' THEN
745 -- IF rstn = '0' THEN
693 MEM_IN_SM_locked(I) <= '0';
746 -- MEM_IN_SM_locked(I) <= '0';
694 ELSIF clk'event AND clk = '1' THEN
747 -- ELSIF clk'event AND clk = '1' THEN
695 MEM_IN_SM_locked(I) <= MEM_IN_SM_Full(I) OR MEM_IN_SM_locked(I); -- TODO
748 -- MEM_IN_SM_locked(I) <= MEM_IN_SM_Full(I) OR MEM_IN_SM_locked(I); -- TODO
696 END IF;
749 -- END IF;
697 END PROCESS;
750 -- END PROCESS;
698 END GENERATE all_lock;
751 --END GENERATE all_lock;
699
752
700 -----------------------------------------------------------------------------
753 -----------------------------------------------------------------------------
701
754 MS_control_1: MS_control
755 PORT MAP (
756 clk => clk,
757 rstn => rstn,
758
759 current_status_ms => status_MS_input,
760
761 fifo_in_lock => MEM_IN_SM_locked,
762 fifo_in_data => MEM_IN_SM_rdata,
763 fifo_in_full => MEM_IN_SM_Full,
764 fifo_in_empty => MEM_IN_SM_Empty,
765 fifo_in_ren => MEM_IN_SM_ren,
766 fifo_in_reuse => MEM_IN_SM_ReUse,
767
768 fifo_out_data => SM_in_data,
769 fifo_out_ren => SM_in_ren,
770 fifo_out_empty => SM_in_empty,
771
772 current_status_component => status_component,
773
774 correlation_start => SM_correlation_start,
775 correlation_auto => SM_correlation_auto,
776 correlation_done => SM_correlation_done);
702
777
703
778
704
779 MS_calculation_1: MS_calculation
780 PORT MAP (
781 clk => clk,
782 rstn => rstn,
783
784 fifo_in_data => SM_in_data,
785 fifo_in_ren => SM_in_ren,
786 fifo_in_empty => SM_in_empty,
787
788 fifo_out_data => MEM_OUT_SM_Data_in_s, -- TODO
789 fifo_out_wen => MEM_OUT_SM_Write_s, -- TODO
790 fifo_out_full => MEM_OUT_SM_Full_s, -- TODO
791
792 correlation_start => SM_correlation_start,
793 correlation_auto => SM_correlation_auto,
794 correlation_begin => SM_correlation_begin,
795 correlation_done => SM_correlation_done);
705
796
706 -----------------------------------------------------------------------------
797 -----------------------------------------------------------------------------
707 SM0 : MatriceSpectrale
798 PROCESS (clk, rstn)
708 GENERIC MAP (
799 BEGIN -- PROCESS
709 Input_SZ => 16,
800 IF rstn = '0' THEN -- asynchronous reset (active low)
710 Result_SZ => 32)
801 current_matrix_write <= '0';
711 PORT MAP (
802 current_matrix_wait_empty <= '1';
712 clkm => clk,
803 status_component_fifo_0 <= (OTHERS => '0');
713 rstn => rstn,
804 status_component_fifo_1 <= (OTHERS => '0');
805 status_component_fifo_0_new <= '0';
806 status_component_fifo_1_new <= '0';
807 status_component_fifo_0_end <= '0';
808 status_component_fifo_1_end <= '0';
809 SM_correlation_done_reg1 <= '0';
810 SM_correlation_done_reg2 <= '0';
811
812 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
813 SM_correlation_done_reg1 <= SM_correlation_done;
814 SM_correlation_done_reg2 <= SM_correlation_done_reg1;
815
816 status_component_fifo_0_new <= '0';
817 status_component_fifo_1_new <= '0';
818 status_component_fifo_0_end <= '0';
819 status_component_fifo_1_end <= '0';
820
714
821
715 FifoIN_Full => MEM_IN_SM_Full,
822
716 Data_IN => MEM_IN_SM_rData(79 DOWNTO 0),
823 IF SM_correlation_begin = '1' THEN
717 Read => MEM_IN_SM_ren,
824 IF current_matrix_write = '0' THEN
718 ReUse => MEM_IN_SM_ReUse,
825 status_component_fifo_0_new <= '1';
719
826 status_component_fifo_0 <= status_component;
720 SetReUse => fft_linker_ReUse,
827 ELSE
828 status_component_fifo_1_new <= '1';
829 status_component_fifo_1 <= status_component;
830 END IF;
831 END IF;
832
833 IF SM_correlation_done_reg2 = '1' THEN
834 IF current_matrix_write = '0' THEN
835 status_component_fifo_0_end <= '1';
836 ELSE
837 status_component_fifo_1_end <= '1';
838 END IF;
839 current_matrix_wait_empty <= '1';
840 current_matrix_write <= NOT current_matrix_write;
841 END IF;
842
843 IF current_matrix_wait_empty <= '1' THEN
844 IF current_matrix_write = '0' THEN
845 current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(0);
846 ELSE
847 current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(1);
848 END IF;
849 END IF;
850
851 END IF;
852 END PROCESS;
721
853
722 Valid => HEAD_Valid,
854 MEM_OUT_SM_Full_s <= '1' WHEN SM_correlation_done = '1' ELSE
723 ACK => DMA_Header_Ack,
855 '1' WHEN SM_correlation_done_reg1 = '1' ELSE
724 SM_Write => HEAD_SM_Wen,
856 '1' WHEN SM_correlation_done_reg2 = '1' ELSE
725 FlagError => OPEN,
857 '1' WHEN current_matrix_wait_empty = '1' ELSE
726 Statu => HEAD_SM_Param,
858 MEM_OUT_SM_Full(0) WHEN current_matrix_write = '0' ELSE
727 Write => MEM_OUT_SM_Write,
859 MEM_OUT_SM_Full(1);
728 Data_OUT => MEM_OUT_SM_Data_in);
860
861 MEM_OUT_SM_Write(0) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '0' ELSE '1';
862 MEM_OUT_SM_Write(1) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '1' ELSE '1';
863
864 MEM_OUT_SM_Data_in <= MEM_OUT_SM_Data_in_s & MEM_OUT_SM_Data_in_s;
729 -----------------------------------------------------------------------------
865 -----------------------------------------------------------------------------
866
730 Mem_Out_SpectralMatrix : lppFIFOxN
867 Mem_Out_SpectralMatrix : lppFIFOxN
731 GENERIC MAP (
868 GENERIC MAP (
732 tech => 0,
869 tech => 0,
733 Mem_use => Mem_use,
870 Mem_use => Mem_use,
734 Data_sz => 32,
871 Data_sz => 32,
735 Addr_sz => 8,
872 Addr_sz => 8,
736 FifoCnt => 2)
873 FifoCnt => 2)
737 PORT MAP (
874 PORT MAP (
738 clk => clk,
875 clk => clk,
739 rstn => rstn,
876 rstn => rstn,
740
877
741 ReUse => (OTHERS => '0'),
878 ReUse => (OTHERS => '0'),
742
879
743 wen => MEM_OUT_SM_Write,
880 wen => MEM_OUT_SM_Write,
744 wdata => MEM_OUT_SM_Data_in,
881 wdata => MEM_OUT_SM_Data_in,
882
745 ren => MEM_OUT_SM_Read,
883 ren => MEM_OUT_SM_Read,
746 rdata => MEM_OUT_SM_Data_out,
884 rdata => MEM_OUT_SM_Data_out,
747
885
748 full => MEM_OUT_SM_Full,
886 full => MEM_OUT_SM_Full,
749 empty => MEM_OUT_SM_Empty);
887 empty => MEM_OUT_SM_Empty,
888 almost_full => OPEN);
889
750 -----------------------------------------------------------------------------
890 -----------------------------------------------------------------------------
751 Head0 : HeaderBuilder
891 -- MEM_OUT_SM_Read <= "00";
752 GENERIC MAP (
892 PROCESS (clk, rstn)
753 Data_sz => 32)
893 BEGIN
754 PORT MAP (
894 IF rstn = '0' THEN
755 clkm => clk,
895 fifo_0_ready <= '0';
756 rstn => rstn,
896 fifo_1_ready <= '0';
897 fifo_ongoing <= '0';
898 ELSIF clk'event AND clk = '1' THEN
899 IF fifo_0_ready = '1' AND MEM_OUT_SM_Empty(0) = '1' THEN
900 fifo_ongoing <= '1';
901 fifo_0_ready <= '0';
902 ELSIF status_component_fifo_0_end = '1' THEN
903 fifo_0_ready <= '1';
904 END IF;
905
906 IF fifo_1_ready = '1' AND MEM_OUT_SM_Empty(1) = '1' THEN
907 fifo_ongoing <= '0';
908 fifo_1_ready <= '0';
909 ELSIF status_component_fifo_1_end = '1' THEN
910 fifo_1_ready <= '1';
911 END IF;
912
913 END IF;
914 END PROCESS;
915
916 MEM_OUT_SM_Read(0) <= '1' WHEN fifo_ongoing = '1' ELSE
917 '1' WHEN fifo_0_ready = '0' ELSE
918 FSM_DMA_fifo_ren;
757
919
758 Statu => HEAD_SM_Param,
920 MEM_OUT_SM_Read(1) <= '1' WHEN fifo_ongoing = '0' ELSE
759 Matrix_Type => HEAD_WorkFreq, -- TODO IN
921 '1' WHEN fifo_1_ready = '0' ELSE
760 Matrix_Write => HEAD_SM_Wen,
922 FSM_DMA_fifo_ren;
761 Valid => HEAD_Valid,
762
763 dataIN => MEM_OUT_SM_Data_out,
764 emptyIN => MEM_OUT_SM_Empty,
765 RenOUT => MEM_OUT_SM_Read,
766
923
767 dataOUT => HEAD_Data,
924 FSM_DMA_fifo_empty <= MEM_OUT_SM_Empty(0) WHEN fifo_ongoing = '0' AND fifo_0_ready = '1' ELSE
768 emptyOUT => HEAD_Empty,
925 MEM_OUT_SM_Empty(1) WHEN fifo_ongoing = '1' AND fifo_1_ready = '1' ELSE
769 RenIN => HEAD_Read,
926 '1';
927
928 FSM_DMA_fifo_status <= status_component_fifo_0 WHEN fifo_ongoing = '0' ELSE
929 status_component_fifo_1;
770
930
771 header => DMA_Header,
931 FSM_DMA_fifo_data <= MEM_OUT_SM_Data_out(31 DOWNTO 0) WHEN fifo_ongoing = '0' ELSE
772 header_val => DMA_Header_Val,
932 MEM_OUT_SM_Data_out(63 DOWNTO 32);
773 header_ack => DMA_Header_Ack);
933
774 -----------------------------------------------------------------------------
775 -----------------------------------------------------------------------------
934 -----------------------------------------------------------------------------
776 lpp_lfr_ms_fsmdma_1 : lpp_lfr_ms_fsmdma
935 lpp_lfr_ms_fsmdma_1 : lpp_lfr_ms_fsmdma
777 PORT MAP (
936 PORT MAP (
778 HCLK => clk,
937 HCLK => clk,
779 HRESETn => rstn,
938 HRESETn => rstn,
780
939
781 data_time => dma_time,
940 fifo_matrix_type => FSM_DMA_fifo_status( 5 DOWNTO 4),
941 fifo_matrix_component => FSM_DMA_fifo_status( 3 DOWNTO 0),
942 fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6),
943 fifo_data => FSM_DMA_fifo_data,
944 fifo_empty => FSM_DMA_fifo_empty,
945 fifo_ren => FSM_DMA_fifo_ren,
946
947 ---- FIFO IN
948 --data_time => dma_time,
782
949
783 fifo_data => HEAD_Data,
950 --fifo_data => HEAD_Data,
784 fifo_empty => HEAD_Empty,
951 --fifo_empty => HEAD_Empty,
785 fifo_ren => HEAD_Read,
952 --fifo_ren => HEAD_Read,
786
953
787 header => DMA_Header,
954 --header => DMA_Header,
788 header_val => DMA_Header_Val,
955 --header_val => DMA_Header_Val,
789 header_ack => DMA_Header_Ack,
956 --header_ack => DMA_Header_Ack,
790
957
791 dma_addr => dma_addr,
958 dma_addr => dma_addr,
792 dma_data => dma_data,
959 dma_data => dma_data,
793 dma_valid => dma_valid,
960 dma_valid => dma_valid,
794 dma_valid_burst => dma_valid_burst,
961 dma_valid_burst => dma_valid_burst,
795 dma_ren => dma_ren,
962 dma_ren => dma_ren,
796 dma_done => dma_done,
963 dma_done => dma_done,
797
964
798 ready_matrix_f0_0 => ready_matrix_f0_0,
965 ready_matrix_f0 => ready_matrix_f0,
799 ready_matrix_f0_1 => ready_matrix_f0_1,
966 -- ready_matrix_f0_1 => ready_matrix_f0_1,
800 ready_matrix_f1 => ready_matrix_f1,
967 ready_matrix_f1 => ready_matrix_f1,
801 ready_matrix_f2 => ready_matrix_f2,
968 ready_matrix_f2 => ready_matrix_f2,
802 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
969 -- error_anticipating_empty_fifo => error_anticipating_empty_fifo,
803 error_bad_component_error => error_bad_component_error,
970 error_bad_component_error => error_bad_component_error,
971 error_buffer_full => error_buffer_full,
804 debug_reg => debug_reg,
972 debug_reg => debug_reg,
805 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
973 status_ready_matrix_f0 => status_ready_matrix_f0,
806 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
974 -- status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
807 status_ready_matrix_f1 => status_ready_matrix_f1,
975 status_ready_matrix_f1 => status_ready_matrix_f1,
808 status_ready_matrix_f2 => status_ready_matrix_f2,
976 status_ready_matrix_f2 => status_ready_matrix_f2,
809 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
977 -- status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
810 status_error_bad_component_error => status_error_bad_component_error,
978 -- status_error_bad_component_error => status_error_bad_component_error,
979 -- status_error_buffer_full => status_error_buffer_full,
811 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
980 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
812 config_active_interruption_onError => config_active_interruption_onError,
981 config_active_interruption_onError => config_active_interruption_onError,
813 addr_matrix_f0_0 => addr_matrix_f0_0,
982 addr_matrix_f0 => addr_matrix_f0,
814 addr_matrix_f0_1 => addr_matrix_f0_1,
983 -- addr_matrix_f0_1 => addr_matrix_f0_1,
815 addr_matrix_f1 => addr_matrix_f1,
984 addr_matrix_f1 => addr_matrix_f1,
816 addr_matrix_f2 => addr_matrix_f2,
985 addr_matrix_f2 => addr_matrix_f2,
817
986
818 matrix_time_f0_0 => matrix_time_f0_0,
987 matrix_time_f0 => matrix_time_f0,
819 matrix_time_f0_1 => matrix_time_f0_1,
988 -- matrix_time_f0_1 => matrix_time_f0_1,
820 matrix_time_f1 => matrix_time_f1,
989 matrix_time_f1 => matrix_time_f1,
821 matrix_time_f2 => matrix_time_f2
990 matrix_time_f2 => matrix_time_f2
822 );
991 );
823 -----------------------------------------------------------------------------
992 -----------------------------------------------------------------------------
824
993
994
995
996
997
998
999
1000
1001
1002
1003
825 -----------------------------------------------------------------------------
1004 -----------------------------------------------------------------------------
826 -----------------------------------------------------------------------------
1005 -----------------------------------------------------------------------------
827 -----------------------------------------------------------------------------
1006 -----------------------------------------------------------------------------
828 -----------------------------------------------------------------------------
1007 -----------------------------------------------------------------------------
829 -----------------------------------------------------------------------------
1008 -----------------------------------------------------------------------------
830 -----------------------------------------------------------------------------
1009 -----------------------------------------------------------------------------
831
1010
832
1011
833
1012
834
1013
835
1014
836
1015
837 -----------------------------------------------------------------------------
1016 -----------------------------------------------------------------------------
838 -- TIME MANAGMENT
1017 -- TIME MANAGMENT
839 -----------------------------------------------------------------------------
1018 -----------------------------------------------------------------------------
840 all_time <= coarse_time & fine_time;
1019 all_time <= coarse_time & fine_time;
841 --
1020 --
842 time_update_f0_A <= '0' WHEN sample_f0_A_wen = "11111" ELSE
1021 time_update_f0_A <= '0' WHEN sample_f0_A_wen = "11111" ELSE
843 '1' WHEN sample_f0_A_empty = "11111" ELSE
1022 '1' WHEN sample_f0_A_empty = "11111" ELSE
844 '0';
1023 '0';
845
1024
846 s_m_t_m_f0_A : spectral_matrix_time_managment
1025 s_m_t_m_f0_A : spectral_matrix_time_managment
847 PORT MAP (
1026 PORT MAP (
848 clk => clk,
1027 clk => clk,
849 rstn => rstn,
1028 rstn => rstn,
850 time_in => all_time,
1029 time_in => all_time,
851 update_1 => time_update_f0_A,
1030 update_1 => time_update_f0_A,
852 time_out => time_reg_f0_A);
1031 time_out => time_reg_f0_A);
853
1032
854 --
1033 --
855 time_update_f0_B <= '0' WHEN sample_f0_B_wen = "11111" ELSE
1034 time_update_f0_B <= '0' WHEN sample_f0_B_wen = "11111" ELSE
856 '1' WHEN sample_f0_B_empty = "11111" ELSE
1035 '1' WHEN sample_f0_B_empty = "11111" ELSE
857 '0';
1036 '0';
858
1037
859 s_m_t_m_f0_B : spectral_matrix_time_managment
1038 s_m_t_m_f0_B : spectral_matrix_time_managment
860 PORT MAP (
1039 PORT MAP (
861 clk => clk,
1040 clk => clk,
862 rstn => rstn,
1041 rstn => rstn,
863 time_in => all_time,
1042 time_in => all_time,
864 update_1 => time_update_f0_B,
1043 update_1 => time_update_f0_B,
865 time_out => time_reg_f0_B);
1044 time_out => time_reg_f0_B);
866
1045
867 --
1046 --
868 time_update_f1 <= '0' WHEN sample_f1_wen = "11111" ELSE
1047 time_update_f1 <= '0' WHEN sample_f1_wen = "11111" ELSE
869 '1' WHEN sample_f1_empty = "11111" ELSE
1048 '1' WHEN sample_f1_empty = "11111" ELSE
870 '0';
1049 '0';
871
1050
872 s_m_t_m_f1 : spectral_matrix_time_managment
1051 s_m_t_m_f1 : spectral_matrix_time_managment
873 PORT MAP (
1052 PORT MAP (
874 clk => clk,
1053 clk => clk,
875 rstn => rstn,
1054 rstn => rstn,
876 time_in => all_time,
1055 time_in => all_time,
877 update_1 => time_update_f1,
1056 update_1 => time_update_f1,
878 time_out => time_reg_f1);
1057 time_out => time_reg_f1);
879
1058
880 --
1059 --
881 time_update_f2 <= '0' WHEN sample_f2_wen = "11111" ELSE
1060 time_update_f2 <= '0' WHEN sample_f2_wen = "11111" ELSE
882 '1' WHEN sample_f2_empty = "11111" ELSE
1061 '1' WHEN sample_f2_empty = "11111" ELSE
883 '0';
1062 '0';
884
1063
885 s_m_t_m_f2 : spectral_matrix_time_managment
1064 s_m_t_m_f2 : spectral_matrix_time_managment
886 PORT MAP (
1065 PORT MAP (
887 clk => clk,
1066 clk => clk,
888 rstn => rstn,
1067 rstn => rstn,
889 time_in => all_time,
1068 time_in => all_time,
890 update_1 => time_update_f2,
1069 update_1 => time_update_f2,
891 time_out => time_reg_f2);
1070 time_out => time_reg_f2);
892
1071
893 -----------------------------------------------------------------------------
1072 -----------------------------------------------------------------------------
894 dma_time <= (OTHERS => '0'); -- TODO
1073 dma_time <= (OTHERS => '0'); -- TODO
895 -----------------------------------------------------------------------------
1074 -----------------------------------------------------------------------------
896
1075
897
1076
898
1077
899 END Behavioral;
1078 END Behavioral;
Show file before | Show file after | Hide comments
@@ -1,241 +1,243
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 LIBRARY ieee;
22 LIBRARY ieee;
23 USE ieee.std_logic_1164.ALL;
23 USE ieee.std_logic_1164.ALL;
24 LIBRARY grlib;
24 LIBRARY grlib;
25 USE grlib.amba.ALL;
25 USE grlib.amba.ALL;
26 USE std.textio.ALL;
26 USE std.textio.ALL;
27 LIBRARY lpp;
27 LIBRARY lpp;
28 USE lpp.lpp_amba.ALL;
28 USE lpp.lpp_amba.ALL;
29 USE lpp.iir_filter.ALL;
29 USE lpp.iir_filter.ALL;
30 LIBRARY gaisler;
30 LIBRARY gaisler;
31 USE gaisler.misc.ALL;
31 USE gaisler.misc.ALL;
32 USE gaisler.memctrl.ALL;
32 USE gaisler.memctrl.ALL;
33 LIBRARY techmap;
33 LIBRARY techmap;
34 USE techmap.gencomp.ALL;
34 USE techmap.gencomp.ALL;
35
35
36 --! Package contenant tous les programmes qui forment le composant intοΏ½grοΏ½ dans le lοΏ½on
36 --! Package contenant tous les programmes qui forment le composant intοΏ½grοΏ½ dans le lοΏ½on
37
37
38 PACKAGE lpp_memory IS
38 PACKAGE lpp_memory IS
39
39
40 COMPONENT lpp_fifo
40 COMPONENT lpp_fifo
41 GENERIC (
41 GENERIC (
42 tech : INTEGER;
42 tech : INTEGER;
43 Mem_use : INTEGER;
43 Mem_use : INTEGER;
44 DataSz : INTEGER RANGE 1 TO 32;
44 DataSz : INTEGER RANGE 1 TO 32;
45 AddrSz : INTEGER RANGE 2 TO 12);
45 AddrSz : INTEGER RANGE 2 TO 12);
46 PORT (
46 PORT (
47 clk : IN STD_LOGIC;
47 clk : IN STD_LOGIC;
48 rstn : IN STD_LOGIC;
48 rstn : IN STD_LOGIC;
49 reUse : IN STD_LOGIC;
49 reUse : IN STD_LOGIC;
50 ren : IN STD_LOGIC;
50 ren : IN STD_LOGIC;
51 rdata : OUT STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
51 rdata : OUT STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
52 wen : IN STD_LOGIC;
52 wen : IN STD_LOGIC;
53 wdata : IN STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
53 wdata : IN STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
54 empty : OUT STD_LOGIC;
54 empty : OUT STD_LOGIC;
55 full : OUT STD_LOGIC;
55 full : OUT STD_LOGIC;
56 almost_full : OUT STD_LOGIC);
56 almost_full : OUT STD_LOGIC;
57 more_16Data : OUT STD_LOGIC);
57 END COMPONENT;
58 END COMPONENT;
58
59
59 COMPONENT lppFIFOxN
60 COMPONENT lppFIFOxN
60 GENERIC (
61 GENERIC (
61 tech : INTEGER;
62 tech : INTEGER;
62 Mem_use : INTEGER;
63 Mem_use : INTEGER;
63 Data_sz : INTEGER RANGE 1 TO 32;
64 Data_sz : INTEGER RANGE 1 TO 32;
64 Addr_sz : INTEGER RANGE 2 TO 12;
65 Addr_sz : INTEGER RANGE 2 TO 12;
65 FifoCnt : INTEGER);
66 FifoCnt : INTEGER);
66 PORT (
67 PORT (
67 clk : IN STD_LOGIC;
68 clk : IN STD_LOGIC;
68 rstn : IN STD_LOGIC;
69 rstn : IN STD_LOGIC;
69 ReUse : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
70 ReUse : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
70 wen : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
71 wen : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
71 wdata : IN STD_LOGIC_VECTOR((FifoCnt*Data_sz)-1 DOWNTO 0);
72 wdata : IN STD_LOGIC_VECTOR((FifoCnt*Data_sz)-1 DOWNTO 0);
72 ren : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
73 ren : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
73 rdata : OUT STD_LOGIC_VECTOR((FifoCnt*Data_sz)-1 DOWNTO 0);
74 rdata : OUT STD_LOGIC_VECTOR((FifoCnt*Data_sz)-1 DOWNTO 0);
74 empty : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
75 empty : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
75 full : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
76 full : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
76 almost_full : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0));
77 almost_full : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
78 more_16Data : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0));
77 END COMPONENT;
79 END COMPONENT;
78
80
79
81
80
82
81
83
82 COMPONENT APB_FIFO IS
84 COMPONENT APB_FIFO IS
83 GENERIC (
85 GENERIC (
84 tech : INTEGER := apa3;
86 tech : INTEGER := apa3;
85 pindex : INTEGER := 0;
87 pindex : INTEGER := 0;
86 paddr : INTEGER := 0;
88 paddr : INTEGER := 0;
87 pmask : INTEGER := 16#fff#;
89 pmask : INTEGER := 16#fff#;
88 pirq : INTEGER := 0;
90 pirq : INTEGER := 0;
89 abits : INTEGER := 8;
91 abits : INTEGER := 8;
90 FifoCnt : INTEGER := 2;
92 FifoCnt : INTEGER := 2;
91 Data_sz : INTEGER := 16;
93 Data_sz : INTEGER := 16;
92 Addr_sz : INTEGER := 9;
94 Addr_sz : INTEGER := 9;
93 Enable_ReUse : STD_LOGIC := '0';
95 Enable_ReUse : STD_LOGIC := '0';
94 Mem_use : INTEGER := use_RAM;
96 Mem_use : INTEGER := use_RAM;
95 R : INTEGER := 1;
97 R : INTEGER := 1;
96 W : INTEGER := 1
98 W : INTEGER := 1
97 );
99 );
98 PORT (
100 PORT (
99 clk : IN STD_LOGIC; --! Horloge du composant
101 clk : IN STD_LOGIC; --! Horloge du composant
100 rst : IN STD_LOGIC; --! Reset general du composant
102 rst : IN STD_LOGIC; --! Reset general du composant
101 rclk : IN STD_LOGIC;
103 rclk : IN STD_LOGIC;
102 wclk : IN STD_LOGIC;
104 wclk : IN STD_LOGIC;
103 ReUse : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
105 ReUse : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
104 REN : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0); --! Instruction de lecture en mοΏ½moire
106 REN : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0); --! Instruction de lecture en mοΏ½moire
105 WEN : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0); --! Instruction d'οΏ½criture en mοΏ½moire
107 WEN : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0); --! Instruction d'οΏ½criture en mοΏ½moire
106 Empty : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0); --! Flag, MοΏ½moire vide
108 Empty : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0); --! Flag, MοΏ½moire vide
107 Full : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0); --! Flag, MοΏ½moire pleine
109 Full : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0); --! Flag, MοΏ½moire pleine
108 RDATA : OUT STD_LOGIC_VECTOR((FifoCnt*Data_sz)-1 DOWNTO 0); --! Registre de donnοΏ½es en entrοΏ½e
110 RDATA : OUT STD_LOGIC_VECTOR((FifoCnt*Data_sz)-1 DOWNTO 0); --! Registre de donnοΏ½es en entrοΏ½e
109 WDATA : IN STD_LOGIC_VECTOR((FifoCnt*Data_sz)-1 DOWNTO 0); --! Registre de donnοΏ½es en sortie
111 WDATA : IN STD_LOGIC_VECTOR((FifoCnt*Data_sz)-1 DOWNTO 0); --! Registre de donnοΏ½es en sortie
110 WADDR : OUT STD_LOGIC_VECTOR((FifoCnt*Addr_sz)-1 DOWNTO 0); --! Registre d'addresse (οΏ½criture)
112 WADDR : OUT STD_LOGIC_VECTOR((FifoCnt*Addr_sz)-1 DOWNTO 0); --! Registre d'addresse (οΏ½criture)
111 RADDR : OUT STD_LOGIC_VECTOR((FifoCnt*Addr_sz)-1 DOWNTO 0); --! Registre d'addresse (lecture)
113 RADDR : OUT STD_LOGIC_VECTOR((FifoCnt*Addr_sz)-1 DOWNTO 0); --! Registre d'addresse (lecture)
112 apbi : IN apb_slv_in_type; --! Registre de gestion des entrοΏ½es du bus
114 apbi : IN apb_slv_in_type; --! Registre de gestion des entrοΏ½es du bus
113 apbo : OUT apb_slv_out_type --! Registre de gestion des sorties du bus
115 apbo : OUT apb_slv_out_type --! Registre de gestion des sorties du bus
114 );
116 );
115 END COMPONENT;
117 END COMPONENT;
116
118
117 COMPONENT FIFO_pipeline IS
119 COMPONENT FIFO_pipeline IS
118 GENERIC(
120 GENERIC(
119 tech : INTEGER := 0;
121 tech : INTEGER := 0;
120 Mem_use : INTEGER := use_RAM;
122 Mem_use : INTEGER := use_RAM;
121 fifoCount : INTEGER RANGE 2 TO 32 := 8;
123 fifoCount : INTEGER RANGE 2 TO 32 := 8;
122 DataSz : INTEGER RANGE 1 TO 32 := 8;
124 DataSz : INTEGER RANGE 1 TO 32 := 8;
123 abits : INTEGER RANGE 2 TO 12 := 8
125 abits : INTEGER RANGE 2 TO 12 := 8
124 );
126 );
125 PORT(
127 PORT(
126 rstn : IN STD_LOGIC;
128 rstn : IN STD_LOGIC;
127 ReUse : IN STD_LOGIC;
129 ReUse : IN STD_LOGIC;
128 rclk : IN STD_LOGIC;
130 rclk : IN STD_LOGIC;
129 ren : IN STD_LOGIC;
131 ren : IN STD_LOGIC;
130 rdata : OUT STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
132 rdata : OUT STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
131 empty : OUT STD_LOGIC;
133 empty : OUT STD_LOGIC;
132 raddr : OUT STD_LOGIC_VECTOR(abits-1 DOWNTO 0);
134 raddr : OUT STD_LOGIC_VECTOR(abits-1 DOWNTO 0);
133 wclk : IN STD_LOGIC;
135 wclk : IN STD_LOGIC;
134 wen : IN STD_LOGIC;
136 wen : IN STD_LOGIC;
135 wdata : IN STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
137 wdata : IN STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
136 full : OUT STD_LOGIC;
138 full : OUT STD_LOGIC;
137 waddr : OUT STD_LOGIC_VECTOR(abits-1 DOWNTO 0)
139 waddr : OUT STD_LOGIC_VECTOR(abits-1 DOWNTO 0)
138 );
140 );
139 END COMPONENT;
141 END COMPONENT;
140
142
141 --COMPONENT lpp_fifo IS
143 --COMPONENT lpp_fifo IS
142 -- GENERIC(
144 -- GENERIC(
143 -- tech : INTEGER := 0;
145 -- tech : INTEGER := 0;
144 -- Mem_use : INTEGER := use_RAM;
146 -- Mem_use : INTEGER := use_RAM;
145 -- Enable_ReUse : STD_LOGIC := '0';
147 -- Enable_ReUse : STD_LOGIC := '0';
146 -- DataSz : INTEGER RANGE 1 TO 32 := 8;
148 -- DataSz : INTEGER RANGE 1 TO 32 := 8;
147 -- AddrSz : INTEGER RANGE 2 TO 12 := 8
149 -- AddrSz : INTEGER RANGE 2 TO 12 := 8
148 -- );
150 -- );
149 -- PORT(
151 -- PORT(
150 -- rstn : IN STD_LOGIC;
152 -- rstn : IN STD_LOGIC;
151 -- ReUse : IN STD_LOGIC; --27/01/12
153 -- ReUse : IN STD_LOGIC; --27/01/12
152 -- rclk : IN STD_LOGIC;
154 -- rclk : IN STD_LOGIC;
153 -- ren : IN STD_LOGIC;
155 -- ren : IN STD_LOGIC;
154 -- rdata : OUT STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
156 -- rdata : OUT STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
155 -- empty : OUT STD_LOGIC;
157 -- empty : OUT STD_LOGIC;
156 -- raddr : OUT STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0);
158 -- raddr : OUT STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0);
157 -- wclk : IN STD_LOGIC;
159 -- wclk : IN STD_LOGIC;
158 -- wen : IN STD_LOGIC;
160 -- wen : IN STD_LOGIC;
159 -- wdata : IN STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
161 -- wdata : IN STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
160 -- full : OUT STD_LOGIC;
162 -- full : OUT STD_LOGIC;
161 -- almost_full : OUT STD_LOGIC;
163 -- almost_full : OUT STD_LOGIC;
162 -- waddr : OUT STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0)
164 -- waddr : OUT STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0)
163 -- );
165 -- );
164 --END COMPONENT;
166 --END COMPONENT;
165
167
166
168
167 --COMPONENT lppFIFOxN IS
169 --COMPONENT lppFIFOxN IS
168 -- GENERIC(
170 -- GENERIC(
169 -- tech : INTEGER := 0;
171 -- tech : INTEGER := 0;
170 -- Mem_use : INTEGER := use_RAM;
172 -- Mem_use : INTEGER := use_RAM;
171 -- Data_sz : INTEGER RANGE 1 TO 32 := 8;
173 -- Data_sz : INTEGER RANGE 1 TO 32 := 8;
172 -- Addr_sz : INTEGER RANGE 1 TO 32 := 8;
174 -- Addr_sz : INTEGER RANGE 1 TO 32 := 8;
173 -- FifoCnt : INTEGER := 1;
175 -- FifoCnt : INTEGER := 1;
174 -- Enable_ReUse : STD_LOGIC := '0'
176 -- Enable_ReUse : STD_LOGIC := '0'
175 -- );
177 -- );
176 -- PORT(
178 -- PORT(
177 -- rstn : IN STD_LOGIC;
179 -- rstn : IN STD_LOGIC;
178 -- wclk : IN STD_LOGIC;
180 -- wclk : IN STD_LOGIC;
179 -- rclk : IN STD_LOGIC;
181 -- rclk : IN STD_LOGIC;
180 -- ReUse : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
182 -- ReUse : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
181 -- wen : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
183 -- wen : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
182 -- ren : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
184 -- ren : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
183 -- wdata : IN STD_LOGIC_VECTOR((FifoCnt*Data_sz)-1 DOWNTO 0);
185 -- wdata : IN STD_LOGIC_VECTOR((FifoCnt*Data_sz)-1 DOWNTO 0);
184 -- rdata : OUT STD_LOGIC_VECTOR((FifoCnt*Data_sz)-1 DOWNTO 0);
186 -- rdata : OUT STD_LOGIC_VECTOR((FifoCnt*Data_sz)-1 DOWNTO 0);
185 -- full : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
187 -- full : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
186 -- almost_full : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
188 -- almost_full : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
187 -- empty : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0)
189 -- empty : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0)
188 -- );
190 -- );
189 --END COMPONENT;
191 --END COMPONENT;
190
192
191 COMPONENT FillFifo IS
193 COMPONENT FillFifo IS
192 GENERIC(
194 GENERIC(
193 Data_sz : INTEGER RANGE 1 TO 32 := 16;
195 Data_sz : INTEGER RANGE 1 TO 32 := 16;
194 Fifo_cnt : INTEGER RANGE 1 TO 8 := 5
196 Fifo_cnt : INTEGER RANGE 1 TO 8 := 5
195 );
197 );
196 PORT(
198 PORT(
197 clk : IN STD_LOGIC;
199 clk : IN STD_LOGIC;
198 raz : IN STD_LOGIC;
200 raz : IN STD_LOGIC;
199 write : OUT STD_LOGIC_VECTOR(Fifo_cnt-1 DOWNTO 0);
201 write : OUT STD_LOGIC_VECTOR(Fifo_cnt-1 DOWNTO 0);
200 reuse : OUT STD_LOGIC_VECTOR(Fifo_cnt-1 DOWNTO 0);
202 reuse : OUT STD_LOGIC_VECTOR(Fifo_cnt-1 DOWNTO 0);
201 data : OUT STD_LOGIC_VECTOR(Fifo_cnt*Data_sz-1 DOWNTO 0)
203 data : OUT STD_LOGIC_VECTOR(Fifo_cnt*Data_sz-1 DOWNTO 0)
202 );
204 );
203 END COMPONENT;
205 END COMPONENT;
204
206
205 COMPONENT Bridge IS
207 COMPONENT Bridge IS
206 PORT(
208 PORT(
207 clk : IN STD_LOGIC;
209 clk : IN STD_LOGIC;
208 raz : IN STD_LOGIC;
210 raz : IN STD_LOGIC;
209 EmptyUp : IN STD_LOGIC;
211 EmptyUp : IN STD_LOGIC;
210 FullDwn : IN STD_LOGIC;
212 FullDwn : IN STD_LOGIC;
211 WriteDwn : OUT STD_LOGIC;
213 WriteDwn : OUT STD_LOGIC;
212 ReadUp : OUT STD_LOGIC
214 ReadUp : OUT STD_LOGIC
213 );
215 );
214 END COMPONENT;
216 END COMPONENT;
215
217
216 COMPONENT ssram_plugin IS
218 COMPONENT ssram_plugin IS
217 GENERIC (tech : INTEGER := 0);
219 GENERIC (tech : INTEGER := 0);
218 PORT
220 PORT
219 (
221 (
220 clk : IN STD_LOGIC;
222 clk : IN STD_LOGIC;
221 mem_ctrlr_o : IN memory_out_type;
223 mem_ctrlr_o : IN memory_out_type;
222 SSRAM_CLK : OUT STD_LOGIC;
224 SSRAM_CLK : OUT STD_LOGIC;
223 nBWa : OUT STD_LOGIC;
225 nBWa : OUT STD_LOGIC;
224 nBWb : OUT STD_LOGIC;
226 nBWb : OUT STD_LOGIC;
225 nBWc : OUT STD_LOGIC;
227 nBWc : OUT STD_LOGIC;
226 nBWd : OUT STD_LOGIC;
228 nBWd : OUT STD_LOGIC;
227 nBWE : OUT STD_LOGIC;
229 nBWE : OUT STD_LOGIC;
228 nADSC : OUT STD_LOGIC;
230 nADSC : OUT STD_LOGIC;
229 nADSP : OUT STD_LOGIC;
231 nADSP : OUT STD_LOGIC;
230 nADV : OUT STD_LOGIC;
232 nADV : OUT STD_LOGIC;
231 nGW : OUT STD_LOGIC;
233 nGW : OUT STD_LOGIC;
232 nCE1 : OUT STD_LOGIC;
234 nCE1 : OUT STD_LOGIC;
233 CE2 : OUT STD_LOGIC;
235 CE2 : OUT STD_LOGIC;
234 nCE3 : OUT STD_LOGIC;
236 nCE3 : OUT STD_LOGIC;
235 nOE : OUT STD_LOGIC;
237 nOE : OUT STD_LOGIC;
236 MODE : OUT STD_LOGIC;
238 MODE : OUT STD_LOGIC;
237 ZZ : OUT STD_LOGIC
239 ZZ : OUT STD_LOGIC
238 );
240 );
239 END COMPONENT;
241 END COMPONENT;
240
242
241 END;
243 END;
Show file before | Show file after | Hide comments
@@ -1,29 +1,65
1 LIBRARY ieee;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
2 USE ieee.std_logic_1164.ALL;
3
3
4 PACKAGE spectral_matrix_package IS
4 PACKAGE spectral_matrix_package IS
5
5
6 COMPONENT spectral_matrix_switch_f0
6 COMPONENT spectral_matrix_switch_f0
7 PORT (
7 PORT (
8 clk : IN STD_LOGIC;
8 clk : IN STD_LOGIC;
9 rstn : IN STD_LOGIC;
9 rstn : IN STD_LOGIC;
10 sample_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
10 sample_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
11 fifo_A_empty : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
11 fifo_A_empty : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
12 fifo_A_full : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
12 fifo_A_full : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
13 fifo_A_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
13 fifo_A_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
14 fifo_B_empty : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
14 fifo_B_empty : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
15 fifo_B_full : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
15 fifo_B_full : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
16 fifo_B_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
16 fifo_B_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
17 error_wen : OUT STD_LOGIC);
17 error_wen : OUT STD_LOGIC);
18 END COMPONENT;
18 END COMPONENT;
19
19
20 COMPONENT spectral_matrix_time_managment
20 COMPONENT spectral_matrix_time_managment
21 PORT (
21 PORT (
22 clk : IN STD_LOGIC;
22 clk : IN STD_LOGIC;
23 rstn : IN STD_LOGIC;
23 rstn : IN STD_LOGIC;
24 time_in : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
24 time_in : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
25 update_1 : IN STD_LOGIC;
25 update_1 : IN STD_LOGIC;
26 time_out : OUT STD_LOGIC_VECTOR(47 DOWNTO 0));
26 time_out : OUT STD_LOGIC_VECTOR(47 DOWNTO 0));
27 END COMPONENT;
27 END COMPONENT;
28
29 COMPONENT MS_control
30 PORT (
31 clk : IN STD_LOGIC;
32 rstn : IN STD_LOGIC;
33 current_status_ms : IN STD_LOGIC_VECTOR(49 DOWNTO 0); -- TIME(47 .. 0) & Matrix_type(1..0)
34 fifo_in_lock : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
35 fifo_in_data : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
36 fifo_in_full : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
37 fifo_in_empty : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
38 fifo_in_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
39 fifo_in_reuse : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
40 fifo_out_data : OUT STD_LOGIC_VECTOR(32*2-1 DOWNTO 0);
41 fifo_out_ren : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
42 fifo_out_empty : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
43 current_status_component : OUT STD_LOGIC_VECTOR(53 DOWNTO 0); -- TIME(47 .. 0) &
44 correlation_start : OUT STD_LOGIC;
45 correlation_auto : OUT STD_LOGIC;
46 correlation_done : IN STD_LOGIC);
47 END COMPONENT;
48
49 COMPONENT MS_calculation
50 PORT (
51 clk : IN STD_LOGIC;
52 rstn : IN STD_LOGIC;
53 fifo_in_data : IN STD_LOGIC_VECTOR(32*2-1 DOWNTO 0);
54 fifo_in_ren : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
55 fifo_in_empty : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
56 fifo_out_data : OUT STD_LOGIC_VECTOR(32-1 DOWNTO 0);
57 fifo_out_wen : OUT STD_LOGIC;
58 fifo_out_full : IN STD_LOGIC;
59 correlation_start : IN STD_LOGIC;
60 correlation_auto : IN STD_LOGIC;
61 correlation_begin : OUT STD_LOGIC;
62 correlation_done : OUT STD_LOGIC);
63 END COMPONENT;
28
64
29 END spectral_matrix_package;
65 END spectral_matrix_package;
Show file before | Show file after | Hide comments
@@ -1,81 +1,151
1 onerror {resume}
1 onerror {resume}
2 quietly WaveActivateNextPane {} 0
2 quietly WaveActivateNextPane {} 0
3 add wave -noupdate /tb/lpp_lfr_ms_1/sample_f0_wen
3 add wave -noupdate /tb/lpp_lfr_ms_1/sample_f0_wen
4 add wave -noupdate -radix hexadecimal /tb/lpp_lfr_ms_1/sample_f0_wdata
4 add wave -noupdate -radix hexadecimal /tb/lpp_lfr_ms_1/sample_f0_wdata
5 add wave -noupdate /tb/lpp_lfr_ms_1/sample_f1_wen
5 add wave -noupdate /tb/lpp_lfr_ms_1/sample_f1_wen
6 add wave -noupdate -radix hexadecimal /tb/lpp_lfr_ms_1/sample_f1_wdata
6 add wave -noupdate -radix hexadecimal /tb/lpp_lfr_ms_1/sample_f1_wdata
7 add wave -noupdate /tb/lpp_lfr_ms_1/sample_f2_wen
7 add wave -noupdate /tb/lpp_lfr_ms_1/sample_f2_wen
8 add wave -noupdate -radix hexadecimal /tb/lpp_lfr_ms_1/sample_f2_wdata
8 add wave -noupdate -radix hexadecimal /tb/lpp_lfr_ms_1/sample_f2_wdata
9 add wave -noupdate -expand -group FIFO_f0_A /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/wen
9 add wave -noupdate -group FIFO_f0_A /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/wen
10 add wave -noupdate -expand -group FIFO_f0_A /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/full
10 add wave -noupdate -group FIFO_f0_A /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/full
11 add wave -noupdate -expand -group FIFO_f0_A /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/almost_full
11 add wave -noupdate -group FIFO_f0_A /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/almost_full
12 add wave -noupdate -expand -group FIFO_f0_A /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/empty
12 add wave -noupdate -group FIFO_f0_A /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/empty
13 add wave -noupdate -expand -group FIFO_f0_A /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/ren
13 add wave -noupdate -group FIFO_f0_A /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/ren
14 add wave -noupdate -group FIFO_f0_A -radix decimal /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/fifos(0)/lpp_fifo_1/raddr_vect
15 add wave -noupdate -group FIFO_f0_A -radix decimal /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/fifos(0)/lpp_fifo_1/waddr_vect
16 add wave -noupdate -group FIFO_f0_A /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/fifos(0)/lpp_fifo_1/more_16data
17 add wave -noupdate -group FIFO_f0_A -radix hexadecimal /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/fifos(0)/lpp_fifo_1/memcel/cram/ramarray
14 add wave -noupdate -expand -group FIFO_f0_B /tb/lpp_lfr_ms_1/lppfifoxn_f0_b/wen
18 add wave -noupdate -expand -group FIFO_f0_B /tb/lpp_lfr_ms_1/lppfifoxn_f0_b/wen
15 add wave -noupdate -expand -group FIFO_f0_B /tb/lpp_lfr_ms_1/lppfifoxn_f0_b/full
19 add wave -noupdate -expand -group FIFO_f0_B /tb/lpp_lfr_ms_1/lppfifoxn_f0_b/full
16 add wave -noupdate -expand -group FIFO_f0_B /tb/lpp_lfr_ms_1/lppfifoxn_f0_b/almost_full
20 add wave -noupdate -expand -group FIFO_f0_B /tb/lpp_lfr_ms_1/lppfifoxn_f0_b/almost_full
17 add wave -noupdate -expand -group FIFO_f0_B /tb/lpp_lfr_ms_1/lppfifoxn_f0_b/empty
21 add wave -noupdate -expand -group FIFO_f0_B /tb/lpp_lfr_ms_1/lppfifoxn_f0_b/empty
18 add wave -noupdate -expand -group FIFO_f0_B /tb/lpp_lfr_ms_1/lppfifoxn_f0_b/ren
22 add wave -noupdate -expand -group FIFO_f0_B /tb/lpp_lfr_ms_1/lppfifoxn_f0_b/ren
19 add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/wen
23 add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/wen
24 add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/fifos(0)/lpp_fifo_1/memcel/cram/rwclk
20 add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/full
25 add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/full
21 add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/almost_full
26 add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/almost_full
22 add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/empty
27 add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/empty
23 add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/ren
28 add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/ren
29 add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/fifos(0)/lpp_fifo_1/more_16data
30 add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/fifos(0)/lpp_fifo_1/sfull
31 add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/fifos(0)/lpp_fifo_1/sfull_s
32 add wave -noupdate -expand -group FIFO_f1 -radix hexadecimal /tb/lpp_lfr_ms_1/lppfifoxn_f1/fifos(0)/lpp_fifo_1/memcel/cram/ramarray
24 add wave -noupdate -expand -group FIFO_f2 /tb/lpp_lfr_ms_1/lppfifoxn_f2/wen
33 add wave -noupdate -expand -group FIFO_f2 /tb/lpp_lfr_ms_1/lppfifoxn_f2/wen
25 add wave -noupdate -expand -group FIFO_f2 /tb/lpp_lfr_ms_1/lppfifoxn_f2/full
34 add wave -noupdate -expand -group FIFO_f2 /tb/lpp_lfr_ms_1/lppfifoxn_f2/full
26 add wave -noupdate -expand -group FIFO_f2 /tb/lpp_lfr_ms_1/lppfifoxn_f2/almost_full
35 add wave -noupdate -expand -group FIFO_f2 /tb/lpp_lfr_ms_1/lppfifoxn_f2/almost_full
27 add wave -noupdate -expand -group FIFO_f2 /tb/lpp_lfr_ms_1/lppfifoxn_f2/empty
36 add wave -noupdate -expand -group FIFO_f2 /tb/lpp_lfr_ms_1/lppfifoxn_f2/empty
28 add wave -noupdate -expand -group FIFO_f2 /tb/lpp_lfr_ms_1/lppfifoxn_f2/ren
37 add wave -noupdate -expand -group FIFO_f2 /tb/lpp_lfr_ms_1/lppfifoxn_f2/ren
29 add wave -noupdate /tb/lpp_lfr_ms_1/state_fsm_select_channel
38 add wave -noupdate /tb/lpp_lfr_ms_1/state_fsm_select_channel
30 add wave -noupdate /tb/lpp_lfr_ms_1/state_fsm_load_fft
39 add wave -noupdate /tb/lpp_lfr_ms_1/state_fsm_load_fft
31 add wave -noupdate /tb/lpp_lfr_ms_1/corefft_1/ifoload
40 add wave -noupdate /tb/lpp_lfr_ms_1/corefft_1/ifoload
32 add wave -noupdate /tb/lpp_lfr_ms_1/corefft_1/ifid_im
41 add wave -noupdate /tb/lpp_lfr_ms_1/corefft_1/ifid_im
33 add wave -noupdate -radix hexadecimal /tb/lpp_lfr_ms_1/corefft_1/ifid_re
42 add wave -noupdate -radix hexadecimal /tb/lpp_lfr_ms_1/corefft_1/ifid_re
34 add wave -noupdate /tb/lpp_lfr_ms_1/corefft_1/ifid_valid
43 add wave -noupdate /tb/lpp_lfr_ms_1/corefft_1/ifid_valid
35 add wave -noupdate /tb/lpp_lfr_ms_1/corefft_1/ifinreset
44 add wave -noupdate /tb/lpp_lfr_ms_1/corefft_1/ifinreset
36 add wave -noupdate /tb/lpp_lfr_ms_1/corefft_1/ifistart
45 add wave -noupdate /tb/lpp_lfr_ms_1/corefft_1/ifistart
37 add wave -noupdate -expand -group ERROR /tb/lpp_lfr_ms_1/error_wen_f0
46 add wave -noupdate -expand -group ERROR /tb/lpp_lfr_ms_1/error_wen_f0
38 add wave -noupdate -expand -group ERROR /tb/lpp_lfr_ms_1/error_wen_f1
47 add wave -noupdate -expand -group ERROR /tb/lpp_lfr_ms_1/error_wen_f1
39 add wave -noupdate -expand -group ERROR /tb/lpp_lfr_ms_1/error_wen_f2
48 add wave -noupdate -expand -group ERROR /tb/lpp_lfr_ms_1/error_wen_f2
40 add wave -noupdate -expand -group FFT_RESULT_INTERFACE /tb/lpp_lfr_ms_1/corefft_1/ifiread_y
49 add wave -noupdate -expand -group FFT_RESULT_INTERFACE /tb/lpp_lfr_ms_1/corefft_1/ifiread_y
41 add wave -noupdate -expand -group FFT_RESULT_INTERFACE /tb/lpp_lfr_ms_1/corefft_1/ifopong
50 add wave -noupdate -expand -group FFT_RESULT_INTERFACE /tb/lpp_lfr_ms_1/corefft_1/ifopong
42 add wave -noupdate -expand -group FFT_RESULT_INTERFACE /tb/lpp_lfr_ms_1/corefft_1/ifoy_rdy
51 add wave -noupdate -expand -group FFT_RESULT_INTERFACE /tb/lpp_lfr_ms_1/corefft_1/ifoy_rdy
43 add wave -noupdate -expand -group FFT_RESULT_INTERFACE /tb/lpp_lfr_ms_1/corefft_1/ifoy_valid
52 add wave -noupdate -expand -group FFT_RESULT_INTERFACE /tb/lpp_lfr_ms_1/corefft_1/ifoy_valid
44 add wave -noupdate -expand -group FFT_RESULT_INTERFACE -radix hexadecimal /tb/lpp_lfr_ms_1/corefft_1/ifoy_im
53 add wave -noupdate -expand -group FFT_RESULT_INTERFACE -radix hexadecimal /tb/lpp_lfr_ms_1/corefft_1/ifoy_im
45 add wave -noupdate -expand -group FFT_RESULT_INTERFACE -radix hexadecimal /tb/lpp_lfr_ms_1/corefft_1/ifoy_re
54 add wave -noupdate -expand -group FFT_RESULT_INTERFACE -radix hexadecimal /tb/lpp_lfr_ms_1/corefft_1/ifoy_re
46 add wave -noupdate -expand -group FFT_RESULT_INTERFACE -radix hexadecimal /tb/lpp_lfr_ms_1/corefft_1/lpp_fifo_1/memcel/cram/ramarray
55 add wave -noupdate -expand -group FFT_RESULT_INTERFACE -radix hexadecimal /tb/lpp_lfr_ms_1/corefft_1/lpp_fifo_1/memcel/cram/ramarray
47 add wave -noupdate /tb/lpp_lfr_ms_1/status_channel
56 add wave -noupdate /tb/lpp_lfr_ms_1/status_channel
48 add wave -noupdate -expand -group FIFO_MS_INPUT -radix hexadecimal -subitemconfig {/tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(0) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(1) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(2) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(3) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(4) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(5) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(6) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(7) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(8) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(9) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(10) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(11) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(12) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(13) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(14) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(15) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(16) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(17) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(18) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(19) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(20) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(21) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(22) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(23) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(24) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(25) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(26) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(27) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(28) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(29) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(30) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(31) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(32) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(33) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(34) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(35) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(36) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(37) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(38) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(39) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(40) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(41) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(42) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(43) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(44) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(45) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(46) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(47) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(48) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(49) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(50) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(51) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(52) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(53) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(54) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(55) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(56) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(57) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(58) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(59) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(60) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(61) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(62) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(63) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(64) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(65) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(66) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(67) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(68) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(69) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(70) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(71) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(72) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(73) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(74) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(75) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(76) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(77) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(78) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(79) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(80) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(81) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(82) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(83) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(84) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(85) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(86) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(87) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(88) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(89) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(90) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(91) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(92) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(93) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(94) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(95) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(96) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(97) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(98) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(99) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(100) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(101) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(102) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(103) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(104) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(105) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(106) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(107) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(108) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(109) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(110) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(111) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(112) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(113) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(114) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(115) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(116) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(117) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(118) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(119) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(120) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(121) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(122) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(123) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(124) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(125) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(126) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(127) {-height 15 -radix hexadecimal}} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray
57 add wave -noupdate -expand -group FIFO_MS_INPUT -radix hexadecimal /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray
49 add wave -noupdate -expand -group FIFO_MS_INPUT -radix hexadecimal -subitemconfig {/tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(0) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(1) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(2) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(3) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(4) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(5) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(6) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(7) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(8) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(9) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(10) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(11) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(12) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(13) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(14) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(15) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(16) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(17) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(18) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(19) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(20) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(21) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(22) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(23) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(24) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(25) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(26) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(27) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(28) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(29) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(30) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(31) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(32) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(33) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(34) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(35) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(36) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(37) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(38) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(39) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(40) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(41) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(42) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(43) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(44) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(45) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(46) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(47) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(48) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(49) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(50) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(51) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(52) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(53) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(54) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(55) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(56) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(57) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(58) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(59) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(60) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(61) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(62) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(63) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(64) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(65) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(66) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(67) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(68) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(69) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(70) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(71) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(72) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(73) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(74) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(75) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(76) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(77) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(78) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(79) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(80) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(81) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(82) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(83) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(84) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(85) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(86) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(87) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(88) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(89) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(90) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(91) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(92) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(93) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(94) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(95) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(96) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(97) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(98) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(99) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(100) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(101) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(102) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(103) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(104) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(105) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(106) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(107) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(108) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(109) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(110) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(111) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(112) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(113) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(114) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(115) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(116) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(117) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(118) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(119) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(120) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(121) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(122) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(123) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(124) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(125) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(126) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(127) {-height 15 -radix hexadecimal}} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray
58 add wave -noupdate -expand -group FIFO_MS_INPUT -radix hexadecimal /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray
50 add wave -noupdate -expand -group FIFO_MS_INPUT -radix hexadecimal -subitemconfig {/tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(0) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(1) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(2) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(3) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(4) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(5) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(6) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(7) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(8) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(9) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(10) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(11) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(12) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(13) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(14) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(15) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(16) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(17) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(18) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(19) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(20) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(21) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(22) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(23) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(24) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(25) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(26) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(27) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(28) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(29) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(30) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(31) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(32) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(33) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(34) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(35) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(36) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(37) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(38) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(39) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(40) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(41) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(42) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(43) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(44) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(45) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(46) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(47) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(48) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(49) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(50) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(51) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(52) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(53) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(54) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(55) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(56) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(57) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(58) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(59) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(60) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(61) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(62) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(63) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(64) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(65) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(66) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(67) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(68) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(69) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(70) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(71) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(72) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(73) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(74) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(75) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(76) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(77) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(78) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(79) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(80) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(81) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(82) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(83) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(84) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(85) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(86) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(87) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(88) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(89) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(90) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(91) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(92) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(93) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(94) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(95) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(96) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(97) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(98) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(99) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(100) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(101) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(102) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(103) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(104) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(105) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(106) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(107) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(108) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(109) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(110) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(111) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(112) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(113) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(114) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(115) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(116) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(117) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(118) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(119) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(120) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(121) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(122) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(123) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(124) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(125) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(126) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(127) {-radix hexadecimal}} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray
59 add wave -noupdate -expand -group FIFO_MS_INPUT -radix hexadecimal /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray
51 add wave -noupdate -expand -group FIFO_MS_INPUT -radix hexadecimal -subitemconfig {/tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(0) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(1) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(2) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(3) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(4) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(5) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(6) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(7) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(8) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(9) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(10) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(11) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(12) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(13) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(14) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(15) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(16) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(17) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(18) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(19) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(20) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(21) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(22) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(23) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(24) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(25) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(26) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(27) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(28) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(29) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(30) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(31) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(32) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(33) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(34) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(35) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(36) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(37) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(38) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(39) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(40) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(41) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(42) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(43) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(44) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(45) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(46) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(47) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(48) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(49) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(50) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(51) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(52) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(53) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(54) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(55) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(56) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(57) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(58) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(59) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(60) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(61) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(62) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(63) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(64) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(65) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(66) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(67) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(68) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(69) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(70) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(71) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(72) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(73) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(74) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(75) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(76) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(77) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(78) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(79) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(80) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(81) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(82) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(83) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(84) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(85) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(86) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(87) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(88) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(89) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(90) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(91) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(92) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(93) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(94) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(95) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(96) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(97) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(98) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(99) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(100) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(101) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(102) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(103) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(104) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(105) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(106) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(107) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(108) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(109) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(110) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(111) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(112) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(113) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(114) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(115) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(116) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(117) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(118) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(119) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(120) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(121) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(122) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(123) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(124) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(125) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(126) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(127) {-radix hexadecimal}} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray
60 add wave -noupdate -expand -group FIFO_MS_INPUT -radix hexadecimal /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray
52 add wave -noupdate -expand -group FIFO_MS_INPUT -radix hexadecimal -subitemconfig {/tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(0) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(1) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(2) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(3) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(4) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(5) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(6) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(7) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(8) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(9) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(10) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(11) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(12) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(13) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(14) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(15) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(16) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(17) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(18) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(19) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(20) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(21) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(22) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(23) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(24) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(25) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(26) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(27) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(28) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(29) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(30) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(31) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(32) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(33) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(34) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(35) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(36) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(37) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(38) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(39) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(40) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(41) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(42) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(43) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(44) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(45) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(46) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(47) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(48) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(49) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(50) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(51) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(52) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(53) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(54) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(55) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(56) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(57) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(58) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(59) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(60) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(61) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(62) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(63) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(64) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(65) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(66) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(67) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(68) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(69) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(70) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(71) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(72) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(73) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(74) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(75) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(76) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(77) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(78) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(79) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(80) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(81) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(82) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(83) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(84) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(85) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(86) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(87) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(88) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(89) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(90) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(91) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(92) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(93) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(94) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(95) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(96) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(97) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(98) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(99) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(100) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(101) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(102) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(103) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(104) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(105) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(106) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(107) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(108) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(109) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(110) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(111) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(112) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(113) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(114) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(115) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(116) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(117) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(118) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(119) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(120) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(121) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(122) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(123) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(124) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(125) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(126) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(127) {-radix hexadecimal}} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray
61 add wave -noupdate -expand -group FIFO_MS_INPUT -radix hexadecimal /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray
53 add wave -noupdate -radix hexadecimal /tb/lpp_lfr_ms_1/current_fifo_load
62 add wave -noupdate -radix hexadecimal /tb/lpp_lfr_ms_1/current_fifo_load
54 add wave -noupdate /tb/lpp_lfr_ms_1/state_fsm_load_ms_memory
63 add wave -noupdate /tb/lpp_lfr_ms_1/state_fsm_load_ms_memory
55 add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/almost_full
64 add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/almost_full
56 add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/empty
65 add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/empty
57 add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/full
66 add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/full
58 add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/wdata
67 add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/wdata
59 add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/wen
68 add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/wen
60 add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_sm_locked
69 add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_sm_locked
61 add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_sm_rdata
70 add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_sm_rdata
62 add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_sm_ren
71 add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_sm_ren
72 add wave -noupdate -expand -group MS_CALCULATION /tb/lpp_lfr_ms_1/ms_calculation_1/correlation_auto
73 add wave -noupdate -expand -group MS_CALCULATION /tb/lpp_lfr_ms_1/ms_calculation_1/correlation_done
74 add wave -noupdate -expand -group MS_CALCULATION /tb/lpp_lfr_ms_1/ms_calculation_1/correlation_start
75 add wave -noupdate -expand -group MS_CALCULATION -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/fifo_in_data
76 add wave -noupdate -expand -group MS_CALCULATION /tb/lpp_lfr_ms_1/ms_calculation_1/fifo_in_empty
77 add wave -noupdate -expand -group MS_CALCULATION /tb/lpp_lfr_ms_1/ms_calculation_1/fifo_in_ren
78 add wave -noupdate -expand -group MS_CALCULATION -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/fifo_out_data
79 add wave -noupdate -expand -group MS_CALCULATION /tb/lpp_lfr_ms_1/ms_calculation_1/fifo_out_full
80 add wave -noupdate -expand -group MS_CALCULATION /tb/lpp_lfr_ms_1/ms_calculation_1/fifo_out_wen
81 add wave -noupdate -expand -group MS_CALCULATION -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/op1
82 add wave -noupdate -expand -group MS_CALCULATION -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/op2
83 add wave -noupdate -expand -group MS_CALCULATION -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/res
84 add wave -noupdate -expand -group MS_CALCULATION /tb/lpp_lfr_ms_1/ms_calculation_1/state
85 add wave -noupdate /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/empty
86 add wave -noupdate /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/full
87 add wave -noupdate /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/wdata
88 add wave -noupdate /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/wen
89 add wave -noupdate -expand -group FIFO_1 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(1)/lpp_fifo_1/raddr_vect
90 add wave -noupdate -expand -group FIFO_1 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(1)/lpp_fifo_1/raddr_vect_s
91 add wave -noupdate -expand -group FIFO_1 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(1)/lpp_fifo_1/waddr_vect
92 add wave -noupdate -expand -group FIFO_1 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(1)/lpp_fifo_1/waddr_vect_s
93 add wave -noupdate -expand -group FIFO_1 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray
94 add wave -noupdate -expand -group FIF0_0 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/raddr_vect
95 add wave -noupdate -expand -group FIF0_0 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/raddr_vect_s
96 add wave -noupdate -expand -group FIF0_0 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/waddr_vect
97 add wave -noupdate -expand -group FIF0_0 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/waddr_vect_s
98 add wave -noupdate -expand -group FIF0_0 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray
99 add wave -noupdate /tb/lpp_lfr_ms_1/status_component_fifo_0
100 add wave -noupdate /tb/lpp_lfr_ms_1/status_component_fifo_0_end
101 add wave -noupdate /tb/lpp_lfr_ms_1/status_component_fifo_0_new
102 add wave -noupdate /tb/lpp_lfr_ms_1/status_component_fifo_1
103 add wave -noupdate /tb/lpp_lfr_ms_1/status_component_fifo_1_end
104 add wave -noupdate /tb/lpp_lfr_ms_1/status_component_fifo_1_new
105 add wave -noupdate -expand -group FSM_DMA_FIFO_IN -radix hexadecimal /tb/lpp_lfr_ms_1/fifo_0_ready
106 add wave -noupdate -expand -group FSM_DMA_FIFO_IN -radix hexadecimal /tb/lpp_lfr_ms_1/fifo_1_ready
107 add wave -noupdate -expand -group FSM_DMA_FIFO_IN -radix hexadecimal /tb/lpp_lfr_ms_1/fifo_ongoing
108 add wave -noupdate -expand -group FSM_DMA_FIFO_IN -radix hexadecimal /tb/lpp_lfr_ms_1/fsm_dma_fifo_data
109 add wave -noupdate -expand -group FSM_DMA_FIFO_IN -radix hexadecimal /tb/lpp_lfr_ms_1/fsm_dma_fifo_empty
110 add wave -noupdate -expand -group FSM_DMA_FIFO_IN -radix hexadecimal /tb/lpp_lfr_ms_1/fsm_dma_fifo_ren
111 add wave -noupdate -expand -group FSM_DMA_FIFO_IN -radix hexadecimal /tb/lpp_lfr_ms_1/fsm_dma_fifo_status
112 add wave -noupdate -expand -group DMA_OUTPUT /tb/dma_addr
113 add wave -noupdate -expand -group DMA_OUTPUT /tb/dma_data
114 add wave -noupdate -expand -group DMA_OUTPUT /tb/dma_done
115 add wave -noupdate -expand -group DMA_OUTPUT /tb/dma_ren
116 add wave -noupdate -expand -group DMA_OUTPUT /tb/dma_valid
117 add wave -noupdate -expand -group DMA_OUTPUT /tb/dma_valid_burst
118 add wave -noupdate -expand -group DMA_OUTPUT -radix hexadecimal /tb/matrix_time_f0_0
119 add wave -noupdate -expand -group DMA_OUTPUT -radix hexadecimal /tb/matrix_time_f0_1
120 add wave -noupdate -expand -group DMA_OUTPUT -radix hexadecimal /tb/matrix_time_f1
121 add wave -noupdate -expand -group DMA_OUTPUT -radix hexadecimal /tb/matrix_time_f2
122 add wave -noupdate -expand -group DMA_OUTPUT -radix hexadecimal /tb/ready_matrix_f0_0
123 add wave -noupdate -expand -group DMA_OUTPUT -radix hexadecimal /tb/ready_matrix_f0_1
124 add wave -noupdate -expand -group DMA_OUTPUT -radix hexadecimal /tb/ready_matrix_f1
125 add wave -noupdate -expand -group DMA_OUTPUT -radix hexadecimal /tb/ready_matrix_f2
126 add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/state
127 add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/matrix_type
128 add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/component_type_pre
129 add wave -noupdate -radix unsigned /tb/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/component_type
130 add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/header_check_ok
131 add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/fifo_empty
132 add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/log_empty_fifo
63 TreeUpdate [SetDefaultTree]
133 TreeUpdate [SetDefaultTree]
64 WaveRestoreCursors {{Cursor 1} {189796403054 ps} 0} {{Cursor 2} {33725957281 ps} 0} {{Cursor 3} {10434056078 ps} 0} {{Cursor 4} {47317662811 ps} 0} {{Cursor 5} {82561584962 ps} 0}
134 WaveRestoreCursors {{Cursor 1} {189796403054 ps} 0} {{Cursor 2} {44837900611 ps} 0} {{Cursor 3} {10445420000 ps} 0} {{Cursor 4} {61378464308 ps} 0} {{Cursor 5} {99992359332 ps} 0}
65 configure wave -namecolwidth 469
135 configure wave -namecolwidth 469
66 configure wave -valuecolwidth 112
136 configure wave -valuecolwidth 112
67 configure wave -justifyvalue left
137 configure wave -justifyvalue left
68 configure wave -signalnamewidth 0
138 configure wave -signalnamewidth 0
69 configure wave -snapdistance 10
139 configure wave -snapdistance 10
70 configure wave -datasetprefix 0
140 configure wave -datasetprefix 0
71 configure wave -rowmargin 4
141 configure wave -rowmargin 4
72 configure wave -childrowmargin 2
142 configure wave -childrowmargin 2
73 configure wave -gridoffset 0
143 configure wave -gridoffset 0
74 configure wave -gridperiod 1
144 configure wave -gridperiod 1
75 configure wave -griddelta 40
145 configure wave -griddelta 40
76 configure wave -timeline 0
146 configure wave -timeline 0
77 configure wave -timelineunits ps
147 configure wave -timelineunits ps
78 update
148 update
79 WaveRestoreZoom {10429891270 ps} {10442522246 ps}
149 WaveRestoreZoom {10380584292 ps} {10668763932 ps}
80 bookmark add wave bookmark0 {{61745287067 ps} {63754655343 ps}} 0
150 bookmark add wave bookmark0 {{61745287067 ps} {63754655343 ps}} 0
81 bookmark add wave bookmark1 {{61745287067 ps} {63754655343 ps}} 0
151 bookmark add wave bookmark1 {{61745287067 ps} {63754655343 ps}} 0
Show file before | Show file after | Hide comments
@@ -1,323 +1,334
1 LIBRARY ieee;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
2 USE ieee.std_logic_1164.ALL;
3
3
4 LIBRARY grlib;
4 LIBRARY grlib;
5 USE grlib.amba.ALL;
5 USE grlib.amba.ALL;
6
6
7 LIBRARY lpp;
7 LIBRARY lpp;
8 USE lpp.lpp_ad_conv.ALL;
8 USE lpp.lpp_ad_conv.ALL;
9 USE lpp.iir_filter.ALL;
9 USE lpp.iir_filter.ALL;
10 USE lpp.FILTERcfg.ALL;
10 USE lpp.FILTERcfg.ALL;
11 USE lpp.lpp_memory.ALL;
11 USE lpp.lpp_memory.ALL;
12 LIBRARY techmap;
12 LIBRARY techmap;
13 USE techmap.gencomp.ALL;
13 USE techmap.gencomp.ALL;
14
14
15 PACKAGE lpp_lfr_pkg IS
15 PACKAGE lpp_lfr_pkg IS
16
16
17 COMPONENT lpp_lfr_ms
17 COMPONENT lpp_lfr_ms
18 GENERIC (
18 GENERIC (
19 Mem_use : INTEGER
19 Mem_use : INTEGER
20 );
20 );
21 PORT (
21 PORT (
22 clk : IN STD_LOGIC;
22 clk : IN STD_LOGIC;
23 rstn : IN STD_LOGIC;
23 rstn : IN STD_LOGIC;
24
24
25 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
25 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
26 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
26 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
27
27
28 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
28 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
29 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
29 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
30
30 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
31 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
31 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
32 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
32 sample_f3_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
33
33 sample_f3_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
34 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
35 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
34
36
35 dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
37 dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
36 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
38 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
37 dma_valid : OUT STD_LOGIC;
39 dma_valid : OUT STD_LOGIC;
38 dma_valid_burst : OUT STD_LOGIC;
40 dma_valid_burst : OUT STD_LOGIC;
39 dma_ren : IN STD_LOGIC;
41 dma_ren : IN STD_LOGIC;
40 dma_done : IN STD_LOGIC;
42 dma_done : IN STD_LOGIC;
41
43
42 ready_matrix_f0_0 : OUT STD_LOGIC;
44 ready_matrix_f0 : OUT STD_LOGIC;
43 ready_matrix_f0_1 : OUT STD_LOGIC;
45 -- ready_matrix_f0_1 : OUT STD_LOGIC;
44 ready_matrix_f1 : OUT STD_LOGIC;
46 ready_matrix_f1 : OUT STD_LOGIC;
45 ready_matrix_f2 : OUT STD_LOGIC;
47 ready_matrix_f2 : OUT STD_LOGIC;
46 error_anticipating_empty_fifo : OUT STD_LOGIC;
48 -- error_anticipating_empty_fifo : OUT STD_LOGIC;
47 error_bad_component_error : OUT STD_LOGIC;
49 error_bad_component_error : OUT STD_LOGIC;
50 error_buffer_full : OUT STD_LOGIC;
51 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
48 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
52 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
49 status_ready_matrix_f0_0 : IN STD_LOGIC;
53 status_ready_matrix_f0 : IN STD_LOGIC;
50 status_ready_matrix_f0_1 : IN STD_LOGIC;
54 -- status_ready_matrix_f0_1 : IN STD_LOGIC;
51 status_ready_matrix_f1 : IN STD_LOGIC;
55 status_ready_matrix_f1 : IN STD_LOGIC;
52 status_ready_matrix_f2 : IN STD_LOGIC;
56 status_ready_matrix_f2 : IN STD_LOGIC;
53 status_error_anticipating_empty_fifo : IN STD_LOGIC;
57 -- status_error_anticipating_empty_fifo : IN STD_LOGIC;
54 status_error_bad_component_error : IN STD_LOGIC;
58 -- status_error_bad_component_error : IN STD_LOGIC;
55 config_active_interruption_onNewMatrix : IN STD_LOGIC;
59 config_active_interruption_onNewMatrix : IN STD_LOGIC;
56 config_active_interruption_onError : IN STD_LOGIC;
60 config_active_interruption_onError : IN STD_LOGIC;
57 addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
61 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
58 addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
62 -- addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
59 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
63 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
60 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
64 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
61
65
62 matrix_time_f0_0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
66 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
63 matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
67 -- matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
64 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
68 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
65 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0));
69 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0));
66 END COMPONENT;
70 END COMPONENT;
67
71
68 COMPONENT lpp_lfr_ms_fsmdma
72 COMPONENT lpp_lfr_ms_fsmdma
69 PORT (
73 PORT (
70 HCLK : IN STD_ULOGIC;
74 HCLK : IN STD_ULOGIC;
71 HRESETn : IN STD_ULOGIC;
75 HRESETn : IN STD_ULOGIC;
72 data_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
76 fifo_matrix_type : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
73 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
77 fifo_matrix_component : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
74 fifo_empty : IN STD_LOGIC;
78 fifo_matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
75 fifo_ren : OUT STD_LOGIC;
79 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
76 header : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
80 fifo_empty : IN STD_LOGIC;
77 header_val : IN STD_LOGIC;
81 fifo_ren : OUT STD_LOGIC;
78 header_ack : OUT STD_LOGIC;
82 --data_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
83 --fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
84 --fifo_empty : IN STD_LOGIC;
85 --fifo_ren : OUT STD_LOGIC;
86 --header : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
87 --header_val : IN STD_LOGIC;
88 --header_ack : OUT STD_LOGIC;
79 dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
89 dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
80 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
90 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
81 dma_valid : OUT STD_LOGIC;
91 dma_valid : OUT STD_LOGIC;
82 dma_valid_burst : OUT STD_LOGIC;
92 dma_valid_burst : OUT STD_LOGIC;
83 dma_ren : IN STD_LOGIC;
93 dma_ren : IN STD_LOGIC;
84 dma_done : IN STD_LOGIC;
94 dma_done : IN STD_LOGIC;
85 ready_matrix_f0_0 : OUT STD_LOGIC;
95 ready_matrix_f0 : OUT STD_LOGIC;
86 ready_matrix_f0_1 : OUT STD_LOGIC;
96 -- ready_matrix_f0_1 : OUT STD_LOGIC;
87 ready_matrix_f1 : OUT STD_LOGIC;
97 ready_matrix_f1 : OUT STD_LOGIC;
88 ready_matrix_f2 : OUT STD_LOGIC;
98 ready_matrix_f2 : OUT STD_LOGIC;
89 error_anticipating_empty_fifo : OUT STD_LOGIC;
99 -- error_anticipating_empty_fifo : OUT STD_LOGIC;
90 error_bad_component_error : OUT STD_LOGIC;
100 error_bad_component_error : OUT STD_LOGIC;
101 error_buffer_full : OUT STD_LOGIC;
91 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
102 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
92 status_ready_matrix_f0_0 : IN STD_LOGIC;
103 status_ready_matrix_f0 : IN STD_LOGIC;
93 status_ready_matrix_f0_1 : IN STD_LOGIC;
104 -- status_ready_matrix_f0_1 : IN STD_LOGIC;
94 status_ready_matrix_f1 : IN STD_LOGIC;
105 status_ready_matrix_f1 : IN STD_LOGIC;
95 status_ready_matrix_f2 : IN STD_LOGIC;
106 status_ready_matrix_f2 : IN STD_LOGIC;
96 status_error_anticipating_empty_fifo : IN STD_LOGIC;
107 -- status_error_anticipating_empty_fifo : IN STD_LOGIC;
97 status_error_bad_component_error : IN STD_LOGIC;
108 -- status_error_bad_component_error : IN STD_LOGIC;
98 config_active_interruption_onNewMatrix : IN STD_LOGIC;
109 config_active_interruption_onNewMatrix : IN STD_LOGIC;
99 config_active_interruption_onError : IN STD_LOGIC;
110 config_active_interruption_onError : IN STD_LOGIC;
100 addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
111 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
101 addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
112 -- addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
102 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
113 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
103 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
114 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
104
115
105 matrix_time_f0_0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
116 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
106 matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
117 -- matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
107 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
118 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
108 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
119 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
109 );
120 );
110 END COMPONENT;
121 END COMPONENT;
111
122
112
123
113 COMPONENT lpp_lfr_filter
124 COMPONENT lpp_lfr_filter
114 GENERIC (
125 GENERIC (
115 Mem_use : INTEGER);
126 Mem_use : INTEGER);
116 PORT (
127 PORT (
117 sample : IN Samples(7 DOWNTO 0);
128 sample : IN Samples(7 DOWNTO 0);
118 sample_val : IN STD_LOGIC;
129 sample_val : IN STD_LOGIC;
119 clk : IN STD_LOGIC;
130 clk : IN STD_LOGIC;
120 rstn : IN STD_LOGIC;
131 rstn : IN STD_LOGIC;
121 data_shaping_SP0 : IN STD_LOGIC;
132 data_shaping_SP0 : IN STD_LOGIC;
122 data_shaping_SP1 : IN STD_LOGIC;
133 data_shaping_SP1 : IN STD_LOGIC;
123 data_shaping_R0 : IN STD_LOGIC;
134 data_shaping_R0 : IN STD_LOGIC;
124 data_shaping_R1 : IN STD_LOGIC;
135 data_shaping_R1 : IN STD_LOGIC;
125 sample_f0_val : OUT STD_LOGIC;
136 sample_f0_val : OUT STD_LOGIC;
126 sample_f1_val : OUT STD_LOGIC;
137 sample_f1_val : OUT STD_LOGIC;
127 sample_f2_val : OUT STD_LOGIC;
138 sample_f2_val : OUT STD_LOGIC;
128 sample_f3_val : OUT STD_LOGIC;
139 sample_f3_val : OUT STD_LOGIC;
129 sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
140 sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
130 sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
141 sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
131 sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
142 sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
132 sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0));
143 sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0));
133 END COMPONENT;
144 END COMPONENT;
134
145
135 COMPONENT lpp_lfr
146 COMPONENT lpp_lfr
136 GENERIC (
147 GENERIC (
137 Mem_use : INTEGER;
148 Mem_use : INTEGER;
138 nb_data_by_buffer_size : INTEGER;
149 nb_data_by_buffer_size : INTEGER;
139 nb_word_by_buffer_size : INTEGER;
150 nb_word_by_buffer_size : INTEGER;
140 nb_snapshot_param_size : INTEGER;
151 nb_snapshot_param_size : INTEGER;
141 delta_vector_size : INTEGER;
152 delta_vector_size : INTEGER;
142 delta_vector_size_f0_2 : INTEGER;
153 delta_vector_size_f0_2 : INTEGER;
143 pindex : INTEGER;
154 pindex : INTEGER;
144 paddr : INTEGER;
155 paddr : INTEGER;
145 pmask : INTEGER;
156 pmask : INTEGER;
146 pirq_ms : INTEGER;
157 pirq_ms : INTEGER;
147 pirq_wfp : INTEGER;
158 pirq_wfp : INTEGER;
148 hindex : INTEGER;
159 hindex : INTEGER;
149 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0)
160 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0)
150 );
161 );
151 PORT (
162 PORT (
152 clk : IN STD_LOGIC;
163 clk : IN STD_LOGIC;
153 rstn : IN STD_LOGIC;
164 rstn : IN STD_LOGIC;
154 sample_B : IN Samples(2 DOWNTO 0);
165 sample_B : IN Samples(2 DOWNTO 0);
155 sample_E : IN Samples(4 DOWNTO 0);
166 sample_E : IN Samples(4 DOWNTO 0);
156 sample_val : IN STD_LOGIC;
167 sample_val : IN STD_LOGIC;
157 apbi : IN apb_slv_in_type;
168 apbi : IN apb_slv_in_type;
158 apbo : OUT apb_slv_out_type;
169 apbo : OUT apb_slv_out_type;
159 ahbi : IN AHB_Mst_In_Type;
170 ahbi : IN AHB_Mst_In_Type;
160 ahbo : OUT AHB_Mst_Out_Type;
171 ahbo : OUT AHB_Mst_Out_Type;
161 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
172 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
162 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
173 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
163 data_shaping_BW : OUT STD_LOGIC;
174 data_shaping_BW : OUT STD_LOGIC;
164 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
175 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
165 );
176 );
166 END COMPONENT;
177 END COMPONENT;
167
178
168 -----------------------------------------------------------------------------
179 -----------------------------------------------------------------------------
169 -- LPP_LFR with only WaveForm Picker (and without Spectral Matrix Sub System)
180 -- LPP_LFR with only WaveForm Picker (and without Spectral Matrix Sub System)
170 -----------------------------------------------------------------------------
181 -----------------------------------------------------------------------------
171 COMPONENT lpp_lfr_WFP_nMS
182 COMPONENT lpp_lfr_WFP_nMS
172 GENERIC (
183 GENERIC (
173 Mem_use : INTEGER;
184 Mem_use : INTEGER;
174 nb_data_by_buffer_size : INTEGER;
185 nb_data_by_buffer_size : INTEGER;
175 nb_word_by_buffer_size : INTEGER;
186 nb_word_by_buffer_size : INTEGER;
176 nb_snapshot_param_size : INTEGER;
187 nb_snapshot_param_size : INTEGER;
177 delta_vector_size : INTEGER;
188 delta_vector_size : INTEGER;
178 delta_vector_size_f0_2 : INTEGER;
189 delta_vector_size_f0_2 : INTEGER;
179 pindex : INTEGER;
190 pindex : INTEGER;
180 paddr : INTEGER;
191 paddr : INTEGER;
181 pmask : INTEGER;
192 pmask : INTEGER;
182 pirq_ms : INTEGER;
193 pirq_ms : INTEGER;
183 pirq_wfp : INTEGER;
194 pirq_wfp : INTEGER;
184 hindex : INTEGER;
195 hindex : INTEGER;
185 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0));
196 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0));
186 PORT (
197 PORT (
187 clk : IN STD_LOGIC;
198 clk : IN STD_LOGIC;
188 rstn : IN STD_LOGIC;
199 rstn : IN STD_LOGIC;
189 sample_B : IN Samples(2 DOWNTO 0);
200 sample_B : IN Samples(2 DOWNTO 0);
190 sample_E : IN Samples(4 DOWNTO 0);
201 sample_E : IN Samples(4 DOWNTO 0);
191 sample_val : IN STD_LOGIC;
202 sample_val : IN STD_LOGIC;
192 apbi : IN apb_slv_in_type;
203 apbi : IN apb_slv_in_type;
193 apbo : OUT apb_slv_out_type;
204 apbo : OUT apb_slv_out_type;
194 ahbi : IN AHB_Mst_In_Type;
205 ahbi : IN AHB_Mst_In_Type;
195 ahbo : OUT AHB_Mst_Out_Type;
206 ahbo : OUT AHB_Mst_Out_Type;
196 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
207 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
197 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
208 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
198 data_shaping_BW : OUT STD_LOGIC;
209 data_shaping_BW : OUT STD_LOGIC;
199 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
210 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
200 END COMPONENT;
211 END COMPONENT;
201 -----------------------------------------------------------------------------
212 -----------------------------------------------------------------------------
202
213
203
214
204 COMPONENT lpp_lfr_apbreg
215 COMPONENT lpp_lfr_apbreg
205 GENERIC (
216 GENERIC (
206 nb_data_by_buffer_size : INTEGER;
217 nb_data_by_buffer_size : INTEGER;
207 nb_word_by_buffer_size : INTEGER;
218 nb_word_by_buffer_size : INTEGER;
208 nb_snapshot_param_size : INTEGER;
219 nb_snapshot_param_size : INTEGER;
209 delta_vector_size : INTEGER;
220 delta_vector_size : INTEGER;
210 delta_vector_size_f0_2 : INTEGER;
221 delta_vector_size_f0_2 : INTEGER;
211 pindex : INTEGER;
222 pindex : INTEGER;
212 paddr : INTEGER;
223 paddr : INTEGER;
213 pmask : INTEGER;
224 pmask : INTEGER;
214 pirq_ms : INTEGER;
225 pirq_ms : INTEGER;
215 pirq_wfp : INTEGER;
226 pirq_wfp : INTEGER;
216 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0));
227 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0));
217 PORT (
228 PORT (
218 HCLK : IN STD_ULOGIC;
229 HCLK : IN STD_ULOGIC;
219 HRESETn : IN STD_ULOGIC;
230 HRESETn : IN STD_ULOGIC;
220 apbi : IN apb_slv_in_type;
231 apbi : IN apb_slv_in_type;
221 apbo : OUT apb_slv_out_type;
232 apbo : OUT apb_slv_out_type;
222 run_ms : OUT STD_LOGIC;
233 run_ms : OUT STD_LOGIC;
223 ready_matrix_f0_0 : IN STD_LOGIC;
234 ready_matrix_f0_0 : IN STD_LOGIC;
224 ready_matrix_f0_1 : IN STD_LOGIC;
235 ready_matrix_f0_1 : IN STD_LOGIC;
225 ready_matrix_f1 : IN STD_LOGIC;
236 ready_matrix_f1 : IN STD_LOGIC;
226 ready_matrix_f2 : IN STD_LOGIC;
237 ready_matrix_f2 : IN STD_LOGIC;
227 error_anticipating_empty_fifo : IN STD_LOGIC;
238 error_anticipating_empty_fifo : IN STD_LOGIC;
228 error_bad_component_error : IN STD_LOGIC;
239 error_bad_component_error : IN STD_LOGIC;
229 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
240 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
230 status_ready_matrix_f0_0 : OUT STD_LOGIC;
241 status_ready_matrix_f0_0 : OUT STD_LOGIC;
231 status_ready_matrix_f0_1 : OUT STD_LOGIC;
242 status_ready_matrix_f0_1 : OUT STD_LOGIC;
232 status_ready_matrix_f1 : OUT STD_LOGIC;
243 status_ready_matrix_f1 : OUT STD_LOGIC;
233 status_ready_matrix_f2 : OUT STD_LOGIC;
244 status_ready_matrix_f2 : OUT STD_LOGIC;
234 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
245 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
235 status_error_bad_component_error : OUT STD_LOGIC;
246 status_error_bad_component_error : OUT STD_LOGIC;
236 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
247 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
237 config_active_interruption_onError : OUT STD_LOGIC;
248 config_active_interruption_onError : OUT STD_LOGIC;
238 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
249 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
239 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
250 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
240 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
251 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
241 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
252 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
242
253
243 matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
254 matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
244 matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
255 matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
245 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
256 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
246 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
257 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
247
258
248 status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
259 status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
249 status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
260 status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
250 status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
261 status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
251 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
262 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
252 data_shaping_BW : OUT STD_LOGIC;
263 data_shaping_BW : OUT STD_LOGIC;
253 data_shaping_SP0 : OUT STD_LOGIC;
264 data_shaping_SP0 : OUT STD_LOGIC;
254 data_shaping_SP1 : OUT STD_LOGIC;
265 data_shaping_SP1 : OUT STD_LOGIC;
255 data_shaping_R0 : OUT STD_LOGIC;
266 data_shaping_R0 : OUT STD_LOGIC;
256 data_shaping_R1 : OUT STD_LOGIC;
267 data_shaping_R1 : OUT STD_LOGIC;
257 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
268 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
258 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
269 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
259 delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
270 delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
260 delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
271 delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
261 delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
272 delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
262 nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
273 nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
263 nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
274 nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
264 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
275 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
265 enable_f0 : OUT STD_LOGIC;
276 enable_f0 : OUT STD_LOGIC;
266 enable_f1 : OUT STD_LOGIC;
277 enable_f1 : OUT STD_LOGIC;
267 enable_f2 : OUT STD_LOGIC;
278 enable_f2 : OUT STD_LOGIC;
268 enable_f3 : OUT STD_LOGIC;
279 enable_f3 : OUT STD_LOGIC;
269 burst_f0 : OUT STD_LOGIC;
280 burst_f0 : OUT STD_LOGIC;
270 burst_f1 : OUT STD_LOGIC;
281 burst_f1 : OUT STD_LOGIC;
271 burst_f2 : OUT STD_LOGIC;
282 burst_f2 : OUT STD_LOGIC;
272 run : OUT STD_LOGIC;
283 run : OUT STD_LOGIC;
273 addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
284 addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
274 addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
285 addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
275 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
286 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
276 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
287 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
277 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
288 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
278 ---------------------------------------------------------------------------
289 ---------------------------------------------------------------------------
279 debug_reg0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
290 debug_reg0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
280 debug_reg1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
291 debug_reg1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
281 debug_reg2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
292 debug_reg2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
282 debug_reg3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
293 debug_reg3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
283 debug_reg4 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
294 debug_reg4 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
284 debug_reg5 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
295 debug_reg5 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
285 debug_reg6 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
296 debug_reg6 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
286 debug_reg7 : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
297 debug_reg7 : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
287 END COMPONENT;
298 END COMPONENT;
288
299
289 COMPONENT lpp_top_ms
300 COMPONENT lpp_top_ms
290 GENERIC (
301 GENERIC (
291 Mem_use : INTEGER;
302 Mem_use : INTEGER;
292 nb_burst_available_size : INTEGER;
303 nb_burst_available_size : INTEGER;
293 nb_snapshot_param_size : INTEGER;
304 nb_snapshot_param_size : INTEGER;
294 delta_snapshot_size : INTEGER;
305 delta_snapshot_size : INTEGER;
295 delta_f2_f0_size : INTEGER;
306 delta_f2_f0_size : INTEGER;
296 delta_f2_f1_size : INTEGER;
307 delta_f2_f1_size : INTEGER;
297 pindex : INTEGER;
308 pindex : INTEGER;
298 paddr : INTEGER;
309 paddr : INTEGER;
299 pmask : INTEGER;
310 pmask : INTEGER;
300 pirq_ms : INTEGER;
311 pirq_ms : INTEGER;
301 pirq_wfp : INTEGER;
312 pirq_wfp : INTEGER;
302 hindex_wfp : INTEGER;
313 hindex_wfp : INTEGER;
303 hindex_ms : INTEGER);
314 hindex_ms : INTEGER);
304 PORT (
315 PORT (
305 clk : IN STD_LOGIC;
316 clk : IN STD_LOGIC;
306 rstn : IN STD_LOGIC;
317 rstn : IN STD_LOGIC;
307 sample_B : IN Samples14v(2 DOWNTO 0);
318 sample_B : IN Samples14v(2 DOWNTO 0);
308 sample_E : IN Samples14v(4 DOWNTO 0);
319 sample_E : IN Samples14v(4 DOWNTO 0);
309 sample_val : IN STD_LOGIC;
320 sample_val : IN STD_LOGIC;
310 apbi : IN apb_slv_in_type;
321 apbi : IN apb_slv_in_type;
311 apbo : OUT apb_slv_out_type;
322 apbo : OUT apb_slv_out_type;
312 ahbi_ms : IN AHB_Mst_In_Type;
323 ahbi_ms : IN AHB_Mst_In_Type;
313 ahbo_ms : OUT AHB_Mst_Out_Type;
324 ahbo_ms : OUT AHB_Mst_Out_Type;
314 data_shaping_BW : OUT STD_LOGIC;
325 data_shaping_BW : OUT STD_LOGIC;
315 matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
326 matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
316 matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
327 matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
317 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
328 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
318 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0)
329 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0)
319
330
320 );
331 );
321 END COMPONENT;
332 END COMPONENT;
322
333
323 END lpp_lfr_pkg;
334 END lpp_lfr_pkg;
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