@@ -6,7 +6,9 ENTITY MS_control IS | |||
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6 | 6 | PORT ( |
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7 | 7 | clk : IN STD_LOGIC; |
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8 | 8 | rstn : IN STD_LOGIC; |
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9 | ||
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9 | -- IN | |
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10 | current_status_ms : IN STD_LOGIC_VECTOR(49 DOWNTO 0); -- TIME(47 .. 0) & Matrix_type(1..0) | |
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11 | ||
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10 | 12 | -- IN |
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11 | 13 | fifo_in_lock : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); |
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12 | 14 | fifo_in_data : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); |
@@ -19,6 +21,9 ENTITY MS_control IS | |||
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19 | 21 | fifo_out_ren : IN STD_LOGIC_VECTOR(1 DOWNTO 0); |
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20 | 22 | fifo_out_empty : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); |
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21 | 23 | -- OUT |
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24 | current_status_component : OUT STD_LOGIC_VECTOR(53 DOWNTO 0); -- TIME(47 .. 0) & | |
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25 | -- Matrix_type (1..0) | |
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26 | -- ComponentType (3..0) | |
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22 | 27 | correlation_start : OUT STD_LOGIC; |
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23 | 28 | correlation_auto : OUT STD_LOGIC; -- 1 => auto correlation / 0 => inter correlation |
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24 | 29 | correlation_done : IN STD_LOGIC |
@@ -30,7 +35,7 ARCHITECTURE beh OF MS_control IS | |||
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30 | 35 | TYPE fsm_control_MS IS (WAIT_DATA, CORRELATION_ONGOING); |
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31 | 36 | SIGNAL state : fsm_control_MS; |
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32 | 37 | |
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33 | SUBTYPE fifo_pointer IS RANGE 0 TO 4; | |
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38 | SUBTYPE fifo_pointer IS INTEGER RANGE 0 TO 4; | |
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34 | 39 | SIGNAL fifo_1 : fifo_pointer; |
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35 | 40 | SIGNAL fifo_2 : fifo_pointer; |
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36 | 41 | |
@@ -52,11 +57,13 BEGIN -- beh | |||
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52 | 57 | fifo_in_reuse_s <= (OTHERS => '0'); |
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53 | 58 | correlation_start <= '0'; |
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54 | 59 | correlation_auto <= '0'; |
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60 | current_status_component <= (OTHERS => '0'); | |
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55 | 61 | ELSIF clk'event AND clk = '1' THEN |
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56 | 62 | CASE state IS |
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63 | ||
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57 | 64 |
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58 | 65 | fifo_in_reuse_s <= (OTHERS => '0'); |
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59 |
IF fifo_in_full |
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66 | IF fifo_in_full(fifo_1) = '1' AND fifo_in_full(fifo_2) = '1' THEN | |
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60 | 67 | fifo_in_lock_s(fifo_1) <= '1'; |
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61 | 68 | fifo_in_lock_s(fifo_2) <= '1'; |
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62 | 69 | correlation_start <= '1'; |
@@ -64,6 +71,18 BEGIN -- beh | |||
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64 | 71 | correlation_auto <= '1'; |
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65 | 72 | END IF; |
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66 | 73 | state <= CORRELATION_ONGOING; |
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74 | IF fifo_1 = 0 AND fifo_2 = 0 THEN | |
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75 | current_status_component(53 DOWNTO 4) <= current_status_ms; | |
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76 | END IF; | |
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77 | CASE fifo_1 IS | |
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78 | WHEN 0 => current_status_component(3 DOWNTO 0) <= STD_LOGIC_VECTOR(to_unsigned( fifo_2,4)); | |
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79 | WHEN 1 => current_status_component(3 DOWNTO 0) <= STD_LOGIC_VECTOR(to_unsigned(4+fifo_2,4)); | |
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80 | WHEN 2 => current_status_component(3 DOWNTO 0) <= STD_LOGIC_VECTOR(to_unsigned(7+fifo_2,4)); | |
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81 | WHEN 3 => current_status_component(3 DOWNTO 0) <= STD_LOGIC_VECTOR(to_unsigned(9+fifo_2,4)); | |
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82 | WHEN 4 => current_status_component(3 DOWNTO 0) <= STD_LOGIC_VECTOR(to_unsigned(14 ,4)); | |
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83 | WHEN OTHERS => NULL; | |
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84 | END CASE; | |
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85 | --current_status_component(3 DOWNTO 0) <= STD_LOGIC_VECTOR(to_unsigned(fifo_1*5+fifo_2,4)); | |
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67 | 86 | END IF; |
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68 | 87 | |
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69 | 88 | WHEN CORRELATION_ONGOING => |
@@ -94,14 +113,14 BEGIN -- beh | |||
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94 | 113 | END PROCESS; |
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95 | 114 | |
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96 | 115 | |
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97 |
fifo_out_data(31 DOWNTO 0) <= fifo_in_data(3 |
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116 | fifo_out_data(31 DOWNTO 0) <= fifo_in_data(32*1-1 DOWNTO 32*0) WHEN fifo_1 = 0 ELSE | |
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98 | 117 | fifo_in_data(32*2-1 DOWNTO 32*1) WHEN fifo_1 = 1 ELSE |
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99 | 118 | fifo_in_data(32*3-1 DOWNTO 32*2) WHEN fifo_1 = 2 ELSE |
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100 | 119 | fifo_in_data(32*4-1 DOWNTO 32*3) WHEN fifo_1 = 3 ELSE |
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101 | 120 | fifo_in_data(32*5-1 DOWNTO 32*4);-- WHEN fifo_1 = 4 |
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102 | 121 | |
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103 | 122 | |
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104 |
fifo_out_data(63 DOWNTO 32) <= fifo_in_data(3 |
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123 | fifo_out_data(63 DOWNTO 32) <= fifo_in_data(32*1-1 DOWNTO 32*0) WHEN fifo_2 = 0 ELSE | |
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105 | 124 | fifo_in_data(32*2-1 DOWNTO 32*1) WHEN fifo_2 = 1 ELSE |
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106 | 125 | fifo_in_data(32*3-1 DOWNTO 32*2) WHEN fifo_2 = 2 ELSE |
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107 | 126 | fifo_in_data(32*4-1 DOWNTO 32*3) WHEN fifo_2 = 3 ELSE |
@@ -121,8 +140,8 BEGIN -- beh | |||
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121 | 140 | |
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122 | 141 | |
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123 | 142 | all_fifo: FOR I IN 0 TO 4 GENERATE |
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124 |
fifo_in_ren(I) <= fifo_out_ren( |
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125 |
fifo_out_ren( |
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143 | fifo_in_ren(I) <= fifo_out_ren(0) WHEN fifo_1 = I ELSE | |
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144 | fifo_out_ren(1) WHEN fifo_2 = I ELSE | |
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126 | 145 | '1'; |
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127 | 146 | END GENERATE all_fifo; |
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128 | 147 |
@@ -59,6 +59,8 vcom_tb: | |||
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59 | 59 | $(CMD_VCOM) lpp spectral_matrix_package.vhd |
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60 | 60 | $(CMD_VCOM) lpp spectral_matrix_switch_f0.vhd |
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61 | 61 | $(CMD_VCOM) lpp spectral_matrix_time_managment.vhd |
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62 | $(CMD_VCOM) lpp MS_control.vhd | |
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63 | $(CMD_VCOM) lpp MS_calculation.vhd | |
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62 | 64 | $(CMD_VCOM) lpp lpp_lfr_ms.vhd |
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63 | 65 | $(CMD_VCOM) work TB.vhd |
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64 | 66 | @echo "vcom done" |
@@ -391,7 +393,7 vcom_lpp: | |||
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391 | 393 | $(CMD_VCOM) lpp lpp_memory.vhd |
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392 | 394 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/CoreFFT_simu.vhd |
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393 | 395 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd |
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394 |
$(CMD_VCOM) lpp |
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396 | $(CMD_VCOM) lpp lpp_lfr_ms_fsmdma.vhd | |
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395 | 397 | @echo "vcom lpp done" |
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396 | 398 | |
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397 | 399 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_amba/apb_devices_list.vhd |
@@ -25,6 +25,7 USE IEEE.STD_LOGIC_1164.ALL; | |||
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25 | 25 | USE IEEE.NUMERIC_STD.ALL; |
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26 | 26 | |
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27 | 27 | LIBRARY lpp; |
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28 | USE lpp.lpp_lfr_pkg.ALL; | |
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28 | 29 | USE lpp.lpp_memory.ALL; |
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29 | 30 | USE lpp.iir_filter.ALL; |
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30 | 31 | USE lpp.spectral_matrix_package.ALL; |
@@ -38,51 +39,6 END TB; | |||
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38 | 39 | |
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39 | 40 | |
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40 | 41 | ARCHITECTURE beh OF TB IS |
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41 | ||
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42 | COMPONENT lpp_lfr_ms | |
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43 | GENERIC ( | |
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44 | Mem_use : INTEGER); | |
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45 | PORT ( | |
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46 | clk : IN STD_LOGIC; | |
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47 | rstn : IN STD_LOGIC; | |
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48 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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49 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); | |
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50 | sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
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51 | sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
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52 | sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
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53 | sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
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54 | sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
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55 | sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
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56 | dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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57 | dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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58 | dma_valid : OUT STD_LOGIC; | |
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59 | dma_valid_burst : OUT STD_LOGIC; | |
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60 | dma_ren : IN STD_LOGIC; | |
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61 | dma_done : IN STD_LOGIC; | |
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62 | ready_matrix_f0_0 : OUT STD_LOGIC; | |
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63 | ready_matrix_f0_1 : OUT STD_LOGIC; | |
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64 | ready_matrix_f1 : OUT STD_LOGIC; | |
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65 | ready_matrix_f2 : OUT STD_LOGIC; | |
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66 | error_anticipating_empty_fifo : OUT STD_LOGIC; | |
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67 | error_bad_component_error : OUT STD_LOGIC; | |
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68 | debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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69 | status_ready_matrix_f0_0 : IN STD_LOGIC; | |
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70 | status_ready_matrix_f0_1 : IN STD_LOGIC; | |
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71 | status_ready_matrix_f1 : IN STD_LOGIC; | |
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72 | status_ready_matrix_f2 : IN STD_LOGIC; | |
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73 | status_error_anticipating_empty_fifo : IN STD_LOGIC; | |
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74 | status_error_bad_component_error : IN STD_LOGIC; | |
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75 | config_active_interruption_onNewMatrix : IN STD_LOGIC; | |
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76 | config_active_interruption_onError : IN STD_LOGIC; | |
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77 | addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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78 | addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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79 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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80 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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81 | matrix_time_f0_0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
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82 | matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
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83 | matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
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84 | matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)); | |
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85 | END COMPONENT; | |
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86 | 42 | |
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87 | 43 | ----------------------------------------------------------------------------- |
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88 | 44 | SIGNAL clk25MHz : STD_LOGIC := '0'; |
@@ -103,27 +59,27 ARCHITECTURE beh OF TB IS | |||
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103 | 59 | SIGNAL dma_valid_burst : STD_LOGIC; |
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104 | 60 | SIGNAL dma_ren : STD_LOGIC; |
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105 | 61 | SIGNAL dma_done : STD_LOGIC; |
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106 |
SIGNAL ready_matrix_f0 |
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107 | SIGNAL ready_matrix_f0_1 : STD_LOGIC; | |
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62 | SIGNAL ready_matrix_f0 : STD_LOGIC; | |
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63 | -- SIGNAL ready_matrix_f0_1 : STD_LOGIC; | |
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108 | 64 | SIGNAL ready_matrix_f1 : STD_LOGIC; |
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109 | 65 | SIGNAL ready_matrix_f2 : STD_LOGIC; |
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110 | SIGNAL error_anticipating_empty_fifo : STD_LOGIC; | |
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66 | -- SIGNAL error_anticipating_empty_fifo : STD_LOGIC; | |
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111 | 67 | SIGNAL error_bad_component_error : STD_LOGIC; |
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112 | 68 | SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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113 |
SIGNAL status_ready_matrix_f0 |
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114 | SIGNAL status_ready_matrix_f0_1 : STD_LOGIC; | |
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69 | SIGNAL status_ready_matrix_f0 : STD_LOGIC; | |
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70 | -- SIGNAL status_ready_matrix_f0_1 : STD_LOGIC; | |
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115 | 71 | SIGNAL status_ready_matrix_f1 : STD_LOGIC; |
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116 | 72 | SIGNAL status_ready_matrix_f2 : STD_LOGIC; |
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117 | SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC; | |
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118 | SIGNAL status_error_bad_component_error : STD_LOGIC; | |
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73 | -- SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC; | |
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74 | -- SIGNAL status_error_bad_component_error : STD_LOGIC; | |
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119 | 75 | SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC; |
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120 | 76 | SIGNAL config_active_interruption_onError : STD_LOGIC; |
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121 |
SIGNAL addr_matrix_f0 |
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122 | SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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77 | SIGNAL addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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78 | -- SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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123 | 79 | SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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124 | 80 | SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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125 |
SIGNAL matrix_time_f0 |
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126 | SIGNAL matrix_time_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
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81 | SIGNAL matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
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82 | -- SIGNAL matrix_time_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
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127 | 83 | SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0); |
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128 | 84 | SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0); |
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129 | 85 | |
@@ -143,6 +99,9 ARCHITECTURE beh OF TB IS | |||
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143 | 99 | SIGNAL sample_f0_val : STD_LOGIC; |
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144 | 100 | SIGNAL sample_f1_val : STD_LOGIC; |
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145 | 101 | SIGNAL sample_f2_val : STD_LOGIC; |
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102 | ||
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103 | ----------------------------------------------------------------------------- | |
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104 | SIGNAL ren_counter : INTEGER; | |
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146 | 105 | |
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147 | 106 | BEGIN -- beh |
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148 | 107 | |
@@ -245,7 +204,7 BEGIN -- beh | |||
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245 | 204 | sample_f2_wen <= NOT(sample_f2_val) & NOT(sample_f2_val) & NOT(sample_f2_val) & NOT(sample_f2_val) & NOT(sample_f2_val); |
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246 | 205 | ----------------------------------------------------------------------------- |
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247 | 206 | |
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248 |
lpp_lfr_ms_1: |
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207 | lpp_lfr_ms_1: lpp_lfr_ms | |
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249 | 208 | GENERIC MAP ( |
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250 | 209 | Mem_use => use_CEL) |
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251 | 210 | PORT MAP ( |
@@ -268,46 +227,95 BEGIN -- beh | |||
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268 | 227 | dma_valid_burst => dma_valid_burst, |
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269 | 228 | dma_ren => dma_ren, |
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270 | 229 | dma_done => dma_done, |
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271 | ready_matrix_f0_0 => ready_matrix_f0_0, | |
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272 |
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230 | ||
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231 | ready_matrix_f0 => ready_matrix_f0, | |
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232 | -- ready_matrix_f0_1 => ready_matrix_f0_1, | |
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273 | 233 | ready_matrix_f1 => ready_matrix_f1, |
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274 | 234 | ready_matrix_f2 => ready_matrix_f2, |
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275 | error_anticipating_empty_fifo => error_anticipating_empty_fifo, | |
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235 | -- error_anticipating_empty_fifo => error_anticipating_empty_fifo, | |
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276 | 236 | error_bad_component_error => error_bad_component_error, |
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237 | error_buffer_full => OPEN, | |
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238 | error_input_fifo_write => OPEN, | |
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239 | ||
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277 | 240 |
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278 |
status_ready_matrix_f0 |
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279 |
status_ready_matrix_f0 |
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241 | status_ready_matrix_f0 => status_ready_matrix_f0, | |
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242 | -- status_ready_matrix_f0 => status_ready_matrix_f0_1, | |
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280 | 243 | status_ready_matrix_f1 => status_ready_matrix_f1, |
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281 | 244 | status_ready_matrix_f2 => status_ready_matrix_f2, |
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282 | status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo, | |
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283 | status_error_bad_component_error => status_error_bad_component_error, | |
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245 | -- status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo, | |
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246 | -- status_error_bad_component_error => status_error_bad_component_error, | |
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284 | 247 | config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, |
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285 | 248 | config_active_interruption_onError => config_active_interruption_onError, |
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286 |
addr_matrix_f0 |
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287 | addr_matrix_f0_1 => addr_matrix_f0_1, | |
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249 | addr_matrix_f0 => addr_matrix_f0, | |
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250 | -- addr_matrix_f0_1 => addr_matrix_f0_1, | |
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288 | 251 | addr_matrix_f1 => addr_matrix_f1, |
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289 | 252 | addr_matrix_f2 => addr_matrix_f2, |
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290 |
matrix_time_f0 |
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291 | matrix_time_f0_1 => matrix_time_f0_1, | |
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253 | matrix_time_f0 => matrix_time_f0, | |
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254 | -- matrix_time_f0_1 => matrix_time_f0_1, | |
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292 | 255 | matrix_time_f1 => matrix_time_f1, |
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293 | 256 | matrix_time_f2 => matrix_time_f2); |
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294 | 257 | |
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295 | dma_ren <= '0'; | |
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296 | dma_done <= '0'; | |
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258 | ||
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259 | ||
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260 | ||
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297 | 261 |
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298 | status_ready_matrix_f0_0 <= '0'; | |
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299 | status_ready_matrix_f0_1 <= '0'; | |
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300 | status_ready_matrix_f1 <= '0'; | |
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301 |
status_ready_matrix_f |
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302 | status_error_anticipating_empty_fifo <= '0'; | |
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303 | status_error_bad_component_error <= '0'; | |
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262 | PROCESS (clk25MHz, rstn) | |
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263 | BEGIN -- PROCESS | |
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264 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
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265 | status_ready_matrix_f0 <= '0'; | |
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266 | -- status_ready_matrix_f0_1 <= '0'; | |
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267 | status_ready_matrix_f1 <= '0'; | |
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268 | status_ready_matrix_f2 <= '0'; | |
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269 | ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge | |
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270 | status_ready_matrix_f0 <= status_ready_matrix_f0 OR ready_matrix_f0; | |
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271 | -- status_ready_matrix_f0_1 <= status_ready_matrix_f0_1 OR ready_matrix_f0_1; | |
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272 | status_ready_matrix_f1 <= status_ready_matrix_f1 OR ready_matrix_f1; | |
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273 | status_ready_matrix_f2 <= status_ready_matrix_f2 OR ready_matrix_f2; | |
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274 | END IF; | |
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275 | END PROCESS; | |
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276 | ||
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277 | ||
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278 | ||
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279 | ||
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280 | -- status_error_anticipating_empty_fifo <= '0'; | |
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281 | -- status_error_bad_component_error <= '0'; | |
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304 | 282 | |
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305 | 283 | config_active_interruption_onNewMatrix <= '0'; |
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306 | 284 | config_active_interruption_onError <= '0'; |
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307 |
addr_matrix_f0 |
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308 | addr_matrix_f0_1 <= (OTHERS => '0'); | |
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285 | addr_matrix_f0 <= (OTHERS => '0'); | |
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286 | -- addr_matrix_f0_1 <= (OTHERS => '0'); | |
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309 | 287 | addr_matrix_f1 <= (OTHERS => '0'); |
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310 | 288 | addr_matrix_f2 <= (OTHERS => '0'); |
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289 | ||
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290 | ||
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291 | PROCESS (clk25MHz, rstn) | |
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292 | BEGIN -- PROCESS | |
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293 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
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294 | ||
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295 | dma_ren <= '1'; | |
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296 | dma_done <= '0'; | |
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297 | ren_counter <= 0; | |
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298 | ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge | |
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299 | dma_ren <= '1'; | |
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300 | dma_done <= '0'; | |
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301 | ||
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302 | IF dma_valid_burst = '1' THEN | |
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303 | ren_counter <= 17; | |
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304 | END IF; | |
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305 | ||
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306 | IF ren_counter > 1 THEN | |
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307 | ren_counter <= ren_counter - 1; | |
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308 | dma_ren <= '0'; | |
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309 | END IF; | |
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310 | ||
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311 | IF ren_counter = 1 THEN | |
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312 | ren_counter <= 0; | |
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313 | dma_done <= '1'; | |
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314 | END IF; | |
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315 | ||
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316 | END IF; | |
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317 | END PROCESS; | |
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318 | ||
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311 | 319 | |
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312 | 320 | END beh; |
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313 | 321 |
@@ -50,7 +50,8 ENTITY lppFIFOxN IS | |||
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50 | 50 | |
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51 | 51 | empty : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0); |
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52 | 52 | full : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0); |
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53 | almost_full : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0) | |
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53 | almost_full : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0); | |
|
54 | more_16Data : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0) | |
|
54 | 55 | ); |
|
55 | 56 | END ENTITY; |
|
56 | 57 | |
@@ -76,7 +77,8 BEGIN | |||
|
76 | 77 | wdata => wdata(((I+1)*Data_sz)-1 DOWNTO (I*Data_sz)), |
|
77 | 78 | empty => empty(I), |
|
78 | 79 | full => full(I), |
|
79 |
almost_full => almost_full(I) |
|
|
80 | almost_full => almost_full(I), | |
|
81 | more_16Data => more_16Data(I)); | |
|
80 | 82 | END GENERATE; |
|
81 | 83 | |
|
82 | 84 | END ARCHITECTURE; |
@@ -51,7 +51,8 ENTITY lpp_fifo IS | |||
|
51 | 51 | |
|
52 | 52 | empty : OUT STD_LOGIC; |
|
53 | 53 | full : OUT STD_LOGIC; |
|
54 | almost_full : OUT STD_LOGIC | |
|
54 | almost_full : OUT STD_LOGIC; | |
|
55 | more_16Data : OUT STD_LOGIC | |
|
55 | 56 | ); |
|
56 | 57 | END ENTITY; |
|
57 | 58 | |
@@ -160,6 +161,15 BEGIN | |||
|
160 | 161 | full <= sFull_s; |
|
161 | 162 | empty <= sEmpty_s; |
|
162 | 163 | |
|
164 | ||
|
165 | more_16Data <= '1' WHEN ReUse = '1' ELSE | |
|
166 | '1' WHEN sFull = '1' ELSE | |
|
167 | '1' WHEN UNSIGNED(Waddr_vect) > UNSIGNED(Raddr_vect) AND UNSIGNED(Waddr_vect) > UNSIGNED(Raddr_vect) + 15 ELSE | |
|
168 | '1' WHEN UNSIGNED(Waddr_vect) < UNSIGNED(Raddr_vect) AND 2**AddrSz - UNSIGNED(Raddr_vect) + UNSIGNED(Waddr_vect) > 15 ELSE | |
|
169 | '0'; | |
|
170 | ||
|
171 | ||
|
172 | ||
|
163 | 173 | END ARCHITECTURE; |
|
164 | 174 | |
|
165 | 175 |
@@ -49,31 +49,35 ENTITY lpp_lfr_ms IS | |||
|
49 | 49 | dma_done : IN STD_LOGIC; |
|
50 | 50 | |
|
51 | 51 | -- Reg out |
|
52 |
ready_matrix_f0 |
|
|
53 |
ready_matrix_f0 |
|
|
52 | ready_matrix_f0 : OUT STD_LOGIC; | |
|
53 | -- ready_matrix_f0 : OUT STD_LOGIC; | |
|
54 | 54 | ready_matrix_f1 : OUT STD_LOGIC; |
|
55 | 55 | ready_matrix_f2 : OUT STD_LOGIC; |
|
56 | error_anticipating_empty_fifo : OUT STD_LOGIC; | |
|
56 | --error_anticipating_empty_fifo : OUT STD_LOGIC; | |
|
57 | 57 | error_bad_component_error : OUT STD_LOGIC; |
|
58 | error_buffer_full : OUT STD_LOGIC; | |
|
59 | error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); | |
|
60 | ||
|
58 | 61 |
|
|
59 | 62 | |
|
60 | 63 | -- Reg In |
|
61 |
status_ready_matrix_f0 |
|
|
62 | status_ready_matrix_f0_1 : IN STD_LOGIC; | |
|
64 | status_ready_matrix_f0 : IN STD_LOGIC; | |
|
65 | -- status_ready_matrix_f0_1 : IN STD_LOGIC; | |
|
63 | 66 | status_ready_matrix_f1 : IN STD_LOGIC; |
|
64 | 67 | status_ready_matrix_f2 : IN STD_LOGIC; |
|
65 | status_error_anticipating_empty_fifo : IN STD_LOGIC; | |
|
66 | status_error_bad_component_error : IN STD_LOGIC; | |
|
68 | -- status_error_anticipating_empty_fifo : IN STD_LOGIC; | |
|
69 | -- status_error_bad_component_error : IN STD_LOGIC; | |
|
70 | -- status_error_buffer_full : IN STD_LOGIC; | |
|
67 | 71 | |
|
68 | 72 | config_active_interruption_onNewMatrix : IN STD_LOGIC; |
|
69 | 73 | config_active_interruption_onError : IN STD_LOGIC; |
|
70 | addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
71 |
addr_matrix_f0 |
|
|
74 | -- addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
75 | addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
72 | 76 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
73 | 77 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
74 | 78 | |
|
75 |
matrix_time_f0 |
|
|
76 | matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
79 | matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
80 | -- matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
77 | 81 | matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
78 | 82 | matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) |
|
79 | 83 | |
@@ -171,6 +175,40 ARCHITECTURE Behavioral OF lpp_lfr_ms IS | |||
|
171 | 175 | SIGNAL MEM_IN_SM_Full : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
172 | 176 | SIGNAL MEM_IN_SM_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
173 | 177 | ----------------------------------------------------------------------------- |
|
178 | SIGNAL SM_in_data : STD_LOGIC_VECTOR(32*2-1 DOWNTO 0); | |
|
179 | SIGNAL SM_in_ren : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
180 | SIGNAL SM_in_empty : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
181 | ||
|
182 | SIGNAL SM_correlation_start : STD_LOGIC; | |
|
183 | SIGNAL SM_correlation_auto : STD_LOGIC; | |
|
184 | SIGNAL SM_correlation_done : STD_LOGIC; | |
|
185 | SIGNAL SM_correlation_done_reg1 : STD_LOGIC; | |
|
186 | SIGNAL SM_correlation_done_reg2 : STD_LOGIC; | |
|
187 | SIGNAL SM_correlation_begin : STD_LOGIC; | |
|
188 | ||
|
189 | SIGNAL temp_ongoing : STD_LOGIC; | |
|
190 | SIGNAL temp_auto : STD_LOGIC; | |
|
191 | ||
|
192 | SIGNAL MEM_OUT_SM_Full_s : STD_LOGIC; | |
|
193 | SIGNAL MEM_OUT_SM_Data_in_s : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
194 | SIGNAL MEM_OUT_SM_Write_s : STD_LOGIC; | |
|
195 | ||
|
196 | SIGNAL current_matrix_write : STD_LOGIC; | |
|
197 | SIGNAL current_matrix_wait_empty : STD_LOGIC; | |
|
198 | ||
|
199 | --SIGNAL MEM_OUT_SM_BURST_available : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
200 | ||
|
201 | ----------------------------------------------------------------------------- | |
|
202 | SIGNAL fifo_0_ready : STD_LOGIC; | |
|
203 | SIGNAL fifo_1_ready : STD_LOGIC; | |
|
204 | SIGNAL fifo_ongoing : STD_LOGIC; | |
|
205 | ||
|
206 | SIGNAL FSM_DMA_fifo_ren : STD_LOGIC; | |
|
207 | SIGNAL FSM_DMA_fifo_empty : STD_LOGIC; | |
|
208 | SIGNAL FSM_DMA_fifo_data : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
209 | SIGNAL FSM_DMA_fifo_status : STD_LOGIC_VECTOR(53 DOWNTO 0); | |
|
210 | ||
|
211 | ----------------------------------------------------------------------------- | |
|
174 | 212 | SIGNAL HEAD_SM_Param : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
175 | 213 | SIGNAL HEAD_WorkFreq : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
176 | 214 | SIGNAL HEAD_SM_Wen : STD_LOGIC; |
@@ -185,7 +223,7 ARCHITECTURE Behavioral OF lpp_lfr_ms IS | |||
|
185 | 223 | SIGNAL MEM_OUT_SM_Data_in : STD_LOGIC_VECTOR(63 DOWNTO 0); |
|
186 | 224 | SIGNAL MEM_OUT_SM_Data_out : STD_LOGIC_VECTOR(63 DOWNTO 0); |
|
187 | 225 | SIGNAL MEM_OUT_SM_Full : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
188 |
SIGNAL MEM_OUT_SM_Empty |
|
|
226 | SIGNAL MEM_OUT_SM_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
189 | 227 | ----------------------------------------------------------------------------- |
|
190 | 228 | SIGNAL DMA_Header : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
191 | 229 | SIGNAL DMA_Header_Val : STD_LOGIC; |
@@ -207,12 +245,25 ARCHITECTURE Behavioral OF lpp_lfr_ms IS | |||
|
207 | 245 | SIGNAL time_update_f2 : STD_LOGIC; |
|
208 | 246 | -- |
|
209 | 247 | SIGNAL status_channel : STD_LOGIC_VECTOR(49 DOWNTO 0); |
|
248 | SIGNAL status_MS_input : STD_LOGIC_VECTOR(49 DOWNTO 0); | |
|
249 | SIGNAL status_component : STD_LOGIC_VECTOR(53 DOWNTO 0); | |
|
250 | ||
|
251 | SIGNAL status_component_fifo_0 : STD_LOGIC_VECTOR(53 DOWNTO 0); | |
|
252 | SIGNAL status_component_fifo_1 : STD_LOGIC_VECTOR(53 DOWNTO 0); | |
|
253 | SIGNAL status_component_fifo_0_new : STD_LOGIC; | |
|
254 | SIGNAL status_component_fifo_1_new : STD_LOGIC; | |
|
255 | SIGNAL status_component_fifo_0_end : STD_LOGIC; | |
|
256 | SIGNAL status_component_fifo_1_end : STD_LOGIC; | |
|
210 | 257 | |
|
211 | 258 | SIGNAL dma_time : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
212 | 259 | ----------------------------------------------------------------------------- |
|
213 | 260 | |
|
214 | 261 | BEGIN |
|
215 | 262 | |
|
263 | ||
|
264 | error_input_fifo_write <= error_wen_f2 & error_wen_f1 & error_wen_f0; | |
|
265 | ||
|
266 | ||
|
216 | 267 |
|
|
217 | 268 | PORT MAP ( |
|
218 | 269 | clk => clk, |
@@ -453,6 +504,7 BEGIN | |||
|
453 | 504 | IF rstn = '0' THEN |
|
454 | 505 | sample_ren_s <= (OTHERS => '1'); |
|
455 | 506 | state_fsm_load_FFT <= IDLE; |
|
507 | status_MS_input <= (OTHERS => '0'); | |
|
456 | 508 | --next_state_fsm_load_FFT <= IDLE; |
|
457 | 509 | --sample_valid <= '0'; |
|
458 | 510 | ELSIF clk'EVENT AND clk = '1' THEN |
@@ -462,6 +514,7 BEGIN | |||
|
462 | 514 | sample_ren_s <= (OTHERS => '1'); |
|
463 | 515 | IF sample_full = "11111" AND sample_load = '1' THEN |
|
464 | 516 | state_fsm_load_FFT <= FIFO_1; |
|
517 | status_MS_input <= status_channel; | |
|
465 | 518 | END IF; |
|
466 | 519 | |
|
467 | 520 | WHEN FIFO_1 => |
@@ -686,47 +739,131 BEGIN | |||
|
686 | 739 | empty => MEM_IN_SM_Empty); |
|
687 | 740 | |
|
688 | 741 | |
|
689 | all_lock: FOR I IN 4 DOWNTO 0 GENERATE | |
|
690 | PROCESS (clk, rstn) | |
|
691 | BEGIN | |
|
692 | IF rstn = '0' THEN | |
|
693 | MEM_IN_SM_locked(I) <= '0'; | |
|
694 | ELSIF clk'event AND clk = '1' THEN | |
|
695 |
|
|
|
696 | END IF; | |
|
697 | END PROCESS; | |
|
698 | END GENERATE all_lock; | |
|
742 | --all_lock: FOR I IN 4 DOWNTO 0 GENERATE | |
|
743 | -- PROCESS (clk, rstn) | |
|
744 | -- BEGIN | |
|
745 | -- IF rstn = '0' THEN | |
|
746 | -- MEM_IN_SM_locked(I) <= '0'; | |
|
747 | -- ELSIF clk'event AND clk = '1' THEN | |
|
748 | -- MEM_IN_SM_locked(I) <= MEM_IN_SM_Full(I) OR MEM_IN_SM_locked(I); -- TODO | |
|
749 | -- END IF; | |
|
750 | -- END PROCESS; | |
|
751 | --END GENERATE all_lock; | |
|
699 | 752 | |
|
700 | 753 | ----------------------------------------------------------------------------- |
|
701 | ||
|
754 | MS_control_1: MS_control | |
|
755 | PORT MAP ( | |
|
756 | clk => clk, | |
|
757 | rstn => rstn, | |
|
758 | ||
|
759 | current_status_ms => status_MS_input, | |
|
760 | ||
|
761 | fifo_in_lock => MEM_IN_SM_locked, | |
|
762 | fifo_in_data => MEM_IN_SM_rdata, | |
|
763 | fifo_in_full => MEM_IN_SM_Full, | |
|
764 | fifo_in_empty => MEM_IN_SM_Empty, | |
|
765 | fifo_in_ren => MEM_IN_SM_ren, | |
|
766 | fifo_in_reuse => MEM_IN_SM_ReUse, | |
|
767 | ||
|
768 | fifo_out_data => SM_in_data, | |
|
769 | fifo_out_ren => SM_in_ren, | |
|
770 | fifo_out_empty => SM_in_empty, | |
|
771 | ||
|
772 | current_status_component => status_component, | |
|
773 | ||
|
774 | correlation_start => SM_correlation_start, | |
|
775 | correlation_auto => SM_correlation_auto, | |
|
776 | correlation_done => SM_correlation_done); | |
|
702 | 777 | |
|
703 | 778 | |
|
704 | ||
|
779 | MS_calculation_1: MS_calculation | |
|
780 | PORT MAP ( | |
|
781 | clk => clk, | |
|
782 | rstn => rstn, | |
|
783 | ||
|
784 | fifo_in_data => SM_in_data, | |
|
785 | fifo_in_ren => SM_in_ren, | |
|
786 | fifo_in_empty => SM_in_empty, | |
|
787 | ||
|
788 | fifo_out_data => MEM_OUT_SM_Data_in_s, -- TODO | |
|
789 | fifo_out_wen => MEM_OUT_SM_Write_s, -- TODO | |
|
790 | fifo_out_full => MEM_OUT_SM_Full_s, -- TODO | |
|
791 | ||
|
792 | correlation_start => SM_correlation_start, | |
|
793 | correlation_auto => SM_correlation_auto, | |
|
794 | correlation_begin => SM_correlation_begin, | |
|
795 | correlation_done => SM_correlation_done); | |
|
705 | 796 | |
|
706 | 797 | ----------------------------------------------------------------------------- |
|
707 | SM0 : MatriceSpectrale | |
|
708 | GENERIC MAP ( | |
|
709 | Input_SZ => 16, | |
|
710 | Result_SZ => 32) | |
|
711 | PORT MAP ( | |
|
712 | clkm => clk, | |
|
713 | rstn => rstn, | |
|
798 | PROCESS (clk, rstn) | |
|
799 | BEGIN -- PROCESS | |
|
800 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
|
801 | current_matrix_write <= '0'; | |
|
802 | current_matrix_wait_empty <= '1'; | |
|
803 | status_component_fifo_0 <= (OTHERS => '0'); | |
|
804 | status_component_fifo_1 <= (OTHERS => '0'); | |
|
805 | status_component_fifo_0_new <= '0'; | |
|
806 | status_component_fifo_1_new <= '0'; | |
|
807 | status_component_fifo_0_end <= '0'; | |
|
808 | status_component_fifo_1_end <= '0'; | |
|
809 | SM_correlation_done_reg1 <= '0'; | |
|
810 | SM_correlation_done_reg2 <= '0'; | |
|
811 | ||
|
812 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |
|
813 | SM_correlation_done_reg1 <= SM_correlation_done; | |
|
814 | SM_correlation_done_reg2 <= SM_correlation_done_reg1; | |
|
815 | ||
|
816 | status_component_fifo_0_new <= '0'; | |
|
817 | status_component_fifo_1_new <= '0'; | |
|
818 | status_component_fifo_0_end <= '0'; | |
|
819 | status_component_fifo_1_end <= '0'; | |
|
820 | ||
|
714 | 821 | |
|
715 | FifoIN_Full => MEM_IN_SM_Full, | |
|
716 | Data_IN => MEM_IN_SM_rData(79 DOWNTO 0), | |
|
717 | Read => MEM_IN_SM_ren, | |
|
718 | ReUse => MEM_IN_SM_ReUse, | |
|
719 | ||
|
720 | SetReUse => fft_linker_ReUse, | |
|
822 | ||
|
823 | IF SM_correlation_begin = '1' THEN | |
|
824 | IF current_matrix_write = '0' THEN | |
|
825 | status_component_fifo_0_new <= '1'; | |
|
826 | status_component_fifo_0 <= status_component; | |
|
827 | ELSE | |
|
828 | status_component_fifo_1_new <= '1'; | |
|
829 | status_component_fifo_1 <= status_component; | |
|
830 | END IF; | |
|
831 | END IF; | |
|
832 | ||
|
833 | IF SM_correlation_done_reg2 = '1' THEN | |
|
834 | IF current_matrix_write = '0' THEN | |
|
835 | status_component_fifo_0_end <= '1'; | |
|
836 | ELSE | |
|
837 | status_component_fifo_1_end <= '1'; | |
|
838 | END IF; | |
|
839 | current_matrix_wait_empty <= '1'; | |
|
840 | current_matrix_write <= NOT current_matrix_write; | |
|
841 | END IF; | |
|
842 | ||
|
843 | IF current_matrix_wait_empty <= '1' THEN | |
|
844 | IF current_matrix_write = '0' THEN | |
|
845 | current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(0); | |
|
846 | ELSE | |
|
847 | current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(1); | |
|
848 | END IF; | |
|
849 | END IF; | |
|
850 | ||
|
851 | END IF; | |
|
852 | END PROCESS; | |
|
721 | 853 | |
|
722 | Valid => HEAD_Valid, | |
|
723 | ACK => DMA_Header_Ack, | |
|
724 | SM_Write => HEAD_SM_Wen, | |
|
725 | FlagError => OPEN, | |
|
726 | Statu => HEAD_SM_Param, | |
|
727 | Write => MEM_OUT_SM_Write, | |
|
728 | Data_OUT => MEM_OUT_SM_Data_in); | |
|
854 | MEM_OUT_SM_Full_s <= '1' WHEN SM_correlation_done = '1' ELSE | |
|
855 | '1' WHEN SM_correlation_done_reg1 = '1' ELSE | |
|
856 | '1' WHEN SM_correlation_done_reg2 = '1' ELSE | |
|
857 | '1' WHEN current_matrix_wait_empty = '1' ELSE | |
|
858 | MEM_OUT_SM_Full(0) WHEN current_matrix_write = '0' ELSE | |
|
859 | MEM_OUT_SM_Full(1); | |
|
860 | ||
|
861 | MEM_OUT_SM_Write(0) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '0' ELSE '1'; | |
|
862 | MEM_OUT_SM_Write(1) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '1' ELSE '1'; | |
|
863 | ||
|
864 | MEM_OUT_SM_Data_in <= MEM_OUT_SM_Data_in_s & MEM_OUT_SM_Data_in_s; | |
|
729 | 865 | ----------------------------------------------------------------------------- |
|
866 | ||
|
730 | 867 |
|
|
731 | 868 | GENERIC MAP ( |
|
732 | 869 | tech => 0, |
@@ -742,51 +879,81 BEGIN | |||
|
742 | 879 | |
|
743 | 880 | wen => MEM_OUT_SM_Write, |
|
744 | 881 | wdata => MEM_OUT_SM_Data_in, |
|
882 | ||
|
745 | 883 |
|
|
746 | 884 | rdata => MEM_OUT_SM_Data_out, |
|
747 | 885 | |
|
748 | 886 | full => MEM_OUT_SM_Full, |
|
749 |
empty => MEM_OUT_SM_Empty |
|
|
887 | empty => MEM_OUT_SM_Empty, | |
|
888 | almost_full => OPEN); | |
|
889 | ||
|
750 | 890 | ----------------------------------------------------------------------------- |
|
751 | Head0 : HeaderBuilder | |
|
752 | GENERIC MAP ( | |
|
753 | Data_sz => 32) | |
|
754 | PORT MAP ( | |
|
755 | clkm => clk, | |
|
756 | rstn => rstn, | |
|
891 | -- MEM_OUT_SM_Read <= "00"; | |
|
892 | PROCESS (clk, rstn) | |
|
893 | BEGIN | |
|
894 | IF rstn = '0' THEN | |
|
895 | fifo_0_ready <= '0'; | |
|
896 | fifo_1_ready <= '0'; | |
|
897 | fifo_ongoing <= '0'; | |
|
898 | ELSIF clk'event AND clk = '1' THEN | |
|
899 | IF fifo_0_ready = '1' AND MEM_OUT_SM_Empty(0) = '1' THEN | |
|
900 | fifo_ongoing <= '1'; | |
|
901 | fifo_0_ready <= '0'; | |
|
902 | ELSIF status_component_fifo_0_end = '1' THEN | |
|
903 | fifo_0_ready <= '1'; | |
|
904 | END IF; | |
|
905 | ||
|
906 | IF fifo_1_ready = '1' AND MEM_OUT_SM_Empty(1) = '1' THEN | |
|
907 | fifo_ongoing <= '0'; | |
|
908 | fifo_1_ready <= '0'; | |
|
909 | ELSIF status_component_fifo_1_end = '1' THEN | |
|
910 | fifo_1_ready <= '1'; | |
|
911 | END IF; | |
|
912 | ||
|
913 | END IF; | |
|
914 | END PROCESS; | |
|
915 | ||
|
916 | MEM_OUT_SM_Read(0) <= '1' WHEN fifo_ongoing = '1' ELSE | |
|
917 | '1' WHEN fifo_0_ready = '0' ELSE | |
|
918 | FSM_DMA_fifo_ren; | |
|
757 | 919 | |
|
758 | Statu => HEAD_SM_Param, | |
|
759 | Matrix_Type => HEAD_WorkFreq, -- TODO IN | |
|
760 | Matrix_Write => HEAD_SM_Wen, | |
|
761 | Valid => HEAD_Valid, | |
|
762 | ||
|
763 | dataIN => MEM_OUT_SM_Data_out, | |
|
764 | emptyIN => MEM_OUT_SM_Empty, | |
|
765 | RenOUT => MEM_OUT_SM_Read, | |
|
920 | MEM_OUT_SM_Read(1) <= '1' WHEN fifo_ongoing = '0' ELSE | |
|
921 | '1' WHEN fifo_1_ready = '0' ELSE | |
|
922 | FSM_DMA_fifo_ren; | |
|
766 | 923 | |
|
767 | dataOUT => HEAD_Data, | |
|
768 | emptyOUT => HEAD_Empty, | |
|
769 | RenIN => HEAD_Read, | |
|
924 | FSM_DMA_fifo_empty <= MEM_OUT_SM_Empty(0) WHEN fifo_ongoing = '0' AND fifo_0_ready = '1' ELSE | |
|
925 | MEM_OUT_SM_Empty(1) WHEN fifo_ongoing = '1' AND fifo_1_ready = '1' ELSE | |
|
926 | '1'; | |
|
927 | ||
|
928 | FSM_DMA_fifo_status <= status_component_fifo_0 WHEN fifo_ongoing = '0' ELSE | |
|
929 | status_component_fifo_1; | |
|
770 | 930 | |
|
771 | header => DMA_Header, | |
|
772 | header_val => DMA_Header_Val, | |
|
773 | header_ack => DMA_Header_Ack); | |
|
774 | ----------------------------------------------------------------------------- | |
|
931 | FSM_DMA_fifo_data <= MEM_OUT_SM_Data_out(31 DOWNTO 0) WHEN fifo_ongoing = '0' ELSE | |
|
932 | MEM_OUT_SM_Data_out(63 DOWNTO 32); | |
|
933 | ||
|
775 | 934 | ----------------------------------------------------------------------------- |
|
776 | 935 | lpp_lfr_ms_fsmdma_1 : lpp_lfr_ms_fsmdma |
|
777 | 936 | PORT MAP ( |
|
778 | 937 | HCLK => clk, |
|
779 | 938 | HRESETn => rstn, |
|
780 | 939 | |
|
781 | data_time => dma_time, | |
|
940 | fifo_matrix_type => FSM_DMA_fifo_status( 5 DOWNTO 4), | |
|
941 | fifo_matrix_component => FSM_DMA_fifo_status( 3 DOWNTO 0), | |
|
942 | fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6), | |
|
943 | fifo_data => FSM_DMA_fifo_data, | |
|
944 | fifo_empty => FSM_DMA_fifo_empty, | |
|
945 | fifo_ren => FSM_DMA_fifo_ren, | |
|
946 | ||
|
947 | ---- FIFO IN | |
|
948 | --data_time => dma_time, | |
|
782 | 949 | |
|
783 | fifo_data => HEAD_Data, | |
|
784 | fifo_empty => HEAD_Empty, | |
|
785 | fifo_ren => HEAD_Read, | |
|
950 | --fifo_data => HEAD_Data, | |
|
951 | --fifo_empty => HEAD_Empty, | |
|
952 | --fifo_ren => HEAD_Read, | |
|
786 | 953 | |
|
787 | header => DMA_Header, | |
|
788 | header_val => DMA_Header_Val, | |
|
789 | header_ack => DMA_Header_Ack, | |
|
954 | --header => DMA_Header, | |
|
955 | --header_val => DMA_Header_Val, | |
|
956 | --header_ack => DMA_Header_Ack, | |
|
790 | 957 | |
|
791 | 958 | dma_addr => dma_addr, |
|
792 | 959 | dma_data => dma_data, |
@@ -795,33 +962,45 BEGIN | |||
|
795 | 962 | dma_ren => dma_ren, |
|
796 | 963 | dma_done => dma_done, |
|
797 | 964 | |
|
798 |
ready_matrix_f0 |
|
|
799 | ready_matrix_f0_1 => ready_matrix_f0_1, | |
|
965 | ready_matrix_f0 => ready_matrix_f0, | |
|
966 | -- ready_matrix_f0_1 => ready_matrix_f0_1, | |
|
800 | 967 | ready_matrix_f1 => ready_matrix_f1, |
|
801 | 968 | ready_matrix_f2 => ready_matrix_f2, |
|
802 | error_anticipating_empty_fifo => error_anticipating_empty_fifo, | |
|
969 | -- error_anticipating_empty_fifo => error_anticipating_empty_fifo, | |
|
803 | 970 | error_bad_component_error => error_bad_component_error, |
|
971 | error_buffer_full => error_buffer_full, | |
|
804 | 972 | debug_reg => debug_reg, |
|
805 |
status_ready_matrix_f0 |
|
|
806 | status_ready_matrix_f0_1 => status_ready_matrix_f0_1, | |
|
973 | status_ready_matrix_f0 => status_ready_matrix_f0, | |
|
974 | -- status_ready_matrix_f0_1 => status_ready_matrix_f0_1, | |
|
807 | 975 | status_ready_matrix_f1 => status_ready_matrix_f1, |
|
808 | 976 | status_ready_matrix_f2 => status_ready_matrix_f2, |
|
809 | status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo, | |
|
810 | status_error_bad_component_error => status_error_bad_component_error, | |
|
977 | -- status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo, | |
|
978 | -- status_error_bad_component_error => status_error_bad_component_error, | |
|
979 | -- status_error_buffer_full => status_error_buffer_full, | |
|
811 | 980 | config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, |
|
812 | 981 | config_active_interruption_onError => config_active_interruption_onError, |
|
813 |
addr_matrix_f0 |
|
|
814 | addr_matrix_f0_1 => addr_matrix_f0_1, | |
|
982 | addr_matrix_f0 => addr_matrix_f0, | |
|
983 | -- addr_matrix_f0_1 => addr_matrix_f0_1, | |
|
815 | 984 | addr_matrix_f1 => addr_matrix_f1, |
|
816 | 985 | addr_matrix_f2 => addr_matrix_f2, |
|
817 | 986 | |
|
818 |
matrix_time_f0 |
|
|
819 | matrix_time_f0_1 => matrix_time_f0_1, | |
|
987 | matrix_time_f0 => matrix_time_f0, | |
|
988 | -- matrix_time_f0_1 => matrix_time_f0_1, | |
|
820 | 989 | matrix_time_f1 => matrix_time_f1, |
|
821 | 990 | matrix_time_f2 => matrix_time_f2 |
|
822 | 991 | ); |
|
823 | 992 | ----------------------------------------------------------------------------- |
|
824 | 993 | |
|
994 | ||
|
995 | ||
|
996 | ||
|
997 | ||
|
998 | ||
|
999 | ||
|
1000 | ||
|
1001 | ||
|
1002 | ||
|
1003 | ||
|
825 | 1004 |
|
|
826 | 1005 | ----------------------------------------------------------------------------- |
|
827 | 1006 | ----------------------------------------------------------------------------- |
@@ -53,7 +53,8 PACKAGE lpp_memory IS | |||
|
53 | 53 | wdata : IN STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0); |
|
54 | 54 | empty : OUT STD_LOGIC; |
|
55 | 55 | full : OUT STD_LOGIC; |
|
56 |
almost_full : OUT STD_LOGIC |
|
|
56 | almost_full : OUT STD_LOGIC; | |
|
57 | more_16Data : OUT STD_LOGIC); | |
|
57 | 58 | END COMPONENT; |
|
58 | 59 | |
|
59 | 60 | COMPONENT lppFIFOxN |
@@ -73,7 +74,8 PACKAGE lpp_memory IS | |||
|
73 | 74 | rdata : OUT STD_LOGIC_VECTOR((FifoCnt*Data_sz)-1 DOWNTO 0); |
|
74 | 75 | empty : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0); |
|
75 | 76 | full : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0); |
|
76 |
almost_full : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0) |
|
|
77 | almost_full : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0); | |
|
78 | more_16Data : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0)); | |
|
77 | 79 | END COMPONENT; |
|
78 | 80 | |
|
79 | 81 |
@@ -25,5 +25,41 PACKAGE spectral_matrix_package IS | |||
|
25 | 25 | update_1 : IN STD_LOGIC; |
|
26 | 26 | time_out : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)); |
|
27 | 27 | END COMPONENT; |
|
28 | ||
|
29 | COMPONENT MS_control | |
|
30 | PORT ( | |
|
31 | clk : IN STD_LOGIC; | |
|
32 | rstn : IN STD_LOGIC; | |
|
33 | current_status_ms : IN STD_LOGIC_VECTOR(49 DOWNTO 0); -- TIME(47 .. 0) & Matrix_type(1..0) | |
|
34 | fifo_in_lock : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
35 | fifo_in_data : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); | |
|
36 | fifo_in_full : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
37 | fifo_in_empty : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
38 | fifo_in_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
39 | fifo_in_reuse : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
40 | fifo_out_data : OUT STD_LOGIC_VECTOR(32*2-1 DOWNTO 0); | |
|
41 | fifo_out_ren : IN STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
42 | fifo_out_empty : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
43 | current_status_component : OUT STD_LOGIC_VECTOR(53 DOWNTO 0); -- TIME(47 .. 0) & | |
|
44 | correlation_start : OUT STD_LOGIC; | |
|
45 | correlation_auto : OUT STD_LOGIC; | |
|
46 | correlation_done : IN STD_LOGIC); | |
|
47 | END COMPONENT; | |
|
48 | ||
|
49 | COMPONENT MS_calculation | |
|
50 | PORT ( | |
|
51 | clk : IN STD_LOGIC; | |
|
52 | rstn : IN STD_LOGIC; | |
|
53 | fifo_in_data : IN STD_LOGIC_VECTOR(32*2-1 DOWNTO 0); | |
|
54 | fifo_in_ren : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
55 | fifo_in_empty : IN STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
56 | fifo_out_data : OUT STD_LOGIC_VECTOR(32-1 DOWNTO 0); | |
|
57 | fifo_out_wen : OUT STD_LOGIC; | |
|
58 | fifo_out_full : IN STD_LOGIC; | |
|
59 | correlation_start : IN STD_LOGIC; | |
|
60 | correlation_auto : IN STD_LOGIC; | |
|
61 | correlation_begin : OUT STD_LOGIC; | |
|
62 | correlation_done : OUT STD_LOGIC); | |
|
63 | END COMPONENT; | |
|
28 | 64 | |
|
29 | 65 | END spectral_matrix_package; |
@@ -6,21 +6,30 add wave -noupdate /tb/lpp_lfr_ms_1/samp | |||
|
6 | 6 | add wave -noupdate -radix hexadecimal /tb/lpp_lfr_ms_1/sample_f1_wdata |
|
7 | 7 | add wave -noupdate /tb/lpp_lfr_ms_1/sample_f2_wen |
|
8 | 8 | add wave -noupdate -radix hexadecimal /tb/lpp_lfr_ms_1/sample_f2_wdata |
|
9 |
add wave -noupdate |
|
|
10 |
add wave -noupdate |
|
|
11 |
add wave -noupdate |
|
|
12 |
add wave -noupdate |
|
|
13 |
add wave -noupdate |
|
|
9 | add wave -noupdate -group FIFO_f0_A /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/wen | |
|
10 | add wave -noupdate -group FIFO_f0_A /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/full | |
|
11 | add wave -noupdate -group FIFO_f0_A /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/almost_full | |
|
12 | add wave -noupdate -group FIFO_f0_A /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/empty | |
|
13 | add wave -noupdate -group FIFO_f0_A /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/ren | |
|
14 | add wave -noupdate -group FIFO_f0_A -radix decimal /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/fifos(0)/lpp_fifo_1/raddr_vect | |
|
15 | add wave -noupdate -group FIFO_f0_A -radix decimal /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/fifos(0)/lpp_fifo_1/waddr_vect | |
|
16 | add wave -noupdate -group FIFO_f0_A /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/fifos(0)/lpp_fifo_1/more_16data | |
|
17 | add wave -noupdate -group FIFO_f0_A -radix hexadecimal /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/fifos(0)/lpp_fifo_1/memcel/cram/ramarray | |
|
14 | 18 | add wave -noupdate -expand -group FIFO_f0_B /tb/lpp_lfr_ms_1/lppfifoxn_f0_b/wen |
|
15 | 19 | add wave -noupdate -expand -group FIFO_f0_B /tb/lpp_lfr_ms_1/lppfifoxn_f0_b/full |
|
16 | 20 | add wave -noupdate -expand -group FIFO_f0_B /tb/lpp_lfr_ms_1/lppfifoxn_f0_b/almost_full |
|
17 | 21 | add wave -noupdate -expand -group FIFO_f0_B /tb/lpp_lfr_ms_1/lppfifoxn_f0_b/empty |
|
18 | 22 | add wave -noupdate -expand -group FIFO_f0_B /tb/lpp_lfr_ms_1/lppfifoxn_f0_b/ren |
|
19 | 23 | add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/wen |
|
24 | add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/fifos(0)/lpp_fifo_1/memcel/cram/rwclk | |
|
20 | 25 | add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/full |
|
21 | 26 | add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/almost_full |
|
22 | 27 | add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/empty |
|
23 | 28 | add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/ren |
|
29 | add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/fifos(0)/lpp_fifo_1/more_16data | |
|
30 | add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/fifos(0)/lpp_fifo_1/sfull | |
|
31 | add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/fifos(0)/lpp_fifo_1/sfull_s | |
|
32 | add wave -noupdate -expand -group FIFO_f1 -radix hexadecimal /tb/lpp_lfr_ms_1/lppfifoxn_f1/fifos(0)/lpp_fifo_1/memcel/cram/ramarray | |
|
24 | 33 | add wave -noupdate -expand -group FIFO_f2 /tb/lpp_lfr_ms_1/lppfifoxn_f2/wen |
|
25 | 34 | add wave -noupdate -expand -group FIFO_f2 /tb/lpp_lfr_ms_1/lppfifoxn_f2/full |
|
26 | 35 | add wave -noupdate -expand -group FIFO_f2 /tb/lpp_lfr_ms_1/lppfifoxn_f2/almost_full |
@@ -45,11 +54,11 add wave -noupdate -expand -group FFT_RE | |||
|
45 | 54 | add wave -noupdate -expand -group FFT_RESULT_INTERFACE -radix hexadecimal /tb/lpp_lfr_ms_1/corefft_1/ifoy_re |
|
46 | 55 | add wave -noupdate -expand -group FFT_RESULT_INTERFACE -radix hexadecimal /tb/lpp_lfr_ms_1/corefft_1/lpp_fifo_1/memcel/cram/ramarray |
|
47 | 56 | add wave -noupdate /tb/lpp_lfr_ms_1/status_channel |
|
48 | add wave -noupdate -expand -group FIFO_MS_INPUT -radix hexadecimal -subitemconfig {/tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(0) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(1) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(2) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(3) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(4) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(5) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(6) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(7) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(8) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(9) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(10) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(11) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(12) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(13) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(14) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(15) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(16) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(17) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(18) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(19) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(20) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(21) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(22) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(23) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(24) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(25) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(26) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(27) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(28) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(29) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(30) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(31) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(32) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(33) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(34) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(35) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(36) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(37) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(38) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(39) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(40) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(41) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(42) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(43) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(44) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(45) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(46) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(47) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(48) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(49) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(50) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(51) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(52) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(53) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(54) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(55) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(56) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(57) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(58) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(59) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(60) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(61) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(62) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(63) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(64) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(65) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(66) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(67) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(68) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(69) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(70) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(71) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(72) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(73) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(74) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(75) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(76) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(77) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(78) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(79) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(80) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(81) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(82) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(83) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(84) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(85) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(86) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(87) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(88) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(89) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(90) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(91) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(92) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(93) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(94) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(95) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(96) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(97) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(98) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(99) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(100) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(101) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(102) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(103) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(104) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(105) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(106) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(107) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(108) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(109) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(110) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(111) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(112) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(113) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(114) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(115) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(116) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(117) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(118) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(119) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(120) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(121) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(122) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(123) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(124) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(125) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(126) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(127) {-height 15 -radix hexadecimal}} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray | |
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49 | add wave -noupdate -expand -group FIFO_MS_INPUT -radix hexadecimal -subitemconfig {/tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(0) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(1) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(2) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(3) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(4) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(5) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(6) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(7) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(8) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(9) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(10) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(11) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(12) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(13) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(14) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(15) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(16) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(17) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(18) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(19) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(20) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(21) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(22) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(23) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(24) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(25) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(26) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(27) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(28) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(29) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(30) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(31) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(32) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(33) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(34) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(35) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(36) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(37) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(38) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(39) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(40) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(41) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(42) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(43) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(44) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(45) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(46) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(47) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(48) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(49) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(50) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(51) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(52) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(53) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(54) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(55) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(56) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(57) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(58) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(59) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(60) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(61) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(62) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(63) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(64) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(65) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(66) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(67) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(68) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(69) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(70) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(71) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(72) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(73) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(74) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(75) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(76) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(77) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(78) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(79) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(80) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(81) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(82) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(83) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(84) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(85) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(86) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(87) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(88) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(89) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(90) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(91) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(92) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(93) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(94) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(95) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(96) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(97) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(98) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(99) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(100) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(101) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(102) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(103) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(104) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(105) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(106) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(107) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(108) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(109) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(110) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(111) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(112) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(113) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(114) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(115) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(116) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(117) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(118) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(119) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(120) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(121) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(122) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(123) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(124) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(125) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(126) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(127) {-height 15 -radix hexadecimal}} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray | |
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50 | add wave -noupdate -expand -group FIFO_MS_INPUT -radix hexadecimal -subitemconfig {/tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(0) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(1) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(2) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(3) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(4) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(5) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(6) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(7) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(8) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(9) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(10) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(11) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(12) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(13) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(14) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(15) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(16) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(17) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(18) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(19) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(20) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(21) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(22) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(23) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(24) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(25) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(26) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(27) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(28) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(29) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(30) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(31) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(32) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(33) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(34) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(35) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(36) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(37) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(38) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(39) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(40) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(41) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(42) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(43) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(44) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(45) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(46) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(47) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(48) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(49) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(50) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(51) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(52) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(53) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(54) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(55) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(56) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(57) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(58) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(59) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(60) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(61) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(62) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(63) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(64) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(65) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(66) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(67) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(68) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(69) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(70) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(71) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(72) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(73) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(74) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(75) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(76) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(77) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(78) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(79) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(80) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(81) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(82) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(83) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(84) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(85) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(86) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(87) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(88) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(89) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(90) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(91) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(92) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(93) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(94) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(95) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(96) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(97) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(98) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(99) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(100) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(101) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(102) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(103) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(104) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(105) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(106) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(107) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(108) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(109) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(110) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(111) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(112) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(113) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(114) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(115) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(116) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(117) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(118) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(119) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(120) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(121) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(122) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(123) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(124) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(125) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(126) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(127) {-radix hexadecimal}} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray | |
|
51 | add wave -noupdate -expand -group FIFO_MS_INPUT -radix hexadecimal -subitemconfig {/tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(0) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(1) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(2) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(3) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(4) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(5) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(6) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(7) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(8) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(9) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(10) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(11) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(12) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(13) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(14) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(15) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(16) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(17) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(18) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(19) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(20) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(21) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(22) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(23) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(24) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(25) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(26) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(27) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(28) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(29) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(30) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(31) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(32) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(33) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(34) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(35) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(36) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(37) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(38) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(39) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(40) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(41) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(42) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(43) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(44) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(45) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(46) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(47) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(48) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(49) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(50) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(51) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(52) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(53) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(54) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(55) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(56) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(57) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(58) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(59) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(60) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(61) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(62) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(63) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(64) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(65) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(66) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(67) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(68) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(69) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(70) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(71) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(72) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(73) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(74) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(75) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(76) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(77) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(78) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(79) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(80) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(81) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(82) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(83) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(84) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(85) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(86) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(87) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(88) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(89) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(90) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(91) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(92) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(93) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(94) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(95) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(96) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(97) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(98) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(99) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(100) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(101) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(102) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(103) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(104) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(105) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(106) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(107) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(108) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(109) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(110) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(111) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(112) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(113) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(114) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(115) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(116) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(117) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(118) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(119) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(120) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(121) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(122) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(123) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(124) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(125) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(126) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(127) {-radix hexadecimal}} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray | |
|
52 | add wave -noupdate -expand -group FIFO_MS_INPUT -radix hexadecimal -subitemconfig {/tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(0) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(1) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(2) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(3) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(4) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(5) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(6) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(7) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(8) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(9) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(10) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(11) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(12) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(13) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(14) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(15) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(16) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(17) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(18) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(19) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(20) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(21) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(22) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(23) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(24) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(25) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(26) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(27) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(28) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(29) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(30) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(31) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(32) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(33) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(34) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(35) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(36) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(37) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(38) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(39) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(40) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(41) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(42) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(43) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(44) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(45) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(46) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(47) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(48) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(49) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(50) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(51) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(52) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(53) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(54) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(55) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(56) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(57) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(58) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(59) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(60) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(61) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(62) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(63) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(64) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(65) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(66) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(67) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(68) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(69) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(70) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(71) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(72) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(73) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(74) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(75) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(76) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(77) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(78) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(79) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(80) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(81) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(82) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(83) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(84) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(85) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(86) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(87) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(88) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(89) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(90) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(91) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(92) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(93) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(94) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(95) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(96) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(97) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(98) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(99) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(100) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(101) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(102) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(103) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(104) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(105) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(106) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(107) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(108) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(109) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(110) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(111) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(112) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(113) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(114) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(115) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(116) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(117) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(118) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(119) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(120) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(121) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(122) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(123) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(124) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(125) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(126) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(127) {-radix hexadecimal}} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray | |
|
57 | add wave -noupdate -expand -group FIFO_MS_INPUT -radix hexadecimal /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray | |
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58 | add wave -noupdate -expand -group FIFO_MS_INPUT -radix hexadecimal /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray | |
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59 | add wave -noupdate -expand -group FIFO_MS_INPUT -radix hexadecimal /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray | |
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60 | add wave -noupdate -expand -group FIFO_MS_INPUT -radix hexadecimal /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray | |
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61 | add wave -noupdate -expand -group FIFO_MS_INPUT -radix hexadecimal /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray | |
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53 | 62 | add wave -noupdate -radix hexadecimal /tb/lpp_lfr_ms_1/current_fifo_load |
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54 | 63 | add wave -noupdate /tb/lpp_lfr_ms_1/state_fsm_load_ms_memory |
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55 | 64 | add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/almost_full |
@@ -60,8 +69,69 add wave -noupdate /tb/lpp_lfr_ms_1/mem_ | |||
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60 | 69 | add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_sm_locked |
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61 | 70 | add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_sm_rdata |
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62 | 71 | add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_sm_ren |
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72 | add wave -noupdate -expand -group MS_CALCULATION /tb/lpp_lfr_ms_1/ms_calculation_1/correlation_auto | |
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73 | add wave -noupdate -expand -group MS_CALCULATION /tb/lpp_lfr_ms_1/ms_calculation_1/correlation_done | |
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74 | add wave -noupdate -expand -group MS_CALCULATION /tb/lpp_lfr_ms_1/ms_calculation_1/correlation_start | |
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75 | add wave -noupdate -expand -group MS_CALCULATION -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/fifo_in_data | |
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76 | add wave -noupdate -expand -group MS_CALCULATION /tb/lpp_lfr_ms_1/ms_calculation_1/fifo_in_empty | |
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77 | add wave -noupdate -expand -group MS_CALCULATION /tb/lpp_lfr_ms_1/ms_calculation_1/fifo_in_ren | |
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78 | add wave -noupdate -expand -group MS_CALCULATION -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/fifo_out_data | |
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79 | add wave -noupdate -expand -group MS_CALCULATION /tb/lpp_lfr_ms_1/ms_calculation_1/fifo_out_full | |
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80 | add wave -noupdate -expand -group MS_CALCULATION /tb/lpp_lfr_ms_1/ms_calculation_1/fifo_out_wen | |
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81 | add wave -noupdate -expand -group MS_CALCULATION -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/op1 | |
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82 | add wave -noupdate -expand -group MS_CALCULATION -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/op2 | |
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83 | add wave -noupdate -expand -group MS_CALCULATION -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/res | |
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84 | add wave -noupdate -expand -group MS_CALCULATION /tb/lpp_lfr_ms_1/ms_calculation_1/state | |
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85 | add wave -noupdate /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/empty | |
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86 | add wave -noupdate /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/full | |
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87 | add wave -noupdate /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/wdata | |
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88 | add wave -noupdate /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/wen | |
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89 | add wave -noupdate -expand -group FIFO_1 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(1)/lpp_fifo_1/raddr_vect | |
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90 | add wave -noupdate -expand -group FIFO_1 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(1)/lpp_fifo_1/raddr_vect_s | |
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91 | add wave -noupdate -expand -group FIFO_1 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(1)/lpp_fifo_1/waddr_vect | |
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92 | add wave -noupdate -expand -group FIFO_1 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(1)/lpp_fifo_1/waddr_vect_s | |
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93 | add wave -noupdate -expand -group FIFO_1 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray | |
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94 | add wave -noupdate -expand -group FIF0_0 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/raddr_vect | |
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95 | add wave -noupdate -expand -group FIF0_0 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/raddr_vect_s | |
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96 | add wave -noupdate -expand -group FIF0_0 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/waddr_vect | |
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97 | add wave -noupdate -expand -group FIF0_0 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/waddr_vect_s | |
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98 | add wave -noupdate -expand -group FIF0_0 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray | |
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99 | add wave -noupdate /tb/lpp_lfr_ms_1/status_component_fifo_0 | |
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100 | add wave -noupdate /tb/lpp_lfr_ms_1/status_component_fifo_0_end | |
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101 | add wave -noupdate /tb/lpp_lfr_ms_1/status_component_fifo_0_new | |
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102 | add wave -noupdate /tb/lpp_lfr_ms_1/status_component_fifo_1 | |
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103 | add wave -noupdate /tb/lpp_lfr_ms_1/status_component_fifo_1_end | |
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104 | add wave -noupdate /tb/lpp_lfr_ms_1/status_component_fifo_1_new | |
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105 | add wave -noupdate -expand -group FSM_DMA_FIFO_IN -radix hexadecimal /tb/lpp_lfr_ms_1/fifo_0_ready | |
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106 | add wave -noupdate -expand -group FSM_DMA_FIFO_IN -radix hexadecimal /tb/lpp_lfr_ms_1/fifo_1_ready | |
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107 | add wave -noupdate -expand -group FSM_DMA_FIFO_IN -radix hexadecimal /tb/lpp_lfr_ms_1/fifo_ongoing | |
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108 | add wave -noupdate -expand -group FSM_DMA_FIFO_IN -radix hexadecimal /tb/lpp_lfr_ms_1/fsm_dma_fifo_data | |
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109 | add wave -noupdate -expand -group FSM_DMA_FIFO_IN -radix hexadecimal /tb/lpp_lfr_ms_1/fsm_dma_fifo_empty | |
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110 | add wave -noupdate -expand -group FSM_DMA_FIFO_IN -radix hexadecimal /tb/lpp_lfr_ms_1/fsm_dma_fifo_ren | |
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111 | add wave -noupdate -expand -group FSM_DMA_FIFO_IN -radix hexadecimal /tb/lpp_lfr_ms_1/fsm_dma_fifo_status | |
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112 | add wave -noupdate -expand -group DMA_OUTPUT /tb/dma_addr | |
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113 | add wave -noupdate -expand -group DMA_OUTPUT /tb/dma_data | |
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114 | add wave -noupdate -expand -group DMA_OUTPUT /tb/dma_done | |
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115 | add wave -noupdate -expand -group DMA_OUTPUT /tb/dma_ren | |
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116 | add wave -noupdate -expand -group DMA_OUTPUT /tb/dma_valid | |
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117 | add wave -noupdate -expand -group DMA_OUTPUT /tb/dma_valid_burst | |
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118 | add wave -noupdate -expand -group DMA_OUTPUT -radix hexadecimal /tb/matrix_time_f0_0 | |
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119 | add wave -noupdate -expand -group DMA_OUTPUT -radix hexadecimal /tb/matrix_time_f0_1 | |
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120 | add wave -noupdate -expand -group DMA_OUTPUT -radix hexadecimal /tb/matrix_time_f1 | |
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121 | add wave -noupdate -expand -group DMA_OUTPUT -radix hexadecimal /tb/matrix_time_f2 | |
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122 | add wave -noupdate -expand -group DMA_OUTPUT -radix hexadecimal /tb/ready_matrix_f0_0 | |
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123 | add wave -noupdate -expand -group DMA_OUTPUT -radix hexadecimal /tb/ready_matrix_f0_1 | |
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124 | add wave -noupdate -expand -group DMA_OUTPUT -radix hexadecimal /tb/ready_matrix_f1 | |
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125 | add wave -noupdate -expand -group DMA_OUTPUT -radix hexadecimal /tb/ready_matrix_f2 | |
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126 | add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/state | |
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127 | add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/matrix_type | |
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128 | add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/component_type_pre | |
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129 | add wave -noupdate -radix unsigned /tb/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/component_type | |
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130 | add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/header_check_ok | |
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131 | add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/fifo_empty | |
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132 | add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/log_empty_fifo | |
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63 | 133 | TreeUpdate [SetDefaultTree] |
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64 |
WaveRestoreCursors {{Cursor 1} {189796403054 ps} 0} {{Cursor 2} { |
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134 | WaveRestoreCursors {{Cursor 1} {189796403054 ps} 0} {{Cursor 2} {44837900611 ps} 0} {{Cursor 3} {10445420000 ps} 0} {{Cursor 4} {61378464308 ps} 0} {{Cursor 5} {99992359332 ps} 0} | |
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65 | 135 | configure wave -namecolwidth 469 |
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66 | 136 | configure wave -valuecolwidth 112 |
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67 | 137 | configure wave -justifyvalue left |
@@ -76,6 +146,6 configure wave -griddelta 40 | |||
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76 | 146 | configure wave -timeline 0 |
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77 | 147 | configure wave -timelineunits ps |
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78 | 148 | update |
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79 |
WaveRestoreZoom {10429 |
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149 | WaveRestoreZoom {10380584292 ps} {10668763932 ps} | |
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80 | 150 | bookmark add wave bookmark0 {{61745287067 ps} {63754655343 ps}} 0 |
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81 | 151 | bookmark add wave bookmark1 {{61745287067 ps} {63754655343 ps}} 0 |
@@ -27,10 +27,12 PACKAGE lpp_lfr_pkg IS | |||
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27 | 27 | |
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28 | 28 | sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
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29 | 29 | sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
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30 | ||
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30 | 31 | sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
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31 | 32 | sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
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32 | sample_f3_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
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33 |
sample_f |
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33 | ||
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34 | sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
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35 | sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
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34 | 36 | |
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35 | 37 | dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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36 | 38 | dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
@@ -39,28 +41,30 PACKAGE lpp_lfr_pkg IS | |||
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39 | 41 | dma_ren : IN STD_LOGIC; |
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40 | 42 | dma_done : IN STD_LOGIC; |
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41 | 43 | |
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42 |
ready_matrix_f0 |
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43 | ready_matrix_f0_1 : OUT STD_LOGIC; | |
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44 | ready_matrix_f0 : OUT STD_LOGIC; | |
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45 | -- ready_matrix_f0_1 : OUT STD_LOGIC; | |
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44 | 46 | ready_matrix_f1 : OUT STD_LOGIC; |
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45 | 47 | ready_matrix_f2 : OUT STD_LOGIC; |
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46 | error_anticipating_empty_fifo : OUT STD_LOGIC; | |
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48 | -- error_anticipating_empty_fifo : OUT STD_LOGIC; | |
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47 | 49 | error_bad_component_error : OUT STD_LOGIC; |
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50 | error_buffer_full : OUT STD_LOGIC; | |
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51 | error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); | |
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48 | 52 | debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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49 |
status_ready_matrix_f0 |
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50 | status_ready_matrix_f0_1 : IN STD_LOGIC; | |
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53 | status_ready_matrix_f0 : IN STD_LOGIC; | |
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54 | -- status_ready_matrix_f0_1 : IN STD_LOGIC; | |
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51 | 55 | status_ready_matrix_f1 : IN STD_LOGIC; |
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52 | 56 | status_ready_matrix_f2 : IN STD_LOGIC; |
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53 | status_error_anticipating_empty_fifo : IN STD_LOGIC; | |
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54 | status_error_bad_component_error : IN STD_LOGIC; | |
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57 | -- status_error_anticipating_empty_fifo : IN STD_LOGIC; | |
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58 | -- status_error_bad_component_error : IN STD_LOGIC; | |
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55 | 59 | config_active_interruption_onNewMatrix : IN STD_LOGIC; |
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56 | 60 | config_active_interruption_onError : IN STD_LOGIC; |
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57 |
addr_matrix_f0 |
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58 | addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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61 | addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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62 | -- addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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59 | 63 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
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60 | 64 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
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61 | 65 | |
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62 |
matrix_time_f0 |
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63 | matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
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66 | matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
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67 | -- matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
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64 | 68 | matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
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65 | 69 | matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)); |
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66 | 70 | END COMPONENT; |
@@ -69,41 +73,48 PACKAGE lpp_lfr_pkg IS | |||
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69 | 73 | PORT ( |
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70 | 74 | HCLK : IN STD_ULOGIC; |
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71 | 75 | HRESETn : IN STD_ULOGIC; |
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72 |
|
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73 |
fifo_ |
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74 | fifo_empty : IN STD_LOGIC; | |
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75 | fifo_ren : OUT STD_LOGIC; | |
|
76 | header : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
77 | header_val : IN STD_LOGIC; | |
|
78 |
|
|
|
76 | fifo_matrix_type : IN STD_LOGIC_VECTOR(1 DOWNTO 0); | |
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77 | fifo_matrix_component : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
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78 | fifo_matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
79 | fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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80 | fifo_empty : IN STD_LOGIC; | |
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81 | fifo_ren : OUT STD_LOGIC; | |
|
82 | --data_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
83 | --fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
84 | --fifo_empty : IN STD_LOGIC; | |
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85 | --fifo_ren : OUT STD_LOGIC; | |
|
86 | --header : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
87 | --header_val : IN STD_LOGIC; | |
|
88 | --header_ack : OUT STD_LOGIC; | |
|
79 | 89 | dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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80 | 90 | dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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81 | 91 | dma_valid : OUT STD_LOGIC; |
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82 | 92 | dma_valid_burst : OUT STD_LOGIC; |
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83 | 93 | dma_ren : IN STD_LOGIC; |
|
84 | 94 | dma_done : IN STD_LOGIC; |
|
85 |
ready_matrix_f0 |
|
|
86 | ready_matrix_f0_1 : OUT STD_LOGIC; | |
|
95 | ready_matrix_f0 : OUT STD_LOGIC; | |
|
96 | -- ready_matrix_f0_1 : OUT STD_LOGIC; | |
|
87 | 97 | ready_matrix_f1 : OUT STD_LOGIC; |
|
88 | 98 | ready_matrix_f2 : OUT STD_LOGIC; |
|
89 | error_anticipating_empty_fifo : OUT STD_LOGIC; | |
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99 | -- error_anticipating_empty_fifo : OUT STD_LOGIC; | |
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90 | 100 | error_bad_component_error : OUT STD_LOGIC; |
|
101 | error_buffer_full : OUT STD_LOGIC; | |
|
91 | 102 | debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
92 |
status_ready_matrix_f0 |
|
|
93 | status_ready_matrix_f0_1 : IN STD_LOGIC; | |
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103 | status_ready_matrix_f0 : IN STD_LOGIC; | |
|
104 | -- status_ready_matrix_f0_1 : IN STD_LOGIC; | |
|
94 | 105 | status_ready_matrix_f1 : IN STD_LOGIC; |
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95 | 106 | status_ready_matrix_f2 : IN STD_LOGIC; |
|
96 | status_error_anticipating_empty_fifo : IN STD_LOGIC; | |
|
97 | status_error_bad_component_error : IN STD_LOGIC; | |
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107 | -- status_error_anticipating_empty_fifo : IN STD_LOGIC; | |
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108 | -- status_error_bad_component_error : IN STD_LOGIC; | |
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98 | 109 | config_active_interruption_onNewMatrix : IN STD_LOGIC; |
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99 | 110 | config_active_interruption_onError : IN STD_LOGIC; |
|
100 |
addr_matrix_f0 |
|
|
101 | addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
111 | addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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112 | -- addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
102 | 113 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
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103 | 114 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
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104 | 115 | |
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105 |
matrix_time_f0 |
|
|
106 | matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
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116 | matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
117 | -- matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
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107 | 118 | matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
108 | 119 | matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) |
|
109 | 120 | ); |
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