@@ -139,6 +139,9 ARCHITECTURE beh OF LFR_em IS | |||
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139 | 139 | ----------------------------------------------------------------------------- |
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140 | 140 | SIGNAL rstn : STD_LOGIC; |
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141 | 141 | |
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142 | SIGNAL LFR_soft_rstn : STD_LOGIC; | |
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143 | SIGNAL LFR_rstn : STD_LOGIC; | |
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144 | ||
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142 | 145 |
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143 | 146 | |
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144 | 147 | BEGIN -- beh |
@@ -252,7 +255,9 BEGIN -- beh | |||
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252 | 255 | apbi => apbi_ext, |
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253 | 256 | apbo => apbo_ext(6), |
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254 | 257 | coarse_time => coarse_time, |
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255 |
fine_time => fine_time |
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258 | fine_time => fine_time, | |
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259 | LFR_soft_rstn => LFR_soft_rstn | |
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260 | ); | |
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256 | 261 | |
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257 | 262 | ----------------------------------------------------------------------- |
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258 | 263 | --- SpaceWire -------------------------------------------------------- |
@@ -343,6 +348,8 BEGIN -- beh | |||
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343 | 348 | ------------------------------------------------------------------------------- |
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344 | 349 | -- LFR ------------------------------------------------------------------------ |
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345 | 350 | ------------------------------------------------------------------------------- |
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351 | LFR_rstn <= LFR_soft_rstn AND rstn; | |
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352 | ||
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346 | 353 |
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347 | 354 | GENERIC MAP ( |
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348 | 355 | Mem_use => use_RAM, |
@@ -357,13 +364,13 BEGIN -- beh | |||
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357 | 364 | pirq_ms => 6, |
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358 | 365 | pirq_wfp => 14, |
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359 | 366 | hindex => 2, |
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360 |
top_lfr_version => X"01012 |
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367 | top_lfr_version => X"010122") -- aa.bb.cc version | |
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361 | 368 | -- AA : BOARD NUMBER |
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362 | 369 | -- 0 => MINI_LFR |
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363 | 370 | -- 1 => EM |
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364 | 371 | PORT MAP ( |
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365 | 372 | clk => clk_25, |
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366 | rstn => rstn, | |
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373 | rstn => LFR_rstn, | |
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367 | 374 | sample_B => sample_s(2 DOWNTO 0), |
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368 | 375 | sample_E => sample_s(7 DOWNTO 3), |
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369 | 376 | sample_val => sample_val, |
@@ -122,12 +122,12 ARCHITECTURE beh OF MINI_LFR_top IS | |||
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122 | 122 | -- |
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123 | 123 | SIGNAL errorn : STD_LOGIC; |
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124 | 124 | -- UART AHB --------------------------------------------------------------- |
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125 | SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data | |
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126 | SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data | |
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125 | -- SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data | |
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126 | -- SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data | |
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127 | 127 | |
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128 | 128 | -- UART APB --------------------------------------------------------------- |
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129 | SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data | |
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130 | SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data | |
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129 | -- SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data | |
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130 | -- SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data | |
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131 | 131 | -- |
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132 | 132 | SIGNAL I00_s : STD_LOGIC; |
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133 | 133 | |
@@ -439,6 +439,8 BEGIN -- beh | |||
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439 | 439 | dconnect => swni.dconnect(j*2+1 DOWNTO j*2)); |
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440 | 440 | END GENERATE spw_inputloop; |
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441 | 441 | |
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442 | swni.rmapnodeaddr <= (others => '0'); | |
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443 | ||
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442 | 444 | -- SPW core |
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443 | 445 | sw0 : grspwm GENERIC MAP( |
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444 | 446 | tech => apa3e, |
@@ -514,12 +516,14 BEGIN -- beh | |||
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514 | 516 | fine_time => fine_time, |
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515 | 517 | data_shaping_BW => bias_fail_sw_sig); |
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516 | 518 | |
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519 | observation_reg <= (others => '0'); | |
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520 | observation_vector_0 <= (others => '0'); | |
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521 | observation_vector_1 <= (others => '0'); | |
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522 | ||
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517 | 523 | all_sample: FOR I IN 7 DOWNTO 0 GENERATE |
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518 | 524 | sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0'; |
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519 | 525 | END GENERATE all_sample; |
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520 | 526 | |
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521 | ||
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522 | ||
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523 | 527 | top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2 |
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524 | 528 | GENERIC MAP( |
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525 | 529 | ChannelCount => 8, |
@@ -556,6 +560,9 BEGIN -- beh | |||
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556 | 560 | GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8) |
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557 | 561 | PORT MAP(rstn_25, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo); |
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558 | 562 | |
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563 | gpioi.sig_en <= (others => '0'); | |
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564 | gpioi.sig_in <= (others => '0'); | |
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565 | gpioi.din <= (others => '0'); | |
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559 | 566 | --pio_pad_0 : iopad |
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560 | 567 | -- GENERIC MAP (tech => CFG_PADTECH) |
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561 | 568 | -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0)); |
@@ -688,4 +695,4 BEGIN -- beh | |||
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688 | 695 | END GENERATE ahbo_m_ext_not_used; |
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689 | 696 | END GENERATE all_ahbo_m_ext; |
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690 | 697 | |
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691 |
END beh; |
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698 | END beh; No newline at end of file |
@@ -19,6 +19,9 USE lpp.lpp_sim_pkg.ALL; | |||
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19 | 19 | USE lpp.lpp_lfr_apbreg_pkg.ALL; |
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20 | 20 | USE lpp.lpp_lfr_time_management_apbreg_pkg.ALL; |
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21 | 21 | |
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22 | LIBRARY postlayout; | |
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23 | USE postlayout.ALL; | |
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24 | ||
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22 | 25 | ENTITY testbench IS |
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23 | 26 | END; |
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24 | 27 |
@@ -84,8 +84,8 ARCHITECTURE ar_MAC OF MAC IS | |||
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84 | 84 | -- SIGNAL clr_MAC_D_D : STD_LOGIC; |
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85 | 85 | -- SIGNAL MAC_MUL_ADD_2C_D : STD_LOGIC_VECTOR(1 DOWNTO 0); |
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86 | 86 | |
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87 | SIGNAL load_mult_result : STD_LOGIC; | |
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88 | SIGNAL load_mult_result_D : STD_LOGIC; | |
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87 | -- SIGNAL load_mult_result : STD_LOGIC; | |
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88 | -- SIGNAL load_mult_result_D : STD_LOGIC; | |
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89 | 89 | |
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90 | 90 | BEGIN |
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91 | 91 | |
@@ -100,7 +100,7 BEGIN | |||
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100 | 100 | ctrl => MAC_MUL_ADD_s, |
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101 | 101 | MULT => mult, |
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102 | 102 | ADD => add, |
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103 | LOAD_ADDER => load_mult_result, | |
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103 | --LOAD_ADDER => load_mult_result, | |
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104 | 104 | MACMUX_sel => MACMUXsel, |
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105 | 105 | MACMUX2_sel => MACMUX2sel |
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106 | 106 | |
@@ -128,14 +128,14 BEGIN | |||
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128 | 128 | ); |
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129 | 129 | --============================================================== |
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130 | 130 | |
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131 | PROCESS (clk, reset) | |
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132 | BEGIN -- PROCESS | |
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133 | IF reset = '0' THEN -- asynchronous reset (active low) | |
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134 | load_mult_result_D <= '0'; | |
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135 |
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136 | load_mult_result_D <= load_mult_result; | |
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137 | END IF; | |
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138 | END PROCESS; | |
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131 | --PROCESS (clk, reset) | |
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132 | --BEGIN -- PROCESS | |
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133 | -- IF reset = '0' THEN -- asynchronous reset (active low) | |
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134 | -- load_mult_result_D <= '0'; | |
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135 | -- ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |
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136 | -- load_mult_result_D <= load_mult_result; | |
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137 | -- END IF; | |
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138 | --END PROCESS; | |
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139 | 139 | |
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140 | 140 | --============================================================== |
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141 | 141 | --======================A D D E R ============================== |
@@ -149,7 +149,7 BEGIN | |||
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149 | 149 | clk => clk, |
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150 | 150 | reset => reset, |
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151 | 151 | clr => clr_MAC_D, |
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152 |
load => |
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152 | load => MACMUX2sel_D, --load_mult_result_D, | |
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153 | 153 | add => add_D, |
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154 | 154 | OP1 => ADDERinA, |
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155 | 155 | OP2 => ADDERinB, |
@@ -186,7 +186,6 BEGIN | |||
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186 | 186 | RES => OP2_2C |
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187 | 187 | ); |
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188 | 188 | |
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189 | ||
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190 | 189 | clr_MACREG_comp : MAC_REG |
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191 | 190 | GENERIC MAP(size => 1) |
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192 | 191 | PORT MAP( |
@@ -31,7 +31,7 port( | |||
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31 | 31 | ctrl : in std_logic_vector(1 downto 0); |
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32 | 32 | MULT : out std_logic; |
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33 | 33 | ADD : out std_logic; |
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34 | LOAD_ADDER : out std_logic; | |
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34 | -- LOAD_ADDER : out std_logic; | |
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35 | 35 | MACMUX_sel : out std_logic; |
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36 | 36 | MACMUX2_sel : out std_logic |
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37 | 37 | |
@@ -50,7 +50,7 begin | |||
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50 | 50 | |
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51 | 51 | MULT <= '0' when (ctrl = "00" or ctrl = "11") else '1'; |
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52 | 52 | ADD <= '0' when (ctrl = "00" or ctrl = "10") else '1'; |
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53 | LOAD_ADDER <= '1' when (ctrl = "10") else '0'; -- PATCH JC : mem mult result | |
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53 | --LOAD_ADDER <= '1' when ( ctrl = "10") else '0'; -- PATCH JC : mem mult result | |
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54 | 54 | -- to permit to compute a |
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55 | 55 | -- MULT follow by a MAC |
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56 | 56 | --MACMUX_sel <= '0' when (ctrl = "00" or ctrl = "01") else '1'; |
@@ -217,7 +217,7 Constant CLR_MAC_V0 : std_logic_vector(3 | |||
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217 | 217 | ctrl : IN STD_LOGIC_VECTOR(1 DOWNTO 0); |
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218 | 218 | MULT : OUT STD_LOGIC; |
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219 | 219 | ADD : OUT STD_LOGIC; |
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220 | LOAD_ADDER : out std_logic; | |
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220 | -- LOAD_ADDER : out std_logic; | |
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221 | 221 | MACMUX_sel : OUT STD_LOGIC; |
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222 | 222 | MACMUX2_sel : OUT STD_LOGIC |
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223 | 223 | ); |
@@ -57,7 +57,7 ARCHITECTURE ar_ADS7886_drvr_v2 OF ADS78 | |||
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57 | 57 | SIGNAL cnv_sync_r : STD_LOGIC; |
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58 | 58 | SIGNAL cnv_done : STD_LOGIC; |
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59 | 59 | SIGNAL sample_bit_counter : INTEGER; |
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60 | SIGNAL shift_reg : Samples(ChannelCount-1 DOWNTO 0); | |
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60 | SIGNAL shift_reg : Samples_15(ChannelCount-1 DOWNTO 0); | |
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61 | 61 | |
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62 | 62 | BEGIN |
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63 | 63 | |
@@ -82,7 +82,7 cnv_sync <= cnv_clk; | |||
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82 | 82 | BEGIN -- PROCESS |
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83 | 83 | IF rstn = '0' THEN |
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84 | 84 | FOR k IN 0 TO ChannelCount-1 LOOP |
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85 |
shift_reg(k)(1 |
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85 | shift_reg(k)(14 downto 0) <= (OTHERS => '0'); | |
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86 | 86 |
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87 | 87 | END LOOP; |
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88 | 88 | sample_bit_counter <= 0; |
@@ -107,7 +107,7 cnv_sync <= cnv_clk; | |||
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107 | 107 | IF (sample_bit_counter MOD 2) = 1 THEN -- get data on each channel |
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108 | 108 | FOR k IN 0 TO ChannelCount-1 LOOP |
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109 | 109 | shift_reg(k)(0) <= sdo(k); |
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110 |
shift_reg(k)(1 |
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110 | shift_reg(k)(14 DOWNTO 1) <= shift_reg(k)(13 DOWNTO 0); | |
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111 | 111 | END LOOP; |
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112 | 112 | SCK <= '0'; |
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113 | 113 | ELSE |
@@ -116,4 +116,4 cnv_sync <= cnv_clk; | |||
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116 | 116 | END IF; |
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117 | 117 | END PROCESS; |
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118 | 118 | |
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119 | END ar_ADS7886_drvr_v2; No newline at end of file | |
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119 | END ar_ADS7886_drvr_v2; |
@@ -48,6 +48,7 PACKAGE lpp_ad_conv IS | |||
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48 | 48 | --TYPE AD7688_in IS ARRAY(NATURAL RANGE <>) OF AD7688_in_element; |
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49 | 49 | |
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50 | 50 | TYPE Samples IS ARRAY(NATURAL RANGE <>) OF STD_LOGIC_VECTOR(15 DOWNTO 0); |
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51 | TYPE Samples_15 IS ARRAY(NATURAL RANGE <>) OF STD_LOGIC_VECTOR(14 DOWNTO 0); | |
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51 | 52 | |
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52 | 53 | SUBTYPE Samples24 IS STD_LOGIC_VECTOR(23 DOWNTO 0); |
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53 | 54 |
@@ -91,11 +91,11 ARCHITECTURE beh OF lpp_lfr IS | |||
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91 | 91 | |
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92 | 92 | -- SM |
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93 | 93 | SIGNAL ready_matrix_f0 : STD_LOGIC; |
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94 | SIGNAL ready_matrix_f0_1 : STD_LOGIC; | |
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94 | -- SIGNAL ready_matrix_f0_1 : STD_LOGIC; | |
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95 | 95 | SIGNAL ready_matrix_f1 : STD_LOGIC; |
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96 | 96 | SIGNAL ready_matrix_f2 : STD_LOGIC; |
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97 | 97 | SIGNAL status_ready_matrix_f0 : STD_LOGIC; |
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98 | SIGNAL status_ready_matrix_f0_1 : STD_LOGIC; | |
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98 | -- SIGNAL status_ready_matrix_f0_1 : STD_LOGIC; | |
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99 | 99 | SIGNAL status_ready_matrix_f1 : STD_LOGIC; |
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100 | 100 | SIGNAL status_ready_matrix_f2 : STD_LOGIC; |
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101 | 101 | SIGNAL addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
@@ -129,24 +129,24 ARCHITECTURE beh OF lpp_lfr IS | |||
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129 | 129 | ----------------------------------------------------------------------------- |
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130 | 130 | -- |
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131 | 131 | ----------------------------------------------------------------------------- |
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132 | SIGNAL data_f0_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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133 | SIGNAL data_f0_data_out_valid_s : STD_LOGIC; | |
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134 | SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC; | |
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132 | -- SIGNAL data_f0_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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133 | -- SIGNAL data_f0_data_out_valid_s : STD_LOGIC; | |
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134 | -- SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC; | |
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135 | 135 | --f1 |
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136 | SIGNAL data_f1_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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137 | SIGNAL data_f1_data_out_valid_s : STD_LOGIC; | |
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138 | SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC; | |
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136 | -- SIGNAL data_f1_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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137 | -- SIGNAL data_f1_data_out_valid_s : STD_LOGIC; | |
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138 | -- SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC; | |
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139 | 139 | --f2 |
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140 | SIGNAL data_f2_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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141 | SIGNAL data_f2_data_out_valid_s : STD_LOGIC; | |
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142 | SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC; | |
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140 | -- SIGNAL data_f2_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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141 | -- SIGNAL data_f2_data_out_valid_s : STD_LOGIC; | |
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142 | -- SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC; | |
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143 | 143 | --f3 |
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144 | SIGNAL data_f3_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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145 | SIGNAL data_f3_data_out_valid_s : STD_LOGIC; | |
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146 | SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC; | |
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144 | -- SIGNAL data_f3_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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145 | -- SIGNAL data_f3_data_out_valid_s : STD_LOGIC; | |
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146 | -- SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC; | |
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147 | 147 | |
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148 | 148 | SIGNAL wfp_status_buffer_ready : STD_LOGIC_VECTOR(3 DOWNTO 0); |
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149 | SIGNAL wfp_addr_buffer : STD_LOGIC_VECTOR(32*4 DOWNTO 0); | |
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149 | SIGNAL wfp_addr_buffer : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0); | |
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150 | 150 | SIGNAL wfp_length_buffer : STD_LOGIC_VECTOR(25 DOWNTO 0); |
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151 | 151 | SIGNAL wfp_ready_buffer : STD_LOGIC_VECTOR(3 DOWNTO 0); |
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152 | 152 | SIGNAL wfp_buffer_time : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0); |
@@ -154,51 +154,51 ARCHITECTURE beh OF lpp_lfr IS | |||
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154 | 154 | ----------------------------------------------------------------------------- |
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155 | 155 | -- DMA RR |
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156 | 156 | ----------------------------------------------------------------------------- |
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157 | SIGNAL dma_sel_valid : STD_LOGIC; | |
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158 | SIGNAL dma_rr_valid : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
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159 | SIGNAL dma_rr_grant_s : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
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160 | SIGNAL dma_rr_grant_ms : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
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161 | SIGNAL dma_rr_valid_ms : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
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157 | -- SIGNAL dma_sel_valid : STD_LOGIC; | |
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158 | -- SIGNAL dma_rr_valid : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
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159 | -- SIGNAL dma_rr_grant_s : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
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160 | -- SIGNAL dma_rr_grant_ms : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
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161 | -- SIGNAL dma_rr_valid_ms : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
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162 | 162 | |
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163 | SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
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164 | SIGNAL dma_sel : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
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163 | -- SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
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164 | -- SIGNAL dma_sel : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
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165 | 165 | |
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166 | 166 | ----------------------------------------------------------------------------- |
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167 | 167 | -- DMA_REG |
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168 | 168 | ----------------------------------------------------------------------------- |
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169 | SIGNAL ongoing_reg : STD_LOGIC; | |
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170 | SIGNAL dma_sel_reg : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
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171 | SIGNAL dma_send_reg : STD_LOGIC; | |
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172 | SIGNAL dma_valid_burst_reg : STD_LOGIC; -- (1 => BURST , 0 => SINGLE) | |
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173 | SIGNAL dma_address_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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174 | SIGNAL dma_data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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169 | -- SIGNAL ongoing_reg : STD_LOGIC; | |
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170 | -- SIGNAL dma_sel_reg : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
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171 | -- SIGNAL dma_send_reg : STD_LOGIC; | |
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172 | -- SIGNAL dma_valid_burst_reg : STD_LOGIC; -- (1 => BURST , 0 => SINGLE) | |
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173 | -- SIGNAL dma_address_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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174 | -- SIGNAL dma_data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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175 | 175 | |
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176 | 176 | |
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177 | 177 | ----------------------------------------------------------------------------- |
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178 | 178 | -- DMA |
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179 | 179 | ----------------------------------------------------------------------------- |
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180 | SIGNAL dma_send : STD_LOGIC; | |
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181 | SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE) | |
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182 | SIGNAL dma_done : STD_LOGIC; | |
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183 | SIGNAL dma_ren : STD_LOGIC; | |
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184 | SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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185 | SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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186 | SIGNAL dma_data_2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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180 | -- SIGNAL dma_send : STD_LOGIC; | |
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181 | -- SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE) | |
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182 | -- SIGNAL dma_done : STD_LOGIC; | |
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183 | -- SIGNAL dma_ren : STD_LOGIC; | |
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184 | -- SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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185 | -- SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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186 | -- SIGNAL dma_data_2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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187 | 187 | |
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188 | 188 | ----------------------------------------------------------------------------- |
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189 | 189 | -- MS |
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190 | 190 | ----------------------------------------------------------------------------- |
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191 | 191 | |
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192 | SIGNAL data_ms_addr : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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193 | SIGNAL data_ms_data : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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194 | SIGNAL data_ms_valid : STD_LOGIC; | |
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195 | SIGNAL data_ms_valid_burst : STD_LOGIC; | |
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196 | SIGNAL data_ms_ren : STD_LOGIC; | |
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197 | SIGNAL data_ms_done : STD_LOGIC; | |
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198 | SIGNAL dma_ms_ongoing : STD_LOGIC; | |
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192 | -- SIGNAL data_ms_addr : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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193 | -- SIGNAL data_ms_data : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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194 | -- SIGNAL data_ms_valid : STD_LOGIC; | |
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195 | -- SIGNAL data_ms_valid_burst : STD_LOGIC; | |
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196 | -- SIGNAL data_ms_ren : STD_LOGIC; | |
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197 | -- SIGNAL data_ms_done : STD_LOGIC; | |
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198 | -- SIGNAL dma_ms_ongoing : STD_LOGIC; | |
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199 | 199 | |
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200 | 200 | -- SIGNAL run_ms : STD_LOGIC; |
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201 | SIGNAL ms_softandhard_rstn : STD_LOGIC; | |
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201 | -- SIGNAL ms_softandhard_rstn : STD_LOGIC; | |
|
202 | 202 | |
|
203 | 203 | SIGNAL matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
204 | 204 | -- SIGNAL matrix_time_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0); |
@@ -210,7 +210,7 ARCHITECTURE beh OF lpp_lfr IS | |||
|
210 | 210 | SIGNAL error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0); |
|
211 | 211 | |
|
212 | 212 | -- SIGNAL debug_ms : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
213 | SIGNAL debug_signal : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
213 | -- SIGNAL debug_signal : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
214 | 214 | |
|
215 | 215 | ----------------------------------------------------------------------------- |
|
216 | 216 | SIGNAL dma_fifo_burst_valid : STD_LOGIC_VECTOR(4 DOWNTO 0); |
@@ -133,7 +133,7 ENTITY lpp_lfr_apbreg IS | |||
|
133 | 133 | start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0); |
|
134 | 134 | |
|
135 | 135 | wfp_status_buffer_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
136 | wfp_addr_buffer : OUT STD_LOGIC_VECTOR(32*4 DOWNTO 0); | |
|
136 | wfp_addr_buffer : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0); | |
|
137 | 137 | wfp_length_buffer : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); |
|
138 | 138 | wfp_ready_buffer : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
139 | 139 | wfp_buffer_time : IN STD_LOGIC_VECTOR(48*4-1 DOWNTO 0); |
@@ -238,28 +238,28 ARCHITECTURE beh OF lpp_lfr_apbreg IS | |||
|
238 | 238 | -- |
|
239 | 239 | ----------------------------------------------------------------------------- |
|
240 | 240 | SIGNAL reg0_ready_matrix_f0 : STD_LOGIC; |
|
241 | SIGNAL reg0_addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
242 | SIGNAL reg0_matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
241 | -- SIGNAL reg0_addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
242 | -- SIGNAL reg0_matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
243 | 243 | |
|
244 | 244 | SIGNAL reg1_ready_matrix_f0 : STD_LOGIC; |
|
245 | SIGNAL reg1_addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
246 | SIGNAL reg1_matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
245 | -- SIGNAL reg1_addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
246 | -- SIGNAL reg1_matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
247 | 247 | |
|
248 | 248 | SIGNAL reg0_ready_matrix_f1 : STD_LOGIC; |
|
249 | SIGNAL reg0_addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
250 | SIGNAL reg0_matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
249 | -- SIGNAL reg0_addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
250 | -- SIGNAL reg0_matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
251 | 251 | |
|
252 | 252 | SIGNAL reg1_ready_matrix_f1 : STD_LOGIC; |
|
253 | SIGNAL reg1_addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
254 | SIGNAL reg1_matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
253 | -- SIGNAL reg1_addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
254 | -- SIGNAL reg1_matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
255 | 255 | |
|
256 | 256 | SIGNAL reg0_ready_matrix_f2 : STD_LOGIC; |
|
257 | SIGNAL reg0_addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
258 | SIGNAL reg0_matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
257 | -- SIGNAL reg0_addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
258 | -- SIGNAL reg0_matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
259 | 259 | |
|
260 | 260 | SIGNAL reg1_ready_matrix_f2 : STD_LOGIC; |
|
261 | SIGNAL reg1_addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
262 | SIGNAL reg1_matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
261 | -- SIGNAL reg1_addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
262 | -- SIGNAL reg1_matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
263 | 263 | SIGNAL apbo_irq_ms : STD_LOGIC; |
|
264 | 264 | SIGNAL apbo_irq_wfp : STD_LOGIC; |
|
265 | 265 | ----------------------------------------------------------------------------- |
@@ -778,4 +778,4 BEGIN -- beh | |||
|
778 | 778 | |
|
779 | 779 | END beh; |
|
780 | 780 | |
|
781 |
------------------------------------------------------------------------------- |
|
|
781 | ------------------------------------------------------------------------------- No newline at end of file |
@@ -121,7 +121,9 ARCHITECTURE Behavioral OF lpp_lfr_ms IS | |||
|
121 | 121 | ----------------------------------------------------------------------------- |
|
122 | 122 | TYPE fsm_select_channel IS (IDLE, SWITCH_F0_A, SWITCH_F0_B, SWITCH_F1, SWITCH_F2); |
|
123 | 123 | SIGNAL state_fsm_select_channel : fsm_select_channel; |
|
124 | SIGNAL pre_state_fsm_select_channel : fsm_select_channel; | |
|
124 | -- SIGNAL pre_state_fsm_select_channel : fsm_select_channel; | |
|
125 | SIGNAL select_channel : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
126 | SIGNAL select_channel_reg : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
125 | 127 | |
|
126 | 128 |
|
|
127 | 129 | SIGNAL sample_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); |
@@ -133,7 +135,9 ARCHITECTURE Behavioral OF lpp_lfr_ms IS | |||
|
133 | 135 | ----------------------------------------------------------------------------- |
|
134 | 136 | TYPE fsm_load_FFT IS (IDLE, FIFO_1, FIFO_2, FIFO_3, FIFO_4, FIFO_5); |
|
135 | 137 | SIGNAL state_fsm_load_FFT : fsm_load_FFT; |
|
136 | SIGNAL next_state_fsm_load_FFT : fsm_load_FFT; | |
|
138 | -- SIGNAL next_state_fsm_load_FFT : fsm_load_FFT; | |
|
139 | SIGNAL select_fifo : STD_LOGIC_VECTOR(2 DOWNTO 0); | |
|
140 | SIGNAL select_fifo_reg : STD_LOGIC_VECTOR(2 DOWNTO 0); | |
|
137 | 141 | |
|
138 | 142 | SIGNAL sample_ren_s : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
139 | 143 | SIGNAL sample_load : STD_LOGIC; |
@@ -199,7 +203,7 ARCHITECTURE Behavioral OF lpp_lfr_ms IS | |||
|
199 | 203 | SIGNAL FSM_DMA_fifo_empty : STD_LOGIC; |
|
200 | 204 | SIGNAL FSM_DMA_fifo_empty_threshold : STD_LOGIC; |
|
201 | 205 | SIGNAL FSM_DMA_fifo_data : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
202 |
SIGNAL FSM_DMA_fifo_status : STD_LOGIC_VECTOR(53 DOWNTO |
|
|
206 | SIGNAL FSM_DMA_fifo_status : STD_LOGIC_VECTOR(53 DOWNTO 4); | |
|
203 | 207 | ----------------------------------------------------------------------------- |
|
204 | 208 | SIGNAL MEM_OUT_SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
205 | 209 | SIGNAL MEM_OUT_SM_Read : STD_LOGIC_VECTOR(1 DOWNTO 0); |
@@ -233,8 +237,8 ARCHITECTURE Behavioral OF lpp_lfr_ms IS | |||
|
233 | 237 | SIGNAL status_MS_input : STD_LOGIC_VECTOR(49 DOWNTO 0); |
|
234 | 238 | SIGNAL status_component : STD_LOGIC_VECTOR(53 DOWNTO 0); |
|
235 | 239 | |
|
236 |
SIGNAL status_component_fifo_0 : STD_LOGIC_VECTOR(53 DOWNTO |
|
|
237 |
SIGNAL status_component_fifo_1 : STD_LOGIC_VECTOR(53 DOWNTO |
|
|
240 | SIGNAL status_component_fifo_0 : STD_LOGIC_VECTOR(53 DOWNTO 4); | |
|
241 | SIGNAL status_component_fifo_1 : STD_LOGIC_VECTOR(53 DOWNTO 4); | |
|
238 | 242 | SIGNAL status_component_fifo_0_end : STD_LOGIC; |
|
239 | 243 | SIGNAL status_component_fifo_1_end : STD_LOGIC; |
|
240 | 244 | ----------------------------------------------------------------------------- |
@@ -471,36 +475,45 BEGIN | |||
|
471 | 475 | BEGIN |
|
472 | 476 | IF rstn = '0' THEN |
|
473 | 477 | state_fsm_select_channel <= IDLE; |
|
478 | select_channel <= (OTHERS => '0'); | |
|
474 | 479 | ELSIF clk'EVENT AND clk = '1' THEN |
|
475 | 480 | CASE state_fsm_select_channel IS |
|
476 | 481 | WHEN IDLE => |
|
477 | 482 | IF sample_f1_full = "11111" THEN |
|
478 | 483 | state_fsm_select_channel <= SWITCH_F1; |
|
484 | select_channel <= "10"; | |
|
479 | 485 | ELSIF sample_f1_almost_full = "00000" THEN |
|
480 | 486 | IF sample_f0_A_full = "11111" THEN |
|
481 | 487 | state_fsm_select_channel <= SWITCH_F0_A; |
|
488 | select_channel <= "00"; | |
|
482 | 489 | ELSIF sample_f0_B_full = "11111" THEN |
|
483 | 490 | state_fsm_select_channel <= SWITCH_F0_B; |
|
491 | select_channel <= "01"; | |
|
484 | 492 | ELSIF sample_f2_full = "11111" THEN |
|
485 | 493 | state_fsm_select_channel <= SWITCH_F2; |
|
494 | select_channel <= "11"; | |
|
486 | 495 | END IF; |
|
487 | 496 | END IF; |
|
488 | 497 | |
|
489 | 498 | WHEN SWITCH_F0_A => |
|
490 | 499 | IF sample_f0_A_empty = "11111" THEN |
|
491 | 500 | state_fsm_select_channel <= IDLE; |
|
501 | select_channel <= (OTHERS => '0'); | |
|
492 | 502 | END IF; |
|
493 | 503 | WHEN SWITCH_F0_B => |
|
494 | 504 | IF sample_f0_B_empty = "11111" THEN |
|
495 | 505 | state_fsm_select_channel <= IDLE; |
|
506 | select_channel <= (OTHERS => '0'); | |
|
496 | 507 | END IF; |
|
497 | 508 | WHEN SWITCH_F1 => |
|
498 | 509 | IF sample_f1_empty = "11111" THEN |
|
499 | 510 | state_fsm_select_channel <= IDLE; |
|
511 | select_channel <= (OTHERS => '0'); | |
|
500 | 512 | END IF; |
|
501 | 513 | WHEN SWITCH_F2 => |
|
502 | 514 | IF sample_f2_empty = "11111" THEN |
|
503 | 515 | state_fsm_select_channel <= IDLE; |
|
516 | select_channel <= (OTHERS => '0'); | |
|
504 | 517 | END IF; |
|
505 | 518 | WHEN OTHERS => NULL; |
|
506 | 519 | END CASE; |
@@ -511,9 +524,11 BEGIN | |||
|
511 | 524 | PROCESS (clk, rstn) |
|
512 | 525 | BEGIN |
|
513 | 526 | IF rstn = '0' THEN |
|
514 | pre_state_fsm_select_channel <= IDLE; | |
|
527 | select_channel_reg <= (OTHERS => '0'); | |
|
528 | --pre_state_fsm_select_channel <= IDLE; | |
|
515 | 529 | ELSIF clk'EVENT AND clk = '1' THEN |
|
516 |
|
|
|
530 | select_channel_reg <= select_channel; | |
|
531 | --pre_state_fsm_select_channel <= state_fsm_select_channel; | |
|
517 | 532 | END IF; |
|
518 | 533 | END PROCESS; |
|
519 | 534 | |
@@ -533,9 +548,13 BEGIN | |||
|
533 | 548 | sample_f2_full WHEN state_fsm_select_channel = SWITCH_F2 ELSE |
|
534 | 549 | (OTHERS => '0'); |
|
535 | 550 | |
|
536 | sample_rdata <= sample_f0_A_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_A ELSE | |
|
537 | sample_f0_B_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_B ELSE | |
|
538 | sample_f1_rdata WHEN pre_state_fsm_select_channel = SWITCH_F1 ELSE | |
|
551 | --sample_rdata <= sample_f0_A_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_A ELSE | |
|
552 | -- sample_f0_B_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_B ELSE | |
|
553 | -- sample_f1_rdata WHEN pre_state_fsm_select_channel = SWITCH_F1 ELSE | |
|
554 | -- sample_f2_rdata; -- WHEN state_fsm_select_channel = SWITCH_F2 ELSE | |
|
555 | sample_rdata <= sample_f0_A_rdata WHEN select_channel_reg = "00" ELSE | |
|
556 | sample_f0_B_rdata WHEN select_channel_reg = "01" ELSE | |
|
557 | sample_f1_rdata WHEN select_channel_reg = "10" ELSE | |
|
539 | 558 | sample_f2_rdata; -- WHEN state_fsm_select_channel = SWITCH_F2 ELSE |
|
540 | 559 | |
|
541 | 560 | |
@@ -564,6 +583,7 BEGIN | |||
|
564 | 583 | sample_ren_s <= (OTHERS => '1'); |
|
565 | 584 | state_fsm_load_FFT <= IDLE; |
|
566 | 585 | status_MS_input <= (OTHERS => '0'); |
|
586 | select_fifo <= "000"; | |
|
567 | 587 | --next_state_fsm_load_FFT <= IDLE; |
|
568 | 588 | --sample_valid <= '0'; |
|
569 | 589 | ELSIF clk'EVENT AND clk = '1' THEN |
@@ -574,6 +594,7 BEGIN | |||
|
574 | 594 | IF sample_full = "11111" AND sample_load = '1' THEN |
|
575 | 595 | state_fsm_load_FFT <= FIFO_1; |
|
576 | 596 | status_MS_input <= status_channel; |
|
597 | select_fifo <= "000"; | |
|
577 | 598 | END IF; |
|
578 | 599 | |
|
579 | 600 | WHEN FIFO_1 => |
@@ -581,6 +602,7 BEGIN | |||
|
581 | 602 | IF sample_empty(0) = '1' THEN |
|
582 | 603 | sample_ren_s <= (OTHERS => '1'); |
|
583 | 604 | state_fsm_load_FFT <= FIFO_2; |
|
605 | select_fifo <= "001"; | |
|
584 | 606 | END IF; |
|
585 | 607 | |
|
586 | 608 | WHEN FIFO_2 => |
@@ -588,6 +610,7 BEGIN | |||
|
588 | 610 | IF sample_empty(1) = '1' THEN |
|
589 | 611 | sample_ren_s <= (OTHERS => '1'); |
|
590 | 612 | state_fsm_load_FFT <= FIFO_3; |
|
613 | select_fifo <= "010"; | |
|
591 | 614 | END IF; |
|
592 | 615 | |
|
593 | 616 | WHEN FIFO_3 => |
@@ -595,6 +618,7 BEGIN | |||
|
595 | 618 | IF sample_empty(2) = '1' THEN |
|
596 | 619 | sample_ren_s <= (OTHERS => '1'); |
|
597 | 620 | state_fsm_load_FFT <= FIFO_4; |
|
621 | select_fifo <= "011"; | |
|
598 | 622 | END IF; |
|
599 | 623 | |
|
600 | 624 | WHEN FIFO_4 => |
@@ -602,6 +626,7 BEGIN | |||
|
602 | 626 | IF sample_empty(3) = '1' THEN |
|
603 | 627 | sample_ren_s <= (OTHERS => '1'); |
|
604 | 628 | state_fsm_load_FFT <= FIFO_5; |
|
629 | select_fifo <= "100"; | |
|
605 | 630 | END IF; |
|
606 | 631 | |
|
607 | 632 | WHEN FIFO_5 => |
@@ -609,6 +634,7 BEGIN | |||
|
609 | 634 | IF sample_empty(4) = '1' THEN |
|
610 | 635 | sample_ren_s <= (OTHERS => '1'); |
|
611 | 636 | state_fsm_load_FFT <= IDLE; |
|
637 | select_fifo <= "000"; | |
|
612 | 638 | END IF; |
|
613 | 639 | WHEN OTHERS => NULL; |
|
614 | 640 | END CASE; |
@@ -619,9 +645,11 BEGIN | |||
|
619 | 645 | BEGIN |
|
620 | 646 | IF rstn = '0' THEN |
|
621 | 647 | sample_valid_r <= '0'; |
|
622 | next_state_fsm_load_FFT <= IDLE; | |
|
648 | select_fifo_reg <= (OTHERS => '0'); | |
|
649 | --next_state_fsm_load_FFT <= IDLE; | |
|
623 | 650 | ELSIF clk'EVENT AND clk = '1' THEN |
|
624 | next_state_fsm_load_FFT <= state_fsm_load_FFT; | |
|
651 | select_fifo_reg <= select_fifo; | |
|
652 | --next_state_fsm_load_FFT <= state_fsm_load_FFT; | |
|
625 | 653 | IF sample_ren_s = "11111" THEN |
|
626 | 654 | sample_valid_r <= '0'; |
|
627 | 655 | ELSE |
@@ -632,10 +660,15 BEGIN | |||
|
632 | 660 | |
|
633 | 661 | sample_valid <= '0' WHEN fft_ongoing_counter = '1' ELSE sample_valid_r AND sample_load; |
|
634 | 662 | |
|
635 | sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN next_state_fsm_load_FFT = FIFO_1 ELSE | |
|
636 | sample_rdata(16*2-1 DOWNTO 16*1) WHEN next_state_fsm_load_FFT = FIFO_2 ELSE | |
|
637 | sample_rdata(16*3-1 DOWNTO 16*2) WHEN next_state_fsm_load_FFT = FIFO_3 ELSE | |
|
638 | sample_rdata(16*4-1 DOWNTO 16*3) WHEN next_state_fsm_load_FFT = FIFO_4 ELSE | |
|
663 | --sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN next_state_fsm_load_FFT = FIFO_1 ELSE | |
|
664 | -- sample_rdata(16*2-1 DOWNTO 16*1) WHEN next_state_fsm_load_FFT = FIFO_2 ELSE | |
|
665 | -- sample_rdata(16*3-1 DOWNTO 16*2) WHEN next_state_fsm_load_FFT = FIFO_3 ELSE | |
|
666 | -- sample_rdata(16*4-1 DOWNTO 16*3) WHEN next_state_fsm_load_FFT = FIFO_4 ELSE | |
|
667 | -- sample_rdata(16*5-1 DOWNTO 16*4); --WHEN next_state_fsm_load_FFT = FIFO_5 ELSE | |
|
668 | sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN select_fifo_reg = "000" ELSE | |
|
669 | sample_rdata(16*2-1 DOWNTO 16*1) WHEN select_fifo_reg = "001" ELSE | |
|
670 | sample_rdata(16*3-1 DOWNTO 16*2) WHEN select_fifo_reg = "010" ELSE | |
|
671 | sample_rdata(16*4-1 DOWNTO 16*3) WHEN select_fifo_reg = "011" ELSE | |
|
639 | 672 | sample_rdata(16*5-1 DOWNTO 16*4); --WHEN next_state_fsm_load_FFT = FIFO_5 ELSE |
|
640 | 673 | |
|
641 | 674 |
|
@@ -852,9 +885,9 BEGIN | |||
|
852 | 885 | status_component_fifo_1_end <= '0'; |
|
853 | 886 | IF SM_correlation_begin = '1' THEN |
|
854 | 887 | IF current_matrix_write = '0' THEN |
|
855 | status_component_fifo_0 <= status_component; | |
|
888 | status_component_fifo_0 <= status_component(53 DOWNTO 4); | |
|
856 | 889 | ELSE |
|
857 | status_component_fifo_1 <= status_component; | |
|
890 | status_component_fifo_1 <= status_component(53 DOWNTO 4); | |
|
858 | 891 | END IF; |
|
859 | 892 | END IF; |
|
860 | 893 |
@@ -311,7 +311,7 PACKAGE lpp_lfr_pkg IS | |||
|
311 | 311 | run : OUT STD_LOGIC; |
|
312 | 312 | start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0); |
|
313 | 313 | wfp_status_buffer_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
314 | wfp_addr_buffer : OUT STD_LOGIC_VECTOR(32*4 DOWNTO 0); | |
|
314 | wfp_addr_buffer : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0); | |
|
315 | 315 | wfp_length_buffer : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); |
|
316 | 316 | wfp_ready_buffer : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
317 | 317 | wfp_buffer_time : IN STD_LOGIC_VECTOR(48*4-1 DOWNTO 0); |
@@ -84,7 +84,7 ENTITY lpp_waveform IS | |||
|
84 | 84 | |
|
85 | 85 | -- REG DMA |
|
86 | 86 | status_buffer_ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
87 | addr_buffer : IN STD_LOGIC_VECTOR(32*4 DOWNTO 0); | |
|
87 | addr_buffer : IN STD_LOGIC_VECTOR(32*4-1 DOWNTO 0); | |
|
88 | 88 | length_buffer : IN STD_LOGIC_VECTOR(25 DOWNTO 0); |
|
89 | 89 | |
|
90 | 90 | ready_buffer : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
@@ -73,11 +73,11 ARCHITECTURE ar_lpp_waveform_fifo_arbite | |||
|
73 | 73 | -- DATA MUX |
|
74 | 74 | ----------------------------------------------------------------------------- |
|
75 | 75 | TYPE WORD_VECTOR IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
76 |
SIGNAL data_0 : WORD_VECTOR( |
|
|
77 |
SIGNAL data_1 : WORD_VECTOR( |
|
|
78 |
SIGNAL data_2 : WORD_VECTOR( |
|
|
79 |
SIGNAL data_3 : WORD_VECTOR( |
|
|
80 |
SIGNAL data_sel : WORD_VECTOR( |
|
|
76 | SIGNAL data_0 : WORD_VECTOR(2 DOWNTO 0); | |
|
77 | SIGNAL data_1 : WORD_VECTOR(2 DOWNTO 0); | |
|
78 | SIGNAL data_2 : WORD_VECTOR(2 DOWNTO 0); | |
|
79 | SIGNAL data_3 : WORD_VECTOR(2 DOWNTO 0); | |
|
80 | SIGNAL data_sel : WORD_VECTOR(2 DOWNTO 0); | |
|
81 | 81 | |
|
82 | 82 | ----------------------------------------------------------------------------- |
|
83 | 83 | -- RR and SELECTION |
@@ -267,4 +267,3 END ARCHITECTURE; | |||
|
267 | 267 | |
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268 | 268 | |
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269 | 269 | |
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270 |
@@ -129,7 +129,7 PACKAGE lpp_waveform_pkg IS | |||
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129 | 129 | nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); |
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130 | 130 | status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
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131 | 131 | status_buffer_ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
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132 | addr_buffer : IN STD_LOGIC_VECTOR(32*4 DOWNTO 0); | |
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132 | addr_buffer : IN STD_LOGIC_VECTOR(32*4-1 DOWNTO 0); | |
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133 | 133 | length_buffer : IN STD_LOGIC_VECTOR(25 DOWNTO 0); |
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134 | 134 | ready_buffer : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
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135 | 135 | buffer_time : OUT STD_LOGIC_VECTOR(48*4-1 DOWNTO 0); |
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