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1.1.34 : idem 1.1.33 avec reset soft pour LFR subsystem
pellion -
r463:832e74562224 (LFR-EM) WFP_MS-1-1-34 JC
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1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -------------------------------------------------------------------------------
22 22 LIBRARY IEEE;
23 23 USE IEEE.numeric_std.ALL;
24 24 USE IEEE.std_logic_1164.ALL;
25 25 LIBRARY grlib;
26 26 USE grlib.amba.ALL;
27 27 USE grlib.stdlib.ALL;
28 28 LIBRARY techmap;
29 29 USE techmap.gencomp.ALL;
30 30 LIBRARY gaisler;
31 31 USE gaisler.memctrl.ALL;
32 32 USE gaisler.leon3.ALL;
33 33 USE gaisler.uart.ALL;
34 34 USE gaisler.misc.ALL;
35 35 USE gaisler.spacewire.ALL;
36 36 LIBRARY esa;
37 37 USE esa.memoryctrl.ALL;
38 38 LIBRARY lpp;
39 39 USE lpp.lpp_memory.ALL;
40 40 USE lpp.lpp_ad_conv.ALL;
41 41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 43 USE lpp.iir_filter.ALL;
44 44 USE lpp.general_purpose.ALL;
45 45 USE lpp.lpp_lfr_time_management.ALL;
46 46 USE lpp.lpp_leon3_soc_pkg.ALL;
47 47
48 48 ENTITY LFR_em IS
49 49
50 50 PORT (
51 51 clk100MHz : IN STD_ULOGIC;
52 52 clk49_152MHz : IN STD_ULOGIC;
53 53 reset : IN STD_ULOGIC;
54 54
55 55 -- TAG --------------------------------------------------------------------
56 56 TAG1 : IN STD_ULOGIC; -- DSU rx data
57 57 TAG3 : OUT STD_ULOGIC; -- DSU tx data
58 58 -- UART APB ---------------------------------------------------------------
59 59 TAG2 : IN STD_ULOGIC; -- UART1 rx data
60 60 TAG4 : OUT STD_ULOGIC; -- UART1 tx data
61 61 -- RAM --------------------------------------------------------------------
62 62 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
63 63 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
64 64 nSRAM_BE0 : OUT STD_LOGIC;
65 65 nSRAM_BE1 : OUT STD_LOGIC;
66 66 nSRAM_BE2 : OUT STD_LOGIC;
67 67 nSRAM_BE3 : OUT STD_LOGIC;
68 68 nSRAM_WE : OUT STD_LOGIC;
69 69 nSRAM_CE : OUT STD_LOGIC;
70 70 nSRAM_OE : OUT STD_LOGIC;
71 71 -- SPW --------------------------------------------------------------------
72 72 spw1_din : IN STD_LOGIC;
73 73 spw1_sin : IN STD_LOGIC;
74 74 spw1_dout : OUT STD_LOGIC;
75 75 spw1_sout : OUT STD_LOGIC;
76 76 spw2_din : IN STD_LOGIC;
77 77 spw2_sin : IN STD_LOGIC;
78 78 spw2_dout : OUT STD_LOGIC;
79 79 spw2_sout : OUT STD_LOGIC;
80 80 -- ADC --------------------------------------------------------------------
81 81 bias_fail_sw : OUT STD_LOGIC;
82 82 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
83 83 ADC_smpclk : OUT STD_LOGIC;
84 84 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
85 85 ---------------------------------------------------------------------------
86 86 TAG8 : OUT STD_LOGIC;
87 87 led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
88 88 );
89 89
90 90 END LFR_em;
91 91
92 92
93 93 ARCHITECTURE beh OF LFR_em IS
94 94 SIGNAL clk_50_s : STD_LOGIC := '0';
95 95 SIGNAL clk_25 : STD_LOGIC := '0';
96 96 SIGNAL clk_24 : STD_LOGIC := '0';
97 97 -----------------------------------------------------------------------------
98 98 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
99 99 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
100 100
101 101 -- CONSTANTS
102 102 CONSTANT CFG_PADTECH : INTEGER := inferred;
103 103 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
104 104 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
105 105 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
106 106
107 107 SIGNAL apbi_ext : apb_slv_in_type;
108 108 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
109 109 SIGNAL ahbi_s_ext : ahb_slv_in_type;
110 110 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
111 111 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
112 112 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
113 113
114 114 -- Spacewire signals
115 115 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
116 116 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
117 117 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
118 118 SIGNAL spw_rxtxclk : STD_ULOGIC;
119 119 SIGNAL spw_rxclkn : STD_ULOGIC;
120 120 SIGNAL spw_clk : STD_LOGIC;
121 121 SIGNAL swni : grspw_in_type;
122 122 SIGNAL swno : grspw_out_type;
123 123
124 124 --GPIO
125 125 SIGNAL gpioi : gpio_in_type;
126 126 SIGNAL gpioo : gpio_out_type;
127 127
128 128 -- AD Converter ADS7886
129 129 SIGNAL sample : Samples14v(7 DOWNTO 0);
130 130 SIGNAL sample_s : Samples(7 DOWNTO 0);
131 131 SIGNAL sample_val : STD_LOGIC;
132 132 SIGNAL ADC_nCS_sig : STD_LOGIC;
133 133 SIGNAL ADC_CLK_sig : STD_LOGIC;
134 134 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
135 135
136 136 -----------------------------------------------------------------------------
137 137 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
138 138
139 139 -----------------------------------------------------------------------------
140 140 SIGNAL rstn : STD_LOGIC;
141
141
142 SIGNAL LFR_soft_rstn : STD_LOGIC;
143 SIGNAL LFR_rstn : STD_LOGIC;
144
142 145 SIGNAL ADC_smpclk_s : STD_LOGIC;
143 146
144 147 BEGIN -- beh
145 148
146 149 -----------------------------------------------------------------------------
147 150 -- CLK
148 151 -----------------------------------------------------------------------------
149 152 rst0 : rstgen PORT MAP (reset, clk_25, '1', rstn, OPEN);
150 153
151 154 PROCESS(clk100MHz)
152 155 BEGIN
153 156 IF clk100MHz'EVENT AND clk100MHz = '1' THEN
154 157 clk_50_s <= NOT clk_50_s;
155 158 END IF;
156 159 END PROCESS;
157 160
158 161 PROCESS(clk_50_s)
159 162 BEGIN
160 163 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
161 164 clk_25 <= NOT clk_25;
162 165 END IF;
163 166 END PROCESS;
164 167
165 168 PROCESS(clk49_152MHz)
166 169 BEGIN
167 170 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
168 171 clk_24 <= NOT clk_24;
169 172 END IF;
170 173 END PROCESS;
171 174
172 175 -----------------------------------------------------------------------------
173 176
174 177 PROCESS (clk_25, rstn)
175 178 BEGIN -- PROCESS
176 179 IF rstn = '0' THEN -- asynchronous reset (active low)
177 180 led(0) <= '0';
178 181 led(1) <= '0';
179 182 led(2) <= '0';
180 183 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
181 184 led(0) <= '0';
182 185 led(1) <= '1';
183 186 led(2) <= '1';
184 187 END IF;
185 188 END PROCESS;
186 189
187 190 --
188 191 leon3_soc_1 : leon3_soc
189 192 GENERIC MAP (
190 193 fabtech => apa3e,
191 194 memtech => apa3e,
192 195 padtech => inferred,
193 196 clktech => inferred,
194 197 disas => 0,
195 198 dbguart => 0,
196 199 pclow => 2,
197 200 clk_freq => 25000,
198 201 NB_CPU => 1,
199 202 ENABLE_FPU => 1,
200 203 FPU_NETLIST => 0,
201 204 ENABLE_DSU => 1,
202 205 ENABLE_AHB_UART => 1,
203 206 ENABLE_APB_UART => 1,
204 207 ENABLE_IRQMP => 1,
205 208 ENABLE_GPT => 1,
206 209 NB_AHB_MASTER => NB_AHB_MASTER,
207 210 NB_AHB_SLAVE => NB_AHB_SLAVE,
208 211 NB_APB_SLAVE => NB_APB_SLAVE)
209 212 PORT MAP (
210 213 clk => clk_25,
211 214 reset => rstn,
212 215 errorn => OPEN,
213 216
214 217 ahbrxd => TAG1,
215 218 ahbtxd => TAG3,
216 219 urxd1 => TAG2,
217 220 utxd1 => TAG4,
218 221
219 222 address => address,
220 223 data => data,
221 224 nSRAM_BE0 => nSRAM_BE0,
222 225 nSRAM_BE1 => nSRAM_BE1,
223 226 nSRAM_BE2 => nSRAM_BE2,
224 227 nSRAM_BE3 => nSRAM_BE3,
225 228 nSRAM_WE => nSRAM_WE,
226 229 nSRAM_CE => nSRAM_CE,
227 230 nSRAM_OE => nSRAM_OE,
228 231
229 232 apbi_ext => apbi_ext,
230 233 apbo_ext => apbo_ext,
231 234 ahbi_s_ext => ahbi_s_ext,
232 235 ahbo_s_ext => ahbo_s_ext,
233 236 ahbi_m_ext => ahbi_m_ext,
234 237 ahbo_m_ext => ahbo_m_ext);
235 238
236 239
237 240 -------------------------------------------------------------------------------
238 241 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
239 242 -------------------------------------------------------------------------------
240 243 apb_lfr_time_management_1 : apb_lfr_time_management
241 244 GENERIC MAP (
242 245 pindex => 6,
243 246 paddr => 6,
244 247 pmask => 16#fff#,
245 248 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
246 249 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
247 250 PORT MAP (
248 251 clk25MHz => clk_25,
249 252 clk24_576MHz => clk_24, -- 49.152MHz/2
250 253 resetn => rstn,
251 254 grspw_tick => swno.tickout,
252 255 apbi => apbi_ext,
253 256 apbo => apbo_ext(6),
254 257 coarse_time => coarse_time,
255 fine_time => fine_time);
258 fine_time => fine_time,
259 LFR_soft_rstn => LFR_soft_rstn
260 );
256 261
257 262 -----------------------------------------------------------------------
258 263 --- SpaceWire --------------------------------------------------------
259 264 -----------------------------------------------------------------------
260 265
261 266 -- SPW_EN <= '1';
262 267
263 268 spw_clk <= clk_50_s;
264 269 spw_rxtxclk <= spw_clk;
265 270 spw_rxclkn <= NOT spw_rxtxclk;
266 271
267 272 -- PADS for SPW1
268 273 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
269 274 PORT MAP (spw1_din, dtmp(0));
270 275 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
271 276 PORT MAP (spw1_sin, stmp(0));
272 277 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
273 278 PORT MAP (spw1_dout, swno.d(0));
274 279 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
275 280 PORT MAP (spw1_sout, swno.s(0));
276 281 -- PADS FOR SPW2
277 282 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
278 283 PORT MAP (spw2_din, dtmp(1));
279 284 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
280 285 PORT MAP (spw2_sin, stmp(1));
281 286 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
282 287 PORT MAP (spw2_dout, swno.d(1));
283 288 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
284 289 PORT MAP (spw2_sout, swno.s(1));
285 290
286 291 -- GRSPW PHY
287 292 --spw1_input: if CFG_SPW_GRSPW = 1 generate
288 293 spw_inputloop : FOR j IN 0 TO 1 GENERATE
289 294 spw_phy0 : grspw_phy
290 295 GENERIC MAP(
291 296 tech => apa3e,
292 297 rxclkbuftype => 1,
293 298 scantest => 0)
294 299 PORT MAP(
295 300 rxrst => swno.rxrst,
296 301 di => dtmp(j),
297 302 si => stmp(j),
298 303 rxclko => spw_rxclk(j),
299 304 do => swni.d(j),
300 305 ndo => swni.nd(j*5+4 DOWNTO j*5),
301 306 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
302 307 END GENERATE spw_inputloop;
303 308
304 309 -- SPW core
305 310 sw0 : grspwm GENERIC MAP(
306 311 tech => apa3e,
307 312 hindex => 1,
308 313 pindex => 5,
309 314 paddr => 5,
310 315 pirq => 11,
311 316 sysfreq => 25000, -- CPU_FREQ
312 317 rmap => 1,
313 318 rmapcrc => 1,
314 319 fifosize1 => 16,
315 320 fifosize2 => 16,
316 321 rxclkbuftype => 1,
317 322 rxunaligned => 0,
318 323 rmapbufs => 4,
319 324 ft => 0,
320 325 netlist => 0,
321 326 ports => 2,
322 327 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
323 328 memtech => apa3e,
324 329 destkey => 2,
325 330 spwcore => 1
326 331 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
327 332 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
328 333 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
329 334 )
330 335 PORT MAP(rstn, clk_25, spw_rxclk(0),
331 336 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
332 337 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
333 338 swni, swno);
334 339
335 340 swni.tickin <= '0';
336 341 swni.rmapen <= '1';
337 342 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
338 343 swni.tickinraw <= '0';
339 344 swni.timein <= (OTHERS => '0');
340 345 swni.dcrstval <= (OTHERS => '0');
341 346 swni.timerrstval <= (OTHERS => '0');
342 347
343 348 -------------------------------------------------------------------------------
344 349 -- LFR ------------------------------------------------------------------------
345 350 -------------------------------------------------------------------------------
351 LFR_rstn <= LFR_soft_rstn AND rstn;
352
346 353 lpp_lfr_1 : lpp_lfr
347 354 GENERIC MAP (
348 355 Mem_use => use_RAM,
349 356 nb_data_by_buffer_size => 32,
350 357 --nb_word_by_buffer_size => 30,
351 358 nb_snapshot_param_size => 32,
352 359 delta_vector_size => 32,
353 360 delta_vector_size_f0_2 => 7, -- log2(96)
354 361 pindex => 15,
355 362 paddr => 15,
356 363 pmask => 16#fff#,
357 364 pirq_ms => 6,
358 365 pirq_wfp => 14,
359 366 hindex => 2,
360 top_lfr_version => X"010121") -- aa.bb.cc version
367 top_lfr_version => X"010122") -- aa.bb.cc version
361 368 -- AA : BOARD NUMBER
362 369 -- 0 => MINI_LFR
363 370 -- 1 => EM
364 371 PORT MAP (
365 372 clk => clk_25,
366 rstn => rstn,
373 rstn => LFR_rstn,
367 374 sample_B => sample_s(2 DOWNTO 0),
368 375 sample_E => sample_s(7 DOWNTO 3),
369 376 sample_val => sample_val,
370 377 apbi => apbi_ext,
371 378 apbo => apbo_ext(15),
372 379 ahbi => ahbi_m_ext,
373 380 ahbo => ahbo_m_ext(2),
374 381 coarse_time => coarse_time,
375 382 fine_time => fine_time,
376 383 data_shaping_BW => bias_fail_sw);--,
377 384 --observation_vector_0 => OPEN,
378 385 --observation_vector_1 => OPEN,
379 386 --observation_reg => observation_reg);
380 387
381 388
382 389 all_sample: FOR I IN 7 DOWNTO 0 GENERATE
383 390 sample_s(I) <= sample(I) & '0' & '0';
384 391 END GENERATE all_sample;
385 392
386 393 -----------------------------------------------------------------------------
387 394 --
388 395 -----------------------------------------------------------------------------
389 396 top_ad_conv_RHF1401_withFilter_1: top_ad_conv_RHF1401_withFilter
390 397 GENERIC MAP (
391 398 ChanelCount => 8,
392 399 ncycle_cnv_high => 13,
393 400 ncycle_cnv => 25)
394 401 PORT MAP (
395 402 cnv_clk => clk_24,
396 403 cnv_rstn => rstn,
397 404 cnv => ADC_smpclk_s,
398 405 clk => clk_25,
399 406 rstn => rstn,
400 407 ADC_data => ADC_data,
401 408 ADC_nOE => ADC_OEB_bar_CH,
402 409 sample => sample,
403 410 sample_val => sample_val);
404 411
405 412
406 413
407 414
408 415 --top_ad_conv_RHF1401_1 : top_ad_conv_RHF1401
409 416 -- GENERIC MAP (
410 417 -- ChanelCount => 8,
411 418 -- ncycle_cnv_high => 40, -- TODO : 79
412 419 -- ncycle_cnv => 250) -- TODO : 500
413 420 -- PORT MAP (
414 421 -- cnv_clk => clk_24, -- TODO : 49.152
415 422 -- cnv_rstn => rstn, -- ok
416 423 -- cnv => ADC_smpclk_s, -- ok
417 424 -- clk => clk_25, -- ok
418 425 -- rstn => rstn, -- ok
419 426 -- ADC_data => ADC_data, -- ok
420 427 -- ADC_nOE => ADC_OEB_bar_CH, -- ok
421 428 -- sample => sample, -- ok
422 429 -- sample_val => sample_val); -- ok
423 430
424 431 ADC_smpclk <= ADC_smpclk_s;
425 432
426 433 TAG8 <= ADC_smpclk_s;
427 434
428 435 END beh;
Show file before | Show file after | Hide comments
@@ -1,691 +1,698
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -------------------------------------------------------------------------------
22 22 LIBRARY IEEE;
23 23 USE IEEE.numeric_std.ALL;
24 24 USE IEEE.std_logic_1164.ALL;
25 25 LIBRARY grlib;
26 26 USE grlib.amba.ALL;
27 27 USE grlib.stdlib.ALL;
28 28 LIBRARY techmap;
29 29 USE techmap.gencomp.ALL;
30 30 LIBRARY gaisler;
31 31 USE gaisler.memctrl.ALL;
32 32 USE gaisler.leon3.ALL;
33 33 USE gaisler.uart.ALL;
34 34 USE gaisler.misc.ALL;
35 35 USE gaisler.spacewire.ALL;
36 36 LIBRARY esa;
37 37 USE esa.memoryctrl.ALL;
38 38 LIBRARY lpp;
39 39 USE lpp.lpp_memory.ALL;
40 40 USE lpp.lpp_ad_conv.ALL;
41 41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 43 USE lpp.iir_filter.ALL;
44 44 USE lpp.general_purpose.ALL;
45 45 USE lpp.lpp_lfr_time_management.ALL;
46 46 USE lpp.lpp_leon3_soc_pkg.ALL;
47 47
48 48 ENTITY MINI_LFR_top IS
49 49
50 50 PORT (
51 51 clk_50 : IN STD_LOGIC;
52 52 clk_49 : IN STD_LOGIC;
53 53 reset : IN STD_LOGIC;
54 54 --BPs
55 55 BP0 : IN STD_LOGIC;
56 56 BP1 : IN STD_LOGIC;
57 57 --LEDs
58 58 LED0 : OUT STD_LOGIC;
59 59 LED1 : OUT STD_LOGIC;
60 60 LED2 : OUT STD_LOGIC;
61 61 --UARTs
62 62 TXD1 : IN STD_LOGIC;
63 63 RXD1 : OUT STD_LOGIC;
64 64 nCTS1 : OUT STD_LOGIC;
65 65 nRTS1 : IN STD_LOGIC;
66 66
67 67 TXD2 : IN STD_LOGIC;
68 68 RXD2 : OUT STD_LOGIC;
69 69 nCTS2 : OUT STD_LOGIC;
70 70 nDTR2 : IN STD_LOGIC;
71 71 nRTS2 : IN STD_LOGIC;
72 72 nDCD2 : OUT STD_LOGIC;
73 73
74 74 --EXT CONNECTOR
75 75 IO0 : INOUT STD_LOGIC;
76 76 IO1 : INOUT STD_LOGIC;
77 77 IO2 : INOUT STD_LOGIC;
78 78 IO3 : INOUT STD_LOGIC;
79 79 IO4 : INOUT STD_LOGIC;
80 80 IO5 : INOUT STD_LOGIC;
81 81 IO6 : INOUT STD_LOGIC;
82 82 IO7 : INOUT STD_LOGIC;
83 83 IO8 : INOUT STD_LOGIC;
84 84 IO9 : INOUT STD_LOGIC;
85 85 IO10 : INOUT STD_LOGIC;
86 86 IO11 : INOUT STD_LOGIC;
87 87
88 88 --SPACE WIRE
89 89 SPW_EN : OUT STD_LOGIC; -- 0 => off
90 90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
91 91 SPW_NOM_SIN : IN STD_LOGIC;
92 92 SPW_NOM_DOUT : OUT STD_LOGIC;
93 93 SPW_NOM_SOUT : OUT STD_LOGIC;
94 94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
95 95 SPW_RED_SIN : IN STD_LOGIC;
96 96 SPW_RED_DOUT : OUT STD_LOGIC;
97 97 SPW_RED_SOUT : OUT STD_LOGIC;
98 98 -- MINI LFR ADC INPUTS
99 99 ADC_nCS : OUT STD_LOGIC;
100 100 ADC_CLK : OUT STD_LOGIC;
101 101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
102 102
103 103 -- SRAM
104 104 SRAM_nWE : OUT STD_LOGIC;
105 105 SRAM_CE : OUT STD_LOGIC;
106 106 SRAM_nOE : OUT STD_LOGIC;
107 107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
108 108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
109 109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
110 110 );
111 111
112 112 END MINI_LFR_top;
113 113
114 114
115 115 ARCHITECTURE beh OF MINI_LFR_top IS
116 116 SIGNAL clk_50_s : STD_LOGIC := '0';
117 117 SIGNAL clk_25 : STD_LOGIC := '0';
118 118 SIGNAL clk_24 : STD_LOGIC := '0';
119 119 -----------------------------------------------------------------------------
120 120 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
121 121 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
122 122 --
123 123 SIGNAL errorn : STD_LOGIC;
124 124 -- UART AHB ---------------------------------------------------------------
125 SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
126 SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
125 -- SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
126 -- SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
127 127
128 128 -- UART APB ---------------------------------------------------------------
129 SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
130 SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
129 -- SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
130 -- SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
131 131 --
132 132 SIGNAL I00_s : STD_LOGIC;
133 133
134 134 -- CONSTANTS
135 135 CONSTANT CFG_PADTECH : INTEGER := inferred;
136 136 --
137 137 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
138 138 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
139 139 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
140 140
141 141 SIGNAL apbi_ext : apb_slv_in_type;
142 142 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5);-- := (OTHERS => apb_none);
143 143 SIGNAL ahbi_s_ext : ahb_slv_in_type;
144 144 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3);-- := (OTHERS => ahbs_none);
145 145 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
146 146 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1);-- := (OTHERS => ahbm_none);
147 147
148 148 -- Spacewire signals
149 149 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 150 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
151 151 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
152 152 SIGNAL spw_rxtxclk : STD_ULOGIC;
153 153 SIGNAL spw_rxclkn : STD_ULOGIC;
154 154 SIGNAL spw_clk : STD_LOGIC;
155 155 SIGNAL swni : grspw_in_type;
156 156 SIGNAL swno : grspw_out_type;
157 157 -- SIGNAL clkmn : STD_ULOGIC;
158 158 -- SIGNAL txclk : STD_ULOGIC;
159 159
160 160 --GPIO
161 161 SIGNAL gpioi : gpio_in_type;
162 162 SIGNAL gpioo : gpio_out_type;
163 163
164 164 -- AD Converter ADS7886
165 165 SIGNAL sample : Samples14v(7 DOWNTO 0);
166 166 SIGNAL sample_s : Samples(7 DOWNTO 0);
167 167 SIGNAL sample_val : STD_LOGIC;
168 168 SIGNAL ADC_nCS_sig : STD_LOGIC;
169 169 SIGNAL ADC_CLK_sig : STD_LOGIC;
170 170 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
171 171
172 172 SIGNAL bias_fail_sw_sig : STD_LOGIC;
173 173
174 174 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
175 175 SIGNAL observation_vector_0: STD_LOGIC_VECTOR(11 DOWNTO 0);
176 176 SIGNAL observation_vector_1: STD_LOGIC_VECTOR(11 DOWNTO 0);
177 177 -----------------------------------------------------------------------------
178 178
179 179 SIGNAL LFR_soft_rstn : STD_LOGIC;
180 180 SIGNAL LFR_rstn : STD_LOGIC;
181 181
182 182
183 183 SIGNAL rstn_25 : STD_LOGIC;
184 184 SIGNAL rstn_25_d1 : STD_LOGIC;
185 185 SIGNAL rstn_25_d2 : STD_LOGIC;
186 186 SIGNAL rstn_25_d3 : STD_LOGIC;
187 187
188 188 SIGNAL rstn_50 : STD_LOGIC;
189 189 SIGNAL rstn_50_d1 : STD_LOGIC;
190 190 SIGNAL rstn_50_d2 : STD_LOGIC;
191 191 SIGNAL rstn_50_d3 : STD_LOGIC;
192 192 BEGIN -- beh
193 193
194 194 -----------------------------------------------------------------------------
195 195 -- CLK
196 196 -----------------------------------------------------------------------------
197 197
198 198 --PROCESS(clk_50)
199 199 --BEGIN
200 200 -- IF clk_50'EVENT AND clk_50 = '1' THEN
201 201 -- clk_50_s <= NOT clk_50_s;
202 202 -- END IF;
203 203 --END PROCESS;
204 204
205 205 --PROCESS(clk_50_s)
206 206 --BEGIN
207 207 -- IF clk_50_s'EVENT AND clk_50_s = '1' THEN
208 208 -- clk_25 <= NOT clk_25;
209 209 -- END IF;
210 210 --END PROCESS;
211 211
212 212 --PROCESS(clk_49)
213 213 --BEGIN
214 214 -- IF clk_49'EVENT AND clk_49 = '1' THEN
215 215 -- clk_24 <= NOT clk_24;
216 216 -- END IF;
217 217 --END PROCESS;
218 218
219 219 --PROCESS(clk_25)
220 220 --BEGIN
221 221 -- IF clk_25'EVENT AND clk_25 = '1' THEN
222 222 -- rstn_25 <= reset;
223 223 -- END IF;
224 224 --END PROCESS;
225 225
226 226 PROCESS (clk_50, reset)
227 227 BEGIN -- PROCESS
228 228 IF reset = '0' THEN -- asynchronous reset (active low)
229 229 clk_50_s <= '0';
230 230 rstn_50 <= '0';
231 231 rstn_50_d1 <= '0';
232 232 rstn_50_d2 <= '0';
233 233 rstn_50_d3 <= '0';
234 234
235 235 ELSIF clk_50'event AND clk_50 = '1' THEN -- rising clock edge
236 236 clk_50_s <= NOT clk_50_s;
237 237 rstn_50_d1 <= '1';
238 238 rstn_50_d2 <= rstn_50_d1;
239 239 rstn_50_d3 <= rstn_50_d2;
240 240 rstn_50 <= rstn_50_d3;
241 241 END IF;
242 242 END PROCESS;
243 243
244 244 PROCESS (clk_50_s, rstn_50)
245 245 BEGIN -- PROCESS
246 246 IF rstn_50 = '0' THEN -- asynchronous reset (active low)
247 247 clk_25 <= '0';
248 248 rstn_25 <= '0';
249 249 rstn_25_d1 <= '0';
250 250 rstn_25_d2 <= '0';
251 251 rstn_25_d3 <= '0';
252 252 ELSIF clk_50_s'event AND clk_50_s = '1' THEN -- rising clock edge
253 253 clk_25 <= NOT clk_25;
254 254 rstn_25_d1 <= '1';
255 255 rstn_25_d2 <= rstn_25_d1;
256 256 rstn_25_d3 <= rstn_25_d2;
257 257 rstn_25 <= rstn_25_d3;
258 258 END IF;
259 259 END PROCESS;
260 260
261 261 PROCESS (clk_49, reset)
262 262 BEGIN -- PROCESS
263 263 IF reset = '0' THEN -- asynchronous reset (active low)
264 264 clk_24 <= '0';
265 265 ELSIF clk_49'event AND clk_49 = '1' THEN -- rising clock edge
266 266 clk_24 <= NOT clk_24;
267 267 END IF;
268 268 END PROCESS;
269 269
270 270 -----------------------------------------------------------------------------
271 271
272 272 PROCESS (clk_25, rstn_25)
273 273 BEGIN -- PROCESS
274 274 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
275 275 LED0 <= '0';
276 276 LED1 <= '0';
277 277 LED2 <= '0';
278 278 --IO1 <= '0';
279 279 --IO2 <= '1';
280 280 --IO3 <= '0';
281 281 --IO4 <= '0';
282 282 --IO5 <= '0';
283 283 --IO6 <= '0';
284 284 --IO7 <= '0';
285 285 --IO8 <= '0';
286 286 --IO9 <= '0';
287 287 --IO10 <= '0';
288 288 --IO11 <= '0';
289 289 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
290 290 LED0 <= '0';
291 291 LED1 <= '1';
292 292 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
293 293 --IO1 <= '1';
294 294 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
295 295 --IO3 <= ADC_SDO(0);
296 296 --IO4 <= ADC_SDO(1);
297 297 --IO5 <= ADC_SDO(2);
298 298 --IO6 <= ADC_SDO(3);
299 299 --IO7 <= ADC_SDO(4);
300 300 --IO8 <= ADC_SDO(5);
301 301 --IO9 <= ADC_SDO(6);
302 302 --IO10 <= ADC_SDO(7);
303 303 --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
304 304 END IF;
305 305 END PROCESS;
306 306
307 307 PROCESS (clk_24, rstn_25)
308 308 BEGIN -- PROCESS
309 309 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
310 310 I00_s <= '0';
311 311 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
312 312 I00_s <= NOT I00_s ;
313 313 END IF;
314 314 END PROCESS;
315 315 -- IO0 <= I00_s;
316 316
317 317 --UARTs
318 318 nCTS1 <= '1';
319 319 nCTS2 <= '1';
320 320 nDCD2 <= '1';
321 321
322 322 --EXT CONNECTOR
323 323
324 324 --SPACE WIRE
325 325
326 326 leon3_soc_1 : leon3_soc
327 327 GENERIC MAP (
328 328 fabtech => apa3e,
329 329 memtech => apa3e,
330 330 padtech => inferred,
331 331 clktech => inferred,
332 332 disas => 0,
333 333 dbguart => 0,
334 334 pclow => 2,
335 335 clk_freq => 25000,
336 336 NB_CPU => 1,
337 337 ENABLE_FPU => 1,
338 338 FPU_NETLIST => 0,
339 339 ENABLE_DSU => 1,
340 340 ENABLE_AHB_UART => 1,
341 341 ENABLE_APB_UART => 1,
342 342 ENABLE_IRQMP => 1,
343 343 ENABLE_GPT => 1,
344 344 NB_AHB_MASTER => NB_AHB_MASTER,
345 345 NB_AHB_SLAVE => NB_AHB_SLAVE,
346 346 NB_APB_SLAVE => NB_APB_SLAVE,
347 347 ADDRESS_SIZE => 20)
348 348 PORT MAP (
349 349 clk => clk_25,
350 350 reset => rstn_25,
351 351 errorn => errorn,
352 352 ahbrxd => TXD1,
353 353 ahbtxd => RXD1,
354 354 urxd1 => TXD2,
355 355 utxd1 => RXD2,
356 356 address => SRAM_A,
357 357 data => SRAM_DQ,
358 358 nSRAM_BE0 => SRAM_nBE(0),
359 359 nSRAM_BE1 => SRAM_nBE(1),
360 360 nSRAM_BE2 => SRAM_nBE(2),
361 361 nSRAM_BE3 => SRAM_nBE(3),
362 362 nSRAM_WE => SRAM_nWE,
363 363 nSRAM_CE => SRAM_CE,
364 364 nSRAM_OE => SRAM_nOE,
365 365
366 366 apbi_ext => apbi_ext,
367 367 apbo_ext => apbo_ext,
368 368 ahbi_s_ext => ahbi_s_ext,
369 369 ahbo_s_ext => ahbo_s_ext,
370 370 ahbi_m_ext => ahbi_m_ext,
371 371 ahbo_m_ext => ahbo_m_ext);
372 372
373 373 -------------------------------------------------------------------------------
374 374 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
375 375 -------------------------------------------------------------------------------
376 376 apb_lfr_time_management_1 : apb_lfr_time_management
377 377 GENERIC MAP (
378 378 pindex => 6,
379 379 paddr => 6,
380 380 pmask => 16#fff#,
381 381 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
382 382 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
383 383 PORT MAP (
384 384 clk25MHz => clk_25,
385 385 clk24_576MHz => clk_24, -- 49.152MHz/2
386 386 resetn => rstn_25,
387 387 grspw_tick => swno.tickout,
388 388 apbi => apbi_ext,
389 389 apbo => apbo_ext(6),
390 390 coarse_time => coarse_time,
391 391 fine_time => fine_time,
392 392 LFR_soft_rstn => LFR_soft_rstn
393 393 );
394 394
395 395 -----------------------------------------------------------------------
396 396 --- SpaceWire --------------------------------------------------------
397 397 -----------------------------------------------------------------------
398 398
399 399 SPW_EN <= '1';
400 400
401 401 spw_clk <= clk_50_s;
402 402 spw_rxtxclk <= spw_clk;
403 403 spw_rxclkn <= NOT spw_rxtxclk;
404 404
405 405 -- PADS for SPW1
406 406 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
407 407 PORT MAP (SPW_NOM_DIN, dtmp(0));
408 408 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
409 409 PORT MAP (SPW_NOM_SIN, stmp(0));
410 410 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
411 411 PORT MAP (SPW_NOM_DOUT, swno.d(0));
412 412 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
413 413 PORT MAP (SPW_NOM_SOUT, swno.s(0));
414 414 -- PADS FOR SPW2
415 415 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
416 416 PORT MAP (SPW_RED_SIN, dtmp(1));
417 417 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
418 418 PORT MAP (SPW_RED_DIN, stmp(1));
419 419 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
420 420 PORT MAP (SPW_RED_DOUT, swno.d(1));
421 421 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
422 422 PORT MAP (SPW_RED_SOUT, swno.s(1));
423 423
424 424 -- GRSPW PHY
425 425 --spw1_input: if CFG_SPW_GRSPW = 1 generate
426 426 spw_inputloop : FOR j IN 0 TO 1 GENERATE
427 427 spw_phy0 : grspw_phy
428 428 GENERIC MAP(
429 429 tech => apa3e,
430 430 rxclkbuftype => 1,
431 431 scantest => 0)
432 432 PORT MAP(
433 433 rxrst => swno.rxrst,
434 434 di => dtmp(j),
435 435 si => stmp(j),
436 436 rxclko => spw_rxclk(j),
437 437 do => swni.d(j),
438 438 ndo => swni.nd(j*5+4 DOWNTO j*5),
439 439 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
440 440 END GENERATE spw_inputloop;
441 441
442 swni.rmapnodeaddr <= (others => '0');
443
442 444 -- SPW core
443 445 sw0 : grspwm GENERIC MAP(
444 446 tech => apa3e,
445 447 hindex => 1,
446 448 pindex => 5,
447 449 paddr => 5,
448 450 pirq => 11,
449 451 sysfreq => 25000, -- CPU_FREQ
450 452 rmap => 1,
451 453 rmapcrc => 1,
452 454 fifosize1 => 16,
453 455 fifosize2 => 16,
454 456 rxclkbuftype => 1,
455 457 rxunaligned => 0,
456 458 rmapbufs => 4,
457 459 ft => 0,
458 460 netlist => 0,
459 461 ports => 2,
460 462 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
461 463 memtech => apa3e,
462 464 destkey => 2,
463 465 spwcore => 1
464 466 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
465 467 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
466 468 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
467 469 )
468 470 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
469 471 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
470 472 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
471 473 swni, swno);
472 474
473 475 swni.tickin <= '0';
474 476 swni.rmapen <= '1';
475 477 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
476 478 swni.tickinraw <= '0';
477 479 swni.timein <= (OTHERS => '0');
478 480 swni.dcrstval <= (OTHERS => '0');
479 481 swni.timerrstval <= (OTHERS => '0');
480 482
481 483 -------------------------------------------------------------------------------
482 484 -- LFR ------------------------------------------------------------------------
483 485 -------------------------------------------------------------------------------
484 486
485 487
486 488 --LFR_rstn <= LFR_soft_rstn AND rstn_25;
487 489 LFR_rstn <= rstn_25;
488 490
489 491 lpp_lfr_1 : lpp_lfr
490 492 GENERIC MAP (
491 493 Mem_use => use_RAM,
492 494 nb_data_by_buffer_size => 32,
493 495 nb_snapshot_param_size => 32,
494 496 delta_vector_size => 32,
495 497 delta_vector_size_f0_2 => 7, -- log2(96)
496 498 pindex => 15,
497 499 paddr => 15,
498 500 pmask => 16#fff#,
499 501 pirq_ms => 6,
500 502 pirq_wfp => 14,
501 503 hindex => 2,
502 504 top_lfr_version => X"000122") -- aa.bb.cc version
503 505 PORT MAP (
504 506 clk => clk_25,
505 507 rstn => LFR_rstn,
506 508 sample_B => sample_s(2 DOWNTO 0),
507 509 sample_E => sample_s(7 DOWNTO 3),
508 510 sample_val => sample_val,
509 511 apbi => apbi_ext,
510 512 apbo => apbo_ext(15),
511 513 ahbi => ahbi_m_ext,
512 514 ahbo => ahbo_m_ext(2),
513 515 coarse_time => coarse_time,
514 516 fine_time => fine_time,
515 517 data_shaping_BW => bias_fail_sw_sig);
516 518
519 observation_reg <= (others => '0');
520 observation_vector_0 <= (others => '0');
521 observation_vector_1 <= (others => '0');
522
517 523 all_sample: FOR I IN 7 DOWNTO 0 GENERATE
518 524 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
519 525 END GENERATE all_sample;
520 526
521
522
523 527 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
524 528 GENERIC MAP(
525 529 ChannelCount => 8,
526 530 SampleNbBits => 14,
527 531 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
528 532 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
529 533 PORT MAP (
530 534 -- CONV
531 535 cnv_clk => clk_24,
532 536 cnv_rstn => rstn_25,
533 537 cnv => ADC_nCS_sig,
534 538 -- DATA
535 539 clk => clk_25,
536 540 rstn => rstn_25,
537 541 sck => ADC_CLK_sig,
538 542 sdo => ADC_SDO_sig,
539 543 -- SAMPLE
540 544 sample => sample,
541 545 sample_val => sample_val);
542 546
543 547 --IO10 <= ADC_SDO_sig(5);
544 548 --IO9 <= ADC_SDO_sig(4);
545 549 --IO8 <= ADC_SDO_sig(3);
546 550
547 551 ADC_nCS <= ADC_nCS_sig;
548 552 ADC_CLK <= ADC_CLK_sig;
549 553 ADC_SDO_sig <= ADC_SDO;
550 554
551 555 ----------------------------------------------------------------------
552 556 --- GPIO -----------------------------------------------------------
553 557 ----------------------------------------------------------------------
554 558
555 559 grgpio0 : grgpio
556 560 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
557 561 PORT MAP(rstn_25, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
558 562
563 gpioi.sig_en <= (others => '0');
564 gpioi.sig_in <= (others => '0');
565 gpioi.din <= (others => '0');
559 566 --pio_pad_0 : iopad
560 567 -- GENERIC MAP (tech => CFG_PADTECH)
561 568 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
562 569 --pio_pad_1 : iopad
563 570 -- GENERIC MAP (tech => CFG_PADTECH)
564 571 -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
565 572 --pio_pad_2 : iopad
566 573 -- GENERIC MAP (tech => CFG_PADTECH)
567 574 -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
568 575 --pio_pad_3 : iopad
569 576 -- GENERIC MAP (tech => CFG_PADTECH)
570 577 -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
571 578 --pio_pad_4 : iopad
572 579 -- GENERIC MAP (tech => CFG_PADTECH)
573 580 -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
574 581 --pio_pad_5 : iopad
575 582 -- GENERIC MAP (tech => CFG_PADTECH)
576 583 -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
577 584 --pio_pad_6 : iopad
578 585 -- GENERIC MAP (tech => CFG_PADTECH)
579 586 -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
580 587 --pio_pad_7 : iopad
581 588 -- GENERIC MAP (tech => CFG_PADTECH)
582 589 -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
583 590
584 591 PROCESS (clk_25, rstn_25)
585 592 BEGIN -- PROCESS
586 593 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
587 594 IO0 <= '0';
588 595 IO1 <= '0';
589 596 IO2 <= '0';
590 597 IO3 <= '0';
591 598 IO4 <= '0';
592 599 IO5 <= '0';
593 600 IO6 <= '0';
594 601 IO7 <= '0';
595 602 IO8 <= '0';
596 603 IO9 <= '0';
597 604 IO10 <= '0';
598 605 IO11 <= '0';
599 606 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
600 607 CASE gpioo.dout(2 DOWNTO 0) IS
601 608 WHEN "011" =>
602 609 IO0 <= observation_reg(0 );
603 610 IO1 <= observation_reg(1 );
604 611 IO2 <= observation_reg(2 );
605 612 IO3 <= observation_reg(3 );
606 613 IO4 <= observation_reg(4 );
607 614 IO5 <= observation_reg(5 );
608 615 IO6 <= observation_reg(6 );
609 616 IO7 <= observation_reg(7 );
610 617 IO8 <= observation_reg(8 );
611 618 IO9 <= observation_reg(9 );
612 619 IO10 <= observation_reg(10);
613 620 IO11 <= observation_reg(11);
614 621 WHEN "001" =>
615 622 IO0 <= observation_reg(0 + 12);
616 623 IO1 <= observation_reg(1 + 12);
617 624 IO2 <= observation_reg(2 + 12);
618 625 IO3 <= observation_reg(3 + 12);
619 626 IO4 <= observation_reg(4 + 12);
620 627 IO5 <= observation_reg(5 + 12);
621 628 IO6 <= observation_reg(6 + 12);
622 629 IO7 <= observation_reg(7 + 12);
623 630 IO8 <= observation_reg(8 + 12);
624 631 IO9 <= observation_reg(9 + 12);
625 632 IO10 <= observation_reg(10 + 12);
626 633 IO11 <= observation_reg(11 + 12);
627 634 WHEN "010" =>
628 635 IO0 <= observation_reg(0 + 12 + 12);
629 636 IO1 <= observation_reg(1 + 12 + 12);
630 637 IO2 <= observation_reg(2 + 12 + 12);
631 638 IO3 <= observation_reg(3 + 12 + 12);
632 639 IO4 <= observation_reg(4 + 12 + 12);
633 640 IO5 <= observation_reg(5 + 12 + 12);
634 641 IO6 <= observation_reg(6 + 12 + 12);
635 642 IO7 <= observation_reg(7 + 12 + 12);
636 643 IO8 <= '0';
637 644 IO9 <= '0';
638 645 IO10 <= '0';
639 646 IO11 <= '0';
640 647 WHEN "000" =>
641 648 IO0 <= observation_vector_0(0 );
642 649 IO1 <= observation_vector_0(1 );
643 650 IO2 <= observation_vector_0(2 );
644 651 IO3 <= observation_vector_0(3 );
645 652 IO4 <= observation_vector_0(4 );
646 653 IO5 <= observation_vector_0(5 );
647 654 IO6 <= observation_vector_0(6 );
648 655 IO7 <= observation_vector_0(7 );
649 656 IO8 <= observation_vector_0(8 );
650 657 IO9 <= observation_vector_0(9 );
651 658 IO10 <= observation_vector_0(10);
652 659 IO11 <= observation_vector_0(11);
653 660 WHEN "100" =>
654 661 IO0 <= observation_vector_1(0 );
655 662 IO1 <= observation_vector_1(1 );
656 663 IO2 <= observation_vector_1(2 );
657 664 IO3 <= observation_vector_1(3 );
658 665 IO4 <= observation_vector_1(4 );
659 666 IO5 <= observation_vector_1(5 );
660 667 IO6 <= observation_vector_1(6 );
661 668 IO7 <= observation_vector_1(7 );
662 669 IO8 <= observation_vector_1(8 );
663 670 IO9 <= observation_vector_1(9 );
664 671 IO10 <= observation_vector_1(10);
665 672 IO11 <= observation_vector_1(11);
666 673 WHEN OTHERS => NULL;
667 674 END CASE;
668 675
669 676 END IF;
670 677 END PROCESS;
671 678 -----------------------------------------------------------------------------
672 679 --
673 680 -----------------------------------------------------------------------------
674 681 all_apbo_ext: FOR I IN NB_APB_SLAVE-1+5 DOWNTO 5 GENERATE
675 682 apbo_ext_not_used: IF I /= 5 AND I /= 6 AND I /= 11 AND I /= 15 GENERATE
676 683 apbo_ext(I) <= apb_none;
677 684 END GENERATE apbo_ext_not_used;
678 685 END GENERATE all_apbo_ext;
679 686
680 687
681 688 all_ahbo_ext: FOR I IN NB_AHB_SLAVE-1+3 DOWNTO 3 GENERATE
682 689 ahbo_s_ext(I) <= ahbs_none;
683 690 END GENERATE all_ahbo_ext;
684 691
685 692 all_ahbo_m_ext: FOR I IN NB_AHB_MASTER-1+1 DOWNTO 1 GENERATE
686 693 ahbo_m_ext_not_used: IF I /=1 AND I /= 2 GENERATE
687 694 ahbo_m_ext(I) <= ahbm_none;
688 695 END GENERATE ahbo_m_ext_not_used;
689 696 END GENERATE all_ahbo_m_ext;
690 697
691 END beh;
698 END beh; No newline at end of file
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@@ -1,270 +1,273
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
3 USE ieee.numeric_std.ALL;
4 use IEEE.std_logic_textio.all;
5 LIBRARY STD;
6 use std.textio.all;
7
8 LIBRARY grlib;
9 USE grlib.stdlib.ALL;
10 LIBRARY gaisler;
11 USE gaisler.libdcom.ALL;
12 USE gaisler.sim.ALL;
13 USE gaisler.jtagtst.ALL;
14 LIBRARY techmap;
15 USE techmap.gencomp.ALL;
16
17 LIBRARY lpp;
18 USE lpp.lpp_sim_pkg.ALL;
19 USE lpp.lpp_lfr_apbreg_pkg.ALL;
20 USE lpp.lpp_lfr_time_management_apbreg_pkg.ALL;
21
22 ENTITY testbench IS
23 END;
24
25 ARCHITECTURE behav OF testbench IS
26
27 COMPONENT MINI_LFR_top
28 PORT (
29 clk_50 : IN STD_LOGIC;
30 clk_49 : IN STD_LOGIC;
31 reset : IN STD_LOGIC;
32 BP0 : IN STD_LOGIC;
33 BP1 : IN STD_LOGIC;
34 LED0 : OUT STD_LOGIC;
35 LED1 : OUT STD_LOGIC;
36 LED2 : OUT STD_LOGIC;
37 TXD1 : IN STD_LOGIC;
38 RXD1 : OUT STD_LOGIC;
39 nCTS1 : OUT STD_LOGIC;
40 nRTS1 : IN STD_LOGIC;
41 TXD2 : IN STD_LOGIC;
42 RXD2 : OUT STD_LOGIC;
43 nCTS2 : OUT STD_LOGIC;
44 nDTR2 : IN STD_LOGIC;
45 nRTS2 : IN STD_LOGIC;
46 nDCD2 : OUT STD_LOGIC;
47 IO0 : INOUT STD_LOGIC;
48 IO1 : INOUT STD_LOGIC;
49 IO2 : INOUT STD_LOGIC;
50 IO3 : INOUT STD_LOGIC;
51 IO4 : INOUT STD_LOGIC;
52 IO5 : INOUT STD_LOGIC;
53 IO6 : INOUT STD_LOGIC;
54 IO7 : INOUT STD_LOGIC;
55 IO8 : INOUT STD_LOGIC;
56 IO9 : INOUT STD_LOGIC;
57 IO10 : INOUT STD_LOGIC;
58 IO11 : INOUT STD_LOGIC;
59 SPW_EN : OUT STD_LOGIC;
60 SPW_NOM_DIN : IN STD_LOGIC;
61 SPW_NOM_SIN : IN STD_LOGIC;
62 SPW_NOM_DOUT : OUT STD_LOGIC;
63 SPW_NOM_SOUT : OUT STD_LOGIC;
64 SPW_RED_DIN : IN STD_LOGIC;
65 SPW_RED_SIN : IN STD_LOGIC;
66 SPW_RED_DOUT : OUT STD_LOGIC;
67 SPW_RED_SOUT : OUT STD_LOGIC;
68 ADC_nCS : OUT STD_LOGIC;
69 ADC_CLK : OUT STD_LOGIC;
70 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
71 SRAM_nWE : OUT STD_LOGIC;
72 SRAM_CE : OUT STD_LOGIC;
73 SRAM_nOE : OUT STD_LOGIC;
74 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
75 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
76 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0));
77 END COMPONENT;
78
79 -----------------------------------------------------------------------------
80 SIGNAL clk_50 : STD_LOGIC := '0';
81 SIGNAL clk_49 : STD_LOGIC := '0';
82 SIGNAL reset : STD_LOGIC;
83 SIGNAL BP0 : STD_LOGIC;
84 SIGNAL BP1 : STD_LOGIC;
85 SIGNAL LED0 : STD_LOGIC;
86 SIGNAL LED1 : STD_LOGIC;
87 SIGNAL LED2 : STD_LOGIC;
88 SIGNAL TXD1 : STD_LOGIC;
89 SIGNAL RXD1 : STD_LOGIC;
90 SIGNAL nCTS1 : STD_LOGIC;
91 SIGNAL nRTS1 : STD_LOGIC;
92 SIGNAL TXD2 : STD_LOGIC;
93 SIGNAL RXD2 : STD_LOGIC;
94 SIGNAL nCTS2 : STD_LOGIC;
95 SIGNAL nDTR2 : STD_LOGIC;
96 SIGNAL nRTS2 : STD_LOGIC;
97 SIGNAL nDCD2 : STD_LOGIC;
98 SIGNAL IO0 : STD_LOGIC;
99 SIGNAL IO1 : STD_LOGIC;
100 SIGNAL IO2 : STD_LOGIC;
101 SIGNAL IO3 : STD_LOGIC;
102 SIGNAL IO4 : STD_LOGIC;
103 SIGNAL IO5 : STD_LOGIC;
104 SIGNAL IO6 : STD_LOGIC;
105 SIGNAL IO7 : STD_LOGIC;
106 SIGNAL IO8 : STD_LOGIC;
107 SIGNAL IO9 : STD_LOGIC;
108 SIGNAL IO10 : STD_LOGIC;
109 SIGNAL IO11 : STD_LOGIC;
110 SIGNAL SPW_EN : STD_LOGIC;
111 SIGNAL SPW_NOM_DIN : STD_LOGIC;
112 SIGNAL SPW_NOM_SIN : STD_LOGIC;
113 SIGNAL SPW_NOM_DOUT : STD_LOGIC;
114 SIGNAL SPW_NOM_SOUT : STD_LOGIC;
115 SIGNAL SPW_RED_DIN : STD_LOGIC;
116 SIGNAL SPW_RED_SIN : STD_LOGIC;
117 SIGNAL SPW_RED_DOUT : STD_LOGIC;
118 SIGNAL SPW_RED_SOUT : STD_LOGIC;
119 SIGNAL ADC_nCS : STD_LOGIC;
120 SIGNAL ADC_CLK : STD_LOGIC;
121 SIGNAL ADC_SDO : STD_LOGIC_VECTOR(7 DOWNTO 0);
122 SIGNAL SRAM_nWE : STD_LOGIC;
123 SIGNAL SRAM_CE : STD_LOGIC;
124 SIGNAL SRAM_nOE : STD_LOGIC;
125 SIGNAL SRAM_nBE : STD_LOGIC_VECTOR(3 DOWNTO 0);
126 SIGNAL SRAM_A : STD_LOGIC_VECTOR(19 DOWNTO 0);
127 SIGNAL SRAM_DQ : STD_LOGIC_VECTOR(31 DOWNTO 0);
128 -----------------------------------------------------------------------------
129
130 CONSTANT ADDR_BASE_LFR : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000F";
131 CONSTANT ADDR_BASE_TIME_MANAGMENT : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"800006";
132 CONSTANT ADDR_BASE_GPIO : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000B";
133
134
135 SIGNAL message_simu : STRING(1 TO 15) := "---------------";
136
137 BEGIN
138
139 -----------------------------------------------------------------------------
140 -- TB
141 -----------------------------------------------------------------------------
142 PROCESS
143 CONSTANT txp : TIME := 320 ns;
144 BEGIN -- PROCESS
145 TXD1 <= '1';
146 reset <= '0';
147 WAIT FOR 500 ns;
148 reset <= '1';
149 WAIT FOR 10000 ns;
150 message_simu <= "0 - UART init ";
151 UART_INIT(TXD1,txp);
152
153 message_simu <= "1 - UART test ";
154 UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000010",X"0000FFFF");
155 UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000001",X"00000A0A");
156 UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000001",X"00000B0B");
157
158 -- UNSET the LFR reset
159 message_simu <= "2 - LFR UNRESET";
160 UART_WRITE(TXD1,txp,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_CONTROL , X"00000000");
161 UART_WRITE(TXD1,txp,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_TIME_LOAD , X"00000000");
162 --
163 message_simu <= "3 - LFR CONFIG ";
164 UART_WRITE(TXD1,txp,ADDR_BASE_LFR & ADDR_LFR_SM_F0_0_ADDR , X"00000B0B");
165
166 WAIT;
167 END PROCESS;
168
169 -----------------------------------------------------------------------------
170 -- CLOCK
171 -----------------------------------------------------------------------------
172 clk_50 <= NOT clk_50 AFTER 5 ns;
173 clk_49 <= NOT clk_49 AFTER 10172 ps;
174
175 -----------------------------------------------------------------------------
176 -- DON'T CARE
177 -----------------------------------------------------------------------------
178 BP0 <= '0';
179 BP1 <= '0';
180 nRTS1 <= '0' ;
181
182 TXD2 <= '1';
183 nRTS2 <= '1';
184 nDTR2 <= '1';
185
186 SPW_NOM_DIN <= '1';
187 SPW_NOM_SIN <= '1';
188 SPW_RED_DIN <= '1';
189 SPW_RED_SIN <= '1';
190
191 ADC_SDO <= x"AA";
192
193 SRAM_DQ <= (OTHERS => 'Z');
194 IO0 <= 'Z';
195 IO1 <= 'Z';
196 IO2 <= 'Z';
197 IO3 <= 'Z';
198 IO4 <= 'Z';
199 IO5 <= 'Z';
200 IO6 <= 'Z';
201 IO7 <= 'Z';
202 IO8 <= 'Z';
203 IO9 <= 'Z';
204 IO10 <= 'Z';
205 IO11 <= 'Z';
206
207 -----------------------------------------------------------------------------
208 -- DUT
209 -----------------------------------------------------------------------------
210 MINI_LFR_top_1: MINI_LFR_top
211 PORT MAP (
212 clk_50 => clk_50,
213 clk_49 => clk_49,
214 reset => reset,
215
216 BP0 => BP0,
217 BP1 => BP1,
218
219 LED0 => LED0,
220 LED1 => LED1,
221 LED2 => LED2,
222
223 TXD1 => TXD1,
224 RXD1 => RXD1,
225 nCTS1 => nCTS1,
226 nRTS1 => nRTS1,
227
228 TXD2 => TXD2,
229 RXD2 => RXD2,
230 nCTS2 => nCTS2,
231 nDTR2 => nDTR2,
232 nRTS2 => nRTS2,
233 nDCD2 => nDCD2,
234
235 IO0 => IO0,
236 IO1 => IO1,
237 IO2 => IO2,
238 IO3 => IO3,
239 IO4 => IO4,
240 IO5 => IO5,
241 IO6 => IO6,
242 IO7 => IO7,
243 IO8 => IO8,
244 IO9 => IO9,
245 IO10 => IO10,
246 IO11 => IO11,
247
248 SPW_EN => SPW_EN,
249 SPW_NOM_DIN => SPW_NOM_DIN,
250 SPW_NOM_SIN => SPW_NOM_SIN,
251 SPW_NOM_DOUT => SPW_NOM_DOUT,
252 SPW_NOM_SOUT => SPW_NOM_SOUT,
253 SPW_RED_DIN => SPW_RED_DIN,
254 SPW_RED_SIN => SPW_RED_SIN,
255 SPW_RED_DOUT => SPW_RED_DOUT,
256 SPW_RED_SOUT => SPW_RED_SOUT,
257
258 ADC_nCS => ADC_nCS,
259 ADC_CLK => ADC_CLK,
260 ADC_SDO => ADC_SDO,
261
262 SRAM_nWE => SRAM_nWE,
263 SRAM_CE => SRAM_CE,
264 SRAM_nOE => SRAM_nOE,
265 SRAM_nBE => SRAM_nBE,
266 SRAM_A => SRAM_A,
267 SRAM_DQ => SRAM_DQ);
268
269
270 END;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
3 USE ieee.numeric_std.ALL;
4 use IEEE.std_logic_textio.all;
5 LIBRARY STD;
6 use std.textio.all;
7
8 LIBRARY grlib;
9 USE grlib.stdlib.ALL;
10 LIBRARY gaisler;
11 USE gaisler.libdcom.ALL;
12 USE gaisler.sim.ALL;
13 USE gaisler.jtagtst.ALL;
14 LIBRARY techmap;
15 USE techmap.gencomp.ALL;
16
17 LIBRARY lpp;
18 USE lpp.lpp_sim_pkg.ALL;
19 USE lpp.lpp_lfr_apbreg_pkg.ALL;
20 USE lpp.lpp_lfr_time_management_apbreg_pkg.ALL;
21
22 LIBRARY postlayout;
23 USE postlayout.ALL;
24
25 ENTITY testbench IS
26 END;
27
28 ARCHITECTURE behav OF testbench IS
29
30 COMPONENT MINI_LFR_top
31 PORT (
32 clk_50 : IN STD_LOGIC;
33 clk_49 : IN STD_LOGIC;
34 reset : IN STD_LOGIC;
35 BP0 : IN STD_LOGIC;
36 BP1 : IN STD_LOGIC;
37 LED0 : OUT STD_LOGIC;
38 LED1 : OUT STD_LOGIC;
39 LED2 : OUT STD_LOGIC;
40 TXD1 : IN STD_LOGIC;
41 RXD1 : OUT STD_LOGIC;
42 nCTS1 : OUT STD_LOGIC;
43 nRTS1 : IN STD_LOGIC;
44 TXD2 : IN STD_LOGIC;
45 RXD2 : OUT STD_LOGIC;
46 nCTS2 : OUT STD_LOGIC;
47 nDTR2 : IN STD_LOGIC;
48 nRTS2 : IN STD_LOGIC;
49 nDCD2 : OUT STD_LOGIC;
50 IO0 : INOUT STD_LOGIC;
51 IO1 : INOUT STD_LOGIC;
52 IO2 : INOUT STD_LOGIC;
53 IO3 : INOUT STD_LOGIC;
54 IO4 : INOUT STD_LOGIC;
55 IO5 : INOUT STD_LOGIC;
56 IO6 : INOUT STD_LOGIC;
57 IO7 : INOUT STD_LOGIC;
58 IO8 : INOUT STD_LOGIC;
59 IO9 : INOUT STD_LOGIC;
60 IO10 : INOUT STD_LOGIC;
61 IO11 : INOUT STD_LOGIC;
62 SPW_EN : OUT STD_LOGIC;
63 SPW_NOM_DIN : IN STD_LOGIC;
64 SPW_NOM_SIN : IN STD_LOGIC;
65 SPW_NOM_DOUT : OUT STD_LOGIC;
66 SPW_NOM_SOUT : OUT STD_LOGIC;
67 SPW_RED_DIN : IN STD_LOGIC;
68 SPW_RED_SIN : IN STD_LOGIC;
69 SPW_RED_DOUT : OUT STD_LOGIC;
70 SPW_RED_SOUT : OUT STD_LOGIC;
71 ADC_nCS : OUT STD_LOGIC;
72 ADC_CLK : OUT STD_LOGIC;
73 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
74 SRAM_nWE : OUT STD_LOGIC;
75 SRAM_CE : OUT STD_LOGIC;
76 SRAM_nOE : OUT STD_LOGIC;
77 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
78 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
79 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0));
80 END COMPONENT;
81
82 -----------------------------------------------------------------------------
83 SIGNAL clk_50 : STD_LOGIC := '0';
84 SIGNAL clk_49 : STD_LOGIC := '0';
85 SIGNAL reset : STD_LOGIC;
86 SIGNAL BP0 : STD_LOGIC;
87 SIGNAL BP1 : STD_LOGIC;
88 SIGNAL LED0 : STD_LOGIC;
89 SIGNAL LED1 : STD_LOGIC;
90 SIGNAL LED2 : STD_LOGIC;
91 SIGNAL TXD1 : STD_LOGIC;
92 SIGNAL RXD1 : STD_LOGIC;
93 SIGNAL nCTS1 : STD_LOGIC;
94 SIGNAL nRTS1 : STD_LOGIC;
95 SIGNAL TXD2 : STD_LOGIC;
96 SIGNAL RXD2 : STD_LOGIC;
97 SIGNAL nCTS2 : STD_LOGIC;
98 SIGNAL nDTR2 : STD_LOGIC;
99 SIGNAL nRTS2 : STD_LOGIC;
100 SIGNAL nDCD2 : STD_LOGIC;
101 SIGNAL IO0 : STD_LOGIC;
102 SIGNAL IO1 : STD_LOGIC;
103 SIGNAL IO2 : STD_LOGIC;
104 SIGNAL IO3 : STD_LOGIC;
105 SIGNAL IO4 : STD_LOGIC;
106 SIGNAL IO5 : STD_LOGIC;
107 SIGNAL IO6 : STD_LOGIC;
108 SIGNAL IO7 : STD_LOGIC;
109 SIGNAL IO8 : STD_LOGIC;
110 SIGNAL IO9 : STD_LOGIC;
111 SIGNAL IO10 : STD_LOGIC;
112 SIGNAL IO11 : STD_LOGIC;
113 SIGNAL SPW_EN : STD_LOGIC;
114 SIGNAL SPW_NOM_DIN : STD_LOGIC;
115 SIGNAL SPW_NOM_SIN : STD_LOGIC;
116 SIGNAL SPW_NOM_DOUT : STD_LOGIC;
117 SIGNAL SPW_NOM_SOUT : STD_LOGIC;
118 SIGNAL SPW_RED_DIN : STD_LOGIC;
119 SIGNAL SPW_RED_SIN : STD_LOGIC;
120 SIGNAL SPW_RED_DOUT : STD_LOGIC;
121 SIGNAL SPW_RED_SOUT : STD_LOGIC;
122 SIGNAL ADC_nCS : STD_LOGIC;
123 SIGNAL ADC_CLK : STD_LOGIC;
124 SIGNAL ADC_SDO : STD_LOGIC_VECTOR(7 DOWNTO 0);
125 SIGNAL SRAM_nWE : STD_LOGIC;
126 SIGNAL SRAM_CE : STD_LOGIC;
127 SIGNAL SRAM_nOE : STD_LOGIC;
128 SIGNAL SRAM_nBE : STD_LOGIC_VECTOR(3 DOWNTO 0);
129 SIGNAL SRAM_A : STD_LOGIC_VECTOR(19 DOWNTO 0);
130 SIGNAL SRAM_DQ : STD_LOGIC_VECTOR(31 DOWNTO 0);
131 -----------------------------------------------------------------------------
132
133 CONSTANT ADDR_BASE_LFR : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000F";
134 CONSTANT ADDR_BASE_TIME_MANAGMENT : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"800006";
135 CONSTANT ADDR_BASE_GPIO : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000B";
136
137
138 SIGNAL message_simu : STRING(1 TO 15) := "---------------";
139
140 BEGIN
141
142 -----------------------------------------------------------------------------
143 -- TB
144 -----------------------------------------------------------------------------
145 PROCESS
146 CONSTANT txp : TIME := 320 ns;
147 BEGIN -- PROCESS
148 TXD1 <= '1';
149 reset <= '0';
150 WAIT FOR 500 ns;
151 reset <= '1';
152 WAIT FOR 10000 ns;
153 message_simu <= "0 - UART init ";
154 UART_INIT(TXD1,txp);
155
156 message_simu <= "1 - UART test ";
157 UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000010",X"0000FFFF");
158 UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000001",X"00000A0A");
159 UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000001",X"00000B0B");
160
161 -- UNSET the LFR reset
162 message_simu <= "2 - LFR UNRESET";
163 UART_WRITE(TXD1,txp,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_CONTROL , X"00000000");
164 UART_WRITE(TXD1,txp,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_TIME_LOAD , X"00000000");
165 --
166 message_simu <= "3 - LFR CONFIG ";
167 UART_WRITE(TXD1,txp,ADDR_BASE_LFR & ADDR_LFR_SM_F0_0_ADDR , X"00000B0B");
168
169 WAIT;
170 END PROCESS;
171
172 -----------------------------------------------------------------------------
173 -- CLOCK
174 -----------------------------------------------------------------------------
175 clk_50 <= NOT clk_50 AFTER 5 ns;
176 clk_49 <= NOT clk_49 AFTER 10172 ps;
177
178 -----------------------------------------------------------------------------
179 -- DON'T CARE
180 -----------------------------------------------------------------------------
181 BP0 <= '0';
182 BP1 <= '0';
183 nRTS1 <= '0' ;
184
185 TXD2 <= '1';
186 nRTS2 <= '1';
187 nDTR2 <= '1';
188
189 SPW_NOM_DIN <= '1';
190 SPW_NOM_SIN <= '1';
191 SPW_RED_DIN <= '1';
192 SPW_RED_SIN <= '1';
193
194 ADC_SDO <= x"AA";
195
196 SRAM_DQ <= (OTHERS => 'Z');
197 IO0 <= 'Z';
198 IO1 <= 'Z';
199 IO2 <= 'Z';
200 IO3 <= 'Z';
201 IO4 <= 'Z';
202 IO5 <= 'Z';
203 IO6 <= 'Z';
204 IO7 <= 'Z';
205 IO8 <= 'Z';
206 IO9 <= 'Z';
207 IO10 <= 'Z';
208 IO11 <= 'Z';
209
210 -----------------------------------------------------------------------------
211 -- DUT
212 -----------------------------------------------------------------------------
213 MINI_LFR_top_1: MINI_LFR_top
214 PORT MAP (
215 clk_50 => clk_50,
216 clk_49 => clk_49,
217 reset => reset,
218
219 BP0 => BP0,
220 BP1 => BP1,
221
222 LED0 => LED0,
223 LED1 => LED1,
224 LED2 => LED2,
225
226 TXD1 => TXD1,
227 RXD1 => RXD1,
228 nCTS1 => nCTS1,
229 nRTS1 => nRTS1,
230
231 TXD2 => TXD2,
232 RXD2 => RXD2,
233 nCTS2 => nCTS2,
234 nDTR2 => nDTR2,
235 nRTS2 => nRTS2,
236 nDCD2 => nDCD2,
237
238 IO0 => IO0,
239 IO1 => IO1,
240 IO2 => IO2,
241 IO3 => IO3,
242 IO4 => IO4,
243 IO5 => IO5,
244 IO6 => IO6,
245 IO7 => IO7,
246 IO8 => IO8,
247 IO9 => IO9,
248 IO10 => IO10,
249 IO11 => IO11,
250
251 SPW_EN => SPW_EN,
252 SPW_NOM_DIN => SPW_NOM_DIN,
253 SPW_NOM_SIN => SPW_NOM_SIN,
254 SPW_NOM_DOUT => SPW_NOM_DOUT,
255 SPW_NOM_SOUT => SPW_NOM_SOUT,
256 SPW_RED_DIN => SPW_RED_DIN,
257 SPW_RED_SIN => SPW_RED_SIN,
258 SPW_RED_DOUT => SPW_RED_DOUT,
259 SPW_RED_SOUT => SPW_RED_SOUT,
260
261 ADC_nCS => ADC_nCS,
262 ADC_CLK => ADC_CLK,
263 ADC_SDO => ADC_SDO,
264
265 SRAM_nWE => SRAM_nWE,
266 SRAM_CE => SRAM_CE,
267 SRAM_nOE => SRAM_nOE,
268 SRAM_nBE => SRAM_nBE,
269 SRAM_A => SRAM_A,
270 SRAM_DQ => SRAM_DQ);
271
272
273 END;
Show file before | Show file after | Hide comments
@@ -1,328 +1,327
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Alexis Jeandet
20 20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 21 ----------------------------------------------------------------------------
22 22 LIBRARY IEEE;
23 23 USE IEEE.numeric_std.ALL;
24 24 USE IEEE.std_logic_1164.ALL;
25 25 LIBRARY lpp;
26 26 USE lpp.general_purpose.ALL;
27 27 --TODO
28 28 --terminer le testbensh puis changer le resize dans les instanciations
29 29 --par un resize sur un vecteur en combi
30 30
31 31
32 32 ENTITY MAC IS
33 33 GENERIC(
34 34 Input_SZ_A : INTEGER := 8;
35 35 Input_SZ_B : INTEGER := 8;
36 36 COMP_EN : INTEGER := 0 -- 1 => No Comp
37 37
38 38 );
39 39 PORT(
40 40 clk : IN STD_LOGIC;
41 41 reset : IN STD_LOGIC;
42 42 clr_MAC : IN STD_LOGIC;
43 43 MAC_MUL_ADD : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
44 44 Comp_2C : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
45 45 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
46 46 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
47 47 RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0)
48 48 );
49 49 END MAC;
50 50
51 51
52 52
53 53
54 54 ARCHITECTURE ar_MAC OF MAC IS
55 55
56 56
57 57 SIGNAL clr_MAC_s : STD_LOGIC;
58 58 SIGNAL MAC_MUL_ADD_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
59 59
60 60 SIGNAL add, mult : STD_LOGIC;
61 61 SIGNAL MULTout : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0);
62 62
63 63 SIGNAL ADDERinA : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0);
64 64 SIGNAL ADDERinB : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0);
65 65 SIGNAL ADDERout : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0);
66 66
67 67 SIGNAL MACMUXsel : STD_LOGIC;
68 68 SIGNAL OP1_2C_D_Resz : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0);
69 69 SIGNAL OP2_2C_D_Resz : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0);
70 70
71 71 SIGNAL OP1_2C : STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
72 72 SIGNAL OP2_2C : STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
73 73
74 74 SIGNAL MACMUX2sel : STD_LOGIC;
75 75
76 SIGNAL add_D : STD_LOGIC;
77 SIGNAL OP1_2C_D : STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
78 SIGNAL OP2_2C_D : STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
79 SIGNAL MULTout_D : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0);
80 SIGNAL MACMUXsel_D : STD_LOGIC;
81 SIGNAL MACMUX2sel_D : STD_LOGIC;
82 SIGNAL MACMUX2sel_D_D : STD_LOGIC;
83 SIGNAL clr_MAC_D : STD_LOGIC;
76 SIGNAL add_D : STD_LOGIC;
77 SIGNAL OP1_2C_D : STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
78 SIGNAL OP2_2C_D : STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
79 SIGNAL MULTout_D : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0);
80 SIGNAL MACMUXsel_D : STD_LOGIC;
81 SIGNAL MACMUX2sel_D : STD_LOGIC;
82 SIGNAL MACMUX2sel_D_D : STD_LOGIC;
83 SIGNAL clr_MAC_D : STD_LOGIC;
84 84 -- SIGNAL clr_MAC_D_D : STD_LOGIC;
85 85 -- SIGNAL MAC_MUL_ADD_2C_D : STD_LOGIC_VECTOR(1 DOWNTO 0);
86 86
87 SIGNAL load_mult_result : STD_LOGIC;
88 SIGNAL load_mult_result_D : STD_LOGIC;
87 -- SIGNAL load_mult_result : STD_LOGIC;
88 -- SIGNAL load_mult_result_D : STD_LOGIC;
89 89
90 90 BEGIN
91 91
92 92
93 93
94 94
95 95 --==============================================================
96 96 --=============M A C C O N T R O L E R=========================
97 97 --==============================================================
98 98 MAC_CONTROLER1 : MAC_CONTROLER
99 99 PORT MAP(
100 100 ctrl => MAC_MUL_ADD_s,
101 101 MULT => mult,
102 102 ADD => add,
103 LOAD_ADDER => load_mult_result,
103 --LOAD_ADDER => load_mult_result,
104 104 MACMUX_sel => MACMUXsel,
105 105 MACMUX2_sel => MACMUX2sel
106 106
107 107 );
108 108 --==============================================================
109 109
110 110
111 111
112 112
113 113 --==============================================================
114 114 --=============M U L T I P L I E R==============================
115 115 --==============================================================
116 116 Multiplieri_nst : Multiplier
117 117 GENERIC MAP(
118 118 Input_SZ_A => Input_SZ_A,
119 119 Input_SZ_B => Input_SZ_B
120 120 )
121 121 PORT MAP(
122 122 clk => clk,
123 123 reset => reset,
124 124 mult => mult,
125 125 OP1 => OP1_2C,
126 126 OP2 => OP2_2C,
127 127 RES => MULTout
128 128 );
129 129 --==============================================================
130 130
131 PROCESS (clk, reset)
132 BEGIN -- PROCESS
133 IF reset = '0' THEN -- asynchronous reset (active low)
134 load_mult_result_D <= '0';
135 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
136 load_mult_result_D <= load_mult_result;
137 END IF;
138 END PROCESS;
131 --PROCESS (clk, reset)
132 --BEGIN -- PROCESS
133 -- IF reset = '0' THEN -- asynchronous reset (active low)
134 -- load_mult_result_D <= '0';
135 -- ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
136 -- load_mult_result_D <= load_mult_result;
137 -- END IF;
138 --END PROCESS;
139 139
140 140 --==============================================================
141 141 --======================A D D E R ==============================
142 142 --==============================================================
143 143 adder_inst : Adder
144 144 GENERIC MAP(
145 145 Input_SZ_A => Input_SZ_A+Input_SZ_B,
146 146 Input_SZ_B => Input_SZ_A+Input_SZ_B
147 147 )
148 148 PORT MAP(
149 149 clk => clk,
150 150 reset => reset,
151 151 clr => clr_MAC_D,
152 load => load_mult_result_D,
152 load => MACMUX2sel_D, --load_mult_result_D,
153 153 add => add_D,
154 154 OP1 => ADDERinA,
155 155 OP2 => ADDERinB,
156 156 RES => ADDERout
157 157 );
158 158
159 159 --==============================================================
160 160 --===================TWO COMPLEMENTERS==========================
161 161 --==============================================================
162 162 gen_comp : IF COMP_EN = 0 GENERATE
163 163 TWO_COMPLEMENTER1 : TwoComplementer
164 164 GENERIC MAP(
165 165 Input_SZ => Input_SZ_A
166 166 )
167 167 PORT MAP(
168 168 clk => clk,
169 169 reset => reset,
170 clr => '0',--clr_MAC,
170 clr => '0', --clr_MAC,
171 171 TwoComp => Comp_2C(0),
172 172 OP => OP1,
173 173 RES => OP1_2C
174 174 );
175 175
176 176 TWO_COMPLEMENTER2 : TwoComplementer
177 177 GENERIC MAP(
178 178 Input_SZ => Input_SZ_B
179 179 )
180 180 PORT MAP(
181 181 clk => clk,
182 182 reset => reset,
183 clr => '0',--clr_MAC,
183 clr => '0', --clr_MAC,
184 184 TwoComp => Comp_2C(1),
185 185 OP => OP2,
186 186 RES => OP2_2C
187 187 );
188
189
188
190 189 clr_MACREG_comp : MAC_REG
191 190 GENERIC MAP(size => 1)
192 191 PORT MAP(
193 192 reset => reset,
194 193 clk => clk,
195 194 D(0) => clr_MAC,
196 195 Q(0) => clr_MAC_s
197 196 );
198
197
199 198 MAC_MUL_ADD_REG : MAC_REG
200 GENERIC MAP(size => 2)
201 PORT MAP(
202 reset => reset,
203 clk => clk,
204 D => MAC_MUL_ADD,
205 Q => MAC_MUL_ADD_s
206 );
207
199 GENERIC MAP(size => 2)
200 PORT MAP(
201 reset => reset,
202 clk => clk,
203 D => MAC_MUL_ADD,
204 Q => MAC_MUL_ADD_s
205 );
206
208 207 END GENERATE gen_comp;
209
208
210 209 no_gen_comp : IF COMP_EN = 1 GENERATE
211 210 OP2_2C <= OP2;
212 211 OP1_2C <= OP1;
213 212
214 213 clr_MAC_s <= clr_MAC;
215 214 MAC_MUL_ADD_s <= MAC_MUL_ADD;
216 215 END GENERATE no_gen_comp;
217 216 --==============================================================
218 217
219 218 clr_MACREG1 : MAC_REG
220 219 GENERIC MAP(size => 1)
221 220 PORT MAP(
222 221 reset => reset,
223 222 clk => clk,
224 223 D(0) => clr_MAC_s,
225 224 Q(0) => clr_MAC_D
226 225 );
227 226
228 227 addREG : MAC_REG
229 228 GENERIC MAP(size => 1)
230 229 PORT MAP(
231 230 reset => reset,
232 231 clk => clk,
233 232 D(0) => add,
234 233 Q(0) => add_D
235 234 );
236 235
237 236 OP1REG : MAC_REG
238 237 GENERIC MAP(size => Input_SZ_A)
239 238 PORT MAP(
240 239 reset => reset,
241 240 clk => clk,
242 241 D => OP1_2C,
243 242 Q => OP1_2C_D
244 243 );
245 244
246 245
247 246 OP2REG : MAC_REG
248 247 GENERIC MAP(size => Input_SZ_B)
249 248 PORT MAP(
250 249 reset => reset,
251 250 clk => clk,
252 251 D => OP2_2C,
253 252 Q => OP2_2C_D
254 253 );
255 254
256 255 MULToutREG : MAC_REG
257 256 GENERIC MAP(size => Input_SZ_A+Input_SZ_B)
258 257 PORT MAP(
259 258 reset => reset,
260 259 clk => clk,
261 260 D => MULTout,
262 261 Q => MULTout_D
263 262 );
264 263
265 264 MACMUXselREG : MAC_REG
266 265 GENERIC MAP(size => 1)
267 266 PORT MAP(
268 267 reset => reset,
269 268 clk => clk,
270 269 D(0) => MACMUXsel,
271 270 Q(0) => MACMUXsel_D
272 271 );
273 272
274 273 MACMUX2selREG : MAC_REG
275 274 GENERIC MAP(size => 1)
276 275 PORT MAP(
277 276 reset => reset,
278 277 clk => clk,
279 278 D(0) => MACMUX2sel,
280 279 Q(0) => MACMUX2sel_D
281 280 );
282 281
283 282 MACMUX2selREG2 : MAC_REG
284 283 GENERIC MAP(size => 1)
285 284 PORT MAP(
286 285 reset => reset,
287 286 clk => clk,
288 287 D(0) => MACMUX2sel_D,
289 288 Q(0) => MACMUX2sel_D_D
290 289 );
291 290
292 291 --==============================================================
293 292 --======================M A C M U X ===========================
294 293 --==============================================================
295 294 MACMUX_inst : MAC_MUX
296 295 GENERIC MAP(
297 296 Input_SZ_A => Input_SZ_A+Input_SZ_B,
298 297 Input_SZ_B => Input_SZ_A+Input_SZ_B
299 298
300 299 )
301 300 PORT MAP(
302 301 sel => MACMUXsel_D,
303 302 INA1 => ADDERout,
304 303 INA2 => OP2_2C_D_Resz,
305 304 INB1 => MULTout,
306 305 INB2 => OP1_2C_D_Resz,
307 306 OUTA => ADDERinA,
308 307 OUTB => ADDERinB
309 308 );
310 309 OP1_2C_D_Resz <= STD_LOGIC_VECTOR(resize(SIGNED(OP1_2C_D), Input_SZ_A+Input_SZ_B));
311 310 OP2_2C_D_Resz <= STD_LOGIC_VECTOR(resize(SIGNED(OP2_2C_D), Input_SZ_A+Input_SZ_B));
312 311 --==============================================================
313 312
314 313
315 314 --==============================================================
316 315 --======================M A C M U X2 ==========================
317 316 --==============================================================
318 317 MAC_MUX2_inst : MAC_MUX2
319 318 GENERIC MAP(Input_SZ => Input_SZ_A+Input_SZ_B)
320 319 PORT MAP(
321 320 sel => MACMUX2sel_D_D,
322 321 RES2 => MULTout_D,
323 322 RES1 => ADDERout,
324 323 RES => RES
325 324 );
326 325 --==============================================================
327 326
328 327 END ar_MAC;
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@@ -1,71 +1,71
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Alexis Jeandet
20 20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 21 ----------------------------------------------------------------------------
22 22 library IEEE;
23 23 use IEEE.numeric_std.all;
24 24 use IEEE.std_logic_1164.all;
25 25
26 26 --IDLE =00 MAC =01 MULT =10 ADD =11
27 27
28 28
29 29 entity MAC_CONTROLER is
30 30 port(
31 31 ctrl : in std_logic_vector(1 downto 0);
32 32 MULT : out std_logic;
33 33 ADD : out std_logic;
34 LOAD_ADDER : out std_logic;
34 -- LOAD_ADDER : out std_logic;
35 35 MACMUX_sel : out std_logic;
36 36 MACMUX2_sel : out std_logic
37 37
38 38 );
39 39 end MAC_CONTROLER;
40 40
41 41
42 42
43 43
44 44
45 45 architecture ar_MAC_CONTROLER of MAC_CONTROLER is
46 46
47 47 begin
48 48
49 49
50 50
51 51 MULT <= '0' when (ctrl = "00" or ctrl = "11") else '1';
52 52 ADD <= '0' when (ctrl = "00" or ctrl = "10") else '1';
53 LOAD_ADDER <= '1' when (ctrl = "10") else '0'; -- PATCH JC : mem mult result
54 -- to permit to compute a
55 -- MULT follow by a MAC
53 --LOAD_ADDER <= '1' when ( ctrl = "10") else '0'; -- PATCH JC : mem mult result
54 -- to permit to compute a
55 -- MULT follow by a MAC
56 56 --MACMUX_sel <= '0' when (ctrl = "00" or ctrl = "01") else '1';
57 57 MACMUX_sel <= '0' when (ctrl = "00" or ctrl = "01" OR ctrl = "10") else '1';
58 58 MACMUX2_sel <= '0' when (ctrl = "00" or ctrl = "01" or ctrl = "11") else '1';
59 59
60 60
61 61 end ar_MAC_CONTROLER;
62 62
63 63
64 64
65 65
66 66
67 67
68 68
69 69
70 70
71 71
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@@ -1,395 +1,395
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Alexis Jeandet
20 20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 21 ----------------------------------------------------------------------------
22 22 --UPDATE
23 23 -------------------------------------------------------------------------------
24 24 -- 14-03-2013 - Jean-christophe Pellion
25 25 -- ADD MUXN (a parametric multiplexor (N stage of MUX2))
26 26 -------------------------------------------------------------------------------
27 27
28 28 LIBRARY ieee;
29 29 USE ieee.std_logic_1164.ALL;
30 30 USE IEEE.NUMERIC_STD.ALL;
31 31
32 32
33 33
34 34 PACKAGE general_purpose IS
35 35
36 36 COMPONENT general_counter
37 37 GENERIC (
38 38 CYCLIC : STD_LOGIC;
39 39 NB_BITS_COUNTER : INTEGER);
40 40 PORT (
41 41 clk : IN STD_LOGIC;
42 42 rstn : IN STD_LOGIC;
43 43 RST_VALUE : IN STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0);
44 44 MAX_VALUE : IN STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0);
45 45 set : IN STD_LOGIC;
46 46 set_value : IN STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0);
47 47 add1 : IN STD_LOGIC;
48 48 counter : OUT STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0));
49 49 END COMPONENT;
50 50
51 51 COMPONENT Clk_divider IS
52 52 GENERIC(OSC_freqHz : INTEGER := 50000000;
53 53 TargetFreq_Hz : INTEGER := 50000);
54 54 PORT (clk : IN STD_LOGIC;
55 55 reset : IN STD_LOGIC;
56 56 clk_divided : OUT STD_LOGIC);
57 57 END COMPONENT;
58 58
59 59
60 60 COMPONENT Clk_divider2 IS
61 61 generic(N : integer := 16);
62 62 port(
63 63 clk_in : in std_logic;
64 64 clk_out : out std_logic);
65 65 END COMPONENT;
66 66
67 67 COMPONENT Adder IS
68 68 GENERIC(
69 69 Input_SZ_A : INTEGER := 16;
70 70 Input_SZ_B : INTEGER := 16
71 71
72 72 );
73 73 PORT(
74 74 clk : IN STD_LOGIC;
75 75 reset : IN STD_LOGIC;
76 76 clr : IN STD_LOGIC;
77 77 load : IN STD_LOGIC;
78 78 add : IN STD_LOGIC;
79 79 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
80 80 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
81 81 RES : OUT STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0)
82 82 );
83 83 END COMPONENT;
84 84
85 85 COMPONENT Adder_V0 is
86 86 generic(
87 87 Input_SZ_A : integer := 16;
88 88 Input_SZ_B : integer := 16
89 89
90 90 );
91 91 port(
92 92 clk : in std_logic;
93 93 reset : in std_logic;
94 94 clr : in std_logic;
95 95 add : in std_logic;
96 96 OP1 : in std_logic_vector(Input_SZ_A-1 downto 0);
97 97 OP2 : in std_logic_vector(Input_SZ_B-1 downto 0);
98 98 RES : out std_logic_vector(Input_SZ_A-1 downto 0)
99 99 );
100 100 end COMPONENT;
101 101
102 102 COMPONENT ADDRcntr IS
103 103 PORT(
104 104 clk : IN STD_LOGIC;
105 105 reset : IN STD_LOGIC;
106 106 count : IN STD_LOGIC;
107 107 clr : IN STD_LOGIC;
108 108 Q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
109 109 );
110 110 END COMPONENT;
111 111
112 112 COMPONENT ALU IS
113 113 GENERIC(
114 114 Arith_en : INTEGER := 1;
115 115 Logic_en : INTEGER := 1;
116 116 Input_SZ_1 : INTEGER := 16;
117 117 Input_SZ_2 : INTEGER := 9;
118 118 COMP_EN : INTEGER := 0 -- 1 => No Comp
119 119
120 120 );
121 121 PORT(
122 122 clk : IN STD_LOGIC;
123 123 reset : IN STD_LOGIC;
124 124 ctrl : IN STD_LOGIC_VECTOR(2 downto 0);
125 125 comp : IN STD_LOGIC_VECTOR(1 downto 0);
126 126 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
127 127 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_2-1 DOWNTO 0);
128 128 RES : OUT STD_LOGIC_VECTOR(Input_SZ_1+Input_SZ_2-1 DOWNTO 0)
129 129 );
130 130 END COMPONENT;
131 131
132 132 COMPONENT ALU_V0 IS
133 133 GENERIC(
134 134 Arith_en : INTEGER := 1;
135 135 Logic_en : INTEGER := 1;
136 136 Input_SZ_1 : INTEGER := 16;
137 137 Input_SZ_2 : INTEGER := 9
138 138
139 139 );
140 140 PORT(
141 141 clk : IN STD_LOGIC;
142 142 reset : IN STD_LOGIC;
143 143 ctrl : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
144 144 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
145 145 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_2-1 DOWNTO 0);
146 146 RES : OUT STD_LOGIC_VECTOR(Input_SZ_1+Input_SZ_2-1 DOWNTO 0)
147 147 );
148 148 END COMPONENT;
149 149
150 150 COMPONENT MAC_V0 is
151 151 generic(
152 152 Input_SZ_A : integer := 8;
153 153 Input_SZ_B : integer := 8
154 154
155 155 );
156 156 port(
157 157 clk : in std_logic;
158 158 reset : in std_logic;
159 159 clr_MAC : in std_logic;
160 160 MAC_MUL_ADD : in std_logic_vector(1 downto 0);
161 161 OP1 : in std_logic_vector(Input_SZ_A-1 downto 0);
162 162 OP2 : in std_logic_vector(Input_SZ_B-1 downto 0);
163 163 RES : out std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0)
164 164 );
165 165 end COMPONENT;
166 166
167 167 ---------------------------------------------------------
168 168 -------- // SΓ©lection grace a l'entrΓ©e "ctrl" \\ --------
169 169 ---------------------------------------------------------
170 170 Constant ctrl_IDLE : std_logic_vector(2 downto 0) := "000";
171 171 Constant ctrl_MAC : std_logic_vector(2 downto 0) := "001";
172 172 Constant ctrl_MULT : std_logic_vector(2 downto 0) := "010";
173 173 Constant ctrl_ADD : std_logic_vector(2 downto 0) := "011";
174 174 Constant ctrl_CLRMAC : std_logic_vector(2 downto 0) := "100";
175 175
176 176
177 177 Constant IDLE_V0 : std_logic_vector(3 downto 0) := "0000";
178 178 Constant MAC_op_V0 : std_logic_vector(3 downto 0) := "0001";
179 179 Constant MULT_V0 : std_logic_vector(3 downto 0) := "0010";
180 180 Constant ADD_V0 : std_logic_vector(3 downto 0) := "0011";
181 181 Constant CLR_MAC_V0 : std_logic_vector(3 downto 0) := "0100";
182 182 ---------------------------------------------------------
183 183
184 184 COMPONENT MAC IS
185 185 GENERIC(
186 186 Input_SZ_A : INTEGER := 8;
187 187 Input_SZ_B : INTEGER := 8;
188 188 COMP_EN : INTEGER := 0 -- 1 => No Comp
189 189 );
190 190 PORT(
191 191 clk : IN STD_LOGIC;
192 192 reset : IN STD_LOGIC;
193 193 clr_MAC : IN STD_LOGIC;
194 194 MAC_MUL_ADD : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
195 195 Comp_2C : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
196 196 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
197 197 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
198 198 RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0)
199 199 );
200 200 END COMPONENT;
201 201
202 202 COMPONENT TwoComplementer is
203 203 generic(
204 204 Input_SZ : integer := 16);
205 205 port(
206 206 clk : in std_logic; --! Horloge du composant
207 207 reset : in std_logic; --! Reset general du composant
208 208 clr : in std_logic; --! Un reset spΓ©cifique au programme
209 209 TwoComp : in std_logic; --! Autorise l'utilisation du complΓ©ment
210 210 OP : in std_logic_vector(Input_SZ-1 downto 0); --! OpΓ©rande d'entrΓ©e
211 211 RES : out std_logic_vector(Input_SZ-1 downto 0) --! RΓ©sultat, opΓ©rande complΓ©mentΓ© ou non
212 212 );
213 213 end COMPONENT;
214 214
215 215 COMPONENT MAC_CONTROLER IS
216 216 PORT(
217 217 ctrl : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
218 218 MULT : OUT STD_LOGIC;
219 219 ADD : OUT STD_LOGIC;
220 LOAD_ADDER : out std_logic;
220 -- LOAD_ADDER : out std_logic;
221 221 MACMUX_sel : OUT STD_LOGIC;
222 222 MACMUX2_sel : OUT STD_LOGIC
223 223 );
224 224 END COMPONENT;
225 225
226 226 COMPONENT MAC_MUX IS
227 227 GENERIC(
228 228 Input_SZ_A : INTEGER := 16;
229 229 Input_SZ_B : INTEGER := 16
230 230
231 231 );
232 232 PORT(
233 233 sel : IN STD_LOGIC;
234 234 INA1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
235 235 INA2 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
236 236 INB1 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
237 237 INB2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
238 238 OUTA : OUT STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
239 239 OUTB : OUT STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0)
240 240 );
241 241 END COMPONENT;
242 242
243 243
244 244 COMPONENT MAC_MUX2 IS
245 245 GENERIC(Input_SZ : INTEGER := 16);
246 246 PORT(
247 247 sel : IN STD_LOGIC;
248 248 RES1 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
249 249 RES2 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
250 250 RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0)
251 251 );
252 252 END COMPONENT;
253 253
254 254
255 255 COMPONENT MAC_REG IS
256 256 GENERIC(size : INTEGER := 16);
257 257 PORT(
258 258 reset : IN STD_LOGIC;
259 259 clk : IN STD_LOGIC;
260 260 D : IN STD_LOGIC_VECTOR(size-1 DOWNTO 0);
261 261 Q : OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0)
262 262 );
263 263 END COMPONENT;
264 264
265 265
266 266 COMPONENT MUX2 IS
267 267 GENERIC(Input_SZ : INTEGER := 16);
268 268 PORT(
269 269 sel : IN STD_LOGIC;
270 270 IN1 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
271 271 IN2 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
272 272 RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0)
273 273 );
274 274 END COMPONENT;
275 275
276 276 TYPE MUX_INPUT_TYPE IS ARRAY (NATURAL RANGE <>, NATURAL RANGE <>) OF STD_LOGIC;
277 277 TYPE MUX_OUTPUT_TYPE IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC;
278 278
279 279 COMPONENT MUXN
280 280 GENERIC (
281 281 Input_SZ : INTEGER;
282 282 NbStage : INTEGER);
283 283 PORT (
284 284 sel : IN STD_LOGIC_VECTOR(NbStage-1 DOWNTO 0);
285 285 INPUT : IN MUX_INPUT_TYPE(0 TO (2**NbStage)-1,Input_SZ-1 DOWNTO 0);
286 286 --INPUT : IN ARRAY (0 TO (2**NbStage)-1) OF STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
287 287 RES : OUT MUX_OUTPUT_TYPE(Input_SZ-1 DOWNTO 0));
288 288 END COMPONENT;
289 289
290 290
291 291
292 292 COMPONENT Multiplier IS
293 293 GENERIC(
294 294 Input_SZ_A : INTEGER := 16;
295 295 Input_SZ_B : INTEGER := 16
296 296
297 297 );
298 298 PORT(
299 299 clk : IN STD_LOGIC;
300 300 reset : IN STD_LOGIC;
301 301 mult : IN STD_LOGIC;
302 302 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
303 303 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
304 304 RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0)
305 305 );
306 306 END COMPONENT;
307 307
308 308 COMPONENT REG IS
309 309 GENERIC(size : INTEGER := 16; initial_VALUE : INTEGER := 0);
310 310 PORT(
311 311 reset : IN STD_LOGIC;
312 312 clk : IN STD_LOGIC;
313 313 D : IN STD_LOGIC_VECTOR(size-1 DOWNTO 0);
314 314 Q : OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0)
315 315 );
316 316 END COMPONENT;
317 317
318 318
319 319
320 320 COMPONENT RShifter IS
321 321 GENERIC(
322 322 Input_SZ : INTEGER := 16;
323 323 shift_SZ : INTEGER := 4
324 324 );
325 325 PORT(
326 326 clk : IN STD_LOGIC;
327 327 reset : IN STD_LOGIC;
328 328 shift : IN STD_LOGIC;
329 329 OP : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
330 330 cnt : IN STD_LOGIC_VECTOR(shift_SZ-1 DOWNTO 0);
331 331 RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0)
332 332 );
333 333 END COMPONENT;
334 334
335 335 COMPONENT SYNC_FF
336 336 GENERIC (
337 337 NB_FF_OF_SYNC : INTEGER);
338 338 PORT (
339 339 clk : IN STD_LOGIC;
340 340 rstn : IN STD_LOGIC;
341 341 A : IN STD_LOGIC;
342 342 A_sync : OUT STD_LOGIC);
343 343 END COMPONENT;
344 344
345 345 COMPONENT lpp_front_to_level
346 346 PORT (
347 347 clk : IN STD_LOGIC;
348 348 rstn : IN STD_LOGIC;
349 349 sin : IN STD_LOGIC;
350 350 sout : OUT STD_LOGIC);
351 351 END COMPONENT;
352 352
353 353 COMPONENT lpp_front_detection
354 354 PORT (
355 355 clk : IN STD_LOGIC;
356 356 rstn : IN STD_LOGIC;
357 357 sin : IN STD_LOGIC;
358 358 sout : OUT STD_LOGIC);
359 359 END COMPONENT;
360 360
361 361 COMPONENT lpp_front_positive_detection
362 362 PORT (
363 363 clk : IN STD_LOGIC;
364 364 rstn : IN STD_LOGIC;
365 365 sin : IN STD_LOGIC;
366 366 sout : OUT STD_LOGIC);
367 367 END COMPONENT;
368 368
369 369 COMPONENT SYNC_VALID_BIT
370 370 GENERIC (
371 371 NB_FF_OF_SYNC : INTEGER);
372 372 PORT (
373 373 clk_in : IN STD_LOGIC;
374 374 clk_out : IN STD_LOGIC;
375 375 rstn : IN STD_LOGIC;
376 376 sin : IN STD_LOGIC;
377 377 sout : OUT STD_LOGIC);
378 378 END COMPONENT;
379 379
380 380 COMPONENT RR_Arbiter_4
381 381 PORT (
382 382 clk : IN STD_LOGIC;
383 383 rstn : IN STD_LOGIC;
384 384 in_valid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
385 385 out_grant : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
386 386 END COMPONENT;
387 387
388 388 COMPONENT Clock_Divider is
389 389 generic(N :integer := 10);
390 390 port(
391 391 clk, rst : in std_logic;
392 392 sclk : out std_logic);
393 393 end COMPONENT;
394 394
395 395 END;
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@@ -1,119 +1,119
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Alexis Jeandet
20 20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 21 -------------------------------------------------------------------------------
22 22 -- MODIFIED by Jean-christophe PELLION
23 23 -- jean-christophe.pellion@lpp.polytechnique.fr
24 24 -------------------------------------------------------------------------------
25 25 -------------------------------------------------------------------------------
26 26 -- MODIFIED by Paul LEROY
27 27 -- paul.leroy@lpp.polytechnique.fr
28 28 -------------------------------------------------------------------------------
29 29
30 30 LIBRARY IEEE;
31 31 USE IEEE.STD_LOGIC_1164.ALL;
32 32 LIBRARY lpp;
33 33 USE lpp.lpp_ad_conv.ALL;
34 34
35 35 ENTITY ADS7886_drvr_v2 IS
36 36 GENERIC(
37 37 ChannelCount : INTEGER := 8;
38 38 NbBitsSamples : INTEGER := 16);
39 39 PORT (
40 40 -- CONV --
41 41 cnv_clk : IN STD_LOGIC;
42 42 cnv_rstn : IN STD_LOGIC;
43 43 -- DATA --
44 44 clk : IN STD_LOGIC;
45 45 rstn : IN STD_LOGIC;
46 46 sck : OUT STD_LOGIC;
47 47 sdo : IN STD_LOGIC_VECTOR(ChannelCount-1 DOWNTO 0);
48 48 -- SAMPLE --
49 49 sample : OUT Samples(ChannelCount-1 DOWNTO 0);
50 50 sample_val : OUT STD_LOGIC
51 51 );
52 52 END ADS7886_drvr_v2;
53 53
54 54 ARCHITECTURE ar_ADS7886_drvr_v2 OF ADS7886_drvr_v2 IS
55 55
56 56 SIGNAL cnv_sync : STD_LOGIC;
57 57 SIGNAL cnv_sync_r : STD_LOGIC;
58 58 SIGNAL cnv_done : STD_LOGIC;
59 59 SIGNAL sample_bit_counter : INTEGER;
60 SIGNAL shift_reg : Samples(ChannelCount-1 DOWNTO 0);
60 SIGNAL shift_reg : Samples_15(ChannelCount-1 DOWNTO 0);
61 61
62 62 BEGIN
63 63
64 64 cnv_sync <= cnv_clk;
65 65
66 66 PROCESS (clk, rstn) -- falling edge detection on cnv_sync
67 67 BEGIN
68 68 IF rstn = '0' THEN
69 69 cnv_sync_r <= '1';
70 70 cnv_done <= '0';
71 71 ELSIF clk'EVENT AND clk = '1' THEN
72 72 cnv_sync_r <= cnv_sync;
73 73 cnv_done <= (NOT cnv_sync) AND cnv_sync_r;
74 74 END IF;
75 75 END PROCESS;
76 76
77 77 -----------------------------------------------------------------------------
78 78 -- DATA
79 79 -----------------------------------------------------------------------------
80 80
81 81 PROCESS (clk, rstn)
82 82 BEGIN -- PROCESS
83 83 IF rstn = '0' THEN
84 84 FOR k IN 0 TO ChannelCount-1 LOOP
85 shift_reg(k)(15 downto 0) <= (OTHERS => '0');
86 sample(k)(15 downto 0) <= (OTHERS => '0');
85 shift_reg(k)(14 downto 0) <= (OTHERS => '0');
86 sample(k)(15 downto 0) <= (OTHERS => '0');
87 87 END LOOP;
88 88 sample_bit_counter <= 0;
89 89 sample_val <= '0';
90 90 SCK <= '1';
91 91 ELSIF clk'EVENT AND clk = '1' THEN
92 92 IF (cnv_done = '1') AND (sample_bit_counter = 0) THEN
93 93 sample_bit_counter <= 1;
94 94 ELSIF sample_bit_counter > 0 AND sample_bit_counter < 31 THEN
95 95 sample_bit_counter <= sample_bit_counter + 1;
96 96 ELSIF sample_bit_counter = 31 THEN
97 97 sample_val <= '1';
98 98 FOR k IN 0 TO ChannelCount-1 LOOP
99 99 sample(k)(0) <= sdo(k);
100 100 sample(k)(15 DOWNTO 1) <= shift_reg(k)(14 DOWNTO 0);
101 101 END LOOP;
102 102 sample_bit_counter <= 0;
103 103 ELSE
104 104 sample_val <= '0';
105 105 END IF;
106 106
107 107 IF (sample_bit_counter MOD 2) = 1 THEN -- get data on each channel
108 108 FOR k IN 0 TO ChannelCount-1 LOOP
109 109 shift_reg(k)(0) <= sdo(k);
110 shift_reg(k)(15 DOWNTO 1) <= shift_reg(k)(14 DOWNTO 0);
110 shift_reg(k)(14 DOWNTO 1) <= shift_reg(k)(13 DOWNTO 0);
111 111 END LOOP;
112 112 SCK <= '0';
113 113 ELSE
114 114 SCK <= '1';
115 115 END IF;
116 116 END IF;
117 117 END PROCESS;
118 118
119 END ar_ADS7886_drvr_v2; No newline at end of file
119 END ar_ADS7886_drvr_v2;
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@@ -1,372 +1,373
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Alexis Jeandet
20 20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 21 ----------------------------------------------------------------------------
22 22
23 23 LIBRARY IEEE;
24 24 USE IEEE.STD_LOGIC_1164.ALL;
25 25 LIBRARY grlib;
26 26 USE grlib.amba.ALL;
27 27 USE grlib.stdlib.ALL;
28 28 USE grlib.devices.ALL;
29 29
30 30 PACKAGE lpp_ad_conv IS
31 31
32 32
33 33 --CONSTANT AD7688 : INTEGER := 0;
34 34 --CONSTANT ADS7886 : INTEGER := 1;
35 35
36 36
37 37 --TYPE AD7688_out IS
38 38 --RECORD
39 39 -- CNV : STD_LOGIC;
40 40 -- SCK : STD_LOGIC;
41 41 --END RECORD;
42 42
43 43 --TYPE AD7688_in_element IS
44 44 --RECORD
45 45 -- SDI : STD_LOGIC;
46 46 --END RECORD;
47 47
48 48 --TYPE AD7688_in IS ARRAY(NATURAL RANGE <>) OF AD7688_in_element;
49 49
50 TYPE Samples IS ARRAY(NATURAL RANGE <>) OF STD_LOGIC_VECTOR(15 DOWNTO 0);
50 TYPE Samples IS ARRAY(NATURAL RANGE <>) OF STD_LOGIC_VECTOR(15 DOWNTO 0);
51 TYPE Samples_15 IS ARRAY(NATURAL RANGE <>) OF STD_LOGIC_VECTOR(14 DOWNTO 0);
51 52
52 53 SUBTYPE Samples24 IS STD_LOGIC_VECTOR(23 DOWNTO 0);
53 54
54 55 SUBTYPE Samples16 IS STD_LOGIC_VECTOR(15 DOWNTO 0);
55 56
56 57 SUBTYPE Samples15 IS STD_LOGIC_VECTOR(14 DOWNTO 0);
57 58
58 59 SUBTYPE Samples14 IS STD_LOGIC_VECTOR(13 DOWNTO 0);
59 60
60 61 SUBTYPE Samples12 IS STD_LOGIC_VECTOR(11 DOWNTO 0);
61 62
62 63 SUBTYPE Samples10 IS STD_LOGIC_VECTOR(9 DOWNTO 0);
63 64
64 65 SUBTYPE Samples8 IS STD_LOGIC_VECTOR(7 DOWNTO 0);
65 66
66 67 TYPE Samples24v IS ARRAY(NATURAL RANGE <>) OF Samples24;
67 68
68 69 TYPE Samples16v IS ARRAY(NATURAL RANGE <>) OF Samples16;
69 70
70 71 TYPE Samples15v IS ARRAY(NATURAL RANGE <>) OF Samples15;
71 72
72 73 TYPE Samples14v IS ARRAY(NATURAL RANGE <>) OF Samples14;
73 74
74 75 TYPE Samples12v IS ARRAY(NATURAL RANGE <>) OF Samples12;
75 76
76 77 TYPE Samples10v IS ARRAY(NATURAL RANGE <>) OF Samples10;
77 78
78 79 TYPE Samples8v IS ARRAY(NATURAL RANGE <>) OF Samples8;
79 80
80 81 COMPONENT AD7688_drvr
81 82 GENERIC (
82 83 ChanelCount : INTEGER;
83 84 ncycle_cnv_high : INTEGER := 79;
84 85 ncycle_cnv : INTEGER := 500);
85 86 PORT (
86 87 cnv_clk : IN STD_LOGIC;
87 88 cnv_rstn : IN STD_LOGIC;
88 89 cnv_run : IN STD_LOGIC;
89 90 cnv : OUT STD_LOGIC;
90 91 clk : IN STD_LOGIC;
91 92 rstn : IN STD_LOGIC;
92 93 sck : OUT STD_LOGIC;
93 94 sdo : IN STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
94 95 sample : OUT Samples(ChanelCount-1 DOWNTO 0);
95 96 sample_val : OUT STD_LOGIC);
96 97 END COMPONENT;
97 98
98 99 COMPONENT RHF1401_drvr IS
99 100 GENERIC(
100 101 ChanelCount : INTEGER := 8);
101 102 PORT (
102 103 cnv_clk : IN STD_LOGIC;
103 104 clk : IN STD_LOGIC;
104 105 rstn : IN STD_LOGIC;
105 106 ADC_data : IN Samples14;
106 107 --ADC_smpclk : OUT STD_LOGIC;
107 108 ADC_nOE : OUT STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
108 109 sample : OUT Samples14v(ChanelCount-1 DOWNTO 0);
109 110 sample_val : OUT STD_LOGIC
110 111 );
111 112 END COMPONENT;
112 113
113 114 COMPONENT top_ad_conv_RHF1401
114 115 GENERIC (
115 116 ChanelCount : INTEGER;
116 117 ncycle_cnv_high : INTEGER := 79;
117 118 ncycle_cnv : INTEGER := 500);
118 119 PORT (
119 120 cnv_clk : IN STD_LOGIC;
120 121 cnv_rstn : IN STD_LOGIC;
121 122 cnv : OUT STD_LOGIC;
122 123 clk : IN STD_LOGIC;
123 124 rstn : IN STD_LOGIC;
124 125 ADC_data : IN Samples14;
125 126 ADC_nOE : OUT STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
126 127 sample : OUT Samples14v(ChanelCount-1 DOWNTO 0);
127 128 sample_val : OUT STD_LOGIC);
128 129 END COMPONENT;
129 130
130 131
131 132 COMPONENT AD7688_drvr_sync
132 133 GENERIC (
133 134 ChanelCount : INTEGER;
134 135 ncycle_cnv_high : INTEGER;
135 136 ncycle_cnv : INTEGER);
136 137 PORT (
137 138 cnv_clk : IN STD_LOGIC;
138 139 cnv_rstn : IN STD_LOGIC;
139 140 cnv_run : IN STD_LOGIC;
140 141 cnv : OUT STD_LOGIC;
141 142 sck : OUT STD_LOGIC;
142 143 sdo : IN STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
143 144 sample : OUT Samples(ChanelCount-1 DOWNTO 0);
144 145 sample_val : OUT STD_LOGIC);
145 146 END COMPONENT;
146 147
147 148 COMPONENT TestModule_RHF1401
148 149 GENERIC (
149 150 freq : INTEGER;
150 151 amplitude : INTEGER;
151 152 impulsion : INTEGER);
152 153 PORT (
153 154 ADC_smpclk : IN STD_LOGIC;
154 155 ADC_OEB_bar : IN STD_LOGIC;
155 156 ADC_data : OUT STD_LOGIC_VECTOR(13 DOWNTO 0));
156 157 END COMPONENT;
157 158
158 159 --COMPONENT AD7688_drvr IS
159 160 -- GENERIC(ChanelCount : INTEGER;
160 161 -- clkkHz : INTEGER);
161 162 -- PORT (clk : IN STD_LOGIC;
162 163 -- rstn : IN STD_LOGIC;
163 164 -- enable : IN STD_LOGIC;
164 165 -- smplClk : IN STD_LOGIC;
165 166 -- DataReady : OUT STD_LOGIC;
166 167 -- smpout : OUT Samples_out(ChanelCount-1 DOWNTO 0);
167 168 -- AD_in : IN AD7688_in(ChanelCount-1 DOWNTO 0);
168 169 -- AD_out : OUT AD7688_out);
169 170 --END COMPONENT;
170 171
171 172
172 173 --COMPONENT AD7688_spi_if IS
173 174 -- GENERIC(ChanelCount : INTEGER);
174 175 -- PORT(clk : IN STD_LOGIC;
175 176 -- reset : IN STD_LOGIC;
176 177 -- cnv : IN STD_LOGIC;
177 178 -- DataReady : OUT STD_LOGIC;
178 179 -- sdi : IN AD7688_in(ChanelCount-1 DOWNTO 0);
179 180 -- smpout : OUT Samples_out(ChanelCount-1 DOWNTO 0)
180 181 -- );
181 182 --END COMPONENT;
182 183
183 184
184 185 --COMPONENT lpp_apb_ad_conv
185 186 -- GENERIC(
186 187 -- pindex : INTEGER := 0;
187 188 -- paddr : INTEGER := 0;
188 189 -- pmask : INTEGER := 16#fff#;
189 190 -- pirq : INTEGER := 0;
190 191 -- abits : INTEGER := 8;
191 192 -- ChanelCount : INTEGER := 1;
192 193 -- clkkHz : INTEGER := 50000;
193 194 -- smpClkHz : INTEGER := 100;
194 195 -- ADCref : INTEGER := AD7688);
195 196 -- PORT (
196 197 -- clk : IN STD_LOGIC;
197 198 -- reset : IN STD_LOGIC;
198 199 -- apbi : IN apb_slv_in_type;
199 200 -- apbo : OUT apb_slv_out_type;
200 201 -- AD_in : IN AD7688_in(ChanelCount-1 DOWNTO 0);
201 202 -- AD_out : OUT AD7688_out);
202 203 --END COMPONENT;
203 204
204 205 --COMPONENT ADS7886_drvr IS
205 206 -- GENERIC(ChanelCount : INTEGER;
206 207 -- clkkHz : INTEGER);
207 208 -- PORT (
208 209 -- clk : IN STD_LOGIC;
209 210 -- reset : IN STD_LOGIC;
210 211 -- smplClk : IN STD_LOGIC;
211 212 -- DataReady : OUT STD_LOGIC;
212 213 -- smpout : OUT Samples_out(ChanelCount-1 DOWNTO 0);
213 214 -- AD_in : IN AD7688_in(ChanelCount-1 DOWNTO 0);
214 215 -- AD_out : OUT AD7688_out
215 216 -- );
216 217 --END COMPONENT;
217 218
218 219 --COMPONENT WriteGen_ADC IS
219 220 -- PORT(
220 221 -- clk : IN STD_LOGIC;
221 222 -- rstn : IN STD_LOGIC;
222 223 -- SmplCLK : IN STD_LOGIC;
223 224 -- DataReady : IN STD_LOGIC;
224 225 -- Full : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
225 226 -- ReUse : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
226 227 -- Write : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
227 228 -- );
228 229 --END COMPONENT;
229 230
230 231
231 232 --===========================================================|
232 233 --======================= ADS 127X =========================|
233 234 --===========================================================|
234 235
235 236 TYPE ADS127X_FORMAT_Type IS ARRAY(2 DOWNTO 0) OF STD_LOGIC;
236 237 CONSTANT ADS127X_SPI_FORMAT : ADS127X_FORMAT_Type := "010";
237 238 CONSTANT ADS127X_FSYNC_FORMAT : ADS127X_FORMAT_Type := "101";
238 239
239 240 TYPE ADS127X_MODE_Type IS ARRAY(1 DOWNTO 0) OF STD_LOGIC;
240 241 CONSTANT ADS127X_MODE_low_power : ADS127X_MODE_Type := "10";
241 242 CONSTANT ADS127X_MODE_low_speed : ADS127X_MODE_Type := "11";
242 243 CONSTANT ADS127X_MODE_high_resolution : ADS127X_MODE_Type := "01";
243 244
244 245 TYPE ADS127X_config IS
245 246 RECORD
246 247 SYNC : STD_LOGIC;
247 248 CLKDIV : STD_LOGIC;
248 249 FORMAT : ADS127X_FORMAT_Type;
249 250 MODE : ADS127X_MODE_Type;
250 251 END RECORD;
251 252
252 253 COMPONENT ADS1274_DRIVER IS
253 254 GENERIC(modeCfg : ADS127X_MODE_Type := ADS127X_MODE_low_power; formatCfg : ADS127X_FORMAT_Type := ADS127X_FSYNC_FORMAT);
254 255 PORT(
255 256 Clk : IN STD_LOGIC;
256 257 reset : IN STD_LOGIC;
257 258 SpiClk : OUT STD_LOGIC;
258 259 DIN : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
259 260 Ready : IN STD_LOGIC;
260 261 Format : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
261 262 Mode : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
262 263 ClkDiv : OUT STD_LOGIC;
263 264 PWDOWN : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
264 265 SmplClk : IN STD_LOGIC;
265 266 OUT0 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
266 267 OUT1 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
267 268 OUT2 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
268 269 OUT3 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
269 270 FSynch : OUT STD_LOGIC;
270 271 test : OUT STD_LOGIC
271 272 );
272 273 END COMPONENT;
273 274
274 275 -- todo clean file
275 276 COMPONENT DUAL_ADS1278_DRIVER IS
276 277 PORT(
277 278 Clk : IN STD_LOGIC;
278 279 reset : IN STD_LOGIC;
279 280 SpiClk : OUT STD_LOGIC;
280 281 DIN : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
281 282 SmplClk : IN STD_LOGIC;
282 283 OUT00 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
283 284 OUT01 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
284 285 OUT02 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
285 286 OUT03 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
286 287 OUT04 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
287 288 OUT05 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
288 289 OUT06 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
289 290 OUT07 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
290 291 OUT10 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
291 292 OUT11 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
292 293 OUT12 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
293 294 OUT13 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
294 295 OUT14 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
295 296 OUT15 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
296 297 OUT16 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
297 298 OUT17 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
298 299 FSynch : OUT STD_LOGIC
299 300 );
300 301 END COMPONENT;
301 302
302 303 --===========================================================|
303 304 -- DRIVER ADS7886
304 305 --===========================================================|
305 306 COMPONENT top_ad_conv_ADS7886_v2 IS
306 307 GENERIC(
307 308 ChannelCount : INTEGER := 8;
308 309 SampleNbBits : INTEGER := 14;
309 310 ncycle_cnv_high : INTEGER := 40; -- at least 32 cycles
310 311 ncycle_cnv : INTEGER := 500);
311 312 PORT (
312 313 -- CONV
313 314 cnv_clk : IN STD_LOGIC;
314 315 cnv_rstn : IN STD_LOGIC;
315 316 cnv : OUT STD_LOGIC;
316 317 -- DATA
317 318 clk : IN STD_LOGIC;
318 319 rstn : IN STD_LOGIC;
319 320 sck : OUT STD_LOGIC;
320 321 sdo : IN STD_LOGIC_VECTOR(ChannelCount-1 DOWNTO 0);
321 322 -- SAMPLE
322 323 sample : OUT Samples14v(ChannelCount-1 DOWNTO 0);
323 324 sample_val : OUT STD_LOGIC
324 325 );
325 326 END COMPONENT;
326 327
327 328 COMPONENT ADS7886_drvr_v2 IS
328 329 GENERIC(
329 330 ChannelCount : INTEGER := 8;
330 331 NbBitsSamples : INTEGER := 16);
331 332 PORT (
332 333 -- CONV --
333 334 cnv_clk : IN STD_LOGIC;
334 335 cnv_rstn : IN STD_LOGIC;
335 336 -- DATA --
336 337 clk : IN STD_LOGIC;
337 338 rstn : IN STD_LOGIC;
338 339 sck : OUT STD_LOGIC;
339 340 sdo : IN STD_LOGIC_VECTOR(ChannelCount-1 DOWNTO 0);
340 341 -- SAMPLE --
341 342 sample : OUT Samples(ChannelCount-1 DOWNTO 0);
342 343 sample_val : OUT STD_LOGIC
343 344 );
344 345 END COMPONENT;
345 346
346 347 COMPONENT top_ad_conv_RHF1401_withFilter
347 348 GENERIC (
348 349 ChanelCount : INTEGER;
349 350 ncycle_cnv_high : INTEGER;
350 351 ncycle_cnv : INTEGER);
351 352 PORT (
352 353 cnv_clk : IN STD_LOGIC;
353 354 cnv_rstn : IN STD_LOGIC;
354 355 cnv : OUT STD_LOGIC;
355 356 clk : IN STD_LOGIC;
356 357 rstn : IN STD_LOGIC;
357 358 ADC_data : IN Samples14;
358 359 ADC_nOE : OUT STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
359 360 sample : OUT Samples14v(ChanelCount-1 DOWNTO 0);
360 361 sample_val : OUT STD_LOGIC);
361 362 END COMPONENT;
362 363
363 364
364 365 END lpp_ad_conv;
365 366
366 367
367 368
368 369
369 370
370 371
371 372
372 373
Show file before | Show file after | Hide comments
@@ -1,509 +1,509
1 1 LIBRARY ieee;
2 2 USE ieee.std_logic_1164.ALL;
3 3 USE ieee.numeric_std.ALL;
4 4
5 5 LIBRARY lpp;
6 6 USE lpp.lpp_ad_conv.ALL;
7 7 USE lpp.iir_filter.ALL;
8 8 USE lpp.FILTERcfg.ALL;
9 9 USE lpp.lpp_memory.ALL;
10 10 USE lpp.lpp_waveform_pkg.ALL;
11 11 USE lpp.lpp_dma_pkg.ALL;
12 12 USE lpp.lpp_top_lfr_pkg.ALL;
13 13 USE lpp.lpp_lfr_pkg.ALL;
14 14 USE lpp.general_purpose.ALL;
15 15
16 16 LIBRARY techmap;
17 17 USE techmap.gencomp.ALL;
18 18
19 19 LIBRARY grlib;
20 20 USE grlib.amba.ALL;
21 21 USE grlib.stdlib.ALL;
22 22 USE grlib.devices.ALL;
23 23 USE GRLIB.DMA2AHB_Package.ALL;
24 24
25 25 ENTITY lpp_lfr IS
26 26 GENERIC (
27 27 Mem_use : INTEGER := use_RAM;
28 28 nb_data_by_buffer_size : INTEGER := 11;
29 29 nb_snapshot_param_size : INTEGER := 11;
30 30 delta_vector_size : INTEGER := 20;
31 31 delta_vector_size_f0_2 : INTEGER := 7;
32 32
33 33 pindex : INTEGER := 4;
34 34 paddr : INTEGER := 4;
35 35 pmask : INTEGER := 16#fff#;
36 36 pirq_ms : INTEGER := 0;
37 37 pirq_wfp : INTEGER := 1;
38 38
39 39 hindex : INTEGER := 2;
40 40
41 41 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0')
42 42
43 43 );
44 44 PORT (
45 45 clk : IN STD_LOGIC;
46 46 rstn : IN STD_LOGIC;
47 47 -- SAMPLE
48 48 sample_B : IN Samples(2 DOWNTO 0);
49 49 sample_E : IN Samples(4 DOWNTO 0);
50 50 sample_val : IN STD_LOGIC;
51 51 -- APB
52 52 apbi : IN apb_slv_in_type;
53 53 apbo : OUT apb_slv_out_type;
54 54 -- AHB
55 55 ahbi : IN AHB_Mst_In_Type;
56 56 ahbo : OUT AHB_Mst_Out_Type;
57 57 -- TIME
58 58 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
59 59 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
60 60 --
61 61 data_shaping_BW : OUT STD_LOGIC
62 62 );
63 63 END lpp_lfr;
64 64
65 65 ARCHITECTURE beh OF lpp_lfr IS
66 66 SIGNAL sample_s : Samples(7 DOWNTO 0);
67 67 --
68 68 SIGNAL data_shaping_SP0 : STD_LOGIC;
69 69 SIGNAL data_shaping_SP1 : STD_LOGIC;
70 70 SIGNAL data_shaping_R0 : STD_LOGIC;
71 71 SIGNAL data_shaping_R1 : STD_LOGIC;
72 72 SIGNAL data_shaping_R2 : STD_LOGIC;
73 73 --
74 74 SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
75 75 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
76 76 SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
77 77 --
78 78 SIGNAL sample_f0_val : STD_LOGIC;
79 79 SIGNAL sample_f1_val : STD_LOGIC;
80 80 SIGNAL sample_f2_val : STD_LOGIC;
81 81 SIGNAL sample_f3_val : STD_LOGIC;
82 82 --
83 83 SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
84 84 SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
85 85 SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
86 86 SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
87 87 --
88 88 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
89 89 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
90 90 SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
91 91
92 92 -- SM
93 93 SIGNAL ready_matrix_f0 : STD_LOGIC;
94 SIGNAL ready_matrix_f0_1 : STD_LOGIC;
94 -- SIGNAL ready_matrix_f0_1 : STD_LOGIC;
95 95 SIGNAL ready_matrix_f1 : STD_LOGIC;
96 96 SIGNAL ready_matrix_f2 : STD_LOGIC;
97 97 SIGNAL status_ready_matrix_f0 : STD_LOGIC;
98 SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
98 -- SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
99 99 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
100 100 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
101 101 SIGNAL addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
102 102 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
103 103 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
104 104 SIGNAL length_matrix_f0 : STD_LOGIC_VECTOR(25 DOWNTO 0);
105 105 SIGNAL length_matrix_f1 : STD_LOGIC_VECTOR(25 DOWNTO 0);
106 106 SIGNAL length_matrix_f2 : STD_LOGIC_VECTOR(25 DOWNTO 0);
107 107
108 108 -- WFP
109 109 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
110 110 SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
111 111 SIGNAL delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
112 112 SIGNAL delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
113 113 SIGNAL delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
114 114 SIGNAL delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
115 115
116 116 SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
117 117 SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
118 118 SIGNAL enable_f0 : STD_LOGIC;
119 119 SIGNAL enable_f1 : STD_LOGIC;
120 120 SIGNAL enable_f2 : STD_LOGIC;
121 121 SIGNAL enable_f3 : STD_LOGIC;
122 122 SIGNAL burst_f0 : STD_LOGIC;
123 123 SIGNAL burst_f1 : STD_LOGIC;
124 124 SIGNAL burst_f2 : STD_LOGIC;
125 125
126 126 --SIGNAL run : STD_LOGIC;
127 127 SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
128 128
129 129 -----------------------------------------------------------------------------
130 130 --
131 131 -----------------------------------------------------------------------------
132 SIGNAL data_f0_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
133 SIGNAL data_f0_data_out_valid_s : STD_LOGIC;
134 SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC;
132 -- SIGNAL data_f0_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
133 -- SIGNAL data_f0_data_out_valid_s : STD_LOGIC;
134 -- SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC;
135 135 --f1
136 SIGNAL data_f1_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
137 SIGNAL data_f1_data_out_valid_s : STD_LOGIC;
138 SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC;
136 -- SIGNAL data_f1_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
137 -- SIGNAL data_f1_data_out_valid_s : STD_LOGIC;
138 -- SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC;
139 139 --f2
140 SIGNAL data_f2_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
141 SIGNAL data_f2_data_out_valid_s : STD_LOGIC;
142 SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC;
140 -- SIGNAL data_f2_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
141 -- SIGNAL data_f2_data_out_valid_s : STD_LOGIC;
142 -- SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC;
143 143 --f3
144 SIGNAL data_f3_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
145 SIGNAL data_f3_data_out_valid_s : STD_LOGIC;
146 SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC;
144 -- SIGNAL data_f3_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
145 -- SIGNAL data_f3_data_out_valid_s : STD_LOGIC;
146 -- SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC;
147 147
148 148 SIGNAL wfp_status_buffer_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
149 SIGNAL wfp_addr_buffer : STD_LOGIC_VECTOR(32*4 DOWNTO 0);
149 SIGNAL wfp_addr_buffer : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
150 150 SIGNAL wfp_length_buffer : STD_LOGIC_VECTOR(25 DOWNTO 0);
151 151 SIGNAL wfp_ready_buffer : STD_LOGIC_VECTOR(3 DOWNTO 0);
152 152 SIGNAL wfp_buffer_time : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
153 153 SIGNAL wfp_error_buffer_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
154 154 -----------------------------------------------------------------------------
155 155 -- DMA RR
156 156 -----------------------------------------------------------------------------
157 SIGNAL dma_sel_valid : STD_LOGIC;
158 SIGNAL dma_rr_valid : STD_LOGIC_VECTOR(3 DOWNTO 0);
159 SIGNAL dma_rr_grant_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
160 SIGNAL dma_rr_grant_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
161 SIGNAL dma_rr_valid_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
157 -- SIGNAL dma_sel_valid : STD_LOGIC;
158 -- SIGNAL dma_rr_valid : STD_LOGIC_VECTOR(3 DOWNTO 0);
159 -- SIGNAL dma_rr_grant_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
160 -- SIGNAL dma_rr_grant_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
161 -- SIGNAL dma_rr_valid_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
162 162
163 SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(4 DOWNTO 0);
164 SIGNAL dma_sel : STD_LOGIC_VECTOR(4 DOWNTO 0);
163 -- SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(4 DOWNTO 0);
164 -- SIGNAL dma_sel : STD_LOGIC_VECTOR(4 DOWNTO 0);
165 165
166 166 -----------------------------------------------------------------------------
167 167 -- DMA_REG
168 168 -----------------------------------------------------------------------------
169 SIGNAL ongoing_reg : STD_LOGIC;
170 SIGNAL dma_sel_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
171 SIGNAL dma_send_reg : STD_LOGIC;
172 SIGNAL dma_valid_burst_reg : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
173 SIGNAL dma_address_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
174 SIGNAL dma_data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
169 -- SIGNAL ongoing_reg : STD_LOGIC;
170 -- SIGNAL dma_sel_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
171 -- SIGNAL dma_send_reg : STD_LOGIC;
172 -- SIGNAL dma_valid_burst_reg : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
173 -- SIGNAL dma_address_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
174 -- SIGNAL dma_data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
175 175
176 176
177 177 -----------------------------------------------------------------------------
178 178 -- DMA
179 179 -----------------------------------------------------------------------------
180 SIGNAL dma_send : STD_LOGIC;
181 SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
182 SIGNAL dma_done : STD_LOGIC;
183 SIGNAL dma_ren : STD_LOGIC;
184 SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0);
185 SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
186 SIGNAL dma_data_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
180 -- SIGNAL dma_send : STD_LOGIC;
181 -- SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
182 -- SIGNAL dma_done : STD_LOGIC;
183 -- SIGNAL dma_ren : STD_LOGIC;
184 -- SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0);
185 -- SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
186 -- SIGNAL dma_data_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
187 187
188 188 -----------------------------------------------------------------------------
189 189 -- MS
190 190 -----------------------------------------------------------------------------
191 191
192 SIGNAL data_ms_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
193 SIGNAL data_ms_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
194 SIGNAL data_ms_valid : STD_LOGIC;
195 SIGNAL data_ms_valid_burst : STD_LOGIC;
196 SIGNAL data_ms_ren : STD_LOGIC;
197 SIGNAL data_ms_done : STD_LOGIC;
198 SIGNAL dma_ms_ongoing : STD_LOGIC;
192 -- SIGNAL data_ms_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
193 -- SIGNAL data_ms_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
194 -- SIGNAL data_ms_valid : STD_LOGIC;
195 -- SIGNAL data_ms_valid_burst : STD_LOGIC;
196 -- SIGNAL data_ms_ren : STD_LOGIC;
197 -- SIGNAL data_ms_done : STD_LOGIC;
198 -- SIGNAL dma_ms_ongoing : STD_LOGIC;
199 199
200 200 -- SIGNAL run_ms : STD_LOGIC;
201 SIGNAL ms_softandhard_rstn : STD_LOGIC;
201 -- SIGNAL ms_softandhard_rstn : STD_LOGIC;
202 202
203 203 SIGNAL matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
204 204 -- SIGNAL matrix_time_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
205 205 SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
206 206 SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
207 207
208 208
209 209 SIGNAL error_buffer_full : STD_LOGIC;
210 210 SIGNAL error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0);
211 211
212 212 -- SIGNAL debug_ms : STD_LOGIC_VECTOR(31 DOWNTO 0);
213 SIGNAL debug_signal : STD_LOGIC_VECTOR(31 DOWNTO 0);
213 -- SIGNAL debug_signal : STD_LOGIC_VECTOR(31 DOWNTO 0);
214 214
215 215 -----------------------------------------------------------------------------
216 216 SIGNAL dma_fifo_burst_valid : STD_LOGIC_VECTOR(4 DOWNTO 0);
217 217 SIGNAL dma_fifo_data : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
218 218 SIGNAL dma_fifo_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
219 219 SIGNAL dma_buffer_new : STD_LOGIC_VECTOR(4 DOWNTO 0);
220 220 SIGNAL dma_buffer_addr : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
221 221 SIGNAL dma_buffer_length : STD_LOGIC_VECTOR(26*5-1 DOWNTO 0);
222 222 SIGNAL dma_buffer_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
223 223 SIGNAL dma_buffer_full_err : STD_LOGIC_VECTOR(4 DOWNTO 0);
224 224 SIGNAL dma_grant_error : STD_LOGIC;
225 225
226 226 -----------------------------------------------------------------------------
227 227 -- SIGNAL run_dma : STD_LOGIC;
228 228 BEGIN
229 229
230 230 sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
231 231 sample_s(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
232 232
233 233 --all_channel : FOR i IN 7 DOWNTO 0 GENERATE
234 234 -- sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i);
235 235 --END GENERATE all_channel;
236 236
237 237 -----------------------------------------------------------------------------
238 238 lpp_lfr_filter_1 : lpp_lfr_filter
239 239 GENERIC MAP (
240 240 Mem_use => Mem_use)
241 241 PORT MAP (
242 242 sample => sample_s,
243 243 sample_val => sample_val,
244 244 clk => clk,
245 245 rstn => rstn,
246 246 data_shaping_SP0 => data_shaping_SP0,
247 247 data_shaping_SP1 => data_shaping_SP1,
248 248 data_shaping_R0 => data_shaping_R0,
249 249 data_shaping_R1 => data_shaping_R1,
250 250 data_shaping_R2 => data_shaping_R2,
251 251 sample_f0_val => sample_f0_val,
252 252 sample_f1_val => sample_f1_val,
253 253 sample_f2_val => sample_f2_val,
254 254 sample_f3_val => sample_f3_val,
255 255 sample_f0_wdata => sample_f0_data,
256 256 sample_f1_wdata => sample_f1_data,
257 257 sample_f2_wdata => sample_f2_data,
258 258 sample_f3_wdata => sample_f3_data);
259 259
260 260 -----------------------------------------------------------------------------
261 261 lpp_lfr_apbreg_1 : lpp_lfr_apbreg
262 262 GENERIC MAP (
263 263 nb_data_by_buffer_size => nb_data_by_buffer_size,
264 264 -- nb_word_by_buffer_size => nb_word_by_buffer_size, -- TODO
265 265 nb_snapshot_param_size => nb_snapshot_param_size,
266 266 delta_vector_size => delta_vector_size,
267 267 delta_vector_size_f0_2 => delta_vector_size_f0_2,
268 268 pindex => pindex,
269 269 paddr => paddr,
270 270 pmask => pmask,
271 271 pirq_ms => pirq_ms,
272 272 pirq_wfp => pirq_wfp,
273 273 top_lfr_version => top_lfr_version)
274 274 PORT MAP (
275 275 HCLK => clk,
276 276 HRESETn => rstn,
277 277 apbi => apbi,
278 278 apbo => apbo,
279 279
280 280 run_ms => OPEN,--run_ms,
281 281
282 282 ready_matrix_f0 => ready_matrix_f0,
283 283 ready_matrix_f1 => ready_matrix_f1,
284 284 ready_matrix_f2 => ready_matrix_f2,
285 285 error_buffer_full => error_buffer_full, -- TODO
286 286 error_input_fifo_write => error_input_fifo_write, -- TODO
287 287 status_ready_matrix_f0 => status_ready_matrix_f0,
288 288 status_ready_matrix_f1 => status_ready_matrix_f1,
289 289 status_ready_matrix_f2 => status_ready_matrix_f2,
290 290
291 291 matrix_time_f0 => matrix_time_f0,
292 292 matrix_time_f1 => matrix_time_f1,
293 293 matrix_time_f2 => matrix_time_f2,
294 294
295 295 addr_matrix_f0 => addr_matrix_f0,
296 296 addr_matrix_f1 => addr_matrix_f1,
297 297 addr_matrix_f2 => addr_matrix_f2,
298 298
299 299 length_matrix_f0 => length_matrix_f0,
300 300 length_matrix_f1 => length_matrix_f1,
301 301 length_matrix_f2 => length_matrix_f2,
302 302 -------------------------------------------------------------------------
303 303 --status_full => status_full, -- TODo
304 304 --status_full_ack => status_full_ack, -- TODo
305 305 --status_full_err => status_full_err, -- TODo
306 306 status_new_err => status_new_err,
307 307 data_shaping_BW => data_shaping_BW,
308 308 data_shaping_SP0 => data_shaping_SP0,
309 309 data_shaping_SP1 => data_shaping_SP1,
310 310 data_shaping_R0 => data_shaping_R0,
311 311 data_shaping_R1 => data_shaping_R1,
312 312 data_shaping_R2 => data_shaping_R2,
313 313 delta_snapshot => delta_snapshot,
314 314 delta_f0 => delta_f0,
315 315 delta_f0_2 => delta_f0_2,
316 316 delta_f1 => delta_f1,
317 317 delta_f2 => delta_f2,
318 318 nb_data_by_buffer => nb_data_by_buffer,
319 319 -- nb_word_by_buffer => nb_word_by_buffer, -- TODO
320 320 nb_snapshot_param => nb_snapshot_param,
321 321 enable_f0 => enable_f0,
322 322 enable_f1 => enable_f1,
323 323 enable_f2 => enable_f2,
324 324 enable_f3 => enable_f3,
325 325 burst_f0 => burst_f0,
326 326 burst_f1 => burst_f1,
327 327 burst_f2 => burst_f2,
328 328 run => OPEN, --run,
329 329 start_date => start_date,
330 330 -- debug_signal => debug_signal,
331 331 wfp_status_buffer_ready => wfp_status_buffer_ready,-- TODO
332 332 wfp_addr_buffer => wfp_addr_buffer,-- TODO
333 333 wfp_length_buffer => wfp_length_buffer,-- TODO
334 334
335 335 wfp_ready_buffer => wfp_ready_buffer,-- TODO
336 336 wfp_buffer_time => wfp_buffer_time,-- TODO
337 337 wfp_error_buffer_full => wfp_error_buffer_full -- TODO
338 338 );
339 339
340 340 -----------------------------------------------------------------------------
341 341 -----------------------------------------------------------------------------
342 342 lpp_waveform_1 : lpp_waveform
343 343 GENERIC MAP (
344 344 tech => inferred,
345 345 data_size => 6*16,
346 346 nb_data_by_buffer_size => nb_data_by_buffer_size,
347 347 nb_snapshot_param_size => nb_snapshot_param_size,
348 348 delta_vector_size => delta_vector_size,
349 349 delta_vector_size_f0_2 => delta_vector_size_f0_2
350 350 )
351 351 PORT MAP (
352 352 clk => clk,
353 353 rstn => rstn,
354 354
355 355 reg_run => '1',--run,
356 356 reg_start_date => start_date,
357 357 reg_delta_snapshot => delta_snapshot,
358 358 reg_delta_f0 => delta_f0,
359 359 reg_delta_f0_2 => delta_f0_2,
360 360 reg_delta_f1 => delta_f1,
361 361 reg_delta_f2 => delta_f2,
362 362
363 363 enable_f0 => enable_f0,
364 364 enable_f1 => enable_f1,
365 365 enable_f2 => enable_f2,
366 366 enable_f3 => enable_f3,
367 367 burst_f0 => burst_f0,
368 368 burst_f1 => burst_f1,
369 369 burst_f2 => burst_f2,
370 370
371 371 nb_data_by_buffer => nb_data_by_buffer,
372 372 nb_snapshot_param => nb_snapshot_param,
373 373 status_new_err => status_new_err,
374 374
375 375 status_buffer_ready => wfp_status_buffer_ready,
376 376 addr_buffer => wfp_addr_buffer,
377 377 length_buffer => wfp_length_buffer,
378 378 ready_buffer => wfp_ready_buffer,
379 379 buffer_time => wfp_buffer_time,
380 380 error_buffer_full => wfp_error_buffer_full,
381 381
382 382 coarse_time => coarse_time,
383 383 fine_time => fine_time,
384 384
385 385 --f0
386 386 data_f0_in_valid => sample_f0_val,
387 387 data_f0_in => sample_f0_data,
388 388 --f1
389 389 data_f1_in_valid => sample_f1_val,
390 390 data_f1_in => sample_f1_data,
391 391 --f2
392 392 data_f2_in_valid => sample_f2_val,
393 393 data_f2_in => sample_f2_data,
394 394 --f3
395 395 data_f3_in_valid => sample_f3_val,
396 396 data_f3_in => sample_f3_data,
397 397 -- OUTPUT -- DMA interface
398 398
399 399 dma_fifo_valid_burst => dma_fifo_burst_valid(3 DOWNTO 0),
400 400 dma_fifo_data => dma_fifo_data(32*4-1 DOWNTO 0),
401 401 dma_fifo_ren => dma_fifo_ren(3 DOWNTO 0),
402 402 dma_buffer_new => dma_buffer_new(3 DOWNTO 0),
403 403 dma_buffer_addr => dma_buffer_addr(32*4-1 DOWNTO 0),
404 404 dma_buffer_length => dma_buffer_length(26*4-1 DOWNTO 0),
405 405 dma_buffer_full => dma_buffer_full(3 DOWNTO 0),
406 406 dma_buffer_full_err => dma_buffer_full_err(3 DOWNTO 0)
407 407
408 408 );
409 409
410 410 -----------------------------------------------------------------------------
411 411 -- Matrix Spectral
412 412 -----------------------------------------------------------------------------
413 413 sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) &
414 414 NOT(sample_f0_val) & NOT(sample_f0_val);
415 415 sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) &
416 416 NOT(sample_f1_val) & NOT(sample_f1_val);
417 417 sample_f2_wen <= NOT(sample_f2_val) & NOT(sample_f2_val) & NOT(sample_f2_val) &
418 418 NOT(sample_f2_val) & NOT(sample_f2_val);
419 419
420 420 sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB)
421 421 sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16));
422 422 sample_f2_wdata <= sample_f2_data((3*16)-1 DOWNTO (1*16)) & sample_f2_data((6*16)-1 DOWNTO (3*16));
423 423
424 424 -------------------------------------------------------------------------------
425 425
426 426 --ms_softandhard_rstn <= rstn AND run_ms AND run;
427 427
428 428 -----------------------------------------------------------------------------
429 429 lpp_lfr_ms_1 : lpp_lfr_ms
430 430 GENERIC MAP (
431 431 Mem_use => Mem_use)
432 432 PORT MAP (
433 433 clk => clk,
434 434 --rstn => ms_softandhard_rstn, --rstn,
435 435 rstn => rstn,
436 436
437 437 run => '1',--run_ms,
438 438
439 439 start_date => start_date,
440 440
441 441 coarse_time => coarse_time,
442 442 fine_time => fine_time,
443 443
444 444 sample_f0_wen => sample_f0_wen,
445 445 sample_f0_wdata => sample_f0_wdata,
446 446 sample_f1_wen => sample_f1_wen,
447 447 sample_f1_wdata => sample_f1_wdata,
448 448 sample_f2_wen => sample_f2_wen,
449 449 sample_f2_wdata => sample_f2_wdata,
450 450
451 451 --DMA
452 452 dma_fifo_burst_valid => dma_fifo_burst_valid(4), -- OUT
453 453 dma_fifo_data => dma_fifo_data((4+1)*32-1 DOWNTO 4*32), -- OUT
454 454 dma_fifo_ren => dma_fifo_ren(4), -- IN
455 455 dma_buffer_new => dma_buffer_new(4), -- OUT
456 456 dma_buffer_addr => dma_buffer_addr((4+1)*32-1 DOWNTO 4*32), -- OUT
457 457 dma_buffer_length => dma_buffer_length((4+1)*26-1 DOWNTO 4*26), -- OUT
458 458 dma_buffer_full => dma_buffer_full(4), -- IN
459 459 dma_buffer_full_err => dma_buffer_full_err(4), -- IN
460 460
461 461
462 462
463 463 --REG
464 464 ready_matrix_f0 => ready_matrix_f0,
465 465 ready_matrix_f1 => ready_matrix_f1,
466 466 ready_matrix_f2 => ready_matrix_f2,
467 467 error_buffer_full => error_buffer_full,
468 468 error_input_fifo_write => error_input_fifo_write,
469 469
470 470 status_ready_matrix_f0 => status_ready_matrix_f0,
471 471 status_ready_matrix_f1 => status_ready_matrix_f1,
472 472 status_ready_matrix_f2 => status_ready_matrix_f2,
473 473 addr_matrix_f0 => addr_matrix_f0,
474 474 addr_matrix_f1 => addr_matrix_f1,
475 475 addr_matrix_f2 => addr_matrix_f2,
476 476
477 477 length_matrix_f0 => length_matrix_f0,
478 478 length_matrix_f1 => length_matrix_f1,
479 479 length_matrix_f2 => length_matrix_f2,
480 480
481 481 matrix_time_f0 => matrix_time_f0,
482 482 matrix_time_f1 => matrix_time_f1,
483 483 matrix_time_f2 => matrix_time_f2);
484 484
485 485 -----------------------------------------------------------------------------
486 486 --run_dma <= run_ms OR run;
487 487
488 488 DMA_SubSystem_1 : DMA_SubSystem
489 489 GENERIC MAP (
490 490 hindex => hindex)
491 491 PORT MAP (
492 492 clk => clk,
493 493 rstn => rstn,
494 494 run => '1',--run_dma,
495 495 ahbi => ahbi,
496 496 ahbo => ahbo,
497 497
498 498 fifo_burst_valid => dma_fifo_burst_valid, --fifo_burst_valid,
499 499 fifo_data => dma_fifo_data, --fifo_data,
500 500 fifo_ren => dma_fifo_ren, --fifo_ren,
501 501
502 502 buffer_new => dma_buffer_new, --buffer_new,
503 503 buffer_addr => dma_buffer_addr, --buffer_addr,
504 504 buffer_length => dma_buffer_length, --buffer_length,
505 505 buffer_full => dma_buffer_full, --buffer_full,
506 506 buffer_full_err => dma_buffer_full_err, --buffer_full_err,
507 507 grant_error => dma_grant_error); --grant_error);
508 508
509 509 END beh;
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@@ -1,781 +1,781
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -- jean-christophe.pellion@easii-ic.com
22 22 -------------------------------------------------------------------------------
23 23 LIBRARY ieee;
24 24 USE ieee.std_logic_1164.ALL;
25 25 USE ieee.numeric_std.ALL;
26 26
27 27 LIBRARY grlib;
28 28 USE grlib.amba.ALL;
29 29 USE grlib.stdlib.ALL;
30 30 USE grlib.devices.ALL;
31 31
32 32 LIBRARY lpp;
33 33 USE lpp.lpp_lfr_pkg.ALL;
34 34 USE lpp.apb_devices_list.ALL;
35 35 USE lpp.lpp_memory.ALL;
36 36 USE lpp.lpp_lfr_apbreg_pkg.ALL;
37 37
38 38 LIBRARY techmap;
39 39 USE techmap.gencomp.ALL;
40 40
41 41 ENTITY lpp_lfr_apbreg IS
42 42 GENERIC (
43 43 nb_data_by_buffer_size : INTEGER := 11;
44 44 nb_snapshot_param_size : INTEGER := 11;
45 45 delta_vector_size : INTEGER := 20;
46 46 delta_vector_size_f0_2 : INTEGER := 3;
47 47
48 48 pindex : INTEGER := 4;
49 49 paddr : INTEGER := 4;
50 50 pmask : INTEGER := 16#fff#;
51 51 pirq_ms : INTEGER := 0;
52 52 pirq_wfp : INTEGER := 1;
53 53 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := X"000000");
54 54 PORT (
55 55 -- AMBA AHB system signals
56 56 HCLK : IN STD_ULOGIC;
57 57 HRESETn : IN STD_ULOGIC;
58 58
59 59 -- AMBA APB Slave Interface
60 60 apbi : IN apb_slv_in_type;
61 61 apbo : OUT apb_slv_out_type;
62 62
63 63 ---------------------------------------------------------------------------
64 64 -- Spectral Matrix Reg
65 65 run_ms : OUT STD_LOGIC;
66 66 -- IN
67 67 ready_matrix_f0 : IN STD_LOGIC;
68 68 ready_matrix_f1 : IN STD_LOGIC;
69 69 ready_matrix_f2 : IN STD_LOGIC;
70 70
71 71 -- error_bad_component_error : IN STD_LOGIC;
72 72 error_buffer_full : IN STD_LOGIC; -- TODO
73 73 error_input_fifo_write : IN STD_LOGIC_VECTOR(2 DOWNTO 0); -- TODO
74 74
75 75 -- debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
76 76
77 77 -- OUT
78 78 status_ready_matrix_f0 : OUT STD_LOGIC;
79 79 status_ready_matrix_f1 : OUT STD_LOGIC;
80 80 status_ready_matrix_f2 : OUT STD_LOGIC;
81 81
82 82 --config_active_interruption_onNewMatrix : OUT STD_LOGIC;
83 83 --config_active_interruption_onError : OUT STD_LOGIC;
84 84
85 85 addr_matrix_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
86 86 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
87 87 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
88 88
89 89 length_matrix_f0 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
90 90 length_matrix_f1 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
91 91 length_matrix_f2 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
92 92
93 93 matrix_time_f0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
94 94 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
95 95 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
96 96
97 97 ---------------------------------------------------------------------------
98 98 ---------------------------------------------------------------------------
99 99 -- WaveForm picker Reg
100 100 --status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
101 101 --status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
102 102 --status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
103 103 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
104 104
105 105 -- OUT
106 106 data_shaping_BW : OUT STD_LOGIC;
107 107 data_shaping_SP0 : OUT STD_LOGIC;
108 108 data_shaping_SP1 : OUT STD_LOGIC;
109 109 data_shaping_R0 : OUT STD_LOGIC;
110 110 data_shaping_R1 : OUT STD_LOGIC;
111 111 data_shaping_R2 : OUT STD_LOGIC;
112 112
113 113 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
114 114 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
115 115 delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
116 116 delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
117 117 delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
118 118 nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
119 119 --nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
120 120 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
121 121
122 122 enable_f0 : OUT STD_LOGIC;
123 123 enable_f1 : OUT STD_LOGIC;
124 124 enable_f2 : OUT STD_LOGIC;
125 125 enable_f3 : OUT STD_LOGIC;
126 126
127 127 burst_f0 : OUT STD_LOGIC;
128 128 burst_f1 : OUT STD_LOGIC;
129 129 burst_f2 : OUT STD_LOGIC;
130 130
131 131 run : OUT STD_LOGIC;
132 132
133 133 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
134 134
135 135 wfp_status_buffer_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
136 wfp_addr_buffer : OUT STD_LOGIC_VECTOR(32*4 DOWNTO 0);
136 wfp_addr_buffer : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
137 137 wfp_length_buffer : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
138 138 wfp_ready_buffer : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
139 139 wfp_buffer_time : IN STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
140 140 wfp_error_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0)
141 141
142 142 );
143 143
144 144 END lpp_lfr_apbreg;
145 145
146 146 ARCHITECTURE beh OF lpp_lfr_apbreg IS
147 147
148 148 CONSTANT REVISION : INTEGER := 1;
149 149
150 150 CONSTANT pconfig : apb_config_type := (
151 151 0 => ahb_device_reg (lpp.apb_devices_list.VENDOR_LPP, lpp.apb_devices_list.LPP_LFR, 0, REVISION, pirq_wfp),
152 152 1 => apb_iobar(paddr, pmask));
153 153
154 154 --CONSTANT pconfig : apb_config_type := (
155 155 -- 0 => ahb_device_reg (16#19#, 16#19#, 0, REVISION, pirq_wfp),
156 156 -- 1 => apb_iobar(paddr, pmask));
157 157
158 158 TYPE lpp_SpectralMatrix_regs IS RECORD
159 159 config_active_interruption_onNewMatrix : STD_LOGIC;
160 160 config_active_interruption_onError : STD_LOGIC;
161 161 config_ms_run : STD_LOGIC;
162 162 status_ready_matrix_f0_0 : STD_LOGIC;
163 163 status_ready_matrix_f1_0 : STD_LOGIC;
164 164 status_ready_matrix_f2_0 : STD_LOGIC;
165 165 status_ready_matrix_f0_1 : STD_LOGIC;
166 166 status_ready_matrix_f1_1 : STD_LOGIC;
167 167 status_ready_matrix_f2_1 : STD_LOGIC;
168 168 -- status_error_bad_component_error : STD_LOGIC;
169 169 status_error_buffer_full : STD_LOGIC;
170 170 status_error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0);
171 171
172 172 addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
173 173 addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
174 174 addr_matrix_f1_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
175 175 addr_matrix_f1_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
176 176 addr_matrix_f2_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
177 177 addr_matrix_f2_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
178 178
179 179 length_matrix : STD_LOGIC_VECTOR(25 DOWNTO 0);
180 180
181 181 time_matrix_f0_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
182 182 time_matrix_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
183 183 time_matrix_f1_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
184 184 time_matrix_f1_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
185 185 time_matrix_f2_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
186 186 time_matrix_f2_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
187 187 END RECORD;
188 188 SIGNAL reg_sp : lpp_SpectralMatrix_regs;
189 189
190 190 TYPE lpp_WaveformPicker_regs IS RECORD
191 191 -- status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
192 192 -- status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
193 193 status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
194 194 data_shaping_BW : STD_LOGIC;
195 195 data_shaping_SP0 : STD_LOGIC;
196 196 data_shaping_SP1 : STD_LOGIC;
197 197 data_shaping_R0 : STD_LOGIC;
198 198 data_shaping_R1 : STD_LOGIC;
199 199 data_shaping_R2 : STD_LOGIC;
200 200 delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
201 201 delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
202 202 delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
203 203 delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
204 204 delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
205 205 nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
206 206 -- nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
207 207 nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
208 208 enable_f0 : STD_LOGIC;
209 209 enable_f1 : STD_LOGIC;
210 210 enable_f2 : STD_LOGIC;
211 211 enable_f3 : STD_LOGIC;
212 212 burst_f0 : STD_LOGIC;
213 213 burst_f1 : STD_LOGIC;
214 214 burst_f2 : STD_LOGIC;
215 215 run : STD_LOGIC;
216 216 status_ready_buffer_f : STD_LOGIC_VECTOR(4*2-1 DOWNTO 0);
217 217 addr_buffer_f : STD_LOGIC_VECTOR(4*2*32-1 DOWNTO 0);
218 218 time_buffer_f : STD_LOGIC_VECTOR(4*2*48-1 DOWNTO 0);
219 219 length_buffer : STD_LOGIC_VECTOR(25 DOWNTO 0);
220 220 error_buffer_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
221 221 start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
222 222 END RECORD;
223 223 SIGNAL reg_wp : lpp_WaveformPicker_regs;
224 224
225 225 SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
226 226
227 227 -----------------------------------------------------------------------------
228 228 -- IRQ
229 229 -----------------------------------------------------------------------------
230 230 CONSTANT IRQ_WFP_SIZE : INTEGER := 12;
231 231 SIGNAL irq_wfp_ZERO : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
232 232 SIGNAL irq_wfp_reg_s : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
233 233 SIGNAL irq_wfp_reg : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
234 234 SIGNAL irq_wfp : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
235 235 SIGNAL ored_irq_wfp : STD_LOGIC;
236 236
237 237 -----------------------------------------------------------------------------
238 238 --
239 239 -----------------------------------------------------------------------------
240 240 SIGNAL reg0_ready_matrix_f0 : STD_LOGIC;
241 SIGNAL reg0_addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
242 SIGNAL reg0_matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
241 -- SIGNAL reg0_addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
242 -- SIGNAL reg0_matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
243 243
244 244 SIGNAL reg1_ready_matrix_f0 : STD_LOGIC;
245 SIGNAL reg1_addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
246 SIGNAL reg1_matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
245 -- SIGNAL reg1_addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
246 -- SIGNAL reg1_matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
247 247
248 248 SIGNAL reg0_ready_matrix_f1 : STD_LOGIC;
249 SIGNAL reg0_addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
250 SIGNAL reg0_matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
249 -- SIGNAL reg0_addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
250 -- SIGNAL reg0_matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
251 251
252 252 SIGNAL reg1_ready_matrix_f1 : STD_LOGIC;
253 SIGNAL reg1_addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
254 SIGNAL reg1_matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
253 -- SIGNAL reg1_addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
254 -- SIGNAL reg1_matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
255 255
256 256 SIGNAL reg0_ready_matrix_f2 : STD_LOGIC;
257 SIGNAL reg0_addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
258 SIGNAL reg0_matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
257 -- SIGNAL reg0_addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
258 -- SIGNAL reg0_matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
259 259
260 260 SIGNAL reg1_ready_matrix_f2 : STD_LOGIC;
261 SIGNAL reg1_addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
262 SIGNAL reg1_matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
261 -- SIGNAL reg1_addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
262 -- SIGNAL reg1_matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
263 263 SIGNAL apbo_irq_ms : STD_LOGIC;
264 264 SIGNAL apbo_irq_wfp : STD_LOGIC;
265 265 -----------------------------------------------------------------------------
266 266 SIGNAL reg_ready_buffer_f : STD_LOGIC_VECTOR( 2*4-1 DOWNTO 0);
267 267
268 268 SIGNAL pirq_temp : STD_LOGIC_VECTOR(31 DOWNTO 0);
269 269
270 270 BEGIN -- beh
271 271
272 272 -- status_ready_matrix_f0 <= reg_sp.status_ready_matrix_f0;
273 273 -- status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1;
274 274 -- status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2;
275 275
276 276 -- config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix;
277 277 -- config_active_interruption_onError <= reg_sp.config_active_interruption_onError;
278 278
279 279
280 280 -- addr_matrix_f0 <= reg_sp.addr_matrix_f0;
281 281 -- addr_matrix_f1 <= reg_sp.addr_matrix_f1;
282 282 -- addr_matrix_f2 <= reg_sp.addr_matrix_f2;
283 283
284 284
285 285 data_shaping_BW <= NOT reg_wp.data_shaping_BW;
286 286 data_shaping_SP0 <= reg_wp.data_shaping_SP0;
287 287 data_shaping_SP1 <= reg_wp.data_shaping_SP1;
288 288 data_shaping_R0 <= reg_wp.data_shaping_R0;
289 289 data_shaping_R1 <= reg_wp.data_shaping_R1;
290 290 data_shaping_R2 <= reg_wp.data_shaping_R2;
291 291
292 292 delta_snapshot <= reg_wp.delta_snapshot;
293 293 delta_f0 <= reg_wp.delta_f0;
294 294 delta_f0_2 <= reg_wp.delta_f0_2;
295 295 delta_f1 <= reg_wp.delta_f1;
296 296 delta_f2 <= reg_wp.delta_f2;
297 297 nb_data_by_buffer <= reg_wp.nb_data_by_buffer;
298 298 nb_snapshot_param <= reg_wp.nb_snapshot_param;
299 299
300 300 enable_f0 <= reg_wp.enable_f0;
301 301 enable_f1 <= reg_wp.enable_f1;
302 302 enable_f2 <= reg_wp.enable_f2;
303 303 enable_f3 <= reg_wp.enable_f3;
304 304
305 305 burst_f0 <= reg_wp.burst_f0;
306 306 burst_f1 <= reg_wp.burst_f1;
307 307 burst_f2 <= reg_wp.burst_f2;
308 308
309 309 run <= reg_wp.run;
310 310
311 311 --addr_data_f0 <= reg_wp.addr_data_f0;
312 312 --addr_data_f1 <= reg_wp.addr_data_f1;
313 313 --addr_data_f2 <= reg_wp.addr_data_f2;
314 314 --addr_data_f3 <= reg_wp.addr_data_f3;
315 315
316 316 start_date <= reg_wp.start_date;
317 317
318 318 length_matrix_f0 <= reg_sp.length_matrix;
319 319 length_matrix_f1 <= reg_sp.length_matrix;
320 320 length_matrix_f2 <= reg_sp.length_matrix;
321 321 wfp_length_buffer <= reg_wp.length_buffer;
322 322
323 323
324 324 lpp_lfr_apbreg : PROCESS (HCLK, HRESETn)
325 325 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
326 326 BEGIN -- PROCESS lpp_dma_top
327 327 IF HRESETn = '0' THEN -- asynchronous reset (active low)
328 328 reg_sp.config_active_interruption_onNewMatrix <= '0';
329 329 reg_sp.config_active_interruption_onError <= '0';
330 330 reg_sp.config_ms_run <= '0';
331 331 reg_sp.status_ready_matrix_f0_0 <= '0';
332 332 reg_sp.status_ready_matrix_f1_0 <= '0';
333 333 reg_sp.status_ready_matrix_f2_0 <= '0';
334 334 reg_sp.status_ready_matrix_f0_1 <= '0';
335 335 reg_sp.status_ready_matrix_f1_1 <= '0';
336 336 reg_sp.status_ready_matrix_f2_1 <= '0';
337 337 reg_sp.status_error_buffer_full <= '0';
338 338 reg_sp.status_error_input_fifo_write <= (OTHERS => '0');
339 339
340 340 reg_sp.addr_matrix_f0_0 <= (OTHERS => '0');
341 341 reg_sp.addr_matrix_f1_0 <= (OTHERS => '0');
342 342 reg_sp.addr_matrix_f2_0 <= (OTHERS => '0');
343 343
344 344 reg_sp.addr_matrix_f0_1 <= (OTHERS => '0');
345 345 reg_sp.addr_matrix_f1_1 <= (OTHERS => '0');
346 346 reg_sp.addr_matrix_f2_1 <= (OTHERS => '0');
347 347
348 348 reg_sp.length_matrix <= (OTHERS => '0');
349 349
350 350 -- reg_sp.time_matrix_f0_0 <= (OTHERS => '0'); -- ok
351 351 -- reg_sp.time_matrix_f1_0 <= (OTHERS => '0'); -- ok
352 352 -- reg_sp.time_matrix_f2_0 <= (OTHERS => '0'); -- ok
353 353
354 354 -- reg_sp.time_matrix_f0_1 <= (OTHERS => '0'); -- ok
355 355 --reg_sp.time_matrix_f1_1 <= (OTHERS => '0'); -- ok
356 356 -- reg_sp.time_matrix_f2_1 <= (OTHERS => '0'); -- ok
357 357
358 358 prdata <= (OTHERS => '0');
359 359
360 360
361 361 apbo_irq_ms <= '0';
362 362 apbo_irq_wfp <= '0';
363 363
364 364
365 365 -- status_full_ack <= (OTHERS => '0');
366 366
367 367 reg_wp.data_shaping_BW <= '0';
368 368 reg_wp.data_shaping_SP0 <= '0';
369 369 reg_wp.data_shaping_SP1 <= '0';
370 370 reg_wp.data_shaping_R0 <= '0';
371 371 reg_wp.data_shaping_R1 <= '0';
372 372 reg_wp.data_shaping_R2 <= '0';
373 373 reg_wp.enable_f0 <= '0';
374 374 reg_wp.enable_f1 <= '0';
375 375 reg_wp.enable_f2 <= '0';
376 376 reg_wp.enable_f3 <= '0';
377 377 reg_wp.burst_f0 <= '0';
378 378 reg_wp.burst_f1 <= '0';
379 379 reg_wp.burst_f2 <= '0';
380 380 reg_wp.run <= '0';
381 381 -- reg_wp.status_full <= (OTHERS => '0');
382 382 -- reg_wp.status_full_err <= (OTHERS => '0');
383 383 reg_wp.status_new_err <= (OTHERS => '0');
384 384 reg_wp.error_buffer_full <= (OTHERS => '0');
385 385 reg_wp.delta_snapshot <= (OTHERS => '0');
386 386 reg_wp.delta_f0 <= (OTHERS => '0');
387 387 reg_wp.delta_f0_2 <= (OTHERS => '0');
388 388 reg_wp.delta_f1 <= (OTHERS => '0');
389 389 reg_wp.delta_f2 <= (OTHERS => '0');
390 390 reg_wp.nb_data_by_buffer <= (OTHERS => '0');
391 391 reg_wp.nb_snapshot_param <= (OTHERS => '0');
392 392 reg_wp.start_date <= (OTHERS => '1');
393 393
394 394 reg_wp.status_ready_buffer_f <= (OTHERS => '0');
395 395 reg_wp.length_buffer <= (OTHERS => '0');
396 396
397 397 pirq_temp <= (OTHERS => '0');
398 398
399 399 reg_wp.addr_buffer_f <= (OTHERS => '0');
400 400
401 401 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
402 402
403 403 -- status_full_ack <= (OTHERS => '0');
404 404
405 405 reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR reg0_ready_matrix_f0;
406 406 reg_sp.status_ready_matrix_f1_0 <= reg_sp.status_ready_matrix_f1_0 OR reg0_ready_matrix_f1;
407 407 reg_sp.status_ready_matrix_f2_0 <= reg_sp.status_ready_matrix_f2_0 OR reg0_ready_matrix_f2;
408 408
409 409 reg_sp.status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1 OR reg1_ready_matrix_f0;
410 410 reg_sp.status_ready_matrix_f1_1 <= reg_sp.status_ready_matrix_f1_1 OR reg1_ready_matrix_f1;
411 411 reg_sp.status_ready_matrix_f2_1 <= reg_sp.status_ready_matrix_f2_1 OR reg1_ready_matrix_f2;
412 412
413 413 all_status_ready_buffer_bit: FOR I IN 4*2-1 DOWNTO 0 LOOP
414 414 reg_wp.status_ready_buffer_f(I) <= reg_wp.status_ready_buffer_f(I) OR reg_ready_buffer_f(I);
415 415 END LOOP all_status_ready_buffer_bit;
416 416
417 417
418 418 reg_sp.status_error_buffer_full <= reg_sp.status_error_buffer_full OR error_buffer_full;
419 419 reg_sp.status_error_input_fifo_write(0) <= reg_sp.status_error_input_fifo_write(0) OR error_input_fifo_write(0);
420 420 reg_sp.status_error_input_fifo_write(1) <= reg_sp.status_error_input_fifo_write(1) OR error_input_fifo_write(1);
421 421 reg_sp.status_error_input_fifo_write(2) <= reg_sp.status_error_input_fifo_write(2) OR error_input_fifo_write(2);
422 422
423 423
424 424
425 425 all_status : FOR I IN 3 DOWNTO 0 LOOP
426 426 reg_wp.error_buffer_full(I) <= reg_wp.error_buffer_full(I) OR wfp_error_buffer_full(I);
427 427 reg_wp.status_new_err(I) <= reg_wp.status_new_err(I) OR status_new_err(I);
428 428 END LOOP all_status;
429 429
430 430 paddr := "000000";
431 431 paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
432 432 prdata <= (OTHERS => '0');
433 433 IF apbi.psel(pindex) = '1' THEN
434 434 -- APB DMA READ --
435 435 CASE paddr(7 DOWNTO 2) IS
436 436
437 437 WHEN ADDR_LFR_SM_CONFIG =>
438 438 prdata(0) <= reg_sp.config_active_interruption_onNewMatrix;
439 439 prdata(1) <= reg_sp.config_active_interruption_onError;
440 440 prdata(2) <= reg_sp.config_ms_run;
441 441
442 442 WHEN ADDR_LFR_SM_STATUS =>
443 443 prdata(0) <= reg_sp.status_ready_matrix_f0_0;
444 444 prdata(1) <= reg_sp.status_ready_matrix_f0_1;
445 445 prdata(2) <= reg_sp.status_ready_matrix_f1_0;
446 446 prdata(3) <= reg_sp.status_ready_matrix_f1_1;
447 447 prdata(4) <= reg_sp.status_ready_matrix_f2_0;
448 448 prdata(5) <= reg_sp.status_ready_matrix_f2_1;
449 449 -- prdata(6) <= reg_sp.status_error_bad_component_error;
450 450 prdata(7) <= reg_sp.status_error_buffer_full;
451 451 prdata(8) <= reg_sp.status_error_input_fifo_write(0);
452 452 prdata(9) <= reg_sp.status_error_input_fifo_write(1);
453 453 prdata(10) <= reg_sp.status_error_input_fifo_write(2);
454 454
455 455 WHEN ADDR_LFR_SM_F0_0_ADDR => prdata <= reg_sp.addr_matrix_f0_0;
456 456 WHEN ADDR_LFR_SM_F0_1_ADDR => prdata <= reg_sp.addr_matrix_f0_1;
457 457 WHEN ADDR_LFR_SM_F1_0_ADDR => prdata <= reg_sp.addr_matrix_f1_0;
458 458 WHEN ADDR_LFR_SM_F1_1_ADDR => prdata <= reg_sp.addr_matrix_f1_1;
459 459 WHEN ADDR_LFR_SM_F2_0_ADDR => prdata <= reg_sp.addr_matrix_f2_0;
460 460 WHEN ADDR_LFR_SM_F2_1_ADDR => prdata <= reg_sp.addr_matrix_f2_1;
461 461 WHEN ADDR_LFR_SM_F0_0_TIME_COARSE => prdata <= reg_sp.time_matrix_f0_0(47 DOWNTO 16);
462 462 WHEN ADDR_LFR_SM_F0_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f0_0(15 DOWNTO 0);
463 463 WHEN ADDR_LFR_SM_F0_1_TIME_COARSE => prdata <= reg_sp.time_matrix_f0_1(47 DOWNTO 16);
464 464 WHEN ADDR_LFR_SM_F0_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f0_1(15 DOWNTO 0);
465 465 WHEN ADDR_LFR_SM_F1_0_TIME_COARSE => prdata <= reg_sp.time_matrix_f1_0(47 DOWNTO 16);
466 466 WHEN ADDR_LFR_SM_F1_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f1_0(15 DOWNTO 0);
467 467 WHEN ADDR_LFR_SM_F1_1_TIME_COARSE => prdata <= reg_sp.time_matrix_f1_1(47 DOWNTO 16);
468 468 WHEN ADDR_LFR_SM_F1_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f1_1(15 DOWNTO 0);
469 469 WHEN ADDR_LFR_SM_F2_0_TIME_COARSE => prdata <= reg_sp.time_matrix_f2_0(47 DOWNTO 16);
470 470 WHEN ADDR_LFR_SM_F2_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_0(15 DOWNTO 0);
471 471 WHEN ADDR_LFR_SM_F2_1_TIME_COARSE => prdata <= reg_sp.time_matrix_f2_1(47 DOWNTO 16);
472 472 WHEN ADDR_LFR_SM_F2_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_1(15 DOWNTO 0);
473 473 WHEN ADDR_LFR_SM_LENGTH => prdata(25 DOWNTO 0) <= reg_sp.length_matrix;
474 474 ---------------------------------------------------------------------
475 475 WHEN ADDR_LFR_WP_DATASHAPING =>
476 476 prdata(0) <= reg_wp.data_shaping_BW;
477 477 prdata(1) <= reg_wp.data_shaping_SP0;
478 478 prdata(2) <= reg_wp.data_shaping_SP1;
479 479 prdata(3) <= reg_wp.data_shaping_R0;
480 480 prdata(4) <= reg_wp.data_shaping_R1;
481 481 prdata(5) <= reg_wp.data_shaping_R2;
482 482 WHEN ADDR_LFR_WP_CONTROL =>
483 483 prdata(0) <= reg_wp.enable_f0;
484 484 prdata(1) <= reg_wp.enable_f1;
485 485 prdata(2) <= reg_wp.enable_f2;
486 486 prdata(3) <= reg_wp.enable_f3;
487 487 prdata(4) <= reg_wp.burst_f0;
488 488 prdata(5) <= reg_wp.burst_f1;
489 489 prdata(6) <= reg_wp.burst_f2;
490 490 prdata(7) <= reg_wp.run;
491 491 WHEN ADDR_LFR_WP_F0_0_ADDR => prdata <= reg_wp.addr_buffer_f(32*1-1 DOWNTO 32*0);--0
492 492 WHEN ADDR_LFR_WP_F0_1_ADDR => prdata <= reg_wp.addr_buffer_f(32*2-1 DOWNTO 32*1);
493 493 WHEN ADDR_LFR_WP_F1_0_ADDR => prdata <= reg_wp.addr_buffer_f(32*3-1 DOWNTO 32*2);--1
494 494 WHEN ADDR_LFR_WP_F1_1_ADDR => prdata <= reg_wp.addr_buffer_f(32*4-1 DOWNTO 32*3);
495 495 WHEN ADDR_LFR_WP_F2_0_ADDR => prdata <= reg_wp.addr_buffer_f(32*5-1 DOWNTO 32*4);--2
496 496 WHEN ADDR_LFR_WP_F2_1_ADDR => prdata <= reg_wp.addr_buffer_f(32*6-1 DOWNTO 32*5);
497 497 WHEN ADDR_LFR_WP_F3_0_ADDR => prdata <= reg_wp.addr_buffer_f(32*7-1 DOWNTO 32*6);--3
498 498 WHEN ADDR_LFR_WP_F3_1_ADDR => prdata <= reg_wp.addr_buffer_f(32*8-1 DOWNTO 32*7);
499 499
500 500 WHEN ADDR_LFR_WP_STATUS =>
501 501 prdata(7 DOWNTO 0) <= reg_wp.status_ready_buffer_f;
502 502 prdata(11 DOWNTO 8) <= reg_wp.error_buffer_full;
503 503 prdata(15 DOWNTO 12) <= reg_wp.status_new_err;
504 504
505 505 WHEN ADDR_LFR_WP_DELTASNAPSHOT => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_snapshot;
506 506 WHEN ADDR_LFR_WP_DELTA_F0 => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f0;
507 507 WHEN ADDR_LFR_WP_DELTA_F0_2 => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2;
508 508 WHEN ADDR_LFR_WP_DELTA_F1 => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f1;
509 509 WHEN ADDR_LFR_WP_DELTA_F2 => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2;
510 510 WHEN ADDR_LFR_WP_DATA_IN_BUFFER => prdata(nb_data_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_data_by_buffer;
511 511 WHEN ADDR_LFR_WP_NBSNAPSHOT => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param;
512 512 WHEN ADDR_LFR_WP_START_DATE => prdata(30 DOWNTO 0) <= reg_wp.start_date;
513 513
514 514 WHEN ADDR_LFR_WP_F0_0_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*0 + 31 DOWNTO 48*0);
515 515 WHEN ADDR_LFR_WP_F0_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*0 + 47 DOWNTO 48*0 + 32);
516 516 WHEN ADDR_LFR_WP_F0_1_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*1 + 31 DOWNTO 48*1);
517 517 WHEN ADDR_LFR_WP_F0_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*1 + 47 DOWNTO 48*1 + 32);
518 518
519 519 WHEN ADDR_LFR_WP_F1_0_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*2 + 31 DOWNTO 48*2);
520 520 WHEN ADDR_LFR_WP_F1_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*2 + 47 DOWNTO 48*2 + 32);
521 521 WHEN ADDR_LFR_WP_F1_1_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*3 + 31 DOWNTO 48*3);
522 522 WHEN ADDR_LFR_WP_F1_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*3 + 47 DOWNTO 48*3 + 32);
523 523
524 524 WHEN ADDR_LFR_WP_F2_0_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*4 + 31 DOWNTO 48*4);
525 525 WHEN ADDR_LFR_WP_F2_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*4 + 47 DOWNTO 48*4 + 32);
526 526 WHEN ADDR_LFR_WP_F2_1_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*5 + 31 DOWNTO 48*5);
527 527 WHEN ADDR_LFR_WP_F2_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*5 + 47 DOWNTO 48*5 + 32);
528 528
529 529 WHEN ADDR_LFR_WP_F3_0_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*6 + 31 DOWNTO 48*6);
530 530 WHEN ADDR_LFR_WP_F3_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*6 + 47 DOWNTO 48*6 + 32);
531 531 WHEN ADDR_LFR_WP_F3_1_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*7 + 31 DOWNTO 48*7);
532 532 WHEN ADDR_LFR_WP_F3_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*7 + 47 DOWNTO 48*7 + 32);
533 533
534 534 WHEN ADDR_LFR_WP_LENGTH => prdata(25 DOWNTO 0) <= reg_wp.length_buffer;
535 535 ---------------------------------------------------------------------
536 536 WHEN ADDR_LFR_VERSION => prdata(23 DOWNTO 0) <= top_lfr_version(23 DOWNTO 0);
537 537 WHEN OTHERS => NULL;
538 538
539 539 END CASE;
540 540 IF (apbi.pwrite AND apbi.penable) = '1' THEN
541 541 -- APB DMA WRITE --
542 542 CASE paddr(7 DOWNTO 2) IS
543 543 --
544 544 WHEN ADDR_LFR_SM_CONFIG =>
545 545 reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0);
546 546 reg_sp.config_active_interruption_onError <= apbi.pwdata(1);
547 547 reg_sp.config_ms_run <= apbi.pwdata(2);
548 548
549 549 WHEN ADDR_LFR_SM_STATUS =>
550 550 reg_sp.status_ready_matrix_f0_0 <= ((NOT apbi.pwdata(0) ) AND reg_sp.status_ready_matrix_f0_0 ) OR reg0_ready_matrix_f0;
551 551 reg_sp.status_ready_matrix_f0_1 <= ((NOT apbi.pwdata(1) ) AND reg_sp.status_ready_matrix_f0_1 ) OR reg1_ready_matrix_f0;
552 552 reg_sp.status_ready_matrix_f1_0 <= ((NOT apbi.pwdata(2) ) AND reg_sp.status_ready_matrix_f1_0 ) OR reg0_ready_matrix_f1;
553 553 reg_sp.status_ready_matrix_f1_1 <= ((NOT apbi.pwdata(3) ) AND reg_sp.status_ready_matrix_f1_1 ) OR reg1_ready_matrix_f1;
554 554 reg_sp.status_ready_matrix_f2_0 <= ((NOT apbi.pwdata(4) ) AND reg_sp.status_ready_matrix_f2_0 ) OR reg0_ready_matrix_f2;
555 555 reg_sp.status_ready_matrix_f2_1 <= ((NOT apbi.pwdata(5) ) AND reg_sp.status_ready_matrix_f2_1 ) OR reg1_ready_matrix_f2;
556 556 reg_sp.status_error_buffer_full <= ((NOT apbi.pwdata(7) ) AND reg_sp.status_error_buffer_full ) OR error_buffer_full;
557 557 reg_sp.status_error_input_fifo_write(0) <= ((NOT apbi.pwdata(8) ) AND reg_sp.status_error_input_fifo_write(0)) OR error_input_fifo_write(0);
558 558 reg_sp.status_error_input_fifo_write(1) <= ((NOT apbi.pwdata(9) ) AND reg_sp.status_error_input_fifo_write(1)) OR error_input_fifo_write(1);
559 559 reg_sp.status_error_input_fifo_write(2) <= ((NOT apbi.pwdata(10)) AND reg_sp.status_error_input_fifo_write(2)) OR error_input_fifo_write(2);
560 560 WHEN ADDR_LFR_SM_F0_0_ADDR => reg_sp.addr_matrix_f0_0 <= apbi.pwdata;
561 561 WHEN ADDR_LFR_SM_F0_1_ADDR => reg_sp.addr_matrix_f0_1 <= apbi.pwdata;
562 562 WHEN ADDR_LFR_SM_F1_0_ADDR => reg_sp.addr_matrix_f1_0 <= apbi.pwdata;
563 563 WHEN ADDR_LFR_SM_F1_1_ADDR => reg_sp.addr_matrix_f1_1 <= apbi.pwdata;
564 564 WHEN ADDR_LFR_SM_F2_0_ADDR => reg_sp.addr_matrix_f2_0 <= apbi.pwdata;
565 565 WHEN ADDR_LFR_SM_F2_1_ADDR => reg_sp.addr_matrix_f2_1 <= apbi.pwdata;
566 566
567 567 WHEN ADDR_LFR_SM_LENGTH => reg_sp.length_matrix <= apbi.pwdata(25 DOWNTO 0);
568 568 ---------------------------------------------------------------------
569 569 WHEN ADDR_LFR_WP_DATASHAPING =>
570 570 reg_wp.data_shaping_BW <= apbi.pwdata(0);
571 571 reg_wp.data_shaping_SP0 <= apbi.pwdata(1);
572 572 reg_wp.data_shaping_SP1 <= apbi.pwdata(2);
573 573 reg_wp.data_shaping_R0 <= apbi.pwdata(3);
574 574 reg_wp.data_shaping_R1 <= apbi.pwdata(4);
575 575 reg_wp.data_shaping_R2 <= apbi.pwdata(5);
576 576 WHEN ADDR_LFR_WP_CONTROL =>
577 577 reg_wp.enable_f0 <= apbi.pwdata(0);
578 578 reg_wp.enable_f1 <= apbi.pwdata(1);
579 579 reg_wp.enable_f2 <= apbi.pwdata(2);
580 580 reg_wp.enable_f3 <= apbi.pwdata(3);
581 581 reg_wp.burst_f0 <= apbi.pwdata(4);
582 582 reg_wp.burst_f1 <= apbi.pwdata(5);
583 583 reg_wp.burst_f2 <= apbi.pwdata(6);
584 584 reg_wp.run <= apbi.pwdata(7);
585 585 WHEN ADDR_LFR_WP_F0_0_ADDR => reg_wp.addr_buffer_f(32*1-1 DOWNTO 32*0) <= apbi.pwdata;
586 586 WHEN ADDR_LFR_WP_F0_1_ADDR => reg_wp.addr_buffer_f(32*2-1 DOWNTO 32*1) <= apbi.pwdata;
587 587 WHEN ADDR_LFR_WP_F1_0_ADDR => reg_wp.addr_buffer_f(32*3-1 DOWNTO 32*2) <= apbi.pwdata;
588 588 WHEN ADDR_LFR_WP_F1_1_ADDR => reg_wp.addr_buffer_f(32*4-1 DOWNTO 32*3) <= apbi.pwdata;
589 589 WHEN ADDR_LFR_WP_F2_0_ADDR => reg_wp.addr_buffer_f(32*5-1 DOWNTO 32*4) <= apbi.pwdata;
590 590 WHEN ADDR_LFR_WP_F2_1_ADDR => reg_wp.addr_buffer_f(32*6-1 DOWNTO 32*5) <= apbi.pwdata;
591 591 WHEN ADDR_LFR_WP_F3_0_ADDR => reg_wp.addr_buffer_f(32*7-1 DOWNTO 32*6) <= apbi.pwdata;
592 592 WHEN ADDR_LFR_WP_F3_1_ADDR => reg_wp.addr_buffer_f(32*8-1 DOWNTO 32*7) <= apbi.pwdata;
593 593 WHEN ADDR_LFR_WP_STATUS =>
594 594 all_reg_wp_status_bit: FOR I IN 3 DOWNTO 0 LOOP
595 595 reg_wp.status_ready_buffer_f(I*2) <= ((NOT apbi.pwdata(I*2) ) AND reg_wp.status_ready_buffer_f(I*2) ) OR reg_ready_buffer_f(I*2);
596 596 reg_wp.status_ready_buffer_f(I*2+1) <= ((NOT apbi.pwdata(I*2+1)) AND reg_wp.status_ready_buffer_f(I*2+1)) OR reg_ready_buffer_f(I*2+1);
597 597 reg_wp.error_buffer_full(I) <= ((NOT apbi.pwdata(I+8) ) AND reg_wp.error_buffer_full(I) ) OR wfp_error_buffer_full(I);
598 598 reg_wp.status_new_err(I) <= ((NOT apbi.pwdata(I+12) ) AND reg_wp.status_new_err(I) ) OR status_new_err(I);
599 599 END LOOP all_reg_wp_status_bit;
600 600
601 601 WHEN ADDR_LFR_WP_DELTASNAPSHOT => reg_wp.delta_snapshot <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
602 602 WHEN ADDR_LFR_WP_DELTA_F0 => reg_wp.delta_f0 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
603 603 WHEN ADDR_LFR_WP_DELTA_F0_2 => reg_wp.delta_f0_2 <= apbi.pwdata(delta_vector_size_f0_2-1 DOWNTO 0);
604 604 WHEN ADDR_LFR_WP_DELTA_F1 => reg_wp.delta_f1 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
605 605 WHEN ADDR_LFR_WP_DELTA_F2 => reg_wp.delta_f2 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
606 606 WHEN ADDR_LFR_WP_DATA_IN_BUFFER => reg_wp.nb_data_by_buffer <= apbi.pwdata(nb_data_by_buffer_size-1 DOWNTO 0);
607 607 WHEN ADDR_LFR_WP_NBSNAPSHOT => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0);
608 608 WHEN ADDR_LFR_WP_START_DATE => reg_wp.start_date <= apbi.pwdata(30 DOWNTO 0);
609 609
610 610 WHEN ADDR_LFR_WP_LENGTH => reg_wp.length_buffer <= apbi.pwdata(25 DOWNTO 0);
611 611
612 612 WHEN OTHERS => NULL;
613 613 END CASE;
614 614 END IF;
615 615 END IF;
616 616 --apbo.pirq(pirq_ms) <=
617 617 pirq_temp( pirq_ms) <= apbo_irq_ms;
618 618 pirq_temp(pirq_wfp) <= apbo_irq_wfp;
619 619 apbo_irq_ms <= ((reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0 OR
620 620 ready_matrix_f1 OR
621 621 ready_matrix_f2)
622 622 )
623 623 OR
624 624 (reg_sp.config_active_interruption_onError AND (
625 625 -- error_bad_component_error OR
626 626 error_buffer_full
627 627 OR error_input_fifo_write(0)
628 628 OR error_input_fifo_write(1)
629 629 OR error_input_fifo_write(2))
630 630 ));
631 631 -- apbo.pirq(pirq_wfp)
632 632 apbo_irq_wfp<= ored_irq_wfp;
633 633
634 634 END IF;
635 635 END PROCESS lpp_lfr_apbreg;
636 636
637 637 apbo.pirq <= pirq_temp;
638 638
639 639
640 640 --all_irq: FOR I IN 31 DOWNTO 0 GENERATE
641 641 -- IRQ_is_PIRQ_MS: IF I = pirq_ms GENERATE
642 642 -- apbo.pirq(I) <= apbo_irq_ms;
643 643 -- END GENERATE IRQ_is_PIRQ_MS;
644 644 -- IRQ_is_PIRQ_WFP: IF I = pirq_wfp GENERATE
645 645 -- apbo.pirq(I) <= apbo_irq_wfp;
646 646 -- END GENERATE IRQ_is_PIRQ_WFP;
647 647 -- IRQ_OTHERS: IF I /= pirq_ms AND pirq_wfp /= pirq_wfp GENERATE
648 648 -- apbo.pirq(I) <= '0';
649 649 -- END GENERATE IRQ_OTHERS;
650 650
651 651 --END GENERATE all_irq;
652 652
653 653
654 654
655 655 apbo.pindex <= pindex;
656 656 apbo.pconfig <= pconfig;
657 657 apbo.prdata <= prdata;
658 658
659 659 -----------------------------------------------------------------------------
660 660 -- IRQ
661 661 -----------------------------------------------------------------------------
662 662 irq_wfp_reg_s <= wfp_ready_buffer & wfp_error_buffer_full & status_new_err;
663 663
664 664 PROCESS (HCLK, HRESETn)
665 665 BEGIN -- PROCESS
666 666 IF HRESETn = '0' THEN -- asynchronous reset (active low)
667 667 irq_wfp_reg <= (OTHERS => '0');
668 668 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
669 669 irq_wfp_reg <= irq_wfp_reg_s;
670 670 END IF;
671 671 END PROCESS;
672 672
673 673 all_irq_wfp : FOR I IN IRQ_WFP_SIZE-1 DOWNTO 0 GENERATE
674 674 irq_wfp(I) <= (NOT irq_wfp_reg(I)) AND irq_wfp_reg_s(I);
675 675 END GENERATE all_irq_wfp;
676 676
677 677 irq_wfp_ZERO <= (OTHERS => '0');
678 678 ored_irq_wfp <= '0' WHEN irq_wfp = irq_wfp_ZERO ELSE '1';
679 679
680 680 run_ms <= reg_sp.config_ms_run;
681 681
682 682 -----------------------------------------------------------------------------
683 683 --
684 684 -----------------------------------------------------------------------------
685 685 lpp_apbreg_ms_pointer_f0 : lpp_apbreg_ms_pointer
686 686 PORT MAP (
687 687 clk => HCLK,
688 688 rstn => HRESETn,
689 689
690 690 run => '1',--reg_sp.config_ms_run,
691 691
692 692 reg0_status_ready_matrix => reg_sp.status_ready_matrix_f0_0,
693 693 reg0_ready_matrix => reg0_ready_matrix_f0,
694 694 reg0_addr_matrix => reg_sp.addr_matrix_f0_0, --reg0_addr_matrix_f0,
695 695 reg0_matrix_time => reg_sp.time_matrix_f0_0, --reg0_matrix_time_f0,
696 696
697 697 reg1_status_ready_matrix => reg_sp.status_ready_matrix_f0_1,
698 698 reg1_ready_matrix => reg1_ready_matrix_f0,
699 699 reg1_addr_matrix => reg_sp.addr_matrix_f0_1, --reg1_addr_matrix_f0,
700 700 reg1_matrix_time => reg_sp.time_matrix_f0_1, --reg1_matrix_time_f0,
701 701
702 702 ready_matrix => ready_matrix_f0,
703 703 status_ready_matrix => status_ready_matrix_f0,
704 704 addr_matrix => addr_matrix_f0,
705 705 matrix_time => matrix_time_f0);
706 706
707 707 lpp_apbreg_ms_pointer_f1 : lpp_apbreg_ms_pointer
708 708 PORT MAP (
709 709 clk => HCLK,
710 710 rstn => HRESETn,
711 711
712 712 run => '1',--reg_sp.config_ms_run,
713 713
714 714 reg0_status_ready_matrix => reg_sp.status_ready_matrix_f1_0,
715 715 reg0_ready_matrix => reg0_ready_matrix_f1,
716 716 reg0_addr_matrix => reg_sp.addr_matrix_f1_0, --reg0_addr_matrix_f1,
717 717 reg0_matrix_time => reg_sp.time_matrix_f1_0, --reg0_matrix_time_f1,
718 718
719 719 reg1_status_ready_matrix => reg_sp.status_ready_matrix_f1_1,
720 720 reg1_ready_matrix => reg1_ready_matrix_f1,
721 721 reg1_addr_matrix => reg_sp.addr_matrix_f1_1, --reg1_addr_matrix_f1,
722 722 reg1_matrix_time => reg_sp.time_matrix_f1_1, --reg1_matrix_time_f1,
723 723
724 724 ready_matrix => ready_matrix_f1,
725 725 status_ready_matrix => status_ready_matrix_f1,
726 726 addr_matrix => addr_matrix_f1,
727 727 matrix_time => matrix_time_f1);
728 728
729 729 lpp_apbreg_ms_pointer_f2 : lpp_apbreg_ms_pointer
730 730 PORT MAP (
731 731 clk => HCLK,
732 732 rstn => HRESETn,
733 733
734 734 run => '1',--reg_sp.config_ms_run,
735 735
736 736 reg0_status_ready_matrix => reg_sp.status_ready_matrix_f2_0,
737 737 reg0_ready_matrix => reg0_ready_matrix_f2,
738 738 reg0_addr_matrix => reg_sp.addr_matrix_f2_0, --reg0_addr_matrix_f2,
739 739 reg0_matrix_time => reg_sp.time_matrix_f2_0, --reg0_matrix_time_f2,
740 740
741 741 reg1_status_ready_matrix => reg_sp.status_ready_matrix_f2_1,
742 742 reg1_ready_matrix => reg1_ready_matrix_f2,
743 743 reg1_addr_matrix => reg_sp.addr_matrix_f2_1, --reg1_addr_matrix_f2,
744 744 reg1_matrix_time => reg_sp.time_matrix_f2_1, --reg1_matrix_time_f2,
745 745
746 746 ready_matrix => ready_matrix_f2,
747 747 status_ready_matrix => status_ready_matrix_f2,
748 748 addr_matrix => addr_matrix_f2,
749 749 matrix_time => matrix_time_f2);
750 750
751 751 -----------------------------------------------------------------------------
752 752 all_wfp_pointer: FOR I IN 3 DOWNTO 0 GENERATE
753 753 lpp_apbreg_wfp_pointer_fi : lpp_apbreg_ms_pointer
754 754 PORT MAP (
755 755 clk => HCLK,
756 756 rstn => HRESETn,
757 757
758 758 run => '1',--reg_wp.run,
759 759
760 760 reg0_status_ready_matrix => reg_wp.status_ready_buffer_f(2*I),
761 761 reg0_ready_matrix => reg_ready_buffer_f(2*I),
762 762 reg0_addr_matrix => reg_wp.addr_buffer_f((2*I+1)*32-1 DOWNTO (2*I)*32),
763 763 reg0_matrix_time => reg_wp.time_buffer_f((2*I+1)*48-1 DOWNTO (2*I)*48),
764 764
765 765 reg1_status_ready_matrix => reg_wp.status_ready_buffer_f(2*I+1),
766 766 reg1_ready_matrix => reg_ready_buffer_f(2*I+1),
767 767 reg1_addr_matrix => reg_wp.addr_buffer_f((2*I+2)*32-1 DOWNTO (2*I+1)*32),
768 768 reg1_matrix_time => reg_wp.time_buffer_f((2*I+2)*48-1 DOWNTO (2*I+1)*48),
769 769
770 770 ready_matrix => wfp_ready_buffer(I),
771 771 status_ready_matrix => wfp_status_buffer_ready(I),
772 772 addr_matrix => wfp_addr_buffer((I+1)*32-1 DOWNTO I*32),
773 773 matrix_time => wfp_buffer_time((I+1)*48-1 DOWNTO I*48)
774 774 );
775 775
776 776 END GENERATE all_wfp_pointer;
777 777 -----------------------------------------------------------------------------
778 778
779 779 END beh;
780 780
781 -------------------------------------------------------------------------------
781 ------------------------------------------------------------------------------- No newline at end of file
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@@ -1,1174 +1,1207
1 1 LIBRARY ieee;
2 2 USE ieee.std_logic_1164.ALL;
3 3 USE ieee.numeric_std.ALL;
4 4
5 5
6 6 LIBRARY lpp;
7 7 USE lpp.lpp_memory.ALL;
8 8 USE lpp.iir_filter.ALL;
9 9 USE lpp.spectral_matrix_package.ALL;
10 10 USE lpp.lpp_dma_pkg.ALL;
11 11 USE lpp.lpp_Header.ALL;
12 12 USE lpp.lpp_matrix.ALL;
13 13 USE lpp.lpp_matrix.ALL;
14 14 USE lpp.lpp_lfr_pkg.ALL;
15 15 USE lpp.lpp_fft.ALL;
16 16 USE lpp.fft_components.ALL;
17 17
18 18 ENTITY lpp_lfr_ms IS
19 19 GENERIC (
20 20 Mem_use : INTEGER := use_RAM
21 21 );
22 22 PORT (
23 23 clk : IN STD_LOGIC;
24 24 rstn : IN STD_LOGIC;
25 25 run : IN STD_LOGIC;
26 26
27 27 ---------------------------------------------------------------------------
28 28 -- DATA INPUT
29 29 ---------------------------------------------------------------------------
30 30 start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
31 31 -- TIME
32 32 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
33 33 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
34 34 --
35 35 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
36 36 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
37 37 --
38 38 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
39 39 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
40 40 --
41 41 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
42 42 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
43 43
44 44 ---------------------------------------------------------------------------
45 45 -- DMA
46 46 ---------------------------------------------------------------------------
47 47 dma_fifo_burst_valid: OUT STD_LOGIC; --TODO
48 48 dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --TODO
49 49 dma_fifo_ren : IN STD_LOGIC; --TODO
50 50 dma_buffer_new : OUT STD_LOGIC; --TODOx
51 51 dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --TODO
52 52 dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); --TODO
53 53 dma_buffer_full : IN STD_LOGIC; --TODO
54 54 dma_buffer_full_err : IN STD_LOGIC; --TODO
55 55
56 56 -- Reg out
57 57 ready_matrix_f0 : OUT STD_LOGIC; -- TODO
58 58 ready_matrix_f1 : OUT STD_LOGIC; -- TODO
59 59 ready_matrix_f2 : OUT STD_LOGIC; -- TODO
60 60 -- error_bad_component_error : OUT STD_LOGIC; -- TODO
61 61 error_buffer_full : OUT STD_LOGIC; -- TODO
62 62 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
63 63
64 64 -- Reg In
65 65 status_ready_matrix_f0 : IN STD_LOGIC; -- TODO
66 66 status_ready_matrix_f1 : IN STD_LOGIC; -- TODO
67 67 status_ready_matrix_f2 : IN STD_LOGIC; -- TODO
68 68
69 69 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
70 70 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
71 71 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
72 72
73 73 length_matrix_f0 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); -- TODO
74 74 length_matrix_f1 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); -- TODO
75 75 length_matrix_f2 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); -- TODO
76 76
77 77 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
78 78 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
79 79 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) -- TODO
80 80
81 81 );
82 82 END;
83 83
84 84 ARCHITECTURE Behavioral OF lpp_lfr_ms IS
85 85
86 86 SIGNAL sample_f0_A_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
87 87 SIGNAL sample_f0_A_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
88 88 SIGNAL sample_f0_A_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
89 89 SIGNAL sample_f0_A_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
90 90 SIGNAL sample_f0_A_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
91 91
92 92 SIGNAL sample_f0_B_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
93 93 SIGNAL sample_f0_B_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
94 94 SIGNAL sample_f0_B_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
95 95 SIGNAL sample_f0_B_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
96 96 SIGNAL sample_f0_B_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
97 97
98 98 SIGNAL sample_f1_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
99 99 SIGNAL sample_f1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
100 100 SIGNAL sample_f1_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
101 101 SIGNAL sample_f1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
102 102
103 103 SIGNAL sample_f1_almost_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
104 104
105 105 SIGNAL sample_f2_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
106 106 SIGNAL sample_f2_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
107 107 SIGNAL sample_f2_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
108 108 SIGNAL sample_f2_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
109 109
110 110 SIGNAL error_wen_f0 : STD_LOGIC;
111 111 SIGNAL error_wen_f1 : STD_LOGIC;
112 112 SIGNAL error_wen_f2 : STD_LOGIC;
113 113
114 114 SIGNAL one_sample_f1_full : STD_LOGIC;
115 115 SIGNAL one_sample_f1_wen : STD_LOGIC;
116 116 SIGNAL one_sample_f2_full : STD_LOGIC;
117 117 SIGNAL one_sample_f2_wen : STD_LOGIC;
118 118
119 119 -----------------------------------------------------------------------------
120 120 -- FSM / SWITCH SELECT CHANNEL
121 121 -----------------------------------------------------------------------------
122 122 TYPE fsm_select_channel IS (IDLE, SWITCH_F0_A, SWITCH_F0_B, SWITCH_F1, SWITCH_F2);
123 123 SIGNAL state_fsm_select_channel : fsm_select_channel;
124 SIGNAL pre_state_fsm_select_channel : fsm_select_channel;
125
124 -- SIGNAL pre_state_fsm_select_channel : fsm_select_channel;
125 SIGNAL select_channel : STD_LOGIC_VECTOR(1 DOWNTO 0);
126 SIGNAL select_channel_reg : STD_LOGIC_VECTOR(1 DOWNTO 0);
127
126 128 SIGNAL sample_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
127 129 SIGNAL sample_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
128 130 SIGNAL sample_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
129 131 SIGNAL sample_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
130 132
131 133 -----------------------------------------------------------------------------
132 134 -- FSM LOAD FFT
133 135 -----------------------------------------------------------------------------
134 136 TYPE fsm_load_FFT IS (IDLE, FIFO_1, FIFO_2, FIFO_3, FIFO_4, FIFO_5);
135 137 SIGNAL state_fsm_load_FFT : fsm_load_FFT;
136 SIGNAL next_state_fsm_load_FFT : fsm_load_FFT;
138 -- SIGNAL next_state_fsm_load_FFT : fsm_load_FFT;
139 SIGNAL select_fifo : STD_LOGIC_VECTOR(2 DOWNTO 0);
140 SIGNAL select_fifo_reg : STD_LOGIC_VECTOR(2 DOWNTO 0);
137 141
138 142 SIGNAL sample_ren_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
139 143 SIGNAL sample_load : STD_LOGIC;
140 144 SIGNAL sample_valid : STD_LOGIC;
141 145 SIGNAL sample_valid_r : STD_LOGIC;
142 146 SIGNAL sample_data : STD_LOGIC_VECTOR(15 DOWNTO 0);
143 147
144 148
145 149 -----------------------------------------------------------------------------
146 150 -- FFT
147 151 -----------------------------------------------------------------------------
148 152 SIGNAL fft_read : STD_LOGIC;
149 153 SIGNAL fft_pong : STD_LOGIC;
150 154 SIGNAL fft_data_im : STD_LOGIC_VECTOR(15 DOWNTO 0);
151 155 SIGNAL fft_data_re : STD_LOGIC_VECTOR(15 DOWNTO 0);
152 156 SIGNAL fft_data_valid : STD_LOGIC;
153 157 SIGNAL fft_ready : STD_LOGIC;
154 158 -----------------------------------------------------------------------------
155 159 -- SIGNAL fft_linker_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
156 160 -----------------------------------------------------------------------------
157 161 TYPE fsm_load_MS_memory IS (IDLE, LOAD_FIFO, TRASH_FFT);
158 162 SIGNAL state_fsm_load_MS_memory : fsm_load_MS_memory;
159 163 SIGNAL current_fifo_load : STD_LOGIC_VECTOR(4 DOWNTO 0);
160 164 SIGNAL current_fifo_empty : STD_LOGIC;
161 165 SIGNAL current_fifo_locked : STD_LOGIC;
162 166 SIGNAL current_fifo_full : STD_LOGIC;
163 167 SIGNAL MEM_IN_SM_locked : STD_LOGIC_VECTOR(4 DOWNTO 0);
164 168
165 169 -----------------------------------------------------------------------------
166 170 SIGNAL MEM_IN_SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
167 171 SIGNAL MEM_IN_SM_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
168 172 SIGNAL MEM_IN_SM_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
169 173 SIGNAL MEM_IN_SM_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
170 174 SIGNAL MEM_IN_SM_wData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
171 175 SIGNAL MEM_IN_SM_rData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
172 176 SIGNAL MEM_IN_SM_Full : STD_LOGIC_VECTOR(4 DOWNTO 0);
173 177 SIGNAL MEM_IN_SM_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
174 178 -----------------------------------------------------------------------------
175 179 SIGNAL SM_in_data : STD_LOGIC_VECTOR(32*2-1 DOWNTO 0);
176 180 SIGNAL SM_in_ren : STD_LOGIC_VECTOR(1 DOWNTO 0);
177 181 SIGNAL SM_in_empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
178 182
179 183 SIGNAL SM_correlation_start : STD_LOGIC;
180 184 SIGNAL SM_correlation_auto : STD_LOGIC;
181 185 SIGNAL SM_correlation_done : STD_LOGIC;
182 186 SIGNAL SM_correlation_done_reg1 : STD_LOGIC;
183 187 SIGNAL SM_correlation_done_reg2 : STD_LOGIC;
184 188 SIGNAL SM_correlation_done_reg3 : STD_LOGIC;
185 189 SIGNAL SM_correlation_begin : STD_LOGIC;
186 190
187 191 SIGNAL MEM_OUT_SM_Full_s : STD_LOGIC;
188 192 SIGNAL MEM_OUT_SM_Data_in_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
189 193 SIGNAL MEM_OUT_SM_Write_s : STD_LOGIC;
190 194
191 195 SIGNAL current_matrix_write : STD_LOGIC;
192 196 SIGNAL current_matrix_wait_empty : STD_LOGIC;
193 197 -----------------------------------------------------------------------------
194 198 SIGNAL fifo_0_ready : STD_LOGIC;
195 199 SIGNAL fifo_1_ready : STD_LOGIC;
196 200 SIGNAL fifo_ongoing : STD_LOGIC;
197 201
198 202 SIGNAL FSM_DMA_fifo_ren : STD_LOGIC;
199 203 SIGNAL FSM_DMA_fifo_empty : STD_LOGIC;
200 204 SIGNAL FSM_DMA_fifo_empty_threshold : STD_LOGIC;
201 205 SIGNAL FSM_DMA_fifo_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
202 SIGNAL FSM_DMA_fifo_status : STD_LOGIC_VECTOR(53 DOWNTO 0);
206 SIGNAL FSM_DMA_fifo_status : STD_LOGIC_VECTOR(53 DOWNTO 4);
203 207 -----------------------------------------------------------------------------
204 208 SIGNAL MEM_OUT_SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0);
205 209 SIGNAL MEM_OUT_SM_Read : STD_LOGIC_VECTOR(1 DOWNTO 0);
206 210 SIGNAL MEM_OUT_SM_Data_in : STD_LOGIC_VECTOR(63 DOWNTO 0);
207 211 SIGNAL MEM_OUT_SM_Data_out : STD_LOGIC_VECTOR(63 DOWNTO 0);
208 212 SIGNAL MEM_OUT_SM_Full : STD_LOGIC_VECTOR(1 DOWNTO 0);
209 213 SIGNAL MEM_OUT_SM_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
210 214 SIGNAL MEM_OUT_SM_Empty_Threshold : STD_LOGIC_VECTOR(1 DOWNTO 0);
211 215
212 216 -----------------------------------------------------------------------------
213 217 -- TIME REG & INFOs
214 218 -----------------------------------------------------------------------------
215 219 SIGNAL all_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
216 220
217 221 SIGNAL f_empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
218 222 SIGNAL f_empty_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
219 223 SIGNAL time_update_f : STD_LOGIC_VECTOR(3 DOWNTO 0);
220 224 SIGNAL time_reg_f : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
221 225
222 226 SIGNAL time_reg_f0_A : STD_LOGIC_VECTOR(47 DOWNTO 0);
223 227 SIGNAL time_reg_f0_B : STD_LOGIC_VECTOR(47 DOWNTO 0);
224 228 SIGNAL time_reg_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
225 229 SIGNAL time_reg_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
226 230
227 231 --SIGNAL time_update_f0_A : STD_LOGIC;
228 232 --SIGNAL time_update_f0_B : STD_LOGIC;
229 233 --SIGNAL time_update_f1 : STD_LOGIC;
230 234 --SIGNAL time_update_f2 : STD_LOGIC;
231 235 --
232 236 SIGNAL status_channel : STD_LOGIC_VECTOR(49 DOWNTO 0);
233 237 SIGNAL status_MS_input : STD_LOGIC_VECTOR(49 DOWNTO 0);
234 238 SIGNAL status_component : STD_LOGIC_VECTOR(53 DOWNTO 0);
235 239
236 SIGNAL status_component_fifo_0 : STD_LOGIC_VECTOR(53 DOWNTO 0);
237 SIGNAL status_component_fifo_1 : STD_LOGIC_VECTOR(53 DOWNTO 0);
240 SIGNAL status_component_fifo_0 : STD_LOGIC_VECTOR(53 DOWNTO 4);
241 SIGNAL status_component_fifo_1 : STD_LOGIC_VECTOR(53 DOWNTO 4);
238 242 SIGNAL status_component_fifo_0_end : STD_LOGIC;
239 243 SIGNAL status_component_fifo_1_end : STD_LOGIC;
240 244 -----------------------------------------------------------------------------
241 245 SIGNAL fft_ongoing_counter : STD_LOGIC;--_VECTOR(1 DOWNTO 0);
242 246
243 247 SIGNAL fft_ready_reg : STD_LOGIC;
244 248 SIGNAL fft_ready_rising_down : STD_LOGIC;
245 249
246 250 SIGNAL sample_load_reg : STD_LOGIC;
247 251 SIGNAL sample_load_rising_down : STD_LOGIC;
248 252
249 253 -----------------------------------------------------------------------------
250 254 SIGNAL sample_f1_wen_head : STD_LOGIC_VECTOR(4 DOWNTO 0);
251 255 SIGNAL sample_f1_wen_head_in : STD_LOGIC;
252 256 SIGNAL sample_f1_wen_head_out : STD_LOGIC;
253 257 SIGNAL sample_f1_full_head_in : STD_LOGIC;
254 258 SIGNAL sample_f1_full_head_out : STD_LOGIC;
255 259 SIGNAL sample_f1_empty_head_in : STD_LOGIC;
256 260
257 261 SIGNAL sample_f1_wdata_head : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
258 262 -----------------------------------------------------------------------------
259 263 SIGNAL sample_f0_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
260 264 SIGNAL sample_f1_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
261 265 SIGNAL sample_f2_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
262 266 SIGNAL ongoing : STD_LOGIC;
263 267
264 268 BEGIN
265 269
266 270 PROCESS (clk, rstn)
267 271 BEGIN -- PROCESS
268 272 IF rstn = '0' THEN -- asynchronous reset (active low)
269 273 sample_f0_wen_s <= (OTHERS => '1');
270 274 sample_f1_wen_s <= (OTHERS => '1');
271 275 sample_f2_wen_s <= (OTHERS => '1');
272 276 ongoing <= '0';
273 277 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
274 278 IF ongoing = '1' THEN
275 279 sample_f0_wen_s <= sample_f0_wen;
276 280 sample_f1_wen_s <= sample_f1_wen;
277 281 sample_f2_wen_s <= sample_f2_wen;
278 282 ELSE
279 283 IF start_date = coarse_time(30 DOWNTO 0) THEN
280 284 ongoing <= '1';
281 285 END IF;
282 286 sample_f0_wen_s <= (OTHERS => '1');
283 287 sample_f1_wen_s <= (OTHERS => '1');
284 288 sample_f2_wen_s <= (OTHERS => '1');
285 289 END IF;
286 290 END IF;
287 291 END PROCESS;
288 292
289 293
290 294 error_input_fifo_write <= error_wen_f2 & error_wen_f1 & error_wen_f0;
291 295
292 296
293 297 switch_f0_inst : spectral_matrix_switch_f0
294 298 PORT MAP (
295 299 clk => clk,
296 300 rstn => rstn,
297 301
298 302 sample_wen => sample_f0_wen_s,
299 303
300 304 fifo_A_empty => sample_f0_A_empty,
301 305 fifo_A_full => sample_f0_A_full,
302 306 fifo_A_wen => sample_f0_A_wen,
303 307
304 308 fifo_B_empty => sample_f0_B_empty,
305 309 fifo_B_full => sample_f0_B_full,
306 310 fifo_B_wen => sample_f0_B_wen,
307 311
308 312 error_wen => error_wen_f0); -- TODO
309 313
310 314 -----------------------------------------------------------------------------
311 315 -- FIFO IN
312 316 -----------------------------------------------------------------------------
313 317 lppFIFOxN_f0_a : lppFIFOxN
314 318 GENERIC MAP (
315 319 tech => 0,
316 320 Mem_use => Mem_use,
317 321 Data_sz => 16,
318 322 Addr_sz => 8,
319 323 FifoCnt => 5)
320 324 PORT MAP (
321 325 clk => clk,
322 326 rstn => rstn,
323 327
324 328 ReUse => (OTHERS => '0'),
325 329
326 330 run => (OTHERS => '1'),
327 331
328 332 wen => sample_f0_A_wen,
329 333 wdata => sample_f0_wdata,
330 334
331 335 ren => sample_f0_A_ren,
332 336 rdata => sample_f0_A_rdata,
333 337
334 338 empty => sample_f0_A_empty,
335 339 full => sample_f0_A_full,
336 340 almost_full => OPEN);
337 341
338 342 lppFIFOxN_f0_b : lppFIFOxN
339 343 GENERIC MAP (
340 344 tech => 0,
341 345 Mem_use => Mem_use,
342 346 Data_sz => 16,
343 347 Addr_sz => 8,
344 348 FifoCnt => 5)
345 349 PORT MAP (
346 350 clk => clk,
347 351 rstn => rstn,
348 352
349 353 ReUse => (OTHERS => '0'),
350 354 run => (OTHERS => '1'),
351 355
352 356 wen => sample_f0_B_wen,
353 357 wdata => sample_f0_wdata,
354 358 ren => sample_f0_B_ren,
355 359 rdata => sample_f0_B_rdata,
356 360 empty => sample_f0_B_empty,
357 361 full => sample_f0_B_full,
358 362 almost_full => OPEN);
359 363
360 364 -----------------------------------------------------------------------------
361 365 -- sample_f1_wen in
362 366 -- sample_f1_wdata in
363 367 -- sample_f1_full OUT
364 368
365 369 sample_f1_wen_head_in <= '0' WHEN sample_f1_wen_s = "00000" ELSE '1';
366 370 sample_f1_full_head_in <= '0' WHEN sample_f1_full = "00000" ELSE '1';
367 371 sample_f1_empty_head_in <= '1' WHEN sample_f1_empty = "11111" ELSE '0';
368 372
369 373 lpp_lfr_ms_reg_head_1:lpp_lfr_ms_reg_head
370 374 PORT MAP (
371 375 clk => clk,
372 376 rstn => rstn,
373 377 in_wen => sample_f1_wen_head_in,
374 378 in_data => sample_f1_wdata,
375 379 in_full => sample_f1_full_head_in,
376 380 in_empty => sample_f1_empty_head_in,
377 381 out_wen => sample_f1_wen_head_out,
378 382 out_data => sample_f1_wdata_head,
379 383 out_full => sample_f1_full_head_out);
380 384
381 385 sample_f1_wen_head <= sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out;
382 386
383 387
384 388 lppFIFOxN_f1 : lppFIFOxN
385 389 GENERIC MAP (
386 390 tech => 0,
387 391 Mem_use => Mem_use,
388 392 Data_sz => 16,
389 393 Addr_sz => 8,
390 394 FifoCnt => 5)
391 395 PORT MAP (
392 396 clk => clk,
393 397 rstn => rstn,
394 398
395 399 ReUse => (OTHERS => '0'),
396 400 run => (OTHERS => '1'),
397 401
398 402 wen => sample_f1_wen_head,
399 403 wdata => sample_f1_wdata_head,
400 404 ren => sample_f1_ren,
401 405 rdata => sample_f1_rdata,
402 406 empty => sample_f1_empty,
403 407 full => sample_f1_full,
404 408 almost_full => sample_f1_almost_full);
405 409
406 410
407 411 one_sample_f1_wen <= '0' WHEN sample_f1_wen_s = "11111" ELSE '1';
408 412
409 413 PROCESS (clk, rstn)
410 414 BEGIN -- PROCESS
411 415 IF rstn = '0' THEN -- asynchronous reset (active low)
412 416 one_sample_f1_full <= '0';
413 417 error_wen_f1 <= '0';
414 418 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
415 419 IF sample_f1_full_head_out = '0' THEN
416 420 one_sample_f1_full <= '0';
417 421 ELSE
418 422 one_sample_f1_full <= '1';
419 423 END IF;
420 424 error_wen_f1 <= one_sample_f1_wen AND one_sample_f1_full;
421 425 END IF;
422 426 END PROCESS;
423 427
424 428 -----------------------------------------------------------------------------
425 429
426 430
427 431 lppFIFOxN_f2 : lppFIFOxN
428 432 GENERIC MAP (
429 433 tech => 0,
430 434 Mem_use => Mem_use,
431 435 Data_sz => 16,
432 436 Addr_sz => 8,
433 437 FifoCnt => 5)
434 438 PORT MAP (
435 439 clk => clk,
436 440 rstn => rstn,
437 441
438 442 ReUse => (OTHERS => '0'),
439 443 run => (OTHERS => '1'),
440 444
441 445 wen => sample_f2_wen,
442 446 wdata => sample_f2_wdata,
443 447 ren => sample_f2_ren,
444 448 rdata => sample_f2_rdata,
445 449 empty => sample_f2_empty,
446 450 full => sample_f2_full,
447 451 almost_full => OPEN);
448 452
449 453
450 454 one_sample_f2_wen <= '0' WHEN sample_f2_wen_s = "11111" ELSE '1';
451 455
452 456 PROCESS (clk, rstn)
453 457 BEGIN -- PROCESS
454 458 IF rstn = '0' THEN -- asynchronous reset (active low)
455 459 one_sample_f2_full <= '0';
456 460 error_wen_f2 <= '0';
457 461 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
458 462 IF sample_f2_full = "00000" THEN
459 463 one_sample_f2_full <= '0';
460 464 ELSE
461 465 one_sample_f2_full <= '1';
462 466 END IF;
463 467 error_wen_f2 <= one_sample_f2_wen AND one_sample_f2_full;
464 468 END IF;
465 469 END PROCESS;
466 470
467 471 -----------------------------------------------------------------------------
468 472 -- FSM SELECT CHANNEL
469 473 -----------------------------------------------------------------------------
470 474 PROCESS (clk, rstn)
471 475 BEGIN
472 476 IF rstn = '0' THEN
473 477 state_fsm_select_channel <= IDLE;
478 select_channel <= (OTHERS => '0');
474 479 ELSIF clk'EVENT AND clk = '1' THEN
475 480 CASE state_fsm_select_channel IS
476 481 WHEN IDLE =>
477 482 IF sample_f1_full = "11111" THEN
478 483 state_fsm_select_channel <= SWITCH_F1;
484 select_channel <= "10";
479 485 ELSIF sample_f1_almost_full = "00000" THEN
480 486 IF sample_f0_A_full = "11111" THEN
481 487 state_fsm_select_channel <= SWITCH_F0_A;
488 select_channel <= "00";
482 489 ELSIF sample_f0_B_full = "11111" THEN
483 490 state_fsm_select_channel <= SWITCH_F0_B;
491 select_channel <= "01";
484 492 ELSIF sample_f2_full = "11111" THEN
485 493 state_fsm_select_channel <= SWITCH_F2;
494 select_channel <= "11";
486 495 END IF;
487 496 END IF;
488 497
489 498 WHEN SWITCH_F0_A =>
490 499 IF sample_f0_A_empty = "11111" THEN
491 500 state_fsm_select_channel <= IDLE;
501 select_channel <= (OTHERS => '0');
492 502 END IF;
493 503 WHEN SWITCH_F0_B =>
494 504 IF sample_f0_B_empty = "11111" THEN
495 505 state_fsm_select_channel <= IDLE;
506 select_channel <= (OTHERS => '0');
496 507 END IF;
497 508 WHEN SWITCH_F1 =>
498 509 IF sample_f1_empty = "11111" THEN
499 510 state_fsm_select_channel <= IDLE;
511 select_channel <= (OTHERS => '0');
500 512 END IF;
501 513 WHEN SWITCH_F2 =>
502 514 IF sample_f2_empty = "11111" THEN
503 515 state_fsm_select_channel <= IDLE;
516 select_channel <= (OTHERS => '0');
504 517 END IF;
505 518 WHEN OTHERS => NULL;
506 519 END CASE;
507 520
508 521 END IF;
509 522 END PROCESS;
510 523
511 524 PROCESS (clk, rstn)
512 525 BEGIN
513 526 IF rstn = '0' THEN
514 pre_state_fsm_select_channel <= IDLE;
527 select_channel_reg <= (OTHERS => '0');
528 --pre_state_fsm_select_channel <= IDLE;
515 529 ELSIF clk'EVENT AND clk = '1' THEN
516 pre_state_fsm_select_channel <= state_fsm_select_channel;
530 select_channel_reg <= select_channel;
531 --pre_state_fsm_select_channel <= state_fsm_select_channel;
517 532 END IF;
518 533 END PROCESS;
519 534
520 535
521 536 -----------------------------------------------------------------------------
522 537 -- SWITCH SELECT CHANNEL
523 538 -----------------------------------------------------------------------------
524 539 sample_empty <= sample_f0_A_empty WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
525 540 sample_f0_B_empty WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
526 541 sample_f1_empty WHEN state_fsm_select_channel = SWITCH_F1 ELSE
527 542 sample_f2_empty WHEN state_fsm_select_channel = SWITCH_F2 ELSE
528 543 (OTHERS => '1');
529 544
530 545 sample_full <= sample_f0_A_full WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
531 546 sample_f0_B_full WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
532 547 sample_f1_full WHEN state_fsm_select_channel = SWITCH_F1 ELSE
533 548 sample_f2_full WHEN state_fsm_select_channel = SWITCH_F2 ELSE
534 549 (OTHERS => '0');
535 550
536 sample_rdata <= sample_f0_A_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_A ELSE
537 sample_f0_B_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_B ELSE
538 sample_f1_rdata WHEN pre_state_fsm_select_channel = SWITCH_F1 ELSE
551 --sample_rdata <= sample_f0_A_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_A ELSE
552 -- sample_f0_B_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_B ELSE
553 -- sample_f1_rdata WHEN pre_state_fsm_select_channel = SWITCH_F1 ELSE
554 -- sample_f2_rdata; -- WHEN state_fsm_select_channel = SWITCH_F2 ELSE
555 sample_rdata <= sample_f0_A_rdata WHEN select_channel_reg = "00" ELSE
556 sample_f0_B_rdata WHEN select_channel_reg = "01" ELSE
557 sample_f1_rdata WHEN select_channel_reg = "10" ELSE
539 558 sample_f2_rdata; -- WHEN state_fsm_select_channel = SWITCH_F2 ELSE
540 559
541 560
542 561 sample_f0_A_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_A ELSE (OTHERS => '1');
543 562 sample_f0_B_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_B ELSE (OTHERS => '1');
544 563 sample_f1_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F1 ELSE (OTHERS => '1');
545 564 sample_f2_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F2 ELSE (OTHERS => '1');
546 565
547 566
548 567 status_channel <= time_reg_f0_A & "00" WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
549 568 time_reg_f0_B & "00" WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
550 569 time_reg_f1 & "01" WHEN state_fsm_select_channel = SWITCH_F1 ELSE
551 570 time_reg_f2 & "10"; -- WHEN state_fsm_select_channel = SWITCH_F2
552 571
553 572 -----------------------------------------------------------------------------
554 573 -- FSM LOAD FFT
555 574 -----------------------------------------------------------------------------
556 575
557 576 sample_ren <= (OTHERS => '1') WHEN fft_ongoing_counter = '1' ELSE
558 577 sample_ren_s WHEN sample_load = '1' ELSE
559 578 (OTHERS => '1');
560 579
561 580 PROCESS (clk, rstn)
562 581 BEGIN
563 582 IF rstn = '0' THEN
564 583 sample_ren_s <= (OTHERS => '1');
565 584 state_fsm_load_FFT <= IDLE;
566 585 status_MS_input <= (OTHERS => '0');
586 select_fifo <= "000";
567 587 --next_state_fsm_load_FFT <= IDLE;
568 588 --sample_valid <= '0';
569 589 ELSIF clk'EVENT AND clk = '1' THEN
570 590 CASE state_fsm_load_FFT IS
571 591 WHEN IDLE =>
572 592 --sample_valid <= '0';
573 593 sample_ren_s <= (OTHERS => '1');
574 594 IF sample_full = "11111" AND sample_load = '1' THEN
575 595 state_fsm_load_FFT <= FIFO_1;
576 596 status_MS_input <= status_channel;
597 select_fifo <= "000";
577 598 END IF;
578 599
579 600 WHEN FIFO_1 =>
580 601 sample_ren_s <= "1111" & NOT(sample_load);
581 602 IF sample_empty(0) = '1' THEN
582 603 sample_ren_s <= (OTHERS => '1');
583 604 state_fsm_load_FFT <= FIFO_2;
605 select_fifo <= "001";
584 606 END IF;
585 607
586 608 WHEN FIFO_2 =>
587 609 sample_ren_s <= "111" & NOT(sample_load) & '1';
588 610 IF sample_empty(1) = '1' THEN
589 611 sample_ren_s <= (OTHERS => '1');
590 612 state_fsm_load_FFT <= FIFO_3;
613 select_fifo <= "010";
591 614 END IF;
592 615
593 616 WHEN FIFO_3 =>
594 617 sample_ren_s <= "11" & NOT(sample_load) & "11";
595 618 IF sample_empty(2) = '1' THEN
596 619 sample_ren_s <= (OTHERS => '1');
597 620 state_fsm_load_FFT <= FIFO_4;
621 select_fifo <= "011";
598 622 END IF;
599 623
600 624 WHEN FIFO_4 =>
601 625 sample_ren_s <= '1' & NOT(sample_load) & "111";
602 626 IF sample_empty(3) = '1' THEN
603 627 sample_ren_s <= (OTHERS => '1');
604 628 state_fsm_load_FFT <= FIFO_5;
629 select_fifo <= "100";
605 630 END IF;
606 631
607 632 WHEN FIFO_5 =>
608 633 sample_ren_s <= NOT(sample_load) & "1111";
609 634 IF sample_empty(4) = '1' THEN
610 635 sample_ren_s <= (OTHERS => '1');
611 636 state_fsm_load_FFT <= IDLE;
637 select_fifo <= "000";
612 638 END IF;
613 639 WHEN OTHERS => NULL;
614 640 END CASE;
615 641 END IF;
616 642 END PROCESS;
617 643
618 644 PROCESS (clk, rstn)
619 645 BEGIN
620 646 IF rstn = '0' THEN
621 647 sample_valid_r <= '0';
622 next_state_fsm_load_FFT <= IDLE;
648 select_fifo_reg <= (OTHERS => '0');
649 --next_state_fsm_load_FFT <= IDLE;
623 650 ELSIF clk'EVENT AND clk = '1' THEN
624 next_state_fsm_load_FFT <= state_fsm_load_FFT;
651 select_fifo_reg <= select_fifo;
652 --next_state_fsm_load_FFT <= state_fsm_load_FFT;
625 653 IF sample_ren_s = "11111" THEN
626 654 sample_valid_r <= '0';
627 655 ELSE
628 656 sample_valid_r <= '1';
629 657 END IF;
630 658 END IF;
631 659 END PROCESS;
632 660
633 661 sample_valid <= '0' WHEN fft_ongoing_counter = '1' ELSE sample_valid_r AND sample_load;
634 662
635 sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN next_state_fsm_load_FFT = FIFO_1 ELSE
636 sample_rdata(16*2-1 DOWNTO 16*1) WHEN next_state_fsm_load_FFT = FIFO_2 ELSE
637 sample_rdata(16*3-1 DOWNTO 16*2) WHEN next_state_fsm_load_FFT = FIFO_3 ELSE
638 sample_rdata(16*4-1 DOWNTO 16*3) WHEN next_state_fsm_load_FFT = FIFO_4 ELSE
663 --sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN next_state_fsm_load_FFT = FIFO_1 ELSE
664 -- sample_rdata(16*2-1 DOWNTO 16*1) WHEN next_state_fsm_load_FFT = FIFO_2 ELSE
665 -- sample_rdata(16*3-1 DOWNTO 16*2) WHEN next_state_fsm_load_FFT = FIFO_3 ELSE
666 -- sample_rdata(16*4-1 DOWNTO 16*3) WHEN next_state_fsm_load_FFT = FIFO_4 ELSE
667 -- sample_rdata(16*5-1 DOWNTO 16*4); --WHEN next_state_fsm_load_FFT = FIFO_5 ELSE
668 sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN select_fifo_reg = "000" ELSE
669 sample_rdata(16*2-1 DOWNTO 16*1) WHEN select_fifo_reg = "001" ELSE
670 sample_rdata(16*3-1 DOWNTO 16*2) WHEN select_fifo_reg = "010" ELSE
671 sample_rdata(16*4-1 DOWNTO 16*3) WHEN select_fifo_reg = "011" ELSE
639 672 sample_rdata(16*5-1 DOWNTO 16*4); --WHEN next_state_fsm_load_FFT = FIFO_5 ELSE
640
673
641 674 -----------------------------------------------------------------------------
642 675 -- FFT
643 676 -----------------------------------------------------------------------------
644 677 lpp_lfr_ms_FFT_1 : lpp_lfr_ms_FFT
645 678 PORT MAP (
646 679 clk => clk,
647 680 rstn => rstn,
648 681 sample_valid => sample_valid,
649 682 fft_read => fft_read,
650 683 sample_data => sample_data,
651 684 sample_load => sample_load,
652 685 fft_pong => fft_pong,
653 686 fft_data_im => fft_data_im,
654 687 fft_data_re => fft_data_re,
655 688 fft_data_valid => fft_data_valid,
656 689 fft_ready => fft_ready);
657 690
658 691 -----------------------------------------------------------------------------
659 692 fft_ready_rising_down <= fft_ready_reg AND NOT fft_ready;
660 693 sample_load_rising_down <= sample_load_reg AND NOT sample_load;
661 694
662 695 PROCESS (clk, rstn)
663 696 BEGIN
664 697 IF rstn = '0' THEN
665 698 fft_ready_reg <= '0';
666 699 sample_load_reg <= '0';
667 700
668 701 fft_ongoing_counter <= '0';
669 702 ELSIF clk'event AND clk = '1' THEN
670 703 fft_ready_reg <= fft_ready;
671 704 sample_load_reg <= sample_load;
672 705
673 706 IF fft_ready_rising_down = '1' AND sample_load_rising_down = '0' THEN
674 707 fft_ongoing_counter <= '0';
675 708
676 709 -- CASE fft_ongoing_counter IS
677 710 -- WHEN "01" => fft_ongoing_counter <= "00";
678 711 ---- WHEN "10" => fft_ongoing_counter <= "01";
679 712 -- WHEN OTHERS => NULL;
680 713 -- END CASE;
681 714 ELSIF fft_ready_rising_down = '0' AND sample_load_rising_down = '1' THEN
682 715 fft_ongoing_counter <= '1';
683 716 -- CASE fft_ongoing_counter IS
684 717 -- WHEN "00" => fft_ongoing_counter <= "01";
685 718 ---- WHEN "01" => fft_ongoing_counter <= "10";
686 719 -- WHEN OTHERS => NULL;
687 720 -- END CASE;
688 721 END IF;
689 722
690 723 END IF;
691 724 END PROCESS;
692 725
693 726 -----------------------------------------------------------------------------
694 727 PROCESS (clk, rstn)
695 728 BEGIN
696 729 IF rstn = '0' THEN
697 730 state_fsm_load_MS_memory <= IDLE;
698 731 current_fifo_load <= "00001";
699 732 ELSIF clk'EVENT AND clk = '1' THEN
700 733 CASE state_fsm_load_MS_memory IS
701 734 WHEN IDLE =>
702 735 IF current_fifo_empty = '1' AND fft_ready = '1' AND current_fifo_locked = '0' THEN
703 736 state_fsm_load_MS_memory <= LOAD_FIFO;
704 737 END IF;
705 738 WHEN LOAD_FIFO =>
706 739 IF current_fifo_full = '1' THEN
707 740 state_fsm_load_MS_memory <= TRASH_FFT;
708 741 END IF;
709 742 WHEN TRASH_FFT =>
710 743 IF fft_ready = '0' THEN
711 744 state_fsm_load_MS_memory <= IDLE;
712 745 current_fifo_load <= current_fifo_load(3 DOWNTO 0) & current_fifo_load(4);
713 746 END IF;
714 747 WHEN OTHERS => NULL;
715 748 END CASE;
716 749
717 750 END IF;
718 751 END PROCESS;
719 752
720 753 current_fifo_empty <= MEM_IN_SM_Empty(0) WHEN current_fifo_load(0) = '1' ELSE
721 754 MEM_IN_SM_Empty(1) WHEN current_fifo_load(1) = '1' ELSE
722 755 MEM_IN_SM_Empty(2) WHEN current_fifo_load(2) = '1' ELSE
723 756 MEM_IN_SM_Empty(3) WHEN current_fifo_load(3) = '1' ELSE
724 757 MEM_IN_SM_Empty(4); -- WHEN current_fifo_load(3) = '1' ELSE
725 758
726 759 current_fifo_full <= MEM_IN_SM_Full(0) WHEN current_fifo_load(0) = '1' ELSE
727 760 MEM_IN_SM_Full(1) WHEN current_fifo_load(1) = '1' ELSE
728 761 MEM_IN_SM_Full(2) WHEN current_fifo_load(2) = '1' ELSE
729 762 MEM_IN_SM_Full(3) WHEN current_fifo_load(3) = '1' ELSE
730 763 MEM_IN_SM_Full(4); -- WHEN current_fifo_load(3) = '1' ELSE
731 764
732 765 current_fifo_locked <= MEM_IN_SM_locked(0) WHEN current_fifo_load(0) = '1' ELSE
733 766 MEM_IN_SM_locked(1) WHEN current_fifo_load(1) = '1' ELSE
734 767 MEM_IN_SM_locked(2) WHEN current_fifo_load(2) = '1' ELSE
735 768 MEM_IN_SM_locked(3) WHEN current_fifo_load(3) = '1' ELSE
736 769 MEM_IN_SM_locked(4); -- WHEN current_fifo_load(3) = '1' ELSE
737 770
738 771 fft_read <= '0' WHEN state_fsm_load_MS_memory = IDLE ELSE '1';
739 772
740 773 all_fifo : FOR I IN 4 DOWNTO 0 GENERATE
741 774 MEM_IN_SM_wen_s(I) <= '0' WHEN fft_data_valid = '1'
742 775 AND state_fsm_load_MS_memory = LOAD_FIFO
743 776 AND current_fifo_load(I) = '1'
744 777 ELSE '1';
745 778 END GENERATE all_fifo;
746 779
747 780 PROCESS (clk, rstn)
748 781 BEGIN
749 782 IF rstn = '0' THEN
750 783 MEM_IN_SM_wen <= (OTHERS => '1');
751 784 ELSIF clk'EVENT AND clk = '1' THEN
752 785 MEM_IN_SM_wen <= MEM_IN_SM_wen_s;
753 786 END IF;
754 787 END PROCESS;
755 788
756 789 MEM_IN_SM_wData <= (fft_data_im & fft_data_re) &
757 790 (fft_data_im & fft_data_re) &
758 791 (fft_data_im & fft_data_re) &
759 792 (fft_data_im & fft_data_re) &
760 793 (fft_data_im & fft_data_re);
761 794 -----------------------------------------------------------------------------
762 795
763 796
764 797 -----------------------------------------------------------------------------
765 798 Mem_In_SpectralMatrix : lppFIFOxN
766 799 GENERIC MAP (
767 800 tech => 0,
768 801 Mem_use => Mem_use,
769 802 Data_sz => 32, --16,
770 803 Addr_sz => 7, --8
771 804 FifoCnt => 5)
772 805 PORT MAP (
773 806 clk => clk,
774 807 rstn => rstn,
775 808
776 809 ReUse => MEM_IN_SM_ReUse,
777 810 run => (OTHERS => '1'),
778 811
779 812 wen => MEM_IN_SM_wen,
780 813 wdata => MEM_IN_SM_wData,
781 814
782 815 ren => MEM_IN_SM_ren,
783 816 rdata => MEM_IN_SM_rData,
784 817 full => MEM_IN_SM_Full,
785 818 empty => MEM_IN_SM_Empty,
786 819 almost_full => OPEN);
787 820
788 821
789 822 -----------------------------------------------------------------------------
790 823 MS_control_1 : MS_control
791 824 PORT MAP (
792 825 clk => clk,
793 826 rstn => rstn,
794 827
795 828 current_status_ms => status_MS_input,
796 829
797 830 fifo_in_lock => MEM_IN_SM_locked,
798 831 fifo_in_data => MEM_IN_SM_rdata,
799 832 fifo_in_full => MEM_IN_SM_Full,
800 833 fifo_in_empty => MEM_IN_SM_Empty,
801 834 fifo_in_ren => MEM_IN_SM_ren,
802 835 fifo_in_reuse => MEM_IN_SM_ReUse,
803 836
804 837 fifo_out_data => SM_in_data,
805 838 fifo_out_ren => SM_in_ren,
806 839 fifo_out_empty => SM_in_empty,
807 840
808 841 current_status_component => status_component,
809 842
810 843 correlation_start => SM_correlation_start,
811 844 correlation_auto => SM_correlation_auto,
812 845 correlation_done => SM_correlation_done);
813 846
814 847
815 848 MS_calculation_1 : MS_calculation
816 849 PORT MAP (
817 850 clk => clk,
818 851 rstn => rstn,
819 852
820 853 fifo_in_data => SM_in_data,
821 854 fifo_in_ren => SM_in_ren,
822 855 fifo_in_empty => SM_in_empty,
823 856
824 857 fifo_out_data => MEM_OUT_SM_Data_in_s, -- TODO
825 858 fifo_out_wen => MEM_OUT_SM_Write_s, -- TODO
826 859 fifo_out_full => MEM_OUT_SM_Full_s, -- TODO
827 860
828 861 correlation_start => SM_correlation_start,
829 862 correlation_auto => SM_correlation_auto,
830 863 correlation_begin => SM_correlation_begin,
831 864 correlation_done => SM_correlation_done);
832 865
833 866 -----------------------------------------------------------------------------
834 867 PROCESS (clk, rstn)
835 868 BEGIN -- PROCESS
836 869 IF rstn = '0' THEN -- asynchronous reset (active low)
837 870 current_matrix_write <= '0';
838 871 current_matrix_wait_empty <= '1';
839 872 status_component_fifo_0 <= (OTHERS => '0');
840 873 status_component_fifo_1 <= (OTHERS => '0');
841 874 status_component_fifo_0_end <= '0';
842 875 status_component_fifo_1_end <= '0';
843 876 SM_correlation_done_reg1 <= '0';
844 877 SM_correlation_done_reg2 <= '0';
845 878 SM_correlation_done_reg3 <= '0';
846 879
847 880 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
848 881 SM_correlation_done_reg1 <= SM_correlation_done;
849 882 SM_correlation_done_reg2 <= SM_correlation_done_reg1;
850 883 SM_correlation_done_reg3 <= SM_correlation_done_reg2;
851 884 status_component_fifo_0_end <= '0';
852 885 status_component_fifo_1_end <= '0';
853 886 IF SM_correlation_begin = '1' THEN
854 887 IF current_matrix_write = '0' THEN
855 status_component_fifo_0 <= status_component;
888 status_component_fifo_0 <= status_component(53 DOWNTO 4);
856 889 ELSE
857 status_component_fifo_1 <= status_component;
890 status_component_fifo_1 <= status_component(53 DOWNTO 4);
858 891 END IF;
859 892 END IF;
860 893
861 894 IF SM_correlation_done_reg3 = '1' THEN
862 895 IF current_matrix_write = '0' THEN
863 896 status_component_fifo_0_end <= '1';
864 897 ELSE
865 898 status_component_fifo_1_end <= '1';
866 899 END IF;
867 900 current_matrix_wait_empty <= '1';
868 901 current_matrix_write <= NOT current_matrix_write;
869 902 END IF;
870 903
871 904 IF current_matrix_wait_empty <= '1' THEN
872 905 IF current_matrix_write = '0' THEN
873 906 current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(0);
874 907 ELSE
875 908 current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(1);
876 909 END IF;
877 910 END IF;
878 911
879 912 END IF;
880 913 END PROCESS;
881 914
882 915 MEM_OUT_SM_Full_s <= '1' WHEN SM_correlation_done = '1' ELSE
883 916 '1' WHEN SM_correlation_done_reg1 = '1' ELSE
884 917 '1' WHEN SM_correlation_done_reg2 = '1' ELSE
885 918 '1' WHEN SM_correlation_done_reg3 = '1' ELSE
886 919 '1' WHEN current_matrix_wait_empty = '1' ELSE
887 920 MEM_OUT_SM_Full(0) WHEN current_matrix_write = '0' ELSE
888 921 MEM_OUT_SM_Full(1);
889 922
890 923 MEM_OUT_SM_Write(0) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '0' ELSE '1';
891 924 MEM_OUT_SM_Write(1) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '1' ELSE '1';
892 925
893 926 MEM_OUT_SM_Data_in <= MEM_OUT_SM_Data_in_s & MEM_OUT_SM_Data_in_s;
894 927 -----------------------------------------------------------------------------
895 928
896 929 --Mem_Out_SpectralMatrix : lppFIFOxN
897 930 -- GENERIC MAP (
898 931 -- tech => 0,
899 932 -- Mem_use => Mem_use,
900 933 -- Data_sz => 32,
901 934 -- Addr_sz => 8,
902 935 -- FifoCnt => 2)
903 936 -- PORT MAP (
904 937 -- clk => clk,
905 938 -- rstn => rstn,
906 939
907 940 -- ReUse => (OTHERS => '0'),
908 941 -- run => (OTHERS => '1'),
909 942
910 943 -- wen => MEM_OUT_SM_Write,
911 944 -- wdata => MEM_OUT_SM_Data_in,
912 945
913 946 -- ren => MEM_OUT_SM_Read,
914 947 -- rdata => MEM_OUT_SM_Data_out,
915 948
916 949 -- full => MEM_OUT_SM_Full,
917 950 -- empty => MEM_OUT_SM_Empty,
918 951 -- almost_full => OPEN);
919 952
920 953
921 954 all_Mem_Out_SpectralMatrix: FOR I IN 1 DOWNTO 0 GENERATE
922 955 Mem_Out_SpectralMatrix_I: lpp_fifo
923 956 GENERIC MAP (
924 957 tech => 0,
925 958 Mem_use => Mem_use,
926 959 EMPTY_THRESHOLD_LIMIT => 15,
927 960 FULL_THRESHOLD_LIMIT => 1,
928 961 DataSz => 32,
929 962 AddrSz => 8)
930 963 PORT MAP (
931 964 clk => clk,
932 965 rstn => rstn,
933 966 reUse => '0',
934 967 run => run,
935 968
936 969 ren => MEM_OUT_SM_Read(I),
937 970 rdata => MEM_OUT_SM_Data_out(32*(I+1)-1 DOWNTO 32*i),
938 971
939 972 wen => MEM_OUT_SM_Write(I),
940 973 wdata => MEM_OUT_SM_Data_in(32*(I+1)-1 DOWNTO 32*i),
941 974
942 975 empty => MEM_OUT_SM_Empty(I),
943 976 full => MEM_OUT_SM_Full(I),
944 977 full_almost => OPEN,
945 978 empty_threshold => MEM_OUT_SM_Empty_Threshold(I),
946 979
947 980 full_threshold => OPEN);
948 981
949 982 END GENERATE all_Mem_Out_SpectralMatrix;
950 983
951 984 -----------------------------------------------------------------------------
952 985 -- MEM_OUT_SM_Read <= "00";
953 986 PROCESS (clk, rstn)
954 987 BEGIN
955 988 IF rstn = '0' THEN
956 989 fifo_0_ready <= '0';
957 990 fifo_1_ready <= '0';
958 991 fifo_ongoing <= '0';
959 992 ELSIF clk'EVENT AND clk = '1' THEN
960 993 IF fifo_0_ready = '1' AND MEM_OUT_SM_Empty(0) = '1' THEN
961 994 fifo_ongoing <= '1';
962 995 fifo_0_ready <= '0';
963 996 ELSIF status_component_fifo_0_end = '1' THEN
964 997 fifo_0_ready <= '1';
965 998 END IF;
966 999
967 1000 IF fifo_1_ready = '1' AND MEM_OUT_SM_Empty(1) = '1' THEN
968 1001 fifo_ongoing <= '0';
969 1002 fifo_1_ready <= '0';
970 1003 ELSIF status_component_fifo_1_end = '1' THEN
971 1004 fifo_1_ready <= '1';
972 1005 END IF;
973 1006
974 1007 END IF;
975 1008 END PROCESS;
976 1009
977 1010 MEM_OUT_SM_Read(0) <= '1' WHEN fifo_ongoing = '1' ELSE
978 1011 '1' WHEN fifo_0_ready = '0' ELSE
979 1012 FSM_DMA_fifo_ren;
980 1013
981 1014 MEM_OUT_SM_Read(1) <= '1' WHEN fifo_ongoing = '0' ELSE
982 1015 '1' WHEN fifo_1_ready = '0' ELSE
983 1016 FSM_DMA_fifo_ren;
984 1017
985 1018 FSM_DMA_fifo_empty <= MEM_OUT_SM_Empty(0) WHEN fifo_ongoing = '0' AND fifo_0_ready = '1' ELSE
986 1019 MEM_OUT_SM_Empty(1) WHEN fifo_ongoing = '1' AND fifo_1_ready = '1' ELSE
987 1020 '1';
988 1021
989 1022 FSM_DMA_fifo_status <= status_component_fifo_0 WHEN fifo_ongoing = '0' ELSE
990 1023 status_component_fifo_1;
991 1024
992 1025 FSM_DMA_fifo_data <= MEM_OUT_SM_Data_out(31 DOWNTO 0) WHEN fifo_ongoing = '0' ELSE
993 1026 MEM_OUT_SM_Data_out(63 DOWNTO 32);
994 1027
995 1028
996 1029 FSM_DMA_fifo_empty_threshold <= MEM_OUT_SM_Empty_Threshold(0) WHEN fifo_ongoing = '0' AND fifo_0_ready = '1' ELSE
997 1030 MEM_OUT_SM_Empty_Threshold(1) WHEN fifo_ongoing = '1' AND fifo_1_ready = '1' ELSE
998 1031 '1';
999 1032
1000 1033 -----------------------------------------------------------------------------
1001 1034 -- fifo_matrix_type => FSM_DMA_fifo_status(5 DOWNTO 4), --IN
1002 1035 -- fifo_matrix_component => FSM_DMA_fifo_status(3 DOWNTO 0), --IN
1003 1036 -- fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6), --IN
1004 1037 -- fifo_data => FSM_DMA_fifo_data, --IN
1005 1038 -- fifo_empty => FSM_DMA_fifo_empty, --IN
1006 1039 -- fifo_empty_threshold => FSM_DMA_fifo_empty_threshold, --IN
1007 1040 -- fifo_ren => FSM_DMA_fifo_ren, --OUT
1008 1041
1009 1042
1010 1043 lpp_lfr_ms_fsmdma_1: lpp_lfr_ms_fsmdma
1011 1044 PORT MAP (
1012 1045 clk => clk,
1013 1046 rstn => rstn,
1014 1047 run => run,
1015 1048
1016 1049 fifo_matrix_type => FSM_DMA_fifo_status(5 DOWNTO 4),
1017 1050 fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6),
1018 1051 fifo_data => FSM_DMA_fifo_data,
1019 1052 fifo_empty => FSM_DMA_fifo_empty,
1020 1053 fifo_empty_threshold => FSM_DMA_fifo_empty_threshold,
1021 1054 fifo_ren => FSM_DMA_fifo_ren,
1022 1055
1023 1056 dma_fifo_valid_burst => dma_fifo_burst_valid,
1024 1057 dma_fifo_data => dma_fifo_data,
1025 1058 dma_fifo_ren => dma_fifo_ren,
1026 1059 dma_buffer_new => dma_buffer_new,
1027 1060 dma_buffer_addr => dma_buffer_addr,
1028 1061 dma_buffer_length => dma_buffer_length,
1029 1062 dma_buffer_full => dma_buffer_full,
1030 1063 dma_buffer_full_err => dma_buffer_full_err,
1031 1064
1032 1065 status_ready_matrix_f0 => status_ready_matrix_f0,
1033 1066 status_ready_matrix_f1 => status_ready_matrix_f1,
1034 1067 status_ready_matrix_f2 => status_ready_matrix_f2,
1035 1068 addr_matrix_f0 => addr_matrix_f0,
1036 1069 addr_matrix_f1 => addr_matrix_f1,
1037 1070 addr_matrix_f2 => addr_matrix_f2,
1038 1071 length_matrix_f0 => length_matrix_f0,
1039 1072 length_matrix_f1 => length_matrix_f1,
1040 1073 length_matrix_f2 => length_matrix_f2,
1041 1074 ready_matrix_f0 => ready_matrix_f0,
1042 1075 ready_matrix_f1 => ready_matrix_f1,
1043 1076 ready_matrix_f2 => ready_matrix_f2,
1044 1077 matrix_time_f0 => matrix_time_f0,
1045 1078 matrix_time_f1 => matrix_time_f1,
1046 1079 matrix_time_f2 => matrix_time_f2,
1047 1080 error_buffer_full => error_buffer_full);
1048 1081
1049 1082
1050 1083
1051 1084
1052 1085
1053 1086 --dma_fifo_burst_valid: OUT STD_LOGIC; --TODO
1054 1087 --dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --TODO
1055 1088 --dma_fifo_ren : IN STD_LOGIC; --TODO
1056 1089 --dma_buffer_new : OUT STD_LOGIC; --TODO
1057 1090 --dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --TODO
1058 1091 --dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); --TODO
1059 1092 --dma_buffer_full : IN STD_LOGIC; --TODO
1060 1093 --dma_buffer_full_err : IN STD_LOGIC; --TODO
1061 1094
1062 1095 ---- Reg out
1063 1096 --ready_matrix_f0 : OUT STD_LOGIC; -- TODO
1064 1097 --ready_matrix_f1 : OUT STD_LOGIC; -- TODO
1065 1098 --ready_matrix_f2 : OUT STD_LOGIC; -- TODO
1066 1099 --error_bad_component_error : OUT STD_LOGIC; -- TODO
1067 1100 --error_buffer_full : OUT STD_LOGIC; -- TODO
1068 1101
1069 1102 ---- Reg In
1070 1103 --status_ready_matrix_f0 : IN STD_LOGIC; -- TODO
1071 1104 --status_ready_matrix_f1 : IN STD_LOGIC; -- TODO
1072 1105 --status_ready_matrix_f2 : IN STD_LOGIC; -- TODO
1073 1106
1074 1107 --addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
1075 1108 --addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
1076 1109 --addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
1077 1110
1078 1111 --matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
1079 1112 --matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
1080 1113 --matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) -- TODO
1081 1114 -----------------------------------------------------------------------------
1082 1115
1083 1116 -----------------------------------------------------------------------------
1084 1117 --lpp_lfr_ms_fsmdma_1 : lpp_lfr_ms_fsmdma
1085 1118 -- PORT MAP (
1086 1119 -- HCLK => clk,
1087 1120 -- HRESETn => rstn,
1088 1121
1089 1122 -- fifo_matrix_type => FSM_DMA_fifo_status(5 DOWNTO 4),
1090 1123 -- fifo_matrix_component => FSM_DMA_fifo_status(3 DOWNTO 0),
1091 1124 -- fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6),
1092 1125 -- fifo_data => FSM_DMA_fifo_data,
1093 1126 -- fifo_empty => FSM_DMA_fifo_empty,
1094 1127 -- fifo_ren => FSM_DMA_fifo_ren,
1095 1128
1096 1129 -- dma_addr => dma_addr,
1097 1130 -- dma_data => dma_data,
1098 1131 -- dma_valid => dma_valid,
1099 1132 -- dma_valid_burst => dma_valid_burst,
1100 1133 -- dma_ren => dma_ren,
1101 1134 -- dma_done => dma_done,
1102 1135
1103 1136 -- ready_matrix_f0 => ready_matrix_f0,
1104 1137 -- ready_matrix_f1 => ready_matrix_f1,
1105 1138 -- ready_matrix_f2 => ready_matrix_f2,
1106 1139
1107 1140 -- error_bad_component_error => error_bad_component_error,
1108 1141 -- error_buffer_full => error_buffer_full,
1109 1142
1110 1143 -- debug_reg => debug_reg,
1111 1144 -- status_ready_matrix_f0 => status_ready_matrix_f0,
1112 1145 -- status_ready_matrix_f1 => status_ready_matrix_f1,
1113 1146 -- status_ready_matrix_f2 => status_ready_matrix_f2,
1114 1147
1115 1148 -- config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
1116 1149 -- config_active_interruption_onError => config_active_interruption_onError,
1117 1150
1118 1151 -- addr_matrix_f0 => addr_matrix_f0,
1119 1152 -- addr_matrix_f1 => addr_matrix_f1,
1120 1153 -- addr_matrix_f2 => addr_matrix_f2,
1121 1154
1122 1155 -- matrix_time_f0 => matrix_time_f0,
1123 1156 -- matrix_time_f1 => matrix_time_f1,
1124 1157 -- matrix_time_f2 => matrix_time_f2
1125 1158 -- );
1126 1159 -----------------------------------------------------------------------------
1127 1160
1128 1161
1129 1162
1130 1163
1131 1164
1132 1165
1133 1166 -----------------------------------------------------------------------------
1134 1167 -- TIME MANAGMENT
1135 1168 -----------------------------------------------------------------------------
1136 1169 all_time <= coarse_time & fine_time;
1137 1170 --
1138 1171 f_empty(0) <= '1' WHEN sample_f0_A_empty = "11111" ELSE '0';
1139 1172 f_empty(1) <= '1' WHEN sample_f0_B_empty = "11111" ELSE '0';
1140 1173 f_empty(2) <= '1' WHEN sample_f1_empty = "11111" ELSE '0';
1141 1174 f_empty(3) <= '1' WHEN sample_f2_empty = "11111" ELSE '0';
1142 1175
1143 1176 all_time_reg: FOR I IN 0 TO 3 GENERATE
1144 1177
1145 1178 PROCESS (clk, rstn)
1146 1179 BEGIN
1147 1180 IF rstn = '0' THEN
1148 1181 f_empty_reg(I) <= '1';
1149 1182 ELSIF clk'event AND clk = '1' THEN
1150 1183 f_empty_reg(I) <= f_empty(I);
1151 1184 END IF;
1152 1185 END PROCESS;
1153 1186
1154 1187 time_update_f(I) <= '1' WHEN f_empty(I) = '0' AND f_empty_reg(I) = '1' ELSE '0';
1155 1188
1156 1189 s_m_t_m_f0_A : spectral_matrix_time_managment
1157 1190 PORT MAP (
1158 1191 clk => clk,
1159 1192 rstn => rstn,
1160 1193 time_in => all_time,
1161 1194 update_1 => time_update_f(I),
1162 1195 time_out => time_reg_f((I+1)*48-1 DOWNTO I*48)
1163 1196 );
1164 1197
1165 1198 END GENERATE all_time_reg;
1166 1199
1167 1200 time_reg_f0_A <= time_reg_f((0+1)*48-1 DOWNTO 0*48);
1168 1201 time_reg_f0_B <= time_reg_f((1+1)*48-1 DOWNTO 1*48);
1169 1202 time_reg_f1 <= time_reg_f((2+1)*48-1 DOWNTO 2*48);
1170 1203 time_reg_f2 <= time_reg_f((3+1)*48-1 DOWNTO 3*48);
1171 1204
1172 1205 -----------------------------------------------------------------------------
1173 1206
1174 1207 END Behavioral;
Show file before | Show file after | Hide comments
@@ -1,386 +1,386
1 1 LIBRARY ieee;
2 2 USE ieee.std_logic_1164.ALL;
3 3
4 4 LIBRARY grlib;
5 5 USE grlib.amba.ALL;
6 6
7 7 LIBRARY lpp;
8 8 USE lpp.lpp_ad_conv.ALL;
9 9 USE lpp.iir_filter.ALL;
10 10 USE lpp.FILTERcfg.ALL;
11 11 USE lpp.lpp_memory.ALL;
12 12 LIBRARY techmap;
13 13 USE techmap.gencomp.ALL;
14 14
15 15 PACKAGE lpp_lfr_pkg IS
16 16 -----------------------------------------------------------------------------
17 17 -- TEMP
18 18 -----------------------------------------------------------------------------
19 19 COMPONENT lpp_lfr_ms_test
20 20 GENERIC (
21 21 Mem_use : INTEGER);
22 22 PORT (
23 23 clk : IN STD_LOGIC;
24 24 rstn : IN STD_LOGIC;
25 25
26 26 -- TIME
27 27 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
28 28 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
29 29 --
30 30 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
31 31 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
32 32 --
33 33 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
34 34 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
35 35 --
36 36 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
37 37 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
38 38
39 39
40 40
41 41 ---------------------------------------------------------------------------
42 42 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
43 43
44 44 --
45 45 --sample_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
46 46 --sample_full : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
47 47 --sample_empty : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
48 48 --sample_rdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
49 49
50 50 --status_channel : IN STD_LOGIC_VECTOR(49 DOWNTO 0);
51 51
52 52 -- IN
53 53 MEM_IN_SM_locked : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
54 54
55 55 -----------------------------------------------------------------------------
56 56
57 57 status_component : OUT STD_LOGIC_VECTOR(53 DOWNTO 0);
58 58 SM_in_data : OUT STD_LOGIC_VECTOR(32*2-1 DOWNTO 0);
59 59 SM_in_ren : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
60 60 SM_in_empty : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
61 61
62 62 SM_correlation_start : OUT STD_LOGIC;
63 63 SM_correlation_auto : OUT STD_LOGIC;
64 64 SM_correlation_done : IN STD_LOGIC
65 65 );
66 66 END COMPONENT;
67 67
68 68
69 69 -----------------------------------------------------------------------------
70 70 COMPONENT lpp_lfr_ms
71 71 GENERIC (
72 72 Mem_use : INTEGER);
73 73 PORT (
74 74 clk : IN STD_LOGIC;
75 75 rstn : IN STD_LOGIC;
76 76 run : IN STD_LOGIC;
77 77 start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
78 78 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
79 79 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
80 80 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
81 81 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
82 82 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
83 83 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
84 84 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
85 85 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
86 86 dma_fifo_burst_valid : OUT STD_LOGIC;
87 87 dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
88 88 dma_fifo_ren : IN STD_LOGIC;
89 89 dma_buffer_new : OUT STD_LOGIC;
90 90 dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
91 91 dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
92 92 dma_buffer_full : IN STD_LOGIC;
93 93 dma_buffer_full_err : IN STD_LOGIC;
94 94 ready_matrix_f0 : OUT STD_LOGIC;
95 95 ready_matrix_f1 : OUT STD_LOGIC;
96 96 ready_matrix_f2 : OUT STD_LOGIC;
97 97 error_buffer_full : OUT STD_LOGIC;
98 98 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
99 99 status_ready_matrix_f0 : IN STD_LOGIC;
100 100 status_ready_matrix_f1 : IN STD_LOGIC;
101 101 status_ready_matrix_f2 : IN STD_LOGIC;
102 102 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
103 103 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
104 104 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
105 105 length_matrix_f0 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
106 106 length_matrix_f1 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
107 107 length_matrix_f2 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
108 108 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
109 109 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
110 110 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0));
111 111 END COMPONENT;
112 112
113 113 COMPONENT lpp_lfr_ms_fsmdma
114 114 PORT (
115 115 clk : IN STD_ULOGIC;
116 116 rstn : IN STD_ULOGIC;
117 117 run : IN STD_LOGIC;
118 118 fifo_matrix_type : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
119 119 fifo_matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
120 120 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
121 121 fifo_empty : IN STD_LOGIC;
122 122 fifo_empty_threshold : IN STD_LOGIC;
123 123 fifo_ren : OUT STD_LOGIC;
124 124 dma_fifo_valid_burst : OUT STD_LOGIC;
125 125 dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
126 126 dma_fifo_ren : IN STD_LOGIC;
127 127 dma_buffer_new : OUT STD_LOGIC;
128 128 dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
129 129 dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
130 130 dma_buffer_full : IN STD_LOGIC;
131 131 dma_buffer_full_err : IN STD_LOGIC;
132 132 status_ready_matrix_f0 : IN STD_LOGIC;
133 133 status_ready_matrix_f1 : IN STD_LOGIC;
134 134 status_ready_matrix_f2 : IN STD_LOGIC;
135 135 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
136 136 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
137 137 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
138 138 length_matrix_f0 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
139 139 length_matrix_f1 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
140 140 length_matrix_f2 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
141 141 ready_matrix_f0 : OUT STD_LOGIC;
142 142 ready_matrix_f1 : OUT STD_LOGIC;
143 143 ready_matrix_f2 : OUT STD_LOGIC;
144 144 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
145 145 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
146 146 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
147 147 error_buffer_full : OUT STD_LOGIC);
148 148 END COMPONENT;
149 149
150 150 COMPONENT lpp_lfr_ms_FFT
151 151 PORT (
152 152 clk : IN STD_LOGIC;
153 153 rstn : IN STD_LOGIC;
154 154 sample_valid : IN STD_LOGIC;
155 155 fft_read : IN STD_LOGIC;
156 156 sample_data : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
157 157 sample_load : OUT STD_LOGIC;
158 158 fft_pong : OUT STD_LOGIC;
159 159 fft_data_im : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
160 160 fft_data_re : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
161 161 fft_data_valid : OUT STD_LOGIC;
162 162 fft_ready : OUT STD_LOGIC);
163 163 END COMPONENT;
164 164
165 165 COMPONENT lpp_lfr_filter
166 166 GENERIC (
167 167 Mem_use : INTEGER);
168 168 PORT (
169 169 sample : IN Samples(7 DOWNTO 0);
170 170 sample_val : IN STD_LOGIC;
171 171 clk : IN STD_LOGIC;
172 172 rstn : IN STD_LOGIC;
173 173 data_shaping_SP0 : IN STD_LOGIC;
174 174 data_shaping_SP1 : IN STD_LOGIC;
175 175 data_shaping_R0 : IN STD_LOGIC;
176 176 data_shaping_R1 : IN STD_LOGIC;
177 177 data_shaping_R2 : IN STD_LOGIC;
178 178 sample_f0_val : OUT STD_LOGIC;
179 179 sample_f1_val : OUT STD_LOGIC;
180 180 sample_f2_val : OUT STD_LOGIC;
181 181 sample_f3_val : OUT STD_LOGIC;
182 182 sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
183 183 sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
184 184 sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
185 185 sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0));
186 186 END COMPONENT;
187 187
188 188 COMPONENT lpp_lfr
189 189 GENERIC (
190 190 Mem_use : INTEGER;
191 191 nb_data_by_buffer_size : INTEGER;
192 192 -- nb_word_by_buffer_size : INTEGER;
193 193 nb_snapshot_param_size : INTEGER;
194 194 delta_vector_size : INTEGER;
195 195 delta_vector_size_f0_2 : INTEGER;
196 196 pindex : INTEGER;
197 197 paddr : INTEGER;
198 198 pmask : INTEGER;
199 199 pirq_ms : INTEGER;
200 200 pirq_wfp : INTEGER;
201 201 hindex : INTEGER;
202 202 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0)
203 203 );
204 204 PORT (
205 205 clk : IN STD_LOGIC;
206 206 rstn : IN STD_LOGIC;
207 207 sample_B : IN Samples(2 DOWNTO 0);
208 208 sample_E : IN Samples(4 DOWNTO 0);
209 209 sample_val : IN STD_LOGIC;
210 210 apbi : IN apb_slv_in_type;
211 211 apbo : OUT apb_slv_out_type;
212 212 ahbi : IN AHB_Mst_In_Type;
213 213 ahbo : OUT AHB_Mst_Out_Type;
214 214 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
215 215 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
216 216 data_shaping_BW : OUT STD_LOGIC
217 217 );
218 218 END COMPONENT;
219 219
220 220 -----------------------------------------------------------------------------
221 221 -- LPP_LFR with only WaveForm Picker (and without Spectral Matrix Sub System)
222 222 -----------------------------------------------------------------------------
223 223 COMPONENT lpp_lfr_WFP_nMS
224 224 GENERIC (
225 225 Mem_use : INTEGER;
226 226 nb_data_by_buffer_size : INTEGER;
227 227 nb_word_by_buffer_size : INTEGER;
228 228 nb_snapshot_param_size : INTEGER;
229 229 delta_vector_size : INTEGER;
230 230 delta_vector_size_f0_2 : INTEGER;
231 231 pindex : INTEGER;
232 232 paddr : INTEGER;
233 233 pmask : INTEGER;
234 234 pirq_ms : INTEGER;
235 235 pirq_wfp : INTEGER;
236 236 hindex : INTEGER;
237 237 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0));
238 238 PORT (
239 239 clk : IN STD_LOGIC;
240 240 rstn : IN STD_LOGIC;
241 241 sample_B : IN Samples(2 DOWNTO 0);
242 242 sample_E : IN Samples(4 DOWNTO 0);
243 243 sample_val : IN STD_LOGIC;
244 244 apbi : IN apb_slv_in_type;
245 245 apbo : OUT apb_slv_out_type;
246 246 ahbi : IN AHB_Mst_In_Type;
247 247 ahbo : OUT AHB_Mst_Out_Type;
248 248 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
249 249 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
250 250 data_shaping_BW : OUT STD_LOGIC;
251 251 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
252 252 END COMPONENT;
253 253 -----------------------------------------------------------------------------
254 254
255 255 COMPONENT lpp_lfr_apbreg
256 256 GENERIC (
257 257 nb_data_by_buffer_size : INTEGER;
258 258 nb_snapshot_param_size : INTEGER;
259 259 delta_vector_size : INTEGER;
260 260 delta_vector_size_f0_2 : INTEGER;
261 261 pindex : INTEGER;
262 262 paddr : INTEGER;
263 263 pmask : INTEGER;
264 264 pirq_ms : INTEGER;
265 265 pirq_wfp : INTEGER;
266 266 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0));
267 267 PORT (
268 268 HCLK : IN STD_ULOGIC;
269 269 HRESETn : IN STD_ULOGIC;
270 270 apbi : IN apb_slv_in_type;
271 271 apbo : OUT apb_slv_out_type;
272 272 run_ms : OUT STD_LOGIC;
273 273 ready_matrix_f0 : IN STD_LOGIC;
274 274 ready_matrix_f1 : IN STD_LOGIC;
275 275 ready_matrix_f2 : IN STD_LOGIC;
276 276 error_buffer_full : IN STD_LOGIC;
277 277 error_input_fifo_write : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
278 278 status_ready_matrix_f0 : OUT STD_LOGIC;
279 279 status_ready_matrix_f1 : OUT STD_LOGIC;
280 280 status_ready_matrix_f2 : OUT STD_LOGIC;
281 281 addr_matrix_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
282 282 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
283 283 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
284 284 length_matrix_f0 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
285 285 length_matrix_f1 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
286 286 length_matrix_f2 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
287 287 matrix_time_f0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
288 288 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
289 289 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
290 290 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
291 291 data_shaping_BW : OUT STD_LOGIC;
292 292 data_shaping_SP0 : OUT STD_LOGIC;
293 293 data_shaping_SP1 : OUT STD_LOGIC;
294 294 data_shaping_R0 : OUT STD_LOGIC;
295 295 data_shaping_R1 : OUT STD_LOGIC;
296 296 data_shaping_R2 : OUT STD_LOGIC;
297 297 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
298 298 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
299 299 delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
300 300 delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
301 301 delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
302 302 nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
303 303 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
304 304 enable_f0 : OUT STD_LOGIC;
305 305 enable_f1 : OUT STD_LOGIC;
306 306 enable_f2 : OUT STD_LOGIC;
307 307 enable_f3 : OUT STD_LOGIC;
308 308 burst_f0 : OUT STD_LOGIC;
309 309 burst_f1 : OUT STD_LOGIC;
310 310 burst_f2 : OUT STD_LOGIC;
311 311 run : OUT STD_LOGIC;
312 312 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
313 313 wfp_status_buffer_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
314 wfp_addr_buffer : OUT STD_LOGIC_VECTOR(32*4 DOWNTO 0);
314 wfp_addr_buffer : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
315 315 wfp_length_buffer : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
316 316 wfp_ready_buffer : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
317 317 wfp_buffer_time : IN STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
318 318 wfp_error_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0));
319 319 END COMPONENT;
320 320
321 321 COMPONENT lpp_top_ms
322 322 GENERIC (
323 323 Mem_use : INTEGER;
324 324 nb_burst_available_size : INTEGER;
325 325 nb_snapshot_param_size : INTEGER;
326 326 delta_snapshot_size : INTEGER;
327 327 delta_f2_f0_size : INTEGER;
328 328 delta_f2_f1_size : INTEGER;
329 329 pindex : INTEGER;
330 330 paddr : INTEGER;
331 331 pmask : INTEGER;
332 332 pirq_ms : INTEGER;
333 333 pirq_wfp : INTEGER;
334 334 hindex_wfp : INTEGER;
335 335 hindex_ms : INTEGER);
336 336 PORT (
337 337 clk : IN STD_LOGIC;
338 338 rstn : IN STD_LOGIC;
339 339 sample_B : IN Samples14v(2 DOWNTO 0);
340 340 sample_E : IN Samples14v(4 DOWNTO 0);
341 341 sample_val : IN STD_LOGIC;
342 342 apbi : IN apb_slv_in_type;
343 343 apbo : OUT apb_slv_out_type;
344 344 ahbi_ms : IN AHB_Mst_In_Type;
345 345 ahbo_ms : OUT AHB_Mst_Out_Type;
346 346 data_shaping_BW : OUT STD_LOGIC;
347 347 matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
348 348 matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
349 349 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
350 350 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0)
351 351 );
352 352 END COMPONENT;
353 353
354 354 COMPONENT lpp_apbreg_ms_pointer
355 355 PORT (
356 356 clk : IN STD_LOGIC;
357 357 rstn : IN STD_LOGIC;
358 358 run : IN STD_LOGIC;
359 359 reg0_status_ready_matrix : IN STD_LOGIC;
360 360 reg0_ready_matrix : OUT STD_LOGIC;
361 361 reg0_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
362 362 reg0_matrix_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
363 363 reg1_status_ready_matrix : IN STD_LOGIC;
364 364 reg1_ready_matrix : OUT STD_LOGIC;
365 365 reg1_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
366 366 reg1_matrix_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
367 367 ready_matrix : IN STD_LOGIC;
368 368 status_ready_matrix : OUT STD_LOGIC;
369 369 addr_matrix : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
370 370 matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0));
371 371 END COMPONENT;
372 372
373 373 COMPONENT lpp_lfr_ms_reg_head
374 374 PORT (
375 375 clk : IN STD_LOGIC;
376 376 rstn : IN STD_LOGIC;
377 377 in_wen : IN STD_LOGIC;
378 378 in_data : IN STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
379 379 in_full : IN STD_LOGIC;
380 380 in_empty : IN STD_LOGIC;
381 381 out_wen : OUT STD_LOGIC;
382 382 out_data : OUT STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
383 383 out_full : OUT STD_LOGIC);
384 384 END COMPONENT;
385 385
386 386 END lpp_lfr_pkg;
Show file before | Show file after | Hide comments
@@ -1,471 +1,471
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -- jean-christophe.pellion@easii-ic.com
22 22 -------------------------------------------------------------------------------
23 23 LIBRARY IEEE;
24 24 USE IEEE.STD_LOGIC_1164.ALL;
25 25 USE ieee.numeric_std.ALL;
26 26
27 27 LIBRARY grlib;
28 28 USE grlib.amba.ALL;
29 29 USE grlib.stdlib.ALL;
30 30 USE grlib.devices.ALL;
31 31 USE GRLIB.DMA2AHB_Package.ALL;
32 32
33 33 LIBRARY lpp;
34 34 USE lpp.lpp_waveform_pkg.ALL;
35 35 USE lpp.iir_filter.ALL;
36 36 USE lpp.lpp_memory.ALL;
37 37
38 38 LIBRARY techmap;
39 39 USE techmap.gencomp.ALL;
40 40
41 41 ENTITY lpp_waveform IS
42 42
43 43 GENERIC (
44 44 tech : INTEGER := inferred;
45 45 data_size : INTEGER := 96; --16*6
46 46 nb_data_by_buffer_size : INTEGER := 11;
47 47 -- nb_word_by_buffer_size : INTEGER := 11;
48 48 nb_snapshot_param_size : INTEGER := 11;
49 49 delta_vector_size : INTEGER := 20;
50 50 delta_vector_size_f0_2 : INTEGER := 3);
51 51
52 52 PORT (
53 53 clk : IN STD_LOGIC;
54 54 rstn : IN STD_LOGIC;
55 55
56 56 ---- AMBA AHB Master Interface
57 57 --AHB_Master_In : IN AHB_Mst_In_Type; -- TODO
58 58 --AHB_Master_Out : OUT AHB_Mst_Out_Type; -- TODO
59 59
60 60 --config
61 61 reg_run : IN STD_LOGIC;
62 62 reg_start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
63 63 reg_delta_snapshot : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
64 64 reg_delta_f0 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
65 65 reg_delta_f0_2 : IN STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
66 66 reg_delta_f1 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
67 67 reg_delta_f2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
68 68
69 69 enable_f0 : IN STD_LOGIC;
70 70 enable_f1 : IN STD_LOGIC;
71 71 enable_f2 : IN STD_LOGIC;
72 72 enable_f3 : IN STD_LOGIC;
73 73
74 74 burst_f0 : IN STD_LOGIC;
75 75 burst_f1 : IN STD_LOGIC;
76 76 burst_f2 : IN STD_LOGIC;
77 77
78 78 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
79 79 -- nb_word_by_buffer : IN STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
80 80 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
81 81
82 82 status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma
83 83
84 84
85 85 -- REG DMA
86 86 status_buffer_ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
87 addr_buffer : IN STD_LOGIC_VECTOR(32*4 DOWNTO 0);
87 addr_buffer : IN STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
88 88 length_buffer : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
89 89
90 90 ready_buffer : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
91 91 buffer_time : OUT STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
92 92 error_buffer_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
93 93
94 94 ---------------------------------------------------------------------------
95 95 -- INPUT
96 96 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
97 97 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
98 98
99 99 --f0
100 100 data_f0_in_valid : IN STD_LOGIC;
101 101 data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
102 102 --f1
103 103 data_f1_in_valid : IN STD_LOGIC;
104 104 data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
105 105 --f2
106 106 data_f2_in_valid : IN STD_LOGIC;
107 107 data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
108 108 --f3
109 109 data_f3_in_valid : IN STD_LOGIC;
110 110 data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
111 111
112 112 ---------------------------------------------------------------------------
113 113 -- DMA --------------------------------------------------------------------
114 114
115 115 dma_fifo_valid_burst : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
116 116 dma_fifo_data : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
117 117 dma_fifo_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
118 118 dma_buffer_new : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
119 119 dma_buffer_addr : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
120 120 dma_buffer_length : OUT STD_LOGIC_VECTOR(26*4-1 DOWNTO 0);
121 121 dma_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
122 122 dma_buffer_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0)
123 123
124 124 );
125 125
126 126 END lpp_waveform;
127 127
128 128 ARCHITECTURE beh OF lpp_waveform IS
129 129 SIGNAL start_snapshot_f0 : STD_LOGIC;
130 130 SIGNAL start_snapshot_f1 : STD_LOGIC;
131 131 SIGNAL start_snapshot_f2 : STD_LOGIC;
132 132
133 133 SIGNAL data_f0_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
134 134 SIGNAL data_f1_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
135 135 SIGNAL data_f2_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
136 136 SIGNAL data_f3_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
137 137
138 138 SIGNAL data_f0_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
139 139 SIGNAL data_f1_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
140 140 SIGNAL data_f2_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
141 141 SIGNAL data_f3_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
142 142
143 143 SIGNAL data_f0_out_valid : STD_LOGIC;
144 144 SIGNAL data_f1_out_valid : STD_LOGIC;
145 145 SIGNAL data_f2_out_valid : STD_LOGIC;
146 146 SIGNAL data_f3_out_valid : STD_LOGIC;
147 147 SIGNAL nb_snapshot_param_more_one : STD_LOGIC_VECTOR(nb_snapshot_param_size DOWNTO 0);
148 148 --
149 149 SIGNAL valid_in : STD_LOGIC_VECTOR(3 DOWNTO 0);
150 150 SIGNAL valid_out : STD_LOGIC_VECTOR(3 DOWNTO 0);
151 151 SIGNAL valid_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
152 152 SIGNAL time_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
153 153 SIGNAL data_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
154 154 SIGNAL ready_arb : STD_LOGIC_VECTOR(3 DOWNTO 0);
155 155 SIGNAL data_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
156 156 SIGNAL time_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
157 157 SIGNAL wdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
158 158 SIGNAL full_almost : STD_LOGIC_VECTOR(3 DOWNTO 0);
159 159 SIGNAL full : STD_LOGIC_VECTOR(3 DOWNTO 0);
160 160 SIGNAL empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0);
161 161 SIGNAL empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
162 162 --
163 163 SIGNAL data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
164 164 SIGNAL time_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
165 165 SIGNAL rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
166 166 SIGNAL enable : STD_LOGIC_VECTOR(3 DOWNTO 0);
167 167 --
168 168 SIGNAL run : STD_LOGIC;
169 169 --
170 170 TYPE TIME_VECTOR IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(47 DOWNTO 0);
171 171 SIGNAL data_out : Data_Vector(3 DOWNTO 0, 95 DOWNTO 0);
172 172 SIGNAL time_out_2 : Data_Vector(3 DOWNTO 0, 47 DOWNTO 0);
173 173 SIGNAL time_out : TIME_VECTOR(3 DOWNTO 0);
174 174 SIGNAL time_out_debug : TIME_VECTOR(3 DOWNTO 0); -- TODO : debug
175 175 SIGNAL time_reg1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
176 176 SIGNAL time_reg2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
177 177 --
178 178
179 179 SIGNAL s_empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0); --occupancy is lesser than 16 * 32b
180 180 SIGNAL s_empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
181 181 SIGNAL s_data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
182 182 -- SIGNAL s_rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
183 183 SIGNAL s_rdata_v : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
184 184
185 185 --
186 186 SIGNAL arbiter_time_out : STD_LOGIC_VECTOR(47 DOWNTO 0);
187 187 SIGNAL arbiter_time_out_new : STD_LOGIC_VECTOR(3 DOWNTO 0);
188 188
189 189 SIGNAL fifo_buffer_time : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
190 190
191 191 BEGIN -- beh
192 192
193 193 -----------------------------------------------------------------------------
194 194
195 195 lpp_waveform_snapshot_controler_1 : lpp_waveform_snapshot_controler
196 196 GENERIC MAP (
197 197 delta_vector_size => delta_vector_size,
198 198 delta_vector_size_f0_2 => delta_vector_size_f0_2
199 199 )
200 200 PORT MAP (
201 201 clk => clk,
202 202 rstn => rstn,
203 203 reg_run => reg_run,
204 204 reg_start_date => reg_start_date,
205 205 reg_delta_snapshot => reg_delta_snapshot,
206 206 reg_delta_f0 => reg_delta_f0,
207 207 reg_delta_f0_2 => reg_delta_f0_2,
208 208 reg_delta_f1 => reg_delta_f1,
209 209 reg_delta_f2 => reg_delta_f2,
210 210 coarse_time => coarse_time(30 DOWNTO 0),
211 211 data_f0_valid => data_f0_in_valid,
212 212 data_f2_valid => data_f2_in_valid,
213 213 start_snapshot_f0 => start_snapshot_f0,
214 214 start_snapshot_f1 => start_snapshot_f1,
215 215 start_snapshot_f2 => start_snapshot_f2,
216 216 wfp_on => run);
217 217
218 218 lpp_waveform_snapshot_f0 : lpp_waveform_snapshot
219 219 GENERIC MAP (
220 220 data_size => data_size,
221 221 nb_snapshot_param_size => nb_snapshot_param_size)
222 222 PORT MAP (
223 223 clk => clk,
224 224 rstn => rstn,
225 225 run => run,
226 226 enable => enable_f0,
227 227 burst_enable => burst_f0,
228 228 nb_snapshot_param => nb_snapshot_param,
229 229 start_snapshot => start_snapshot_f0,
230 230 data_in => data_f0_in,
231 231 data_in_valid => data_f0_in_valid,
232 232 data_out => data_f0_out,
233 233 data_out_valid => data_f0_out_valid);
234 234
235 235 nb_snapshot_param_more_one <= ('0' & nb_snapshot_param) ;--+ 1;
236 236
237 237 lpp_waveform_snapshot_f1 : lpp_waveform_snapshot
238 238 GENERIC MAP (
239 239 data_size => data_size,
240 240 nb_snapshot_param_size => nb_snapshot_param_size+1)
241 241 PORT MAP (
242 242 clk => clk,
243 243 rstn => rstn,
244 244 run => run,
245 245 enable => enable_f1,
246 246 burst_enable => burst_f1,
247 247 nb_snapshot_param => nb_snapshot_param_more_one,
248 248 start_snapshot => start_snapshot_f1,
249 249 data_in => data_f1_in,
250 250 data_in_valid => data_f1_in_valid,
251 251 data_out => data_f1_out,
252 252 data_out_valid => data_f1_out_valid);
253 253
254 254 lpp_waveform_snapshot_f2 : lpp_waveform_snapshot
255 255 GENERIC MAP (
256 256 data_size => data_size,
257 257 nb_snapshot_param_size => nb_snapshot_param_size+1)
258 258 PORT MAP (
259 259 clk => clk,
260 260 rstn => rstn,
261 261 run => run,
262 262 enable => enable_f2,
263 263 burst_enable => burst_f2,
264 264 nb_snapshot_param => nb_snapshot_param_more_one,
265 265 start_snapshot => start_snapshot_f2,
266 266 data_in => data_f2_in,
267 267 data_in_valid => data_f2_in_valid,
268 268 data_out => data_f2_out,
269 269 data_out_valid => data_f2_out_valid);
270 270
271 271 lpp_waveform_burst_f3 : lpp_waveform_burst
272 272 GENERIC MAP (
273 273 data_size => data_size)
274 274 PORT MAP (
275 275 clk => clk,
276 276 rstn => rstn,
277 277 run => run,
278 278 enable => enable_f3,
279 279 data_in => data_f3_in,
280 280 data_in_valid => data_f3_in_valid,
281 281 data_out => data_f3_out,
282 282 data_out_valid => data_f3_out_valid);
283 283
284 284 -----------------------------------------------------------------------------
285 285 -- DEBUG -- SNAPSHOT OUT
286 286 --debug_f0_data_valid <= data_f0_out_valid;
287 287 --debug_f0_data <= data_f0_out;
288 288 --debug_f1_data_valid <= data_f1_out_valid;
289 289 --debug_f1_data <= data_f1_out;
290 290 --debug_f2_data_valid <= data_f2_out_valid;
291 291 --debug_f2_data <= data_f2_out;
292 292 --debug_f3_data_valid <= data_f3_out_valid;
293 293 --debug_f3_data <= data_f3_out;
294 294 -----------------------------------------------------------------------------
295 295
296 296 PROCESS (clk, rstn)
297 297 BEGIN -- PROCESS
298 298 IF rstn = '0' THEN -- asynchronous reset (active low)
299 299 time_reg1 <= (OTHERS => '0');
300 300 time_reg2 <= (OTHERS => '0');
301 301 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
302 302 time_reg1 <= fine_time & coarse_time;
303 303 time_reg2 <= time_reg1;
304 304 END IF;
305 305 END PROCESS;
306 306
307 307 valid_in <= data_f3_out_valid & data_f2_out_valid & data_f1_out_valid & data_f0_out_valid;
308 308 all_input_valid : FOR i IN 3 DOWNTO 0 GENERATE
309 309 lpp_waveform_dma_genvalid_I : lpp_waveform_dma_genvalid
310 310 PORT MAP (
311 311 HCLK => clk,
312 312 HRESETn => rstn,
313 313 run => run,
314 314 valid_in => valid_in(I),
315 315 ack_in => valid_ack(I),
316 316 time_in => time_reg2, -- Todo
317 317 valid_out => valid_out(I),
318 318 time_out => time_out(I), -- Todo
319 319 error => status_new_err(I));
320 320 END GENERATE all_input_valid;
321 321
322 322 data_f0_out_swap <= data_f0_out((16*5)-1 DOWNTO 16*4) &
323 323 data_f0_out((16*6)-1 DOWNTO 16*5) &
324 324 data_f0_out((16*3)-1 DOWNTO 16*2) &
325 325 data_f0_out((16*4)-1 DOWNTO 16*3) &
326 326 data_f0_out((16*1)-1 DOWNTO 16*0) &
327 327 data_f0_out((16*2)-1 DOWNTO 16*1) ;
328 328
329 329 data_f1_out_swap <= data_f1_out((16*5)-1 DOWNTO 16*4) &
330 330 data_f1_out((16*6)-1 DOWNTO 16*5) &
331 331 data_f1_out((16*3)-1 DOWNTO 16*2) &
332 332 data_f1_out((16*4)-1 DOWNTO 16*3) &
333 333 data_f1_out((16*1)-1 DOWNTO 16*0) &
334 334 data_f1_out((16*2)-1 DOWNTO 16*1) ;
335 335
336 336 data_f2_out_swap <= data_f2_out((16*5)-1 DOWNTO 16*4) &
337 337 data_f2_out((16*6)-1 DOWNTO 16*5) &
338 338 data_f2_out((16*3)-1 DOWNTO 16*2) &
339 339 data_f2_out((16*4)-1 DOWNTO 16*3) &
340 340 data_f2_out((16*1)-1 DOWNTO 16*0) &
341 341 data_f2_out((16*2)-1 DOWNTO 16*1) ;
342 342
343 343 data_f3_out_swap <= data_f3_out((16*5)-1 DOWNTO 16*4) &
344 344 data_f3_out((16*6)-1 DOWNTO 16*5) &
345 345 data_f3_out((16*3)-1 DOWNTO 16*2) &
346 346 data_f3_out((16*4)-1 DOWNTO 16*3) &
347 347 data_f3_out((16*1)-1 DOWNTO 16*0) &
348 348 data_f3_out((16*2)-1 DOWNTO 16*1) ;
349 349
350 350 all_bit_of_data_out : FOR I IN 95 DOWNTO 0 GENERATE
351 351 data_out(0, I) <= data_f0_out_swap(I);
352 352 data_out(1, I) <= data_f1_out_swap(I);
353 353 data_out(2, I) <= data_f2_out_swap(I);
354 354 data_out(3, I) <= data_f3_out_swap(I);
355 355 END GENERATE all_bit_of_data_out;
356 356
357 357 -----------------------------------------------------------------------------
358 358 -- TODO : debug
359 359 -----------------------------------------------------------------------------
360 360 all_bit_of_time_out : FOR I IN 47 DOWNTO 0 GENERATE
361 361 all_sample_of_time_out : FOR J IN 3 DOWNTO 0 GENERATE
362 362 time_out_2(J, I) <= time_out(J)(I);
363 363 END GENERATE all_sample_of_time_out;
364 364 END GENERATE all_bit_of_time_out;
365 365
366 366 lpp_waveform_fifo_arbiter_1 : lpp_waveform_fifo_arbiter
367 367 GENERIC MAP (tech => tech,
368 368 nb_data_by_buffer_size => nb_data_by_buffer_size)
369 369 PORT MAP (
370 370 clk => clk,
371 371 rstn => rstn,
372 372 run => run,
373 373 nb_data_by_buffer => nb_data_by_buffer,
374 374 data_in_valid => valid_out,
375 375 data_in_ack => valid_ack,
376 376 data_in => data_out,
377 377 time_in => time_out_2,
378 378
379 379 data_out => wdata,
380 380 data_out_wen => data_wen,
381 381 full_almost => full_almost,
382 382 full => full,
383 383
384 384 time_out => arbiter_time_out,
385 385 time_out_new => arbiter_time_out_new
386 386
387 387 );
388 388
389 389 -----------------------------------------------------------------------------
390 390 -----------------------------------------------------------------------------
391 391
392 392 generate_all_fifo: FOR I IN 0 TO 3 GENERATE
393 393 lpp_fifo_1: lpp_fifo
394 394 GENERIC MAP (
395 395 tech => tech,
396 396 Mem_use => use_RAM,
397 397 EMPTY_THRESHOLD_LIMIT => 15,
398 398 FULL_THRESHOLD_LIMIT => 3,
399 399 DataSz => 32,
400 400 AddrSz => 7)
401 401 PORT MAP (
402 402 clk => clk,
403 403 rstn => rstn,
404 404 reUse => '0',
405 405 run => run,
406 406 ren => data_ren(I),
407 407 rdata => s_rdata_v((I+1)*32-1 downto I*32),
408 408 wen => data_wen(I),
409 409 wdata => wdata,
410 410 empty => empty(I),
411 411 full => full(I),
412 412 full_almost => OPEN,
413 413 empty_threshold => empty_almost(I),
414 414 full_threshold => full_almost(I) );
415 415
416 416 END GENERATE generate_all_fifo;
417 417
418 418 -----------------------------------------------------------------------------
419 419 --
420 420 -----------------------------------------------------------------------------
421 421
422 422 all_channel: FOR I IN 3 DOWNTO 0 GENERATE
423 423
424 424 PROCESS (clk, rstn)
425 425 BEGIN
426 426 IF rstn = '0' THEN
427 427 fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I) <= (OTHERS => '0');
428 428 ELSIF clk'event AND clk = '1' THEN
429 429 IF run = '0' THEN
430 430 fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I) <= (OTHERS => '0');
431 431 ELSE
432 432 IF arbiter_time_out_new(I) = '0' THEN
433 433 fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I) <= arbiter_time_out;
434 434 END IF;
435 435 END IF;
436 436 END IF;
437 437 END PROCESS;
438 438
439 439 lpp_waveform_fsmdma_I: lpp_waveform_fsmdma
440 440 PORT MAP (
441 441 clk => clk,
442 442 rstn => rstn,
443 443 run => run,
444 444
445 445 fifo_buffer_time => fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I),
446 446
447 447 fifo_data => s_rdata_v(32*(I+1)-1 DOWNTO 32*I),
448 448 fifo_empty => empty(I),
449 449 fifo_empty_threshold => empty_almost(I),
450 450 fifo_ren => data_ren(I),
451 451
452 452 dma_fifo_valid_burst => dma_fifo_valid_burst(I),
453 453 dma_fifo_data => dma_fifo_data(32*(I+1)-1 DOWNTO 32*I),
454 454 dma_fifo_ren => dma_fifo_ren(I),
455 455 dma_buffer_new => dma_buffer_new(I),
456 456 dma_buffer_addr => dma_buffer_addr(32*(I+1)-1 DOWNTO 32*I),
457 457 dma_buffer_length => dma_buffer_length(26*(I+1)-1 DOWNTO 26*I),
458 458 dma_buffer_full => dma_buffer_full(I),
459 459 dma_buffer_full_err => dma_buffer_full_err(I),
460 460
461 461 status_buffer_ready => status_buffer_ready(I), -- TODO
462 462 addr_buffer => addr_buffer(32*(I+1)-1 DOWNTO 32*I), -- TODO
463 463 length_buffer => length_buffer,--(26*(I+1)-1 DOWNTO 26*I), -- TODO
464 464 ready_buffer => ready_buffer(I), -- TODO
465 465 buffer_time => buffer_time(48*(I+1)-1 DOWNTO 48*I), -- TODO
466 466 error_buffer_full => error_buffer_full(I)); -- TODO
467 467
468 468 END GENERATE all_channel;
469 469
470 470
471 471 END beh;
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@@ -1,270 +1,269
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 ------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe PELLION
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 ------------------------------------------------------------------------------
22 22 LIBRARY IEEE;
23 23 USE IEEE.std_logic_1164.ALL;
24 24 USE IEEE.numeric_std.ALL;
25 25
26 26 LIBRARY lpp;
27 27 USE lpp.lpp_waveform_pkg.ALL;
28 28 USE lpp.general_purpose.ALL;
29 29
30 30 ENTITY lpp_waveform_fifo_arbiter IS
31 31 GENERIC(
32 32 tech : INTEGER := 0;
33 33 nb_data_by_buffer_size : INTEGER := 11
34 34 );
35 35 PORT(
36 36 clk : IN STD_LOGIC;
37 37 rstn : IN STD_LOGIC;
38 38 ---------------------------------------------------------------------------
39 39 run : IN STD_LOGIC;
40 40 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size - 1 DOWNTO 0);
41 41 ---------------------------------------------------------------------------
42 42 -- SNAPSHOT INTERFACE (INPUT)
43 43 ---------------------------------------------------------------------------
44 44 data_in_valid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
45 45 data_in_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
46 46 data_in : IN Data_Vector(3 DOWNTO 0, 95 DOWNTO 0);
47 47
48 48 time_in : IN Data_Vector(3 DOWNTO 0, 47 DOWNTO 0);
49 49
50 50 ---------------------------------------------------------------------------
51 51 -- FIFO INTERFACE (OUTPUT)
52 52 ---------------------------------------------------------------------------
53 53 data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
54 54 data_out_wen : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
55 55 full_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
56 56 full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
57 57
58 58 ---------------------------------------------------------------------------
59 59 -- TIME INTERFACE (OUTPUT)
60 60 ---------------------------------------------------------------------------
61 61 time_out : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
62 62 time_out_new : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
63 63
64 64 );
65 65 END ENTITY;
66 66
67 67
68 68 ARCHITECTURE ar_lpp_waveform_fifo_arbiter OF lpp_waveform_fifo_arbiter IS
69 69 TYPE state_type_fifo_arbiter IS (IDLE,DATA1,DATA2,DATA3,LAST);
70 70 SIGNAL state : state_type_fifo_arbiter;
71 71
72 72 -----------------------------------------------------------------------------
73 73 -- DATA MUX
74 74 -----------------------------------------------------------------------------
75 75 TYPE WORD_VECTOR IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(31 DOWNTO 0);
76 SIGNAL data_0 : WORD_VECTOR(3 DOWNTO 0);
77 SIGNAL data_1 : WORD_VECTOR(3 DOWNTO 0);
78 SIGNAL data_2 : WORD_VECTOR(3 DOWNTO 0);
79 SIGNAL data_3 : WORD_VECTOR(3 DOWNTO 0);
80 SIGNAL data_sel : WORD_VECTOR(3 DOWNTO 0);
76 SIGNAL data_0 : WORD_VECTOR(2 DOWNTO 0);
77 SIGNAL data_1 : WORD_VECTOR(2 DOWNTO 0);
78 SIGNAL data_2 : WORD_VECTOR(2 DOWNTO 0);
79 SIGNAL data_3 : WORD_VECTOR(2 DOWNTO 0);
80 SIGNAL data_sel : WORD_VECTOR(2 DOWNTO 0);
81 81
82 82 -----------------------------------------------------------------------------
83 83 -- RR and SELECTION
84 84 -----------------------------------------------------------------------------
85 85 SIGNAL valid_in_rr : STD_LOGIC_VECTOR(3 DOWNTO 0);
86 86 SIGNAL sel : STD_LOGIC_VECTOR(3 DOWNTO 0);
87 87 SIGNAL sel_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
88 88 SIGNAL sel_reg : STD_LOGIC;
89 89 SIGNAL sel_ack : STD_LOGIC;
90 90 SIGNAL no_sel : STD_LOGIC;
91 91
92 92 -----------------------------------------------------------------------------
93 93 -- REG
94 94 -----------------------------------------------------------------------------
95 95 SIGNAL count_enable : STD_LOGIC;
96 96 SIGNAL count : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
97 97 SIGNAL count_s : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
98 98
99 99 SIGNAL time_sel : STD_LOGIC_VECTOR(47 DOWNTO 0);
100 100
101 101 BEGIN
102 102
103 103 -----------------------------------------------------------------------------
104 104 -- CONTROL
105 105 -----------------------------------------------------------------------------
106 106 PROCESS (clk, rstn)
107 107 BEGIN -- PROCESS
108 108 IF rstn = '0' THEN -- asynchronous reset (active low)
109 109 count_enable <= '0';
110 110 data_in_ack <= (OTHERS => '0');
111 111 data_out_wen <= (OTHERS => '1');
112 112 sel_ack <= '0';
113 113 state <= IDLE;
114 114 time_out <= (OTHERS => '0');
115 115 time_out_new <= (OTHERS => '0');
116 116 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
117 117 count_enable <= '0';
118 118 data_in_ack <= (OTHERS => '0');
119 119 data_out_wen <= (OTHERS => '1');
120 120 sel_ack <= '0';
121 121 time_out_new <= (OTHERS => '0');
122 122 IF run = '0' THEN
123 123 state <= IDLE;
124 124 time_out <= (OTHERS => '0');
125 125 ELSE
126 126 CASE state IS
127 127 WHEN IDLE =>
128 128 IF no_sel = '0' THEN
129 129 state <= DATA1;
130 130 END IF;
131 131 WHEN DATA1 =>
132 132 count_enable <= '1';
133 133 IF UNSIGNED(count) = 0 THEN
134 134 time_out <= time_sel;
135 135 time_out_new <= sel;
136 136 END IF;
137 137 data_out_wen <= NOT sel;
138 138 data_out <= data_sel(0);
139 139 state <= DATA2;
140 140 WHEN DATA2 =>
141 141 data_out_wen <= NOT sel;
142 142 data_out <= data_sel(1);
143 143 state <= DATA3;
144 144 WHEN DATA3 =>
145 145 data_out_wen <= NOT sel;
146 146 data_out <= data_sel(2);
147 147 state <= LAST;
148 148 data_in_ack <= sel;
149 149 WHEN LAST =>
150 150 state <= IDLE;
151 151 sel_ack <= '1';
152 152
153 153 WHEN OTHERS => NULL;
154 154 END CASE;
155 155 END IF;
156 156 END IF;
157 157 END PROCESS;
158 158 -----------------------------------------------------------------------------
159 159
160 160 -----------------------------------------------------------------------------
161 161 -- DATA MUX
162 162 -----------------------------------------------------------------------------
163 163
164 164 all_word: FOR J IN 2 DOWNTO 0 GENERATE
165 165 all_data_bit: FOR I IN 31 DOWNTO 0 GENERATE
166 166 data_0(J)(I) <= data_in(0,I+32*J);
167 167 data_1(J)(I) <= data_in(1,I+32*J);
168 168 data_2(J)(I) <= data_in(2,I+32*J);
169 169 data_3(J)(I) <= data_in(3,I+32*J);
170 170 END GENERATE all_data_bit;
171 171 END GENERATE all_word;
172 172
173 173 data_sel <= data_0 WHEN sel(0) = '1' ELSE
174 174 data_1 WHEN sel(1) = '1' ELSE
175 175 data_2 WHEN sel(2) = '1' ELSE
176 176 data_3;
177 177
178 178 all_time_bit: FOR I IN 47 DOWNTO 0 GENERATE
179 179
180 180 time_sel(I) <= time_in(0,I) WHEN sel(0) = '1' ELSE
181 181 time_in(1,I) WHEN sel(1) = '1' ELSE
182 182 time_in(2,I) WHEN sel(2) = '1' ELSE
183 183 time_in(3,I);
184 184 END GENERATE all_time_bit;
185 185
186 186
187 187 -----------------------------------------------------------------------------
188 188 -- RR and SELECTION
189 189 -----------------------------------------------------------------------------
190 190 all_input_rr : FOR I IN 3 DOWNTO 0 GENERATE
191 191 valid_in_rr(I) <= data_in_valid(I) AND NOT full_almost(I);
192 192 END GENERATE all_input_rr;
193 193
194 194 RR_Arbiter_4_1 : RR_Arbiter_4
195 195 PORT MAP (
196 196 clk => clk,
197 197 rstn => rstn,
198 198 in_valid => valid_in_rr,
199 199 out_grant => sel_s);
200 200
201 201 PROCESS (clk, rstn)
202 202 BEGIN -- PROCESS
203 203 IF rstn = '0' THEN -- asynchronous reset (active low)
204 204 sel <= "0000";
205 205 sel_reg <= '0';
206 206 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
207 207 IF run = '0' THEN
208 208 sel <= "0000";
209 209 sel_reg <= '0';
210 210 ELSE
211 211 IF sel_reg = '0' OR sel_ack = '1' THEN
212 212 sel <= sel_s;
213 213 IF sel_s = "0000" THEN
214 214 sel_reg <= '0';
215 215 ELSE
216 216 sel_reg <= '1';
217 217 END IF;
218 218 END IF;
219 219 END IF;
220 220 END IF;
221 221 END PROCESS;
222 222
223 223 no_sel <= '1' WHEN sel = "0000" ELSE '0';
224 224
225 225 -----------------------------------------------------------------------------
226 226 -- REG
227 227 -----------------------------------------------------------------------------
228 228 reg_count_i: lpp_waveform_fifo_arbiter_reg
229 229 GENERIC MAP (
230 230 data_size => nb_data_by_buffer_size,
231 231 data_nb => 4)
232 232 PORT MAP (
233 233 clk => clk,
234 234 rstn => rstn,
235 235 run => run,
236 236 max_count => nb_data_by_buffer,
237 237 enable => count_enable,
238 238 sel => sel,
239 239 data => count,
240 240 data_s => count_s);
241 241
242 242
243 243
244 244
245 245 END ARCHITECTURE;
246 246
247 247
248 248
249 249
250 250
251 251
252 252
253 253
254 254
255 255
256 256
257 257
258 258
259 259
260 260
261 261
262 262
263 263
264 264
265 265
266 266
267 267
268 268
269 269
270
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@@ -1,116 +1,115
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 ------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe PELLION
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 ------------------------------------------------------------------------------
22 22 LIBRARY IEEE;
23 23 USE IEEE.std_logic_1164.ALL;
24 24 USE IEEE.numeric_std.ALL;
25 25
26 26 LIBRARY lpp;
27 27 USE lpp.lpp_waveform_pkg.ALL;
28 28 USE lpp.general_purpose.ALL;
29 29
30 30 ENTITY lpp_waveform_fifo_arbiter_reg IS
31 31 GENERIC(
32 32 data_size : INTEGER;
33 33 data_nb : INTEGER);
34 34 PORT(
35 35 clk : IN STD_LOGIC;
36 36 rstn : IN STD_LOGIC;
37 37 ---------------------------------------------------------------------------
38 38 run : IN STD_LOGIC;
39 39
40 40 max_count : IN STD_LOGIC_VECTOR(data_size -1 DOWNTO 0);
41 41
42 42 enable : IN STD_LOGIC;
43 43 sel : IN STD_LOGIC_VECTOR(data_nb-1 DOWNTO 0);
44 44
45 45 data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
46 46 data_s : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0)
47 47 );
48 48 END ENTITY;
49 49
50 50
51 51 ARCHITECTURE ar_lpp_waveform_fifo_arbiter_reg OF lpp_waveform_fifo_arbiter_reg IS
52 52
53 53 TYPE Counter_Vector IS ARRAY (NATURAL RANGE <>) OF INTEGER;
54 54 SIGNAL reg : Counter_Vector(data_nb-1 DOWNTO 0);
55 55
56 56 SIGNAL reg_sel : INTEGER := 0;
57 57 SIGNAL reg_sel_s : INTEGER := 0;
58 58
59 59 BEGIN
60 60
61 61 all_reg : FOR I IN data_nb-1 DOWNTO 0 GENERATE
62 62 PROCESS (clk, rstn)
63 63 BEGIN -- PROCESS
64 64 IF rstn = '0' THEN -- asynchronous reset (active low)
65 65 reg(I) <= 0;
66 66 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
67 67 IF run = '0' THEN
68 68 reg(I) <= 0;
69 69 ELSE
70 70 IF sel(I) = '1' THEN
71 71 reg(I) <= reg_sel_s;
72 72 END IF;
73 73 END IF;
74 74 END IF;
75 75 END PROCESS;
76 76 END GENERATE all_reg;
77 77
78 78 reg_sel <= reg(0) WHEN sel(0) = '1' ELSE
79 79 reg(1) WHEN sel(1) = '1' ELSE
80 80 reg(2) WHEN sel(2) = '1' ELSE
81 81 reg(3);
82 82
83 reg_sel_s <= reg_sel WHEN enable = '0' ELSE
83 reg_sel_s <= reg_sel WHEN enable = '0' ELSE
84 84 reg_sel + 1 WHEN reg_sel < UNSIGNED(max_count) ELSE
85 85 0;
86 86
87 87 data <= STD_LOGIC_VECTOR(to_unsigned(reg_sel , data_size));
88 88 data_s <= STD_LOGIC_VECTOR(to_unsigned(reg_sel_s, data_size));
89 89
90 90 END ARCHITECTURE;
91 91
92 92
93 93
94 94
95 95
96 96
97 97
98 98
99 99
100 100
101 101
102 102
103 103
104 104
105 105
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108 108
109 109
110 110
111 111
112 112
113 113
114 114
115 115
116
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@@ -1,370 +1,370
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -- jean-christophe.pellion@easii-ic.com
22 22 -------------------------------------------------------------------------------
23 23 LIBRARY IEEE;
24 24 USE IEEE.STD_LOGIC_1164.ALL;
25 25
26 26 LIBRARY grlib;
27 27 USE grlib.amba.ALL;
28 28 USE grlib.stdlib.ALL;
29 29 USE grlib.devices.ALL;
30 30 USE GRLIB.DMA2AHB_Package.ALL;
31 31
32 32 LIBRARY techmap;
33 33 USE techmap.gencomp.ALL;
34 34
35 35 PACKAGE lpp_waveform_pkg IS
36 36
37 37 TYPE LPP_TYPE_ADDR_FIFO_WAVEFORM IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(6 DOWNTO 0);
38 38
39 39 TYPE Data_Vector IS ARRAY (NATURAL RANGE <>, NATURAL RANGE <>) OF STD_LOGIC;
40 40
41 41 -----------------------------------------------------------------------------
42 42 -- SNAPSHOT
43 43 -----------------------------------------------------------------------------
44 44
45 45 COMPONENT lpp_waveform_snapshot
46 46 GENERIC (
47 47 data_size : INTEGER;
48 48 nb_snapshot_param_size : INTEGER);
49 49 PORT (
50 50 clk : IN STD_LOGIC;
51 51 rstn : IN STD_LOGIC;
52 52 run : IN STD_LOGIC;
53 53 enable : IN STD_LOGIC;
54 54 burst_enable : IN STD_LOGIC;
55 55 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
56 56 start_snapshot : IN STD_LOGIC;
57 57 data_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
58 58 data_in_valid : IN STD_LOGIC;
59 59 data_out : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
60 60 data_out_valid : OUT STD_LOGIC);
61 61 END COMPONENT;
62 62
63 63 COMPONENT lpp_waveform_burst
64 64 GENERIC (
65 65 data_size : INTEGER);
66 66 PORT (
67 67 clk : IN STD_LOGIC;
68 68 rstn : IN STD_LOGIC;
69 69 run : IN STD_LOGIC;
70 70 enable : IN STD_LOGIC;
71 71 data_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
72 72 data_in_valid : IN STD_LOGIC;
73 73 data_out : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
74 74 data_out_valid : OUT STD_LOGIC);
75 75 END COMPONENT;
76 76
77 77 COMPONENT lpp_waveform_snapshot_controler
78 78 GENERIC (
79 79 delta_vector_size : INTEGER;
80 80 delta_vector_size_f0_2 : INTEGER);
81 81 PORT (
82 82 clk : IN STD_LOGIC;
83 83 rstn : IN STD_LOGIC;
84 84 reg_run : IN STD_LOGIC;
85 85 reg_start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
86 86 reg_delta_snapshot : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
87 87 reg_delta_f0 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
88 88 reg_delta_f0_2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
89 89 reg_delta_f1 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
90 90 reg_delta_f2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
91 91 coarse_time : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
92 92 data_f0_valid : IN STD_LOGIC;
93 93 data_f2_valid : IN STD_LOGIC;
94 94 start_snapshot_f0 : OUT STD_LOGIC;
95 95 start_snapshot_f1 : OUT STD_LOGIC;
96 96 start_snapshot_f2 : OUT STD_LOGIC;
97 97 wfp_on : OUT STD_LOGIC);
98 98 END COMPONENT;
99 99
100 100 -----------------------------------------------------------------------------
101 101 --
102 102 -----------------------------------------------------------------------------
103 103 COMPONENT lpp_waveform
104 104 GENERIC (
105 105 tech : INTEGER;
106 106 data_size : INTEGER;
107 107 nb_data_by_buffer_size : INTEGER;
108 108 nb_snapshot_param_size : INTEGER;
109 109 delta_vector_size : INTEGER;
110 110 delta_vector_size_f0_2 : INTEGER);
111 111 PORT (
112 112 clk : IN STD_LOGIC;
113 113 rstn : IN STD_LOGIC;
114 114 reg_run : IN STD_LOGIC;
115 115 reg_start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
116 116 reg_delta_snapshot : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
117 117 reg_delta_f0 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
118 118 reg_delta_f0_2 : IN STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
119 119 reg_delta_f1 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
120 120 reg_delta_f2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
121 121 enable_f0 : IN STD_LOGIC;
122 122 enable_f1 : IN STD_LOGIC;
123 123 enable_f2 : IN STD_LOGIC;
124 124 enable_f3 : IN STD_LOGIC;
125 125 burst_f0 : IN STD_LOGIC;
126 126 burst_f1 : IN STD_LOGIC;
127 127 burst_f2 : IN STD_LOGIC;
128 128 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
129 129 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
130 130 status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
131 131 status_buffer_ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
132 addr_buffer : IN STD_LOGIC_VECTOR(32*4 DOWNTO 0);
132 addr_buffer : IN STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
133 133 length_buffer : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
134 134 ready_buffer : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
135 135 buffer_time : OUT STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
136 136 error_buffer_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
137 137 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
138 138 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
139 139 data_f0_in_valid : IN STD_LOGIC;
140 140 data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
141 141 data_f1_in_valid : IN STD_LOGIC;
142 142 data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
143 143 data_f2_in_valid : IN STD_LOGIC;
144 144 data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
145 145 data_f3_in_valid : IN STD_LOGIC;
146 146 data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
147 147
148 148 dma_fifo_valid_burst : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
149 149 dma_fifo_data : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
150 150 dma_fifo_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
151 151 dma_buffer_new : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
152 152 dma_buffer_addr : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
153 153 dma_buffer_length : OUT STD_LOGIC_VECTOR(26*4-1 DOWNTO 0);
154 154 dma_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
155 155 dma_buffer_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0)
156 156 );
157 157 END COMPONENT;
158 158
159 159 COMPONENT lpp_waveform_dma_genvalid
160 160 PORT (
161 161 HCLK : IN STD_LOGIC;
162 162 HRESETn : IN STD_LOGIC;
163 163 run : IN STD_LOGIC;
164 164 valid_in : IN STD_LOGIC;
165 165 ack_in : IN STD_LOGIC;
166 166 time_in : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
167 167 valid_out : OUT STD_LOGIC;
168 168 time_out : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
169 169 error : OUT STD_LOGIC);
170 170 END COMPONENT;
171 171
172 172 -----------------------------------------------------------------------------
173 173 -- FIFO
174 174 -----------------------------------------------------------------------------
175 175 COMPONENT lpp_waveform_fifo_ctrl
176 176 GENERIC (
177 177 offset : INTEGER;
178 178 length : INTEGER);
179 179 PORT (
180 180 clk : IN STD_LOGIC;
181 181 rstn : IN STD_LOGIC;
182 182 run : IN STD_LOGIC;
183 183 ren : IN STD_LOGIC;
184 184 wen : IN STD_LOGIC;
185 185 mem_re : OUT STD_LOGIC;
186 186 mem_we : OUT STD_LOGIC;
187 187 mem_addr_ren : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
188 188 mem_addr_wen : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
189 189 empty_almost : OUT STD_LOGIC;
190 190 empty : OUT STD_LOGIC;
191 191 full_almost : OUT STD_LOGIC;
192 192 full : OUT STD_LOGIC);
193 193 END COMPONENT;
194 194
195 195 COMPONENT lpp_waveform_fifo_arbiter
196 196 GENERIC (
197 197 tech : INTEGER;
198 198 nb_data_by_buffer_size : INTEGER);
199 199 PORT (
200 200 clk : IN STD_LOGIC;
201 201 rstn : IN STD_LOGIC;
202 202 run : IN STD_LOGIC;
203 203 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size - 1 DOWNTO 0);
204 204 data_in_valid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
205 205 data_in_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
206 206 data_in : IN Data_Vector(3 DOWNTO 0, 95 DOWNTO 0);
207 207 time_in : IN Data_Vector(3 DOWNTO 0, 47 DOWNTO 0);
208 208 data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
209 209 data_out_wen : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
210 210 full_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
211 211 full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
212 212 time_out : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
213 213 time_out_new : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
214 214 );
215 215 END COMPONENT;
216 216
217 217 COMPONENT lpp_waveform_fifo
218 218 GENERIC (
219 219 tech : INTEGER);
220 220 PORT (
221 221 clk : IN STD_LOGIC;
222 222 rstn : IN STD_LOGIC;
223 223 run : IN STD_LOGIC;
224 224 empty_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
225 225 empty : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
226 226 data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
227 227 rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
228 228 full_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
229 229 full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
230 230 data_wen : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
231 231 wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
232 232 END COMPONENT;
233 233
234 234 COMPONENT lpp_waveform_fifo_headreg
235 235 GENERIC (
236 236 tech : INTEGER);
237 237 PORT (
238 238 clk : IN STD_LOGIC;
239 239 rstn : IN STD_LOGIC;
240 240 run : IN STD_LOGIC;
241 241 o_empty_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
242 242 o_empty : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
243 243 o_data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
244 244 o_rdata_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
245 245 o_rdata_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
246 246 o_rdata_2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
247 247 o_rdata_3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
248 248 i_empty_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
249 249 i_empty : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
250 250 i_data_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
251 251 i_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
252 252 END COMPONENT;
253 253
254 254 COMPONENT lpp_waveform_fifo_latencyCorrection
255 255 GENERIC (
256 256 tech : INTEGER);
257 257 PORT (
258 258 clk : IN STD_LOGIC;
259 259 rstn : IN STD_LOGIC;
260 260 run : IN STD_LOGIC;
261 261 empty_almost : OUT STD_LOGIC;
262 262 empty : OUT STD_LOGIC;
263 263 data_ren : IN STD_LOGIC;
264 264 rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
265 265 empty_almost_fifo : IN STD_LOGIC;
266 266 empty_fifo : IN STD_LOGIC;
267 267 data_ren_fifo : OUT STD_LOGIC;
268 268 rdata_fifo : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
269 269 END COMPONENT;
270 270
271 271 COMPONENT lpp_waveform_fifo_withoutLatency
272 272 GENERIC (
273 273 tech : INTEGER);
274 274 PORT (
275 275 clk : IN STD_LOGIC;
276 276 rstn : IN STD_LOGIC;
277 277 run : IN STD_LOGIC;
278 278 empty_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
279 279 empty : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
280 280 data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
281 281 rdata_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
282 282 rdata_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
283 283 rdata_2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
284 284 rdata_3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
285 285 full_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
286 286 full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
287 287 data_wen : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
288 288 wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
289 289 END COMPONENT;
290 290
291 291 -----------------------------------------------------------------------------
292 292 -- GEN ADDRESS
293 293 -----------------------------------------------------------------------------
294 294 COMPONENT lpp_waveform_genaddress
295 295 GENERIC (
296 296 nb_data_by_buffer_size : INTEGER);
297 297 PORT (
298 298 clk : IN STD_LOGIC;
299 299 rstn : IN STD_LOGIC;
300 300 run : IN STD_LOGIC;
301 301 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
302 302 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
303 303 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
304 304 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
305 305 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
306 306 empty : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
307 307 empty_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
308 308 data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
309 309 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
310 310 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
311 311 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
312 312 data_f0_data_out_valid_burst : OUT STD_LOGIC;
313 313 data_f1_data_out_valid_burst : OUT STD_LOGIC;
314 314 data_f2_data_out_valid_burst : OUT STD_LOGIC;
315 315 data_f3_data_out_valid_burst : OUT STD_LOGIC;
316 316 data_f0_data_out_valid : OUT STD_LOGIC;
317 317 data_f1_data_out_valid : OUT STD_LOGIC;
318 318 data_f2_data_out_valid : OUT STD_LOGIC;
319 319 data_f3_data_out_valid : OUT STD_LOGIC;
320 320 data_f0_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
321 321 data_f1_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
322 322 data_f2_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
323 323 data_f3_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
324 324 END COMPONENT;
325 325
326 326 -----------------------------------------------------------------------------
327 327 -- lpp_waveform_fifo_arbiter_reg
328 328 -----------------------------------------------------------------------------
329 329 COMPONENT lpp_waveform_fifo_arbiter_reg
330 330 GENERIC (
331 331 data_size : INTEGER;
332 332 data_nb : INTEGER);
333 333 PORT (
334 334 clk : IN STD_LOGIC;
335 335 rstn : IN STD_LOGIC;
336 336 run : IN STD_LOGIC;
337 337 max_count : IN STD_LOGIC_VECTOR(data_size -1 DOWNTO 0);
338 338 enable : IN STD_LOGIC;
339 339 sel : IN STD_LOGIC_VECTOR(data_nb-1 DOWNTO 0);
340 340 data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
341 341 data_s : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0));
342 342 END COMPONENT;
343 343
344 344 COMPONENT lpp_waveform_fsmdma
345 345 PORT (
346 346 clk : IN STD_ULOGIC;
347 347 rstn : IN STD_ULOGIC;
348 348 run : IN STD_LOGIC;
349 349 fifo_buffer_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
350 350 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
351 351 fifo_empty : IN STD_LOGIC;
352 352 fifo_empty_threshold : IN STD_LOGIC;
353 353 fifo_ren : OUT STD_LOGIC;
354 354 dma_fifo_valid_burst : OUT STD_LOGIC;
355 355 dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
356 356 dma_fifo_ren : IN STD_LOGIC;
357 357 dma_buffer_new : OUT STD_LOGIC;
358 358 dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
359 359 dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
360 360 dma_buffer_full : IN STD_LOGIC;
361 361 dma_buffer_full_err : IN STD_LOGIC;
362 362 status_buffer_ready : IN STD_LOGIC;
363 363 addr_buffer : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
364 364 length_buffer : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
365 365 ready_buffer : OUT STD_LOGIC;
366 366 buffer_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
367 367 error_buffer_full : OUT STD_LOGIC);
368 368 END COMPONENT;
369 369
370 370 END lpp_waveform_pkg;
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