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WaveForm Picker : Big Endian Correction
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r206:82098655f36b em-2013-07-24-vhdlib206 JC
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1 1 LIBRARY IEEE;
2 2 USE IEEE.STD_LOGIC_1164.ALL;
3 3 USE ieee.numeric_std.ALL;
4 4
5 5 LIBRARY grlib;
6 6 USE grlib.amba.ALL;
7 7 USE grlib.stdlib.ALL;
8 8 USE grlib.devices.ALL;
9 9 USE GRLIB.DMA2AHB_Package.ALL;
10 10
11 11 LIBRARY lpp;
12 12 USE lpp.lpp_waveform_pkg.ALL;
13 13
14 14 LIBRARY techmap;
15 15 USE techmap.gencomp.ALL;
16 16
17 17 ENTITY lpp_waveform IS
18 18
19 19 GENERIC (
20 20 hindex : INTEGER := 2;
21 21 tech : INTEGER := inferred;
22 22 data_size : INTEGER := 160;
23 23 nb_burst_available_size : INTEGER := 11;
24 24 nb_snapshot_param_size : INTEGER := 11;
25 25 delta_snapshot_size : INTEGER := 16;
26 26 delta_f2_f0_size : INTEGER := 10;
27 27 delta_f2_f1_size : INTEGER := 10);
28 28
29 29 PORT (
30 30 clk : IN STD_LOGIC;
31 31 rstn : IN STD_LOGIC;
32 32
33 33 -- AMBA AHB Master Interface
34 34 AHB_Master_In : IN AHB_Mst_In_Type;
35 35 AHB_Master_Out : OUT AHB_Mst_Out_Type;
36 36
37 37 coarse_time_0 : IN STD_LOGIC;
38 38
39 39 --config
40 40 delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
41 41 delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
42 42 delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
43 43
44 44 enable_f0 : IN STD_LOGIC;
45 45 enable_f1 : IN STD_LOGIC;
46 46 enable_f2 : IN STD_LOGIC;
47 47 enable_f3 : IN STD_LOGIC;
48 48
49 49 burst_f0 : IN STD_LOGIC;
50 50 burst_f1 : IN STD_LOGIC;
51 51 burst_f2 : IN STD_LOGIC;
52 52
53 53 nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
54 54 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
55 55 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
56 56 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
57 57 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
58 58 status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma
59 59 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
60 60 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
61 61 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
62 62 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
63 63
64 64 data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
65 65 data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
66 66 data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
67 67 data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
68 68
69 69 data_f0_in_valid : IN STD_LOGIC;
70 70 data_f1_in_valid : IN STD_LOGIC;
71 71 data_f2_in_valid : IN STD_LOGIC;
72 72 data_f3_in_valid : IN STD_LOGIC
73 73 );
74 74
75 75 END lpp_waveform;
76 76
77 77 ARCHITECTURE beh OF lpp_waveform IS
78 78 SIGNAL start_snapshot_f0 : STD_LOGIC;
79 79 SIGNAL start_snapshot_f1 : STD_LOGIC;
80 80 SIGNAL start_snapshot_f2 : STD_LOGIC;
81 81
82 82 SIGNAL data_f0_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
83 83 SIGNAL data_f1_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
84 84 SIGNAL data_f2_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
85 85 SIGNAL data_f3_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
86 86
87 87 SIGNAL data_f0_out_valid : STD_LOGIC;
88 88 SIGNAL data_f1_out_valid : STD_LOGIC;
89 89 SIGNAL data_f2_out_valid : STD_LOGIC;
90 90 SIGNAL data_f3_out_valid : STD_LOGIC;
91 91 SIGNAL nb_snapshot_param_more_one : STD_LOGIC_VECTOR(nb_snapshot_param_size DOWNTO 0);
92 92
93 93 --
94 94 SIGNAL valid_in : STD_LOGIC_VECTOR(3 DOWNTO 0);
95 95 SIGNAL valid_out : STD_LOGIC_VECTOR(3 DOWNTO 0);
96 96 SIGNAL valid_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
97 97 SIGNAL ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
98 98 SIGNAL ready_arb : STD_LOGIC_VECTOR(3 DOWNTO 0);
99 99 SIGNAL data_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
100 100 SIGNAL time_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
101 101 SIGNAL wdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
102 102 --
103 103 SIGNAL data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
104 104 SIGNAL time_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
105 105 SIGNAL rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
106 106
107 107 BEGIN -- beh
108 108
109 109 lpp_waveform_snapshot_controler_1: lpp_waveform_snapshot_controler
110 110 GENERIC MAP (
111 111 delta_snapshot_size => delta_snapshot_size,
112 112 delta_f2_f0_size => delta_f2_f0_size,
113 113 delta_f2_f1_size => delta_f2_f1_size)
114 114 PORT MAP (
115 115 clk => clk,
116 116 rstn => rstn,
117 117 delta_snapshot => delta_snapshot,
118 118 delta_f2_f1 => delta_f2_f1,
119 119 delta_f2_f0 => delta_f2_f0,
120 120 coarse_time_0 => coarse_time_0,
121 121 data_f0_in_valid => data_f0_in_valid,
122 122 data_f2_in_valid => data_f2_in_valid,
123 123 start_snapshot_f0 => start_snapshot_f0,
124 124 start_snapshot_f1 => start_snapshot_f1,
125 125 start_snapshot_f2 => start_snapshot_f2);
126 126
127 127 lpp_waveform_snapshot_f0 : lpp_waveform_snapshot
128 128 GENERIC MAP (
129 129 data_size => data_size,
130 130 nb_snapshot_param_size => nb_snapshot_param_size)
131 131 PORT MAP (
132 132 clk => clk,
133 133 rstn => rstn,
134 134 enable => enable_f0,
135 135 burst_enable => burst_f0,
136 136 nb_snapshot_param => nb_snapshot_param,
137 137 start_snapshot => start_snapshot_f0,
138 138 data_in => data_f0_in,
139 139 data_in_valid => data_f0_in_valid,
140 140 data_out => data_f0_out,
141 141 data_out_valid => data_f0_out_valid);
142 142
143 143 nb_snapshot_param_more_one <= ('0' & nb_snapshot_param) + 1;
144 144
145 145 lpp_waveform_snapshot_f1 : lpp_waveform_snapshot
146 146 GENERIC MAP (
147 147 data_size => data_size,
148 148 nb_snapshot_param_size => nb_snapshot_param_size+1)
149 149 PORT MAP (
150 150 clk => clk,
151 151 rstn => rstn,
152 152 enable => enable_f1,
153 153 burst_enable => burst_f1,
154 154 nb_snapshot_param => nb_snapshot_param_more_one,
155 155 start_snapshot => start_snapshot_f1,
156 156 data_in => data_f1_in,
157 157 data_in_valid => data_f1_in_valid,
158 158 data_out => data_f1_out,
159 159 data_out_valid => data_f1_out_valid);
160 160
161 161 lpp_waveform_snapshot_f2 : lpp_waveform_snapshot
162 162 GENERIC MAP (
163 163 data_size => data_size,
164 164 nb_snapshot_param_size => nb_snapshot_param_size+1)
165 165 PORT MAP (
166 166 clk => clk,
167 167 rstn => rstn,
168 168 enable => enable_f2,
169 169 burst_enable => burst_f2,
170 170 nb_snapshot_param => nb_snapshot_param_more_one,
171 171 start_snapshot => start_snapshot_f2,
172 172 data_in => data_f2_in,
173 173 data_in_valid => data_f2_in_valid,
174 174 data_out => data_f2_out,
175 175 data_out_valid => data_f2_out_valid);
176 176
177 177 lpp_waveform_burst_f3: lpp_waveform_burst
178 178 GENERIC MAP (
179 179 data_size => data_size)
180 180 PORT MAP (
181 181 clk => clk,
182 182 rstn => rstn,
183 183 enable => enable_f3,
184 184 data_in => data_f3_in,
185 185 data_in_valid => data_f3_in_valid,
186 186 data_out => data_f3_out,
187 187 data_out_valid => data_f3_out_valid);
188 188
189 189
190 190 valid_in <= data_f3_out_valid & data_f2_out_valid & data_f1_out_valid & data_f0_out_valid;
191 191
192 192 all_input_valid: FOR i IN 3 DOWNTO 0 GENERATE
193 193 lpp_waveform_dma_gen_valid_I: lpp_waveform_dma_gen_valid
194 194 PORT MAP (
195 195 HCLK => clk,
196 196 HRESETn => rstn,
197 197 valid_in => valid_in(I),
198 198 ack_in => valid_ack(I),
199 199 valid_out => valid_out(I),
200 200 error => status_new_err(I));
201 201 END GENERATE all_input_valid;
202 202
203 203 lpp_waveform_fifo_arbiter_1: lpp_waveform_fifo_arbiter
204 204 GENERIC MAP (tech => tech)
205 205 PORT MAP (
206 206 clk => clk,
207 207 rstn => rstn,
208 208 data_f0_valid => valid_out(0),
209 209 data_f1_valid => valid_out(1),
210 210 data_f2_valid => valid_out(2),
211 211 data_f3_valid => valid_out(3),
212 212
213 213 data_valid_ack => valid_ack,
214 214
215 215 data_f0 => data_f0_out,
216 216 data_f1 => data_f1_out,
217 217 data_f2 => data_f2_out,
218 218 data_f3 => data_f3_out,
219 219
220 220 ready => ready_arb,
221 221 time_wen => time_wen,
222 222 data_wen => data_wen,
223 223 data => wdata);
224 224
225 225 ready_arb <= NOT ready;
226 226
227 227 lpp_waveform_fifo_1: lpp_waveform_fifo
228 228 GENERIC MAP (tech => tech)
229 229 PORT MAP (
230 230 clk => clk,
231 231 rstn => rstn,
232 232 ready => ready,
233 233 time_ren => time_ren, -- todo
234 234 data_ren => data_ren, -- todo
235 235 rdata => rdata, -- todo
236 236
237 237 time_wen => time_wen,
238 238 data_wen => data_wen,
239 239 wdata => wdata);
240 240
241 --time_ren <= (OTHERS => '1');
242 --data_ren <= (OTHERS => '1');
243
244 241 pp_waveform_dma_1: lpp_waveform_dma
245 242 GENERIC MAP (
246 243 data_size => data_size,
247 244 tech => tech,
248 245 hindex => hindex,
249 246 nb_burst_available_size => nb_burst_available_size)
250 247 PORT MAP (
251 248 HCLK => clk,
252 249 HRESETn => rstn,
253 250 AHB_Master_In => AHB_Master_In,
254 251 AHB_Master_Out => AHB_Master_Out,
255 252 data_ready => ready,
256 253 data => rdata,
257 254 data_data_ren => data_ren,
258 255 data_time_ren => time_ren,
259 --data_f0_in => data_f0_out,
260 --data_f1_in => data_f1_out,
261 --data_f2_in => data_f2_out,
262 --data_f3_in => data_f3_out,
263 --data_f0_in_valid => data_f0_out_valid,
264 --data_f1_in_valid => data_f1_out_valid,
265 --data_f2_in_valid => data_f2_out_valid,
266 --data_f3_in_valid => data_f3_out_valid,
267 256 nb_burst_available => nb_burst_available,
268 257 status_full => status_full,
269 258 status_full_ack => status_full_ack,
270 259 status_full_err => status_full_err,
271 260 addr_data_f0 => addr_data_f0,
272 261 addr_data_f1 => addr_data_f1,
273 262 addr_data_f2 => addr_data_f2,
274 263 addr_data_f3 => addr_data_f3);
275 264
276 265 END beh;
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@@ -1,386 +1,326
1 1
2 2 ------------------------------------------------------------------------------
3 3 -- This file is a part of the LPP VHDL IP LIBRARY
4 4 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
5 5 --
6 6 -- This program is free software; you can redistribute it and/or modify
7 7 -- it under the terms of the GNU General Public License as published by
8 8 -- the Free Software Foundation; either version 3 of the License, or
9 9 -- (at your option) any later version.
10 10 --
11 11 -- This program is distributed in the hope that it will be useful,
12 12 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
13 13 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 14 -- GNU General Public License for more details.
15 15 --
16 16 -- You should have received a copy of the GNU General Public License
17 17 -- along with this program; if not, write to the Free Software
18 18 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 19 -------------------------------------------------------------------------------
20 20 -- Author : Jean-christophe Pellion
21 21 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
22 22 -- jean-christophe.pellion@easii-ic.com
23 23 -------------------------------------------------------------------------------
24 24 -- 1.0 - initial version
25 25 -- 1.1 - (01/11/2013) FIX boundary error (1kB address should not be crossed by BURSTS)
26 26 -------------------------------------------------------------------------------
27 27 LIBRARY ieee;
28 28 USE ieee.std_logic_1164.ALL;
29 29 USE ieee.numeric_std.ALL;
30 30 LIBRARY grlib;
31 31 USE grlib.amba.ALL;
32 32 USE grlib.stdlib.ALL;
33 33 USE grlib.devices.ALL;
34 34 USE GRLIB.DMA2AHB_Package.ALL;
35 35 LIBRARY lpp;
36 36 USE lpp.lpp_amba.ALL;
37 37 USE lpp.apb_devices_list.ALL;
38 38 USE lpp.lpp_memory.ALL;
39 39 USE lpp.lpp_dma_pkg.ALL;
40 40 USE lpp.lpp_waveform_pkg.ALL;
41 41 LIBRARY techmap;
42 42 USE techmap.gencomp.ALL;
43 43
44 44
45 45 ENTITY lpp_waveform_dma IS
46 46 GENERIC (
47 47 data_size : INTEGER := 160;
48 48 tech : INTEGER := inferred;
49 49 hindex : INTEGER := 2;
50 50 nb_burst_available_size : INTEGER := 11
51 51 );
52 52 PORT (
53 53 -- AMBA AHB system signals
54 54 HCLK : IN STD_ULOGIC;
55 55 HRESETn : IN STD_ULOGIC;
56 56 -- AMBA AHB Master Interface
57 57 AHB_Master_In : IN AHB_Mst_In_Type;
58 58 AHB_Master_Out : OUT AHB_Mst_Out_Type;
59 59 --
60 60 data_ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -- todo
61 61 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
62 62 data_data_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- todo
63 63 data_time_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- todo
64 64 -- Reg
65 65 nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
66 66 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
67 67 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
68 68 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
69 69 -- status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma
70 70 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
71 71 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
72 72 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
73 73 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
74 74 );
75 75 END;
76 76
77 77 ARCHITECTURE Behavioral OF lpp_waveform_dma IS
78 78 -----------------------------------------------------------------------------
79 79 SIGNAL DMAIn : DMA_In_Type;
80 80 SIGNAL DMAOut : DMA_OUt_Type;
81 81 -----------------------------------------------------------------------------
82 82 TYPE state_DMAWriteBurst IS (IDLE,
83 83 SEND_TIME_0, WAIT_TIME_0,
84 84 SEND_TIME_1, WAIT_TIME_1,
85 85 SEND_5_TIME,
86 86 SEND_DATA, WAIT_DATA);
87 87 SIGNAL state : state_DMAWriteBurst ;
88 88 -----------------------------------------------------------------------------
89 89 -- CONTROL
90 90 SIGNAL sel_data_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
91 91 SIGNAL sel_data : STD_LOGIC_VECTOR(1 DOWNTO 0);
92 92 SIGNAL update : STD_LOGIC_VECTOR(1 DOWNTO 0);
93 93 SIGNAL time_select : STD_LOGIC;
94 94 SIGNAL time_write : STD_LOGIC;
95 95 SIGNAL time_already_send : STD_LOGIC_VECTOR(3 DOWNTO 0);
96 96 SIGNAL time_already_send_s : STD_LOGIC;
97 97 -----------------------------------------------------------------------------
98 98 -- SEND TIME MODULE
99 99 SIGNAL time_dmai : DMA_In_Type;
100 100 SIGNAL time_send : STD_LOGIC;
101 101 SIGNAL time_send_ok : STD_LOGIC;
102 102 SIGNAL time_send_ko : STD_LOGIC;
103 103 SIGNAL time_fifo_ren : STD_LOGIC;
104 104 SIGNAL time_ren : STD_LOGIC;
105 105 -----------------------------------------------------------------------------
106 106 -- SEND DATA MODULE
107 107 SIGNAL data_dmai : DMA_In_Type;
108 108 SIGNAL data_send : STD_LOGIC;
109 109 SIGNAL data_send_ok : STD_LOGIC;
110 110 SIGNAL data_send_ko : STD_LOGIC;
111 111 SIGNAL data_fifo_ren : STD_LOGIC;
112 112 SIGNAL data_ren : STD_LOGIC;
113 113 -----------------------------------------------------------------------------
114 114 -- SELECT ADDRESS
115 115 SIGNAL data_address : STD_LOGIC_VECTOR(31 DOWNTO 0);
116 116 SIGNAL update_and_sel : STD_LOGIC_VECTOR(7 DOWNTO 0);
117 117 SIGNAL addr_data_reg_vector : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
118 118 SIGNAL addr_data_vector : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
119 119 -----------------------------------------------------------------------------
120 120 SIGNAL send_16_3_time_reg : STD_LOGIC_VECTOR(3*4-1 DOWNTO 0);
121 121 SIGNAL send_16_3_time_reg_s : STD_LOGIC_VECTOR(3*4-1 DOWNTO 0);
122 122 -----------------------------------------------------------------------------
123 123 SIGNAL send_16_3_time : STD_LOGIC;
124 124 SIGNAL count_send_time : INTEGER;
125 -----------------------------------------------------------------------------
126 SIGNAL data_2_halfword : STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
125 127 BEGIN
126 128
127 129 -----------------------------------------------------------------------------
128 130 -- DMA to AHB interface
129 131 DMA2AHB_1 : DMA2AHB
130 132 GENERIC MAP (
131 133 hindex => hindex,
132 134 vendorid => VENDOR_LPP,
133 135 deviceid => 10,
134 136 version => 0,
135 137 syncrst => 1,
136 138 boundary => 1) -- FIX 11/01/2013
137 139 PORT MAP (
138 140 HCLK => HCLK,
139 141 HRESETn => HRESETn,
140 142 DMAIn => DMAIn,
141 143 DMAOut => DMAOut,
142 144 AHBIn => AHB_Master_In,
143 145 AHBOut => AHB_Master_Out);
144 146 -----------------------------------------------------------------------------
145 147
146 148 -----------------------------------------------------------------------------
147 149 -- This module memorises when the Times info are write. When FSM send
148 150 -- the Times info, the "reg" is set and when a full_ack is received the "reg" is reset.
149 151 all_time_write : FOR I IN 3 DOWNTO 0 GENERATE
150 152 PROCESS (HCLK, HRESETn)
151 153 BEGIN -- PROCESS
152 154 IF HRESETn = '0' THEN -- asynchronous reset (active low)
153 155 time_already_send(I) <= '0';
154 156 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
155 157 IF time_write = '1' AND UNSIGNED(sel_data) = I THEN
156 158 time_already_send(I) <= '1';
157 159 ELSIF status_full_ack(I) = '1' THEN
158 160 time_already_send(I) <= '0';
159 161 END IF;
160 162 END IF;
161 163 END PROCESS;
162 164 END GENERATE all_time_write;
163 165
164 166
165 167
166 168 -----------------------------------------------------------------------------
167 169 sel_data_s <= "00" WHEN data_ready(0) = '1' ELSE
168 170 "01" WHEN data_ready(1) = '1' ELSE
169 171 "10" WHEN data_ready(2) = '1' ELSE
170 172 "11";
171 173
172 174 time_already_send_s <= time_already_send(0) WHEN data_ready(0) = '1' ELSE
173 175 time_already_send(1) WHEN data_ready(1) = '1' ELSE
174 176 time_already_send(2) WHEN data_ready(2) = '1' ELSE
175 177 time_already_send(3);
176 178
177
178 --send_16_3_time <= send_16_3_time_reg(0) WHEN data_ready(0) = '1' ELSE
179 -- send_16_3_time_reg(3) WHEN data_ready(1) = '1' ELSE
180 -- send_16_3_time_reg(6) WHEN data_ready(2) = '1' ELSE
181 -- send_16_3_time_reg(9) ;
182
183 --all_send_16_3: FOR I IN 3 DOWNTO 0 GENERATE
184 -- send_16_3_time_reg_s(3*(I+1)-1 DOWNTO 3*I) <=
185 -- send_16_3_time_reg(3*(I+1)-1 DOWNTO 3*I) WHEN data_ready(I) = '0' ELSE
186 -- send_16_3_time_reg(3*(I+1)-2 DOWNTO 3*I) & send_16_3_time_reg(3*(I+1)-1);
187 --END GENERATE all_send_16_3;
188
189 179 -- DMA control
190 180 DMAWriteFSM_p : PROCESS (HCLK, HRESETn)
191 181 BEGIN -- PROCESS DMAWriteBurst_p
192 182 IF HRESETn = '0' THEN
193 183 state <= IDLE;
194 184
195 185 sel_data <= "00";
196 186 update <= "00";
197 187 time_select <= '0';
198 188 time_fifo_ren <= '1';
199 189 data_send <= '0';
200 190 time_send <= '0';
201 191 time_write <= '0';
202 --send_16_3_time <= "001";
203 --send_16_3_time_reg(3*1-1 DOWNTO 3*0) <= "001";
204 --send_16_3_time_reg(3*2-1 DOWNTO 3*1) <= "001";
205 --send_16_3_time_reg(3*3-1 DOWNTO 3*2) <= "001";
206 --send_16_3_time_reg(3*4-1 DOWNTO 3*3) <= "001";
207 192
208 193 count_send_time <= 0;
209 194 ELSIF HCLK'EVENT AND HCLK = '1' THEN
210 195
211 196 CASE state IS
212 197 WHEN IDLE =>
213 198 count_send_time <= 0;
214 199 sel_data <= "00";
215 200 update <= "00";
216 201 time_select <= '0';
217 202 time_fifo_ren <= '1';
218 203 data_send <= '0';
219 204 time_send <= '0';
220 205 time_write <= '0';
221 206
222 207 IF data_ready = "0000" THEN
223 208 state <= IDLE;
224 209 ELSE
225 210 sel_data <= sel_data_s;
226 --send_16_3_time_reg <= send_16_3_time_reg_s;
227 --IF send_16_3_time = '1' THEN
228 -- state <= SEND_TIME_0;
229 --ELSE
230 -- state <= SEND_5_TIME;
231 --END IF;
232 211 state <= SEND_5_TIME;
233 212 END IF;
234 213
235 --WHEN SEND_TIME_0 =>
236 -- time_select <= '1';
237 -- IF time_already_send_s = '0' THEN
238 -- time_send <= '1';
239 -- state <= WAIT_TIME_0;
240 -- ELSE
241 -- time_send <= '0';
242 -- state <= SEND_TIME_1;
243 -- END IF;
244 -- time_fifo_ren <= '0';
245
246 --WHEN WAIT_TIME_0 =>
247 -- time_fifo_ren <= '1';
248 -- update <= "00";
249 -- time_send <= '0';
250 -- IF time_send_ok = '1' OR time_send_ko = '1' THEN
251 -- update <= "01";
252 -- state <= SEND_TIME_1;
253 -- END IF;
254
255 --WHEN SEND_TIME_1 =>
256 -- time_select <= '1';
257 -- IF time_already_send_s = '0' THEN
258 -- time_send <= '1';
259 -- state <= WAIT_TIME_1;
260 -- ELSE
261 -- time_send <= '0';
262 -- state <= SEND_5_TIME;
263 -- END IF;
264 -- time_fifo_ren <= '0';
265
266 --WHEN WAIT_TIME_1 =>
267 -- time_fifo_ren <= '1';
268 -- update <= "00";
269 -- time_send <= '0';
270 -- IF time_send_ok = '1' OR time_send_ko = '1' THEN
271 -- time_write <= '1';
272 -- update <= "01";
273 -- state <= SEND_5_TIME;
274 -- END IF;
275
276 214 WHEN SEND_5_TIME =>
277 215 update <= "00";
278 216 time_select <= '1';
279 217 time_fifo_ren <= '0';
280 218 count_send_time <= count_send_time + 1;
281 219 IF count_send_time = 10 THEN
282 220 state <= SEND_DATA;
283 221 END IF;
284 222
285 223 WHEN SEND_DATA =>
286 224 time_fifo_ren <= '1';
287 225 time_write <= '0';
288 226 time_send <= '0';
289 227
290 228 time_select <= '0';
291 229 data_send <= '1';
292 230 update <= "00";
293 231 state <= WAIT_DATA;
294 232
295 233 WHEN WAIT_DATA =>
296 234 data_send <= '0';
297 235
298 236 IF data_send_ok = '1' OR data_send_ko = '1' THEN
299 237 state <= IDLE;
300 238 update <= "10";
301 239 END IF;
302 240
303 241 WHEN OTHERS => NULL;
304 242 END CASE;
305 243
306 244 END IF;
307 245 END PROCESS DMAWriteFSM_p;
308 246 -----------------------------------------------------------------------------
309 247
310 248
311 249
312 250 -----------------------------------------------------------------------------
313 251 -- SEND 1 word by DMA
314 252 -----------------------------------------------------------------------------
315 253 lpp_dma_send_1word_1 : lpp_dma_send_1word
316 254 PORT MAP (
317 255 HCLK => HCLK,
318 256 HRESETn => HRESETn,
319 257 DMAIn => time_dmai,
320 258 DMAOut => DMAOut,
321 259
322 260 send => time_send,
323 261 address => data_address,
324 262 data => data,
325 263 send_ok => time_send_ok,
326 264 send_ko => time_send_ko
327 265 );
328 266
329 267 -----------------------------------------------------------------------------
330 268 -- SEND 16 word by DMA (in burst mode)
331 269 -----------------------------------------------------------------------------
270 data_2_halfword(31 DOWNTO 0) <= data(15 DOWNTO 0) & data (31 DOWNTO 16);
271
332 272 lpp_dma_send_16word_1 : lpp_dma_send_16word
333 273 PORT MAP (
334 274 HCLK => HCLK,
335 275 HRESETn => HRESETn,
336 276 DMAIn => data_dmai,
337 277 DMAOut => DMAOut,
338 278
339 279 send => data_send,
340 280 address => data_address,
341 data => data,
281 data => data_2_halfword,
342 282 ren => data_fifo_ren,
343 283 send_ok => data_send_ok,
344 284 send_ko => data_send_ko);
345 285
346 286 DMAIn <= time_dmai WHEN time_select = '1' ELSE data_dmai;
347 287 data_ren <= '1' WHEN time_select = '1' ELSE data_fifo_ren;
348 288 time_ren <= time_fifo_ren WHEN time_select = '1' ELSE '1';
349 289
350 290 all_data_ren : FOR I IN 3 DOWNTO 0 GENERATE
351 291 data_data_ren(I) <= data_ren WHEN UNSIGNED(sel_data) = I ELSE '1';
352 292 data_time_ren(I) <= time_ren WHEN UNSIGNED(sel_data) = I ELSE '1';
353 293 END GENERATE all_data_ren;
354 294
355 295 -----------------------------------------------------------------------------
356 296 -- SELECT ADDRESS
357 297 addr_data_reg_vector <= addr_data_f3 & addr_data_f2 & addr_data_f1 & addr_data_f0;
358 298
359 299 gen_select_address : FOR I IN 3 DOWNTO 0 GENERATE
360 300
361 301 update_and_sel((2*I)+1 DOWNTO 2*I) <= update WHEN UNSIGNED(sel_data) = I ELSE "00";
362 302
363 303 lpp_waveform_dma_selectaddress_I : lpp_waveform_dma_selectaddress
364 304 GENERIC MAP (
365 305 nb_burst_available_size => nb_burst_available_size)
366 306 PORT MAP (
367 307 HCLK => HCLK,
368 308 HRESETn => HRESETn,
369 309 update => update_and_sel((2*I)+1 DOWNTO 2*I),
370 310 nb_burst_available => nb_burst_available,
371 311 addr_data_reg => addr_data_reg_vector(32*I+31 DOWNTO 32*I),
372 312 addr_data => addr_data_vector(32*I+31 DOWNTO 32*I),
373 313 status_full => status_full(I),
374 314 status_full_ack => status_full_ack(I),
375 315 status_full_err => status_full_err(I));
376 316
377 317 END GENERATE gen_select_address;
378 318
379 319 data_address <= addr_data_vector(31 DOWNTO 0) WHEN UNSIGNED(sel_data) = 0 ELSE
380 320 addr_data_vector(32*1+31 DOWNTO 32*1) WHEN UNSIGNED(sel_data) = 1 ELSE
381 321 addr_data_vector(32*2+31 DOWNTO 32*2) WHEN UNSIGNED(sel_data) = 2 ELSE
382 322 addr_data_vector(32*3+31 DOWNTO 32*3);
383 323 -----------------------------------------------------------------------------
384 324
385 325
386 326 END Behavioral;
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