diff --git a/lib/lpp/lpp_waveform/lpp_waveform.vhd b/lib/lpp/lpp_waveform/lpp_waveform.vhd --- a/lib/lpp/lpp_waveform/lpp_waveform.vhd +++ b/lib/lpp/lpp_waveform/lpp_waveform.vhd @@ -237,9 +237,6 @@ BEGIN -- beh time_wen => time_wen, data_wen => data_wen, wdata => wdata); - - --time_ren <= (OTHERS => '1'); - --data_ren <= (OTHERS => '1'); pp_waveform_dma_1: lpp_waveform_dma GENERIC MAP ( @@ -248,29 +245,21 @@ BEGIN -- beh hindex => hindex, nb_burst_available_size => nb_burst_available_size) PORT MAP ( - HCLK => clk, - HRESETn => rstn, - AHB_Master_In => AHB_Master_In, - AHB_Master_Out => AHB_Master_Out, - data_ready => ready, - data => rdata, - data_data_ren => data_ren, - data_time_ren => time_ren, - --data_f0_in => data_f0_out, - --data_f1_in => data_f1_out, - --data_f2_in => data_f2_out, - --data_f3_in => data_f3_out, - --data_f0_in_valid => data_f0_out_valid, - --data_f1_in_valid => data_f1_out_valid, - --data_f2_in_valid => data_f2_out_valid, - --data_f3_in_valid => data_f3_out_valid, + HCLK => clk, + HRESETn => rstn, + AHB_Master_In => AHB_Master_In, + AHB_Master_Out => AHB_Master_Out, + data_ready => ready, + data => rdata, + data_data_ren => data_ren, + data_time_ren => time_ren, nb_burst_available => nb_burst_available, - status_full => status_full, - status_full_ack => status_full_ack, - status_full_err => status_full_err, - addr_data_f0 => addr_data_f0, - addr_data_f1 => addr_data_f1, - addr_data_f2 => addr_data_f2, - addr_data_f3 => addr_data_f3); + status_full => status_full, + status_full_ack => status_full_ack, + status_full_err => status_full_err, + addr_data_f0 => addr_data_f0, + addr_data_f1 => addr_data_f1, + addr_data_f2 => addr_data_f2, + addr_data_f3 => addr_data_f3); END beh; diff --git a/lib/lpp/lpp_waveform/lpp_waveform_dma.vhd b/lib/lpp/lpp_waveform/lpp_waveform_dma.vhd --- a/lib/lpp/lpp_waveform/lpp_waveform_dma.vhd +++ b/lib/lpp/lpp_waveform/lpp_waveform_dma.vhd @@ -122,6 +122,8 @@ ARCHITECTURE Behavioral OF lpp_waveform_ ----------------------------------------------------------------------------- SIGNAL send_16_3_time : STD_LOGIC; SIGNAL count_send_time : INTEGER; + ----------------------------------------------------------------------------- + SIGNAL data_2_halfword : STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo BEGIN ----------------------------------------------------------------------------- @@ -173,18 +175,6 @@ BEGIN time_already_send(1) WHEN data_ready(1) = '1' ELSE time_already_send(2) WHEN data_ready(2) = '1' ELSE time_already_send(3); - - - --send_16_3_time <= send_16_3_time_reg(0) WHEN data_ready(0) = '1' ELSE - -- send_16_3_time_reg(3) WHEN data_ready(1) = '1' ELSE - -- send_16_3_time_reg(6) WHEN data_ready(2) = '1' ELSE - -- send_16_3_time_reg(9) ; - - --all_send_16_3: FOR I IN 3 DOWNTO 0 GENERATE - -- send_16_3_time_reg_s(3*(I+1)-1 DOWNTO 3*I) <= - -- send_16_3_time_reg(3*(I+1)-1 DOWNTO 3*I) WHEN data_ready(I) = '0' ELSE - -- send_16_3_time_reg(3*(I+1)-2 DOWNTO 3*I) & send_16_3_time_reg(3*(I+1)-1); - --END GENERATE all_send_16_3; -- DMA control DMAWriteFSM_p : PROCESS (HCLK, HRESETn) @@ -199,11 +189,6 @@ BEGIN data_send <= '0'; time_send <= '0'; time_write <= '0'; - --send_16_3_time <= "001"; - --send_16_3_time_reg(3*1-1 DOWNTO 3*0) <= "001"; - --send_16_3_time_reg(3*2-1 DOWNTO 3*1) <= "001"; - --send_16_3_time_reg(3*3-1 DOWNTO 3*2) <= "001"; - --send_16_3_time_reg(3*4-1 DOWNTO 3*3) <= "001"; count_send_time <= 0; ELSIF HCLK'EVENT AND HCLK = '1' THEN @@ -223,55 +208,8 @@ BEGIN state <= IDLE; ELSE sel_data <= sel_data_s; - --send_16_3_time_reg <= send_16_3_time_reg_s; - --IF send_16_3_time = '1' THEN - -- state <= SEND_TIME_0; - --ELSE - -- state <= SEND_5_TIME; - --END IF; state <= SEND_5_TIME; END IF; - - --WHEN SEND_TIME_0 => - -- time_select <= '1'; - -- IF time_already_send_s = '0' THEN - -- time_send <= '1'; - -- state <= WAIT_TIME_0; - -- ELSE - -- time_send <= '0'; - -- state <= SEND_TIME_1; - -- END IF; - -- time_fifo_ren <= '0'; - - --WHEN WAIT_TIME_0 => - -- time_fifo_ren <= '1'; - -- update <= "00"; - -- time_send <= '0'; - -- IF time_send_ok = '1' OR time_send_ko = '1' THEN - -- update <= "01"; - -- state <= SEND_TIME_1; - -- END IF; - - --WHEN SEND_TIME_1 => - -- time_select <= '1'; - -- IF time_already_send_s = '0' THEN - -- time_send <= '1'; - -- state <= WAIT_TIME_1; - -- ELSE - -- time_send <= '0'; - -- state <= SEND_5_TIME; - -- END IF; - -- time_fifo_ren <= '0'; - - --WHEN WAIT_TIME_1 => - -- time_fifo_ren <= '1'; - -- update <= "00"; - -- time_send <= '0'; - -- IF time_send_ok = '1' OR time_send_ko = '1' THEN - -- time_write <= '1'; - -- update <= "01"; - -- state <= SEND_5_TIME; - -- END IF; WHEN SEND_5_TIME => update <= "00"; @@ -329,6 +267,8 @@ BEGIN ----------------------------------------------------------------------------- -- SEND 16 word by DMA (in burst mode) ----------------------------------------------------------------------------- + data_2_halfword(31 DOWNTO 0) <= data(15 DOWNTO 0) & data (31 DOWNTO 16); + lpp_dma_send_16word_1 : lpp_dma_send_16word PORT MAP ( HCLK => HCLK, @@ -338,7 +278,7 @@ BEGIN send => data_send, address => data_address, - data => data, + data => data_2_halfword, ren => data_fifo_ren, send_ok => data_send_ok, send_ko => data_send_ko);