HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Commit - r37:81e639333c9d

Fixed some files

Alexis -

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r37:81e639333c9d

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lib/lpp/amba_lcd_16x2_ctrlr/apb_lcd_ctrlr.vhd +1 0

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             -------------------------------------------------------------------------------
             library IEEE;
             use IEEE.STD_LOGIC_1164.ALL;
             use ieee.numeric_std.all;
             library grlib;
             use grlib.amba.all;
             use grlib.stdlib.all;
             use grlib.devices.all;
             library lpp;
             use lpp.amba_lcd_16x2_ctrlr.all;
             use lpp.LCD_16x2_CFG.all;
             use lpp.lpp_amba.all;
+            use lpp.apb_devices_list.all;
             entity apb_lcd_ctrlr is
               generic (
                 pindex   : integer := 0;
                 paddr    : integer := 0;
                 pmask    : integer := 16#fff#;
                 pirq     : integer := 0;
                 abits    : integer := 8);
               port (
             	rst    : in  std_ulogic;
             	clk    : in  std_ulogic;
             	apbi   : in  apb_slv_in_type;
             	apbo   : out apb_slv_out_type;
             	LCD_data 	: out  STD_LOGIC_VECTOR (7 downto 0);
             	LCD_RS 	: out  STD_LOGIC;
             	LCD_RW 	: out  STD_LOGIC;
             	LCD_E  	: out  STD_LOGIC;
             	LCD_RET 	: out  STD_LOGIC;
             	LCD_CS1 	: out  STD_LOGIC;
             	LCD_CS2 	: out  STD_LOGIC;
             	SF_CE0		: out	std_logic
                 );
             end apb_lcd_ctrlr;
             architecture Behavioral of apb_lcd_ctrlr is
             signal	FramBUFF :  FRM_Buff_Space;
             signal	CMD		:	std_logic_vector(10 downto 0);
             signal	Exec		:	std_logic;
             signal	Ready		:	std_logic;
             signal	LCD_CTRL	:	LCD_DRVR_CTRL_BUSS;
             constant REVISION : integer := 1;
             constant pconfig : apb_config_type := (
 => ahb_device_reg (VENDOR_LPP, LPP_LCD_CTRLR, 0, REVISION, 0),
 => apb_iobar(paddr, pmask));
             --type FRM_Buff_El	is std_logic_vector(31 downto 0);
             type FRM_Buff_Reg	is array(lcd_space_size-1 downto 0) of std_logic_vector(31 downto 0);
             type LCD_ctrlr_Reg is record
               CTRL_Reg 		:   std_logic_vector(31 downto 0);
               FRAME_BUFF   :   FRM_Buff_Reg;
             end record;
             signal r : LCD_ctrlr_Reg;
             signal Rdata	:	std_logic_vector(31 downto 0);
             begin
             LCD_data 	<=	LCD_CTRL.LCD_DATA;
             LCD_RS 		<=	LCD_CTRL.LCD_RS;
             LCD_RW 		<=	LCD_CTRL.LCD_RW;
             LCD_E  		<=	LCD_CTRL.LCD_E;
             LCD_RET	<=	'0';
             LCD_CS1	<=	'0';
             LCD_CS2	<=	'0';
             SF_CE0	<=	'1';
             CMD(7 downto 0)	<=	r.CTRL_Reg(7 downto 0); --CMD value
             CMD(9 downto 8)	<=	r.CTRL_Reg(9 downto 8); --CMD tempo value
             r.CTRL_Reg(10)		<=	Ready;
             Driver0 : LCD_16x2_ENGINE
             	generic map(50000)
                 Port map(clk,rst,FramBUFF,CMD,Exec,Ready,LCD_CTRL);
             FRM_BF : for i in 0 to lcd_space_size-1 generate
             	FramBUFF(i)	<=	r.FRAME_BUFF(i)(7 downto 0);
             end generate;
             process(rst,clk)
             begin
                 if rst = '0' then
                     r.CTRL_Reg(9 downto 0) <= (others => '0');
             		  Exec	<=	'0';
                 elsif clk'event and clk = '1' then
             --APB Write OP
                     if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
                         case apbi.paddr(7 downto 2) is
                             when "000000" =>
                                 r.CTRL_Reg(9 downto 0) <= apbi.pwdata(9 downto 0);
             						  Exec	<=	'1';
                             when others =>
                              writeC:   for i in 1 to lcd_space_size loop
             								if TO_INTEGER(unsigned(apbi.paddr(abits-1 downto 2))) =i then
             									r.FRAME_BUFF(i-1)	<=	apbi.pwdata;
             								end if;
             						Exec	<=	'0';
             					end loop;
                         end case;
             			else
             				Exec	<=	'0';
                     end if;
             --APB READ OP
                     if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
                         case apbi.paddr(7 downto 2) is
                             when "000000" =>
                                 Rdata <= r.CTRL_Reg;
                             when others =>
                                 readC:   for i in 1 to lcd_space_size loop
             								if TO_INTEGER(unsigned(apbi.paddr(abits-1 downto 2))) =i then
             									Rdata(7 downto 0) <= r.FRAME_BUFF(i-1)(7 downto 0);
             								end if;
             					end loop;
                         end case;
                     end if;
                 end if;
                 apbo.pconfig <= pconfig;
             end process;
             apbo.prdata <=	Rdata when apbi.penable = '1' ;
             end Behavioral;

lib/lpp/dsp/iir_filter/APB_IIR_CEL.vhd +1 0

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             -------------------------------------------------------------------------------
             library ieee;
             use ieee.std_logic_1164.all;
             use ieee.numeric_std.all;
             library grlib;
             use grlib.amba.all;
             use grlib.stdlib.all;
             use grlib.devices.all;
             library lpp;
             use lpp.iir_filter.all;
             use lpp.general_purpose.all;
             use lpp.lpp_amba.all;
+            use lpp.apb_devices_list.all;
             entity APB_IIR_CEL is
               generic (
                 pindex   : integer  := 0;
                 paddr    : integer  := 0;
                 pmask    : integer  := 16#fff#;
                 pirq     : integer  := 0;
                 abits    : integer  := 8;
                 Sample_SZ : integer := 16;
                 ChanelsCount : integer := 1;
             	 Coef_SZ      : integer := 9;
             	 CoefCntPerCel: integer := 3;
             	 Cels_count   : integer := 5;
             	 virgPos      : integer := 3;
                 Mem_use      : integer := use_RAM
                 );
               port (
                 rst             : in  std_logic;
                 clk             : in  std_logic;
                 apbi            : in  apb_slv_in_type;
                 apbo            : out apb_slv_out_type;
                 sample_clk      : in  std_logic;
                 sample_clk_out  : out std_logic;
                 sample_in   :   in  samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
                 sample_out  :   out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0)
                 );
             end;
             architecture AR_APB_IIR_CEL of APB_IIR_CEL is
             constant REVISION : integer := 1;
             constant pconfig : apb_config_type := (
 => ahb_device_reg (VENDOR_LPP, LPP_IIR_CEL_FILTER, 0, REVISION, 0),
 => apb_iobar(paddr, pmask));
             type FILTERreg is record
               regin     :   in_IIR_CEL_reg;
               regout    :   out_IIR_CEL_reg;
             end record;
             signal Rdata	  :  std_logic_vector(31 downto 0);
             signal  r : FILTERreg;
             signal  filter_reset    :   std_logic:='0';
             signal  smp_cnt : integer :=0;
             signal  sample_clk_out_R : std_logic;
             type    CoefCelT  is array(CoefCntPerCel-1 downto 0) of std_logic_vector(Coef_SZ-1 downto 0);
             type    CoefTblT  is array(Cels_count-1 downto 0) of CoefCelT;
             type    CoefsRegT is record
                 numCoefs    : CoefTblT;
             	 denCoefs    : CoefTblT;
             end record;
             signal  CoefsReg   : CoefsRegT;
             begin
             filter_reset    <=  rst and r.regin.config(0);
             sample_clk_out  <=  sample_clk_out_R;
             filter : IIR_CEL_FILTER
             generic map(Sample_SZ,ChanelsCount,Coef_SZ,CoefCntPerCel,Cels_count,Mem_use)
             port map(
                 reset       =>  filter_reset,
                 clk         =>  clk,
                 sample_clk  =>  sample_clk,
                 regs_in     =>  r.regin,
                 regs_out    =>  r.regout,
                 sample_in   =>  sample_in,
                 sample_out  =>  sample_out
                 );
             process(rst,sample_clk)
             begin
             if rst = '0' then
                 smp_cnt <= 0;
                 sample_clk_out_R <= '0';
             elsif sample_clk'event and sample_clk = '1' then
               if smp_cnt = 1 then
                 smp_cnt <= 0;
                 sample_clk_out_R <= not sample_clk_out_R;
               else
                 smp_cnt <= smp_cnt +1;
               end if;
             end if;
             end process;
             process(rst,clk)
             begin
                 if rst = '0' then
                     r.regin.virgPos          <= std_logic_vector(to_unsigned(virgPos,5));
                 elsif clk'event and clk = '1' then
             --APB Write OP
                     if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
                         case apbi.paddr(7 downto 2) is
                             when "000000" =>
                                 r.regin.config(0) <= apbi.pwdata(0);
                             when "000001" =>
                                   r.regin.virgPos <= apbi.pwdata(4 downto 0);
                             when others =>
                                 for i in 0 to Cels_count-1 loop
                                     if conv_integer(apbi.paddr(7 downto 5)) = i+1 then
                                         case apbi.paddr(4 downto 2) is
                                             when "000" =>
                                                 CoefsReg.numCoefs(i)(0)  <=  (apbi.pwdata(Coef_SZ-1 downto 0));
                                             when "001" =>
                                                 CoefsReg.numCoefs(i)(1)  <=  (apbi.pwdata(Coef_SZ-1 downto 0));
                                             when "010" =>
                                                 CoefsReg.numCoefs(i)(2)  <=  (apbi.pwdata(Coef_SZ-1 downto 0));
                                             when "011" =>
                                                 CoefsReg.denCoefs(i)(0)  <=  (apbi.pwdata(Coef_SZ-1 downto 0));
                                             when "100" =>
                                                 CoefsReg.denCoefs(i)(1)  <=  (apbi.pwdata(Coef_SZ-1 downto 0));
                                             when "101" =>
                                                 CoefsReg.denCoefs(i)(2)  <=  (apbi.pwdata(Coef_SZ-1 downto 0));
                                             when others =>
                                         end case;
                                     end if;
                                 end loop;
                         end case;
                     end if;
             --APB READ OP
                     if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
                         case apbi.paddr(7 downto 2) is
                             when "000000" =>
                             when "000001" =>
                                 Rdata(4 downto 0) <=   r.regin.virgPos;
                             when others =>
                                 for i in 0 to Cels_count-1 loop
                                     if conv_integer(apbi.paddr(7 downto 5)) = i+1 then
                                         case apbi.paddr(4 downto 2) is
                                             when "000" =>
                                                 Rdata(Coef_SZ-1 downto 0)  <= std_logic_vector(CoefsReg.numCoefs(i)(0));
                                             when "001" =>
                                                 Rdata(Coef_SZ-1 downto 0)  <=  std_logic_vector(CoefsReg.numCoefs(i)(1));
                                             when "010" =>
                                                 Rdata(Coef_SZ-1 downto 0)  <=  std_logic_vector(CoefsReg.numCoefs(i)(2));
                                             when "011" =>
                                                 Rdata(Coef_SZ-1 downto 0)  <=  std_logic_vector(CoefsReg.denCoefs(i)(0));
                                             when "100" =>
                                                 Rdata(Coef_SZ-1 downto 0)  <=  std_logic_vector(CoefsReg.denCoefs(i)(1));
                                             when "101" =>
                                                 Rdata(Coef_SZ-1 downto 0)  <=  std_logic_vector(CoefsReg.denCoefs(i)(2));
                                             when others =>
                                         end case;
                                     end if;
                                 end loop;
                         end case;
                     end if;
                 end if;
                 apbo.pconfig <= pconfig;
             end process;
             apbo.prdata <=	Rdata when apbi.penable = '1' ;
             -- pragma translate_off
                 bootmsg : report_version
                 generic map ("apbuart" & tost(pindex) &
             	": Generic UART rev " & tost(REVISION) & ", fifo " & tost(fifosize) &
             	", irq " & tost(pirq));
             -- pragma translate_on
             end ar_APB_IIR_CEL;

lib/lpp/lpp_ad_Conv/lpp_apb_ad_conv.vhd +1 0

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             -------------------------------------------------------------------------------
             library IEEE;
             use IEEE.STD_LOGIC_1164.ALL;
             use ieee.numeric_std.all;
             library grlib;
             use grlib.amba.all;
             use grlib.stdlib.all;
             use grlib.devices.all;
             library lpp;
             use lpp.lpp_ad_conv.all;
             use lpp.lpp_amba.all;
+            use lpp.apb_devices_list.all;
             use lpp.general_purpose.Clk_divider;
             entity lpp_apb_ad_conv is
                 generic(
                       pindex      : integer := 0;
                       paddr       : integer := 0;
                       pmask       : integer := 16#fff#;
                       pirq        : integer := 0;
                       abits       : integer := 8;
                       ChanelCount : integer := 1;
                       clkkHz      : integer := 50000;
             	  smpClkHz    : integer := 100;
                       ADCref      : integer := AD7688);
                 Port (
                       clk        : in   STD_LOGIC;
                       reset      : in   STD_LOGIC;
                       apbi       : in   apb_slv_in_type;
                       apbo       : out  apb_slv_out_type;
                       AD_in      : in   AD7688_in(ChanelCount-1 downto 0);
                       AD_out     : out  AD7688_out);
             end lpp_apb_ad_conv;
             architecture ar_lpp_apb_ad_conv of lpp_apb_ad_conv is
             constant REVISION : integer := 1;
             constant pconfig : apb_config_type := (
 => ahb_device_reg (VENDOR_LPP, LPP_APB_ADC, 0, REVISION, 0),
 => apb_iobar(paddr, pmask));
             signal Rdata	  :  std_logic_vector(31 downto 0);
             signal smpout    :  Samples_out(ChanelCount-1 downto 0);
             signal smplClk   :  STD_LOGIC;
             signal DataReady :  STD_LOGIC;
             type lpp_apb_ad_conv_Reg is record
               CTRL_Reg     :   std_logic_vector(31 downto 0);
               sample       :   Samples_out(ChanelCount-1 downto 0);
             end record;
             signal r         :  lpp_apb_ad_conv_Reg;
             begin
             caseAD7688: if ADCref = AD7688 generate
             AD7688: AD7688_drvr
                 generic map(ChanelCount,clkkHz)
                 Port map(clk,reset,smplClk,DataReady,smpout,AD_in,AD_out);
             end generate;
             caseADS786: if ADCref = ADS7886 generate
             ADS7886: ADS7886_drvr
                 generic map(ChanelCount,clkkHz)
                 Port map(clk,reset,smplClk,DataReady,smpout,AD_in,AD_out);
             end generate;
             clkdivider: Clk_divider
             		 generic map(clkkHz*1000,smpClkHz)
             		 Port map( clk ,reset,smplClk);
             r.CTRL_Reg(0)	<=	DataReady;
             r.sample    <=    smpout;
             process(reset,clk)
             begin
               if reset = '0' then
                     --r.CTRL_Reg(9 downto 0) <= (others => '0');
                 elsif clk'event and clk = '1' then
             --APB Write OP
                   if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
                       case apbi.paddr(7 downto 2) is
                           when "000000" =>
                               --r.CTRL_Reg(9 downto 0)    <=    apbi.pwdata(9 downto 0);
                           when others =>
                       end case;
                   end if;
             --APB READ OP
                   if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
                       case apbi.paddr(7 downto 2) is
                           when "000000" =>
                               Rdata <= r.CTRL_Reg;
                           when others =>
                               readC:   for i in 1 to ChanelCount loop
                                   if TO_INTEGER(unsigned(apbi.paddr(abits-1 downto 2))) =i then
                                       Rdata(15 downto 0)    <=    r.sample(i-1)(15 downto 0);
                                   end if;
                               end loop;
                       end case;
                   end if;
               end if;
               apbo.pconfig <= pconfig;
             end process;
             apbo.prdata <=	Rdata when apbi.penable = '1' ;
             end ar_lpp_apb_ad_conv;

lib/lpp/lpp_cna/APB_CNA.vhd +2 -1

             -- APB_CNA.vhd
             library ieee;
             use ieee.std_logic_1164.all;
             library grlib;
             use grlib.amba.all;
             use grlib.stdlib.all;
             use grlib.devices.all;
             library lpp;
             use lpp.lpp_amba.all;
+            use lpp.apb_devices_list.all;
             use lpp.lpp_cna.all;
             entity APB_CNA is
               generic (
                 pindex   : integer := 0;
                 paddr    : integer := 0;
                 pmask    : integer := 16#fff#;
                 pirq     : integer := 0;
                 abits    : integer := 8);
               port (
                 clk     : in  std_logic;
                 rst     : in  std_logic;
                 apbi    : in  apb_slv_in_type;
                 apbo    : out apb_slv_out_type;
                 SYNC    : out std_logic;
                 SCLK    : out std_logic;
                 DATA    : out std_logic
                 );
             end APB_CNA;
             architecture ar_APB_CNA of APB_CNA is
             constant REVISION : integer := 1;
             constant pconfig : apb_config_type := (
 => ahb_device_reg (VENDOR_LPP, LPP_CNA, 0, REVISION, 0),
 => apb_iobar(paddr, pmask));
             signal enable   : std_logic;
             signal flag_sd : std_logic;
             type CNA_ctrlr_Reg is record
                  CNA_Cfg  : std_logic_vector(1 downto 0);
                  CNA_Data : std_logic_vector(15 downto 0);
             end record;
             signal Rec : CNA_ctrlr_Reg;
             signal Rdata     : std_logic_vector(31 downto 0);
             begin
             enable <= Rec.CNA_Cfg(0);
             Rec.CNA_Cfg(1) <= flag_sd;
                 CONVERTER : entity Work.CNA_TabloC
                     port map(clk,rst,enable,Rec.CNA_Data,SYNC,SCLK,flag_sd,Data);
                 process(rst,clk)
                 begin
                     if(rst='0')then
                         Rec.CNA_Data <=  (others => '0');
                     elsif(clk'event and clk='1')then
                 --APB Write OP
                         if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
                             case apbi.paddr(abits-1 downto 2) is
                                 when "000000" =>
                                     Rec.CNA_Cfg(0) <= apbi.pwdata(0);
                                 when "000001" =>
                                     Rec.CNA_Data <= apbi.pwdata(15 downto 0);
                                 when others =>
                                     null;
                             end case;
                         end if;
                 --APB READ OP
                         if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
                             case apbi.paddr(abits-1 downto 2) is
                                 when "000000" =>
                                     Rdata(31 downto 2) <= X"ABCDEF5" & "00";
                                     Rdata(1 downto 0) <= Rec.CNA_Cfg;
                                 when "000001" =>
                                     Rdata(31 downto 16) <= X"FD18";
                                     Rdata(15 downto 0) <= Rec.CNA_Data;
                                 when others =>
                                     Rdata <= (others => '0');
                             end case;
                         end if;
                     end if;
                     apbo.pconfig <= pconfig;
                 end process;
             apbo.prdata     <=   Rdata when apbi.penable = '1';
-            end ar_APB_CNA;
  No newline at end of file
+            end ar_APB_CNA;

lib/lpp/lpp_uart/APB_UART.vhd +1 0

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             -------------------------------------------------------------------------------
             library ieee;
             use ieee.std_logic_1164.all;
             library grlib;
             use grlib.amba.all;
             use grlib.stdlib.all;
             use grlib.devices.all;
             library lpp;
             use lpp.lpp_amba.all;
+            use lpp.apb_devices_list.all;
             use lpp.lpp_uart.all;
             entity APB_UART is
               generic (
                 pindex   : integer := 0;
                 paddr    : integer := 0;
                 pmask    : integer := 16#fff#;
                 pirq     : integer := 0;
                 abits    : integer := 8;
                 Data_sz  : integer := 8);
               port (
                 clk     : in  std_logic;
                 rst     : in  std_logic;
                 apbi    : in  apb_slv_in_type;
                 apbo    : out apb_slv_out_type;
                 TXD    :   out std_logic;
                 RXD    :   in  std_logic
                 );
             end APB_UART;
             architecture ar_APB_UART of APB_UART is
             constant REVISION : integer := 1;
             constant pconfig : apb_config_type := (
 => ahb_device_reg (VENDOR_LPP, LPP_UART, 0, REVISION, 0),
 => apb_iobar(paddr, pmask));
             signal NwData   : std_logic;
             signal ACK      : std_logic;
             signal Capture  : std_logic;
             signal Send     : std_logic;
             signal Sended   : std_logic;
             type UART_ctrlr_Reg is record
                  UART_Cfg  : std_logic_vector(4 downto 0);
                  UART_Wdata : std_logic_vector(7 downto 0);
                  UART_Rdata : std_logic_vector(7 downto 0);
                  UART_BTrig : std_logic_vector(11 downto 0);
             end record;
             signal Rec : UART_ctrlr_Reg;
             signal Rdata     : std_logic_vector(31 downto 0);
             begin
             Capture <= Rec.UART_Cfg(0);
             --ACK <= Rec.UART_Cfg(1);
             --Send <= Rec.UART_Cfg(2);
             Rec.UART_Cfg(3) <= Sended;
             Rec.UART_Cfg(4) <= NwData;
                 COM0 : entity work.UART
                     generic map (Data_sz)
                     port map (clk,rst,TXD,RXD,Capture,NwData,ACK,Send,Sended,Rec.UART_BTrig,Rec.UART_Rdata,Rec.UART_Wdata);
                 process(rst,clk)
                 begin
                     if(rst='0')then
                         Rec.UART_Wdata <=  (others => '0');
                     elsif(clk'event and clk='1')then
                 --APB Write OP
                         if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
                             case apbi.paddr(7 downto 2) is
                                 when "000000" =>
                                     Rec.UART_Cfg(2 downto 0) <= apbi.pwdata(2 downto 0);
                                 when "000001" =>
                                     Rec.UART_Wdata <= apbi.pwdata(7 downto 0);
             								Send           <=	'1';
                                 when others =>
                                     null;
                             end case;
             				else
             					Send           <=	'0';
                         end if;
                 --APB READ OP
                         if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
                             case apbi.paddr(7 downto 2) is
                                 when "000000" =>
                                     Rdata(4 downto 0) <= Rec.UART_Cfg;
                                     Rdata(26 downto 12) <= (others => '0');
                                     Rdata(27 downto 16) <= Rec.UART_BTrig;
                                 when "000001" =>
                                     Rdata(7 downto 0) <= Rec.UART_Wdata;
                                 when "000010" =>
                                     Rdata(7 downto 0) <= Rec.UART_Rdata;
             								Ack               <= '1';
                                 when others =>
                                     Rdata <= (others => '0');
                             end case;
             				else
             				    Ack               <= '0';
                         end if;
                     end if;
                     apbo.pconfig <= pconfig;
                 end process;
                 apbo.prdata     <=   Rdata when apbi.penable = '1';
             end ar_APB_UART;

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