##// END OF EJS Templates
HG_REPOSITORIES » LPP » INSTRUMENTATION » USERS » PELLION » VHD_Lib
RSS

Clone from http://pc-instru.lpp.polytechnique.fr:5000/VHD_Lib

Issue JIRA : RPWMEB-467...
pellion -
r616:81bdd2b4261c simu_with_Leon3
parent child
Show More
Show file before | Show file after | Hide comments
@@ -35,6 +35,7 ARCHITECTURE ar_top_ad_conv_RHF1401 OF t
35 SIGNAL cnv_s_reg : STD_LOGIC;
35 SIGNAL cnv_s_reg : STD_LOGIC;
36 SIGNAL cnv_sync : STD_LOGIC;
36 SIGNAL cnv_sync : STD_LOGIC;
37 SIGNAL cnv_sync_pre : STD_LOGIC;
37 SIGNAL cnv_sync_pre : STD_LOGIC;
38 SIGNAL cnv_sync_falling_edge : STD_LOGIC;
38
39
39 SIGNAL ADC_nOE_reg : STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
40 SIGNAL ADC_nOE_reg : STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
40 SIGNAL enable_ADC : STD_LOGIC;
41 SIGNAL enable_ADC : STD_LOGIC;
@@ -104,6 +105,7 BEGIN
104 A => cnv_s_reg,
105 A => cnv_s_reg,
105 A_sync => cnv_sync);
106 A_sync => cnv_sync);
106
107
108 cnv_sync_falling_edge <= '1' WHEN cnv_sync = '0' AND cnv_sync_pre = '1' ELSE '0';
107
109
108 -----------------------------------------------------------------------------
110 -----------------------------------------------------------------------------
109 -- DATA GEN Output Enable
111 -- DATA GEN Output Enable
@@ -114,9 +116,9 BEGIN
114 ADC_nOE_reg(ChanelCount-1 DOWNTO 0) <= (OTHERS => '1');
116 ADC_nOE_reg(ChanelCount-1 DOWNTO 0) <= (OTHERS => '1');
115 cnv_sync_pre <= '0';
117 cnv_sync_pre <= '0';
116 enable_ADC <= '0';
118 enable_ADC <= '0';
117 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
119 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
118 cnv_sync_pre <= cnv_sync;
120 cnv_sync_pre <= cnv_sync;
119 IF cnv_sync = '1' AND cnv_sync_pre = '0' THEN
121 IF cnv_sync_falling_edge = '1' THEN
120 enable_ADC <= '1';
122 enable_ADC <= '1';
121 ADC_nOE_reg(0) <= '0';
123 ADC_nOE_reg(0) <= '0';
122 ADC_nOE_reg(ChanelCount-1 DOWNTO 1) <= (OTHERS => '1');
124 ADC_nOE_reg(ChanelCount-1 DOWNTO 1) <= (OTHERS => '1');
@@ -146,8 +148,8 BEGIN
146
148
147 sample_val <= '0';
149 sample_val <= '0';
148 sample_counter <= 0;
150 sample_counter <= 0;
149 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
151 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
150 IF cnv_sync = '1' AND cnv_sync_pre = '0' THEN
152 IF cnv_sync_falling_edge = '1' THEN
151 channel_counter <= 0;
153 channel_counter <= 0;
152 ELSE
154 ELSE
153 IF channel_counter < MAX_COUNTER THEN
155 IF channel_counter < MAX_COUNTER THEN
@@ -206,7 +208,7 BEGIN
206 -- /\/\/\/\/\/\/\ ----------------------------------- /\/\/\/\/\/\/\
208 -- /\/\/\/\/\/\/\ ----------------------------------- /\/\/\/\/\/\/\
207 -----------------------------------------------------------------------------
209 -----------------------------------------------------------------------------
208
210
209 ADC_data_result <= std_logic_vector( (signed( ADC_data_selected(13) & ADC_data_selected) + signed( ADC_data(13) & ADC_data)) );
211 ADC_data_result <= STD_LOGIC_VECTOR((SIGNED(ADC_data_selected(13) & ADC_data_selected) + SIGNED(ADC_data(13) & ADC_data)));
210
212
211 sample <= sample_reg;
213 sample <= sample_reg;
212
214
General Comments 0
You need to be logged in to leave comments. Login now