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Issue JIRA : RPWMEB-467...
pellion -
r616:81bdd2b4261c simu_with_Leon3
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1
2 LIBRARY IEEE;
2 LIBRARY IEEE;
3 USE IEEE.STD_LOGIC_1164.ALL;
3 USE IEEE.STD_LOGIC_1164.ALL;
4 USE IEEE.numeric_std.ALL;
4 USE IEEE.numeric_std.ALL;
5 LIBRARY lpp;
5 LIBRARY lpp;
6 USE lpp.lpp_ad_conv.ALL;
6 USE lpp.lpp_ad_conv.ALL;
7 USE lpp.general_purpose.SYNC_FF;
7 USE lpp.general_purpose.SYNC_FF;
8
8
9 ENTITY top_ad_conv_RHF1401_withFilter IS
9 ENTITY top_ad_conv_RHF1401_withFilter IS
10 GENERIC(
10 GENERIC(
11 ChanelCount : INTEGER := 8;
11 ChanelCount : INTEGER := 8;
12 ncycle_cnv_high : INTEGER := 13;
12 ncycle_cnv_high : INTEGER := 13;
13 ncycle_cnv : INTEGER := 25;
13 ncycle_cnv : INTEGER := 25;
14 FILTER_ENABLED : INTEGER := 16#FF#
14 FILTER_ENABLED : INTEGER := 16#FF#
15 );
15 );
16 PORT (
16 PORT (
17 cnv_clk : IN STD_LOGIC; -- 24Mhz
17 cnv_clk : IN STD_LOGIC; -- 24Mhz
18 cnv_rstn : IN STD_LOGIC;
18 cnv_rstn : IN STD_LOGIC;
19
19
20 cnv : OUT STD_LOGIC;
20 cnv : OUT STD_LOGIC;
21
21
22 clk : IN STD_LOGIC; -- 25MHz
22 clk : IN STD_LOGIC; -- 25MHz
23 rstn : IN STD_LOGIC;
23 rstn : IN STD_LOGIC;
24 ADC_data : IN Samples14;
24 ADC_data : IN Samples14;
25 ADC_nOE : OUT STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
25 ADC_nOE : OUT STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
26 sample : OUT Samples14v(ChanelCount-1 DOWNTO 0);
26 sample : OUT Samples14v(ChanelCount-1 DOWNTO 0);
27 sample_val : OUT STD_LOGIC
27 sample_val : OUT STD_LOGIC
28 );
28 );
29 END top_ad_conv_RHF1401_withFilter;
29 END top_ad_conv_RHF1401_withFilter;
30
30
31 ARCHITECTURE ar_top_ad_conv_RHF1401 OF top_ad_conv_RHF1401_withFilter IS
31 ARCHITECTURE ar_top_ad_conv_RHF1401 OF top_ad_conv_RHF1401_withFilter IS
32
32
33 SIGNAL cnv_cycle_counter : INTEGER RANGE 0 TO ncycle_cnv-1;
33 SIGNAL cnv_cycle_counter : INTEGER RANGE 0 TO ncycle_cnv-1;
34 SIGNAL cnv_s : STD_LOGIC;
34 SIGNAL cnv_s : STD_LOGIC;
35 SIGNAL cnv_s_reg : STD_LOGIC;
35 SIGNAL cnv_s_reg : STD_LOGIC;
36 SIGNAL cnv_sync : STD_LOGIC;
36 SIGNAL cnv_sync : STD_LOGIC;
37 SIGNAL cnv_sync_pre : STD_LOGIC;
37 SIGNAL cnv_sync_pre : STD_LOGIC;
38 SIGNAL cnv_sync_falling_edge : STD_LOGIC;
38
39
39 SIGNAL ADC_nOE_reg : STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
40 SIGNAL ADC_nOE_reg : STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
40 SIGNAL enable_ADC : STD_LOGIC;
41 SIGNAL enable_ADC : STD_LOGIC;
42
41
43
42
44 SIGNAL sample_reg : Samples14v(ChanelCount-1 DOWNTO 0);
43 SIGNAL sample_reg : Samples14v(ChanelCount-1 DOWNTO 0);
44
45
45 SIGNAL channel_counter : INTEGER;
46 SIGNAL channel_counter : INTEGER;
46 CONSTANT MAX_COUNTER : INTEGER := ChanelCount*2+1;
47 CONSTANT MAX_COUNTER : INTEGER := ChanelCount*2+1;
47
48
48 SIGNAL ADC_data_selected : Samples14;
49 SIGNAL ADC_data_selected : Samples14;
49 SIGNAL ADC_data_result : Samples15;
50 SIGNAL ADC_data_result : Samples15;
50
51
51 SIGNAL sample_counter : INTEGER;
52 SIGNAL sample_counter : INTEGER;
52 CONSTANT MAX_SAMPLE_COUNTER : INTEGER := 9;
53 CONSTANT MAX_SAMPLE_COUNTER : INTEGER := 9;
53
54
54 CONSTANT FILTER_ENABLED_STDLOGIC : STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(FILTER_ENABLED,ChanelCount));
55 CONSTANT FILTER_ENABLED_STDLOGIC : STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(FILTER_ENABLED, ChanelCount));
55
56
56 BEGIN
57 BEGIN
57
58
58
59
59 -----------------------------------------------------------------------------
60 -----------------------------------------------------------------------------
60 -- CNV GEN
61 -- CNV GEN
61 -----------------------------------------------------------------------------
62 -----------------------------------------------------------------------------
62 PROCESS (cnv_clk, cnv_rstn)
63 PROCESS (cnv_clk, cnv_rstn)
63 BEGIN -- PROCESS
64 BEGIN -- PROCESS
64 IF cnv_rstn = '0' THEN -- asynchronous reset (active low)
65 IF cnv_rstn = '0' THEN -- asynchronous reset (active low)
65 cnv_cycle_counter <= 0;
66 cnv_cycle_counter <= 0;
66 cnv_s <= '0';
67 cnv_s <= '0';
67 ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge
68 ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge
68 IF cnv_cycle_counter < ncycle_cnv-1 THEN
69 IF cnv_cycle_counter < ncycle_cnv-1 THEN
69 cnv_cycle_counter <= cnv_cycle_counter + 1;
70 cnv_cycle_counter <= cnv_cycle_counter + 1;
70 IF cnv_cycle_counter < ncycle_cnv_high THEN
71 IF cnv_cycle_counter < ncycle_cnv_high THEN
71 cnv_s <= '1';
72 cnv_s <= '1';
72 ELSE
73 ELSE
73 cnv_s <= '0';
74 cnv_s <= '0';
74 END IF;
75 END IF;
75 ELSE
76 ELSE
76 cnv_s <= '1';
77 cnv_s <= '1';
77 cnv_cycle_counter <= 0;
78 cnv_cycle_counter <= 0;
78 END IF;
79 END IF;
79 END IF;
80 END IF;
80 END PROCESS;
81 END PROCESS;
81
82
82 cnv <= cnv_s;
83 cnv <= cnv_s;
83
84
84 PROCESS (cnv_clk, cnv_rstn)
85 PROCESS (cnv_clk, cnv_rstn)
85 BEGIN -- PROCESS
86 BEGIN -- PROCESS
86 IF cnv_rstn = '0' THEN -- asynchronous reset (active low)
87 IF cnv_rstn = '0' THEN -- asynchronous reset (active low)
87 cnv_s_reg <= '0';
88 cnv_s_reg <= '0';
88 ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge
89 ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge
89 cnv_s_reg <= cnv_s;
90 cnv_s_reg <= cnv_s;
90 END IF;
91 END IF;
91 END PROCESS;
92 END PROCESS;
92
93
93
94
94 -----------------------------------------------------------------------------
95 -----------------------------------------------------------------------------
95 -- SYNC CNV
96 -- SYNC CNV
96 -----------------------------------------------------------------------------
97 -----------------------------------------------------------------------------
97
98
98 SYNC_FF_cnv : SYNC_FF
99 SYNC_FF_cnv : SYNC_FF
99 GENERIC MAP (
100 GENERIC MAP (
100 NB_FF_OF_SYNC => 2)
101 NB_FF_OF_SYNC => 2)
101 PORT MAP (
102 PORT MAP (
102 clk => clk,
103 clk => clk,
103 rstn => rstn,
104 rstn => rstn,
104 A => cnv_s_reg,
105 A => cnv_s_reg,
105 A_sync => cnv_sync);
106 A_sync => cnv_sync);
106
107
108 cnv_sync_falling_edge <= '1' WHEN cnv_sync = '0' AND cnv_sync_pre = '1' ELSE '0';
107
109
108 -----------------------------------------------------------------------------
110 -----------------------------------------------------------------------------
109 -- DATA GEN Output Enable
111 -- DATA GEN Output Enable
110 -----------------------------------------------------------------------------
112 -----------------------------------------------------------------------------
111 PROCESS (clk, rstn)
113 PROCESS (clk, rstn)
112 BEGIN -- PROCESS
114 BEGIN -- PROCESS
113 IF rstn = '0' THEN -- asynchronous reset (active low)
115 IF rstn = '0' THEN -- asynchronous reset (active low)
114 ADC_nOE_reg(ChanelCount-1 DOWNTO 0) <= (OTHERS => '1');
116 ADC_nOE_reg(ChanelCount-1 DOWNTO 0) <= (OTHERS => '1');
115 cnv_sync_pre <= '0';
117 cnv_sync_pre <= '0';
116 enable_ADC <= '0';
118 enable_ADC <= '0';
117 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
119 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
118 cnv_sync_pre <= cnv_sync;
120 cnv_sync_pre <= cnv_sync;
119 IF cnv_sync = '1' AND cnv_sync_pre = '0' THEN
121 IF cnv_sync_falling_edge = '1' THEN
120 enable_ADC <= '1';
122 enable_ADC <= '1';
121 ADC_nOE_reg(0) <= '0';
123 ADC_nOE_reg(0) <= '0';
122 ADC_nOE_reg(ChanelCount-1 DOWNTO 1) <= (OTHERS => '1');
124 ADC_nOE_reg(ChanelCount-1 DOWNTO 1) <= (OTHERS => '1');
123 ELSE
125 ELSE
124 enable_ADC <= NOT enable_ADC;
126 enable_ADC <= NOT enable_ADC;
125 IF enable_ADC = '0' THEN
127 IF enable_ADC = '0' THEN
126 ADC_nOE_reg(ChanelCount-1 DOWNTO 0) <= ADC_nOE_reg(ChanelCount-2 DOWNTO 0) & '1';
128 ADC_nOE_reg(ChanelCount-1 DOWNTO 0) <= ADC_nOE_reg(ChanelCount-2 DOWNTO 0) & '1';
127 END IF;
129 END IF;
128 END IF;
130 END IF;
129
131
130 END IF;
132 END IF;
131 END PROCESS;
133 END PROCESS;
132
134
133 ADC_nOE <= (OTHERS => '1') WHEN enable_ADC = '0' ELSE ADC_nOE_reg;
135 ADC_nOE <= (OTHERS => '1') WHEN enable_ADC = '0' ELSE ADC_nOE_reg;
134
136
135 -----------------------------------------------------------------------------
137 -----------------------------------------------------------------------------
136 -- ADC READ DATA
138 -- ADC READ DATA
137 -----------------------------------------------------------------------------
139 -----------------------------------------------------------------------------
138 PROCESS (clk, rstn)
140 PROCESS (clk, rstn)
139 BEGIN -- PROCESS
141 BEGIN -- PROCESS
140 IF rstn = '0' THEN -- asynchronous reset (active low)
142 IF rstn = '0' THEN -- asynchronous reset (active low)
141 channel_counter <= MAX_COUNTER;
143 channel_counter <= MAX_COUNTER;
142
144
143 all_sample_reg_init: FOR I IN ChanelCount-1 DOWNTO 0 LOOP
145 all_sample_reg_init : FOR I IN ChanelCount-1 DOWNTO 0 LOOP
144 sample_reg(I) <= (OTHERS => '0');
146 sample_reg(I) <= (OTHERS => '0');
145 END LOOP all_sample_reg_init;
147 END LOOP all_sample_reg_init;
146
148
147 sample_val <= '0';
149 sample_val <= '0';
148 sample_counter <= 0;
150 sample_counter <= 0;
149 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
151 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
150 IF cnv_sync = '1' AND cnv_sync_pre = '0' THEN
152 IF cnv_sync_falling_edge = '1' THEN
151 channel_counter <= 0;
153 channel_counter <= 0;
152 ELSE
154 ELSE
153 IF channel_counter < MAX_COUNTER THEN
155 IF channel_counter < MAX_COUNTER THEN
154 channel_counter <= channel_counter + 1;
156 channel_counter <= channel_counter + 1;
155 END IF;
157 END IF;
156 END IF;
158 END IF;
157 sample_val <= '0';
159 sample_val <= '0';
158
160
159 all_sample_reg: FOR I IN ChanelCount-1 DOWNTO 0 LOOP
161 all_sample_reg : FOR I IN ChanelCount-1 DOWNTO 0 LOOP
160 IF channel_counter = I*2 THEN
162 IF channel_counter = I*2 THEN
161 IF FILTER_ENABLED_STDLOGIC(I) = '1' THEN
163 IF FILTER_ENABLED_STDLOGIC(I) = '1' THEN
162 sample_reg(I) <= ADC_data_result(14 DOWNTO 1);
164 sample_reg(I) <= ADC_data_result(14 DOWNTO 1);
163 ELSE
165 ELSE
164 sample_reg(I) <= ADC_data;
166 sample_reg(I) <= ADC_data;
165 END IF;
167 END IF;
166 END IF;
168 END IF;
167 END LOOP all_sample_reg;
169 END LOOP all_sample_reg;
168
170
169 IF channel_counter = (ChanelCount-1)*2 THEN
171 IF channel_counter = (ChanelCount-1)*2 THEN
170
172
171 IF sample_counter = MAX_SAMPLE_COUNTER THEN
173 IF sample_counter = MAX_SAMPLE_COUNTER THEN
172 sample_counter <= 0 ;
174 sample_counter <= 0;
173 sample_val <= '1';
175 sample_val <= '1';
174 ELSE
176 ELSE
175 sample_counter <= sample_counter +1;
177 sample_counter <= sample_counter +1;
176 END IF;
178 END IF;
177
179
178 END IF;
180 END IF;
179 END IF;
181 END IF;
180 END PROCESS;
182 END PROCESS;
181
183
182 -- mux_adc: PROCESS (sample_reg)-- (channel_counter, sample_reg)
184 -- mux_adc: PROCESS (sample_reg)-- (channel_counter, sample_reg)
183 -- BEGIN -- PROCESS mux_adc
185 -- BEGIN -- PROCESS mux_adc
184 -- CASE channel_counter IS
186 -- CASE channel_counter IS
185 -- WHEN OTHERS => ADC_data_selected <= sample_reg(channel_counter/2);
187 -- WHEN OTHERS => ADC_data_selected <= sample_reg(channel_counter/2);
186 -- END CASE;
188 -- END CASE;
187 -- END PROCESS mux_adc;
189 -- END PROCESS mux_adc;
188
190
189
191
190 -----------------------------------------------------------------------------
192 -----------------------------------------------------------------------------
191 -- \/\/\/\/\/\/\/ TODO : this part is not GENERIC !!! \/\/\/\/\/\/\/
193 -- \/\/\/\/\/\/\/ TODO : this part is not GENERIC !!! \/\/\/\/\/\/\/
192 -----------------------------------------------------------------------------
194 -----------------------------------------------------------------------------
193
195
194 WITH channel_counter SELECT
196 WITH channel_counter SELECT
195 ADC_data_selected <= sample_reg(0) WHEN 0*2,
197 ADC_data_selected <= sample_reg(0) WHEN 0*2,
196 sample_reg(1) WHEN 1*2,
198 sample_reg(1) WHEN 1*2,
197 sample_reg(2) WHEN 2*2,
199 sample_reg(2) WHEN 2*2,
198 sample_reg(3) WHEN 3*2,
200 sample_reg(3) WHEN 3*2,
199 sample_reg(4) WHEN 4*2,
201 sample_reg(4) WHEN 4*2,
200 sample_reg(5) WHEN 5*2,
202 sample_reg(5) WHEN 5*2,
201 sample_reg(6) WHEN 6*2,
203 sample_reg(6) WHEN 6*2,
202 sample_reg(7) WHEN 7*2,
204 sample_reg(7) WHEN 7*2,
203 sample_reg(8) WHEN OTHERS ;
205 sample_reg(8) WHEN OTHERS;
204
206
205 -----------------------------------------------------------------------------
207 -----------------------------------------------------------------------------
206 -- /\/\/\/\/\/\/\ ----------------------------------- /\/\/\/\/\/\/\
208 -- /\/\/\/\/\/\/\ ----------------------------------- /\/\/\/\/\/\/\
207 -----------------------------------------------------------------------------
209 -----------------------------------------------------------------------------
208
210
209 ADC_data_result <= std_logic_vector( (signed( ADC_data_selected(13) & ADC_data_selected) + signed( ADC_data(13) & ADC_data)) );
211 ADC_data_result <= STD_LOGIC_VECTOR((SIGNED(ADC_data_selected(13) & ADC_data_selected) + SIGNED(ADC_data(13) & ADC_data)));
210
212
211 sample <= sample_reg;
213 sample <= sample_reg;
212
214
213 END ar_top_ad_conv_RHF1401;
215 END ar_top_ad_conv_RHF1401;
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