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Issue JIRA : RPWMEB-467...
pellion -
r616:81bdd2b4261c simu_with_Leon3
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@@ -30,28 +30,29 END top_ad_conv_RHF1401_withFilter;
30 30
31 31 ARCHITECTURE ar_top_ad_conv_RHF1401 OF top_ad_conv_RHF1401_withFilter IS
32 32
33 SIGNAL cnv_cycle_counter : INTEGER RANGE 0 TO ncycle_cnv-1;
34 SIGNAL cnv_s : STD_LOGIC;
35 SIGNAL cnv_s_reg : STD_LOGIC;
36 SIGNAL cnv_sync : STD_LOGIC;
37 SIGNAL cnv_sync_pre : STD_LOGIC;
33 SIGNAL cnv_cycle_counter : INTEGER RANGE 0 TO ncycle_cnv-1;
34 SIGNAL cnv_s : STD_LOGIC;
35 SIGNAL cnv_s_reg : STD_LOGIC;
36 SIGNAL cnv_sync : STD_LOGIC;
37 SIGNAL cnv_sync_pre : STD_LOGIC;
38 SIGNAL cnv_sync_falling_edge : STD_LOGIC;
38 39
39 40 SIGNAL ADC_nOE_reg : STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
40 SIGNAL enable_ADC : STD_LOGIC;
41 SIGNAL enable_ADC : STD_LOGIC;
42
41 43
42
43 SIGNAL sample_reg : Samples14v(ChanelCount-1 DOWNTO 0);
44 SIGNAL sample_reg : Samples14v(ChanelCount-1 DOWNTO 0);
44 45
45 SIGNAL channel_counter : INTEGER;
46 CONSTANT MAX_COUNTER : INTEGER := ChanelCount*2+1;
46 SIGNAL channel_counter : INTEGER;
47 CONSTANT MAX_COUNTER : INTEGER := ChanelCount*2+1;
47 48
48 49 SIGNAL ADC_data_selected : Samples14;
49 50 SIGNAL ADC_data_result : Samples15;
50 51
51 SIGNAL sample_counter : INTEGER;
52 SIGNAL sample_counter : INTEGER;
52 53 CONSTANT MAX_SAMPLE_COUNTER : INTEGER := 9;
53 54
54 CONSTANT FILTER_ENABLED_STDLOGIC : STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(FILTER_ENABLED,ChanelCount));
55 CONSTANT FILTER_ENABLED_STDLOGIC : STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(FILTER_ENABLED, ChanelCount));
55 56
56 57 BEGIN
57 58
@@ -80,13 +81,13 BEGIN
80 81 END PROCESS;
81 82
82 83 cnv <= cnv_s;
83
84
84 85 PROCESS (cnv_clk, cnv_rstn)
85 86 BEGIN -- PROCESS
86 87 IF cnv_rstn = '0' THEN -- asynchronous reset (active low)
87 cnv_s_reg <= '0';
88 cnv_s_reg <= '0';
88 89 ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge
89 cnv_s_reg <= cnv_s;
90 cnv_s_reg <= cnv_s;
90 91 END IF;
91 92 END PROCESS;
92 93
@@ -94,7 +95,7 BEGIN
94 95 -----------------------------------------------------------------------------
95 96 -- SYNC CNV
96 97 -----------------------------------------------------------------------------
97
98
98 99 SYNC_FF_cnv : SYNC_FF
99 100 GENERIC MAP (
100 101 NB_FF_OF_SYNC => 2)
@@ -104,6 +105,7 BEGIN
104 105 A => cnv_s_reg,
105 106 A_sync => cnv_sync);
106 107
108 cnv_sync_falling_edge <= '1' WHEN cnv_sync = '0' AND cnv_sync_pre = '1' ELSE '0';
107 109
108 110 -----------------------------------------------------------------------------
109 111 -- DATA GEN Output Enable
@@ -113,12 +115,12 BEGIN
113 115 IF rstn = '0' THEN -- asynchronous reset (active low)
114 116 ADC_nOE_reg(ChanelCount-1 DOWNTO 0) <= (OTHERS => '1');
115 117 cnv_sync_pre <= '0';
116 enable_ADC <= '0';
117 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
118 cnv_sync_pre <= cnv_sync;
119 IF cnv_sync = '1' AND cnv_sync_pre = '0' THEN
120 enable_ADC <= '1';
121 ADC_nOE_reg(0) <= '0';
118 enable_ADC <= '0';
119 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
120 cnv_sync_pre <= cnv_sync;
121 IF cnv_sync_falling_edge = '1' THEN
122 enable_ADC <= '1';
123 ADC_nOE_reg(0) <= '0';
122 124 ADC_nOE_reg(ChanelCount-1 DOWNTO 1) <= (OTHERS => '1');
123 125 ELSE
124 126 enable_ADC <= NOT enable_ADC;
@@ -129,7 +131,7 BEGIN
129 131
130 132 END IF;
131 133 END PROCESS;
132
134
133 135 ADC_nOE <= (OTHERS => '1') WHEN enable_ADC = '0' ELSE ADC_nOE_reg;
134 136
135 137 -----------------------------------------------------------------------------
@@ -140,42 +142,42 BEGIN
140 142 IF rstn = '0' THEN -- asynchronous reset (active low)
141 143 channel_counter <= MAX_COUNTER;
142 144
143 all_sample_reg_init: FOR I IN ChanelCount-1 DOWNTO 0 LOOP
145 all_sample_reg_init : FOR I IN ChanelCount-1 DOWNTO 0 LOOP
144 146 sample_reg(I) <= (OTHERS => '0');
145 147 END LOOP all_sample_reg_init;
146
148
147 149 sample_val <= '0';
148 150 sample_counter <= 0;
149 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
150 IF cnv_sync = '1' AND cnv_sync_pre = '0' THEN
151 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
152 IF cnv_sync_falling_edge = '1' THEN
151 153 channel_counter <= 0;
152 154 ELSE
153 155 IF channel_counter < MAX_COUNTER THEN
154 156 channel_counter <= channel_counter + 1;
155 157 END IF;
156 END IF;
157 sample_val <= '0';
158 END IF;
159 sample_val <= '0';
158 160
159 all_sample_reg: FOR I IN ChanelCount-1 DOWNTO 0 LOOP
161 all_sample_reg : FOR I IN ChanelCount-1 DOWNTO 0 LOOP
160 162 IF channel_counter = I*2 THEN
161 IF FILTER_ENABLED_STDLOGIC(I) = '1' THEN
163 IF FILTER_ENABLED_STDLOGIC(I) = '1' THEN
162 164 sample_reg(I) <= ADC_data_result(14 DOWNTO 1);
163 165 ELSE
164 166 sample_reg(I) <= ADC_data;
165 167 END IF;
166 168 END IF;
167 169 END LOOP all_sample_reg;
168
170
169 171 IF channel_counter = (ChanelCount-1)*2 THEN
170 172
171 173 IF sample_counter = MAX_SAMPLE_COUNTER THEN
172 sample_counter <= 0 ;
174 sample_counter <= 0;
173 175 sample_val <= '1';
174 176 ELSE
175 177 sample_counter <= sample_counter +1;
176 178 END IF;
177 179
178 END IF;
180 END IF;
179 181 END IF;
180 182 END PROCESS;
181 183
@@ -186,27 +188,27 BEGIN
186 188 -- END CASE;
187 189 -- END PROCESS mux_adc;
188 190
189
190 -----------------------------------------------------------------------------
191
192 -----------------------------------------------------------------------------
191 193 -- \/\/\/\/\/\/\/ TODO : this part is not GENERIC !!! \/\/\/\/\/\/\/
192 194 -----------------------------------------------------------------------------
193 195
194 196 WITH channel_counter SELECT
195 197 ADC_data_selected <= sample_reg(0) WHEN 0*2,
196 sample_reg(1) WHEN 1*2,
197 sample_reg(2) WHEN 2*2,
198 sample_reg(3) WHEN 3*2,
199 sample_reg(4) WHEN 4*2,
200 sample_reg(5) WHEN 5*2,
201 sample_reg(6) WHEN 6*2,
202 sample_reg(7) WHEN 7*2,
203 sample_reg(8) WHEN OTHERS ;
204
198 sample_reg(1) WHEN 1*2,
199 sample_reg(2) WHEN 2*2,
200 sample_reg(3) WHEN 3*2,
201 sample_reg(4) WHEN 4*2,
202 sample_reg(5) WHEN 5*2,
203 sample_reg(6) WHEN 6*2,
204 sample_reg(7) WHEN 7*2,
205 sample_reg(8) WHEN OTHERS;
206
205 207 -----------------------------------------------------------------------------
206 208 -- /\/\/\/\/\/\/\ ----------------------------------- /\/\/\/\/\/\/\
207 209 -----------------------------------------------------------------------------
208 210
209 ADC_data_result <= std_logic_vector( (signed( ADC_data_selected(13) & ADC_data_selected) + signed( ADC_data(13) & ADC_data)) );
211 ADC_data_result <= STD_LOGIC_VECTOR((SIGNED(ADC_data_selected(13) & ADC_data_selected) + SIGNED(ADC_data(13) & ADC_data)));
210 212
211 213 sample <= sample_reg;
212 214
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