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Correction de la FSM qui regule les données entrant dans la FFT
pellion -
r557:7faec0eb9fbb (MINI-LFR) WFP_MS-0-1-67 (LFR-EM) WFP_MS_1-1-67 JC
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1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
29 USE techmap.gencomp.ALL;
30 LIBRARY gaisler;
30 LIBRARY gaisler;
31 USE gaisler.memctrl.ALL;
31 USE gaisler.memctrl.ALL;
32 USE gaisler.leon3.ALL;
32 USE gaisler.leon3.ALL;
33 USE gaisler.uart.ALL;
33 USE gaisler.uart.ALL;
34 USE gaisler.misc.ALL;
34 USE gaisler.misc.ALL;
35 USE gaisler.spacewire.ALL;
35 USE gaisler.spacewire.ALL;
36 LIBRARY esa;
36 LIBRARY esa;
37 USE esa.memoryctrl.ALL;
37 USE esa.memoryctrl.ALL;
38 LIBRARY lpp;
38 LIBRARY lpp;
39 USE lpp.lpp_memory.ALL;
39 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_ad_conv.ALL;
40 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 USE lpp.iir_filter.ALL;
43 USE lpp.iir_filter.ALL;
44 USE lpp.general_purpose.ALL;
44 USE lpp.general_purpose.ALL;
45 USE lpp.lpp_lfr_management.ALL;
45 USE lpp.lpp_lfr_management.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
47
47
48 ENTITY LFR_em IS
48 ENTITY LFR_em IS
49
49
50 PORT (
50 PORT (
51 clk100MHz : IN STD_ULOGIC;
51 clk100MHz : IN STD_ULOGIC;
52 clk49_152MHz : IN STD_ULOGIC;
52 clk49_152MHz : IN STD_ULOGIC;
53 reset : IN STD_ULOGIC;
53 reset : IN STD_ULOGIC;
54
54
55 -- TAG --------------------------------------------------------------------
55 -- TAG --------------------------------------------------------------------
56 TAG1 : IN STD_ULOGIC; -- DSU rx data
56 TAG1 : IN STD_ULOGIC; -- DSU rx data
57 TAG3 : OUT STD_ULOGIC; -- DSU tx data
57 TAG3 : OUT STD_ULOGIC; -- DSU tx data
58 -- UART APB ---------------------------------------------------------------
58 -- UART APB ---------------------------------------------------------------
59 TAG2 : IN STD_ULOGIC; -- UART1 rx data
59 TAG2 : IN STD_ULOGIC; -- UART1 rx data
60 TAG4 : OUT STD_ULOGIC; -- UART1 tx data
60 TAG4 : OUT STD_ULOGIC; -- UART1 tx data
61 -- RAM --------------------------------------------------------------------
61 -- RAM --------------------------------------------------------------------
62 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
62 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
63 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
63 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
64 nSRAM_BE0 : OUT STD_LOGIC;
64 nSRAM_BE0 : OUT STD_LOGIC;
65 nSRAM_BE1 : OUT STD_LOGIC;
65 nSRAM_BE1 : OUT STD_LOGIC;
66 nSRAM_BE2 : OUT STD_LOGIC;
66 nSRAM_BE2 : OUT STD_LOGIC;
67 nSRAM_BE3 : OUT STD_LOGIC;
67 nSRAM_BE3 : OUT STD_LOGIC;
68 nSRAM_WE : OUT STD_LOGIC;
68 nSRAM_WE : OUT STD_LOGIC;
69 nSRAM_CE : OUT STD_LOGIC;
69 nSRAM_CE : OUT STD_LOGIC;
70 nSRAM_OE : OUT STD_LOGIC;
70 nSRAM_OE : OUT STD_LOGIC;
71 -- SPW --------------------------------------------------------------------
71 -- SPW --------------------------------------------------------------------
72 spw1_din : IN STD_LOGIC;
72 spw1_din : IN STD_LOGIC;
73 spw1_sin : IN STD_LOGIC;
73 spw1_sin : IN STD_LOGIC;
74 spw1_dout : OUT STD_LOGIC;
74 spw1_dout : OUT STD_LOGIC;
75 spw1_sout : OUT STD_LOGIC;
75 spw1_sout : OUT STD_LOGIC;
76 spw2_din : IN STD_LOGIC;
76 spw2_din : IN STD_LOGIC;
77 spw2_sin : IN STD_LOGIC;
77 spw2_sin : IN STD_LOGIC;
78 spw2_dout : OUT STD_LOGIC;
78 spw2_dout : OUT STD_LOGIC;
79 spw2_sout : OUT STD_LOGIC;
79 spw2_sout : OUT STD_LOGIC;
80 -- ADC --------------------------------------------------------------------
80 -- ADC --------------------------------------------------------------------
81 bias_fail_sw : OUT STD_LOGIC;
81 bias_fail_sw : OUT STD_LOGIC;
82 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
82 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
83 ADC_smpclk : OUT STD_LOGIC;
83 ADC_smpclk : OUT STD_LOGIC;
84 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
84 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
85 -- DAC --------------------------------------------------------------------
85 -- DAC --------------------------------------------------------------------
86 DAC_SDO : OUT STD_LOGIC;
86 DAC_SDO : OUT STD_LOGIC;
87 DAC_SCK : OUT STD_LOGIC;
87 DAC_SCK : OUT STD_LOGIC;
88 DAC_SYNC : OUT STD_LOGIC;
88 DAC_SYNC : OUT STD_LOGIC;
89 DAC_CAL_EN : OUT STD_LOGIC;
89 DAC_CAL_EN : OUT STD_LOGIC;
90 -- HK ---------------------------------------------------------------------
90 -- HK ---------------------------------------------------------------------
91 HK_smpclk : OUT STD_LOGIC;
91 HK_smpclk : OUT STD_LOGIC;
92 ADC_OEB_bar_HK : OUT STD_LOGIC;
92 ADC_OEB_bar_HK : OUT STD_LOGIC;
93 HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
93 HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
94 ---------------------------------------------------------------------------
94 ---------------------------------------------------------------------------
95 TAG8 : OUT STD_LOGIC;
95 TAG8 : OUT STD_LOGIC;
96 led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
96 led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
97 );
97 );
98
98
99 END LFR_em;
99 END LFR_em;
100
100
101
101
102 ARCHITECTURE beh OF LFR_em IS
102 ARCHITECTURE beh OF LFR_em IS
103 SIGNAL clk_50_s : STD_LOGIC := '0';
103 SIGNAL clk_50_s : STD_LOGIC := '0';
104 SIGNAL clk_25 : STD_LOGIC := '0';
104 SIGNAL clk_25 : STD_LOGIC := '0';
105 SIGNAL clk_24 : STD_LOGIC := '0';
105 SIGNAL clk_24 : STD_LOGIC := '0';
106 -----------------------------------------------------------------------------
106 -----------------------------------------------------------------------------
107 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
107 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
108 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
108 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
109
109
110 -- CONSTANTS
110 -- CONSTANTS
111 CONSTANT CFG_PADTECH : INTEGER := inferred;
111 CONSTANT CFG_PADTECH : INTEGER := inferred;
112 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
112 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
113 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
113 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
114 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
114 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
115
115
116 SIGNAL apbi_ext : apb_slv_in_type;
116 SIGNAL apbi_ext : apb_slv_in_type;
117 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
117 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
118 SIGNAL ahbi_s_ext : ahb_slv_in_type;
118 SIGNAL ahbi_s_ext : ahb_slv_in_type;
119 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
119 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
120 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
120 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
121 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
121 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
122
122
123 -- Spacewire signals
123 -- Spacewire signals
124 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
124 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
125 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
125 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
126 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
126 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
127 SIGNAL spw_rxtxclk : STD_ULOGIC;
127 SIGNAL spw_rxtxclk : STD_ULOGIC;
128 SIGNAL spw_rxclkn : STD_ULOGIC;
128 SIGNAL spw_rxclkn : STD_ULOGIC;
129 SIGNAL spw_clk : STD_LOGIC;
129 SIGNAL spw_clk : STD_LOGIC;
130 SIGNAL swni : grspw_in_type;
130 SIGNAL swni : grspw_in_type;
131 SIGNAL swno : grspw_out_type;
131 SIGNAL swno : grspw_out_type;
132
132
133 --GPIO
133 --GPIO
134 SIGNAL gpioi : gpio_in_type;
134 SIGNAL gpioi : gpio_in_type;
135 SIGNAL gpioo : gpio_out_type;
135 SIGNAL gpioo : gpio_out_type;
136
136
137 -- AD Converter ADS7886
137 -- AD Converter ADS7886
138 SIGNAL sample : Samples14v(8 DOWNTO 0);
138 SIGNAL sample : Samples14v(8 DOWNTO 0);
139 SIGNAL sample_s : Samples(8 DOWNTO 0);
139 SIGNAL sample_s : Samples(8 DOWNTO 0);
140 SIGNAL sample_val : STD_LOGIC;
140 SIGNAL sample_val : STD_LOGIC;
141 SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0);
141 SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0);
142
142
143 -----------------------------------------------------------------------------
143 -----------------------------------------------------------------------------
144 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
144 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
145
145
146 -----------------------------------------------------------------------------
146 -----------------------------------------------------------------------------
147 SIGNAL rstn : STD_LOGIC;
147 SIGNAL rstn : STD_LOGIC;
148
148
149 SIGNAL LFR_soft_rstn : STD_LOGIC;
149 SIGNAL LFR_soft_rstn : STD_LOGIC;
150 SIGNAL LFR_rstn : STD_LOGIC;
150 SIGNAL LFR_rstn : STD_LOGIC;
151
151
152 SIGNAL ADC_smpclk_s : STD_LOGIC;
152 SIGNAL ADC_smpclk_s : STD_LOGIC;
153 -----------------------------------------------------------------------------
153 -----------------------------------------------------------------------------
154 SIGNAL nSRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
154 SIGNAL nSRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
155
155
156 BEGIN -- beh
156 BEGIN -- beh
157
157
158 -----------------------------------------------------------------------------
158 -----------------------------------------------------------------------------
159 -- CLK
159 -- CLK
160 -----------------------------------------------------------------------------
160 -----------------------------------------------------------------------------
161 rst0 : rstgen PORT MAP (reset, clk_25, '1', rstn, OPEN);
161 rst0 : rstgen PORT MAP (reset, clk_25, '1', rstn, OPEN);
162
162
163 PROCESS(clk100MHz)
163 PROCESS(clk100MHz)
164 BEGIN
164 BEGIN
165 IF clk100MHz'EVENT AND clk100MHz = '1' THEN
165 IF clk100MHz'EVENT AND clk100MHz = '1' THEN
166 clk_50_s <= NOT clk_50_s;
166 clk_50_s <= NOT clk_50_s;
167 END IF;
167 END IF;
168 END PROCESS;
168 END PROCESS;
169
169
170 PROCESS(clk_50_s)
170 PROCESS(clk_50_s)
171 BEGIN
171 BEGIN
172 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
172 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
173 clk_25 <= NOT clk_25;
173 clk_25 <= NOT clk_25;
174 END IF;
174 END IF;
175 END PROCESS;
175 END PROCESS;
176
176
177 PROCESS(clk49_152MHz)
177 PROCESS(clk49_152MHz)
178 BEGIN
178 BEGIN
179 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
179 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
180 clk_24 <= NOT clk_24;
180 clk_24 <= NOT clk_24;
181 END IF;
181 END IF;
182 END PROCESS;
182 END PROCESS;
183
183
184 -----------------------------------------------------------------------------
184 -----------------------------------------------------------------------------
185
185
186 PROCESS (clk_25, rstn)
186 PROCESS (clk_25, rstn)
187 BEGIN -- PROCESS
187 BEGIN -- PROCESS
188 IF rstn = '0' THEN -- asynchronous reset (active low)
188 IF rstn = '0' THEN -- asynchronous reset (active low)
189 led(0) <= '0';
189 led(0) <= '0';
190 led(1) <= '0';
190 led(1) <= '0';
191 led(2) <= '0';
191 led(2) <= '0';
192 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
192 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
193 led(0) <= '0';
193 led(0) <= '0';
194 led(1) <= '1';
194 led(1) <= '1';
195 led(2) <= '1';
195 led(2) <= '1';
196 END IF;
196 END IF;
197 END PROCESS;
197 END PROCESS;
198
198
199 --
199 --
200 leon3_soc_1 : leon3_soc
200 leon3_soc_1 : leon3_soc
201 GENERIC MAP (
201 GENERIC MAP (
202 fabtech => apa3e,
202 fabtech => apa3e,
203 memtech => apa3e,
203 memtech => apa3e,
204 padtech => inferred,
204 padtech => inferred,
205 clktech => inferred,
205 clktech => inferred,
206 disas => 0,
206 disas => 0,
207 dbguart => 0,
207 dbguart => 0,
208 pclow => 2,
208 pclow => 2,
209 clk_freq => 25000,
209 clk_freq => 25000,
210 IS_RADHARD => 0,
210 IS_RADHARD => 0,
211 NB_CPU => 1,
211 NB_CPU => 1,
212 ENABLE_FPU => 1,
212 ENABLE_FPU => 1,
213 FPU_NETLIST => 0,
213 FPU_NETLIST => 0,
214 ENABLE_DSU => 1,
214 ENABLE_DSU => 1,
215 ENABLE_AHB_UART => 1,
215 ENABLE_AHB_UART => 1,
216 ENABLE_APB_UART => 1,
216 ENABLE_APB_UART => 1,
217 ENABLE_IRQMP => 1,
217 ENABLE_IRQMP => 1,
218 ENABLE_GPT => 1,
218 ENABLE_GPT => 1,
219 NB_AHB_MASTER => NB_AHB_MASTER,
219 NB_AHB_MASTER => NB_AHB_MASTER,
220 NB_AHB_SLAVE => NB_AHB_SLAVE,
220 NB_AHB_SLAVE => NB_AHB_SLAVE,
221 NB_APB_SLAVE => NB_APB_SLAVE,
221 NB_APB_SLAVE => NB_APB_SLAVE,
222 ADDRESS_SIZE => 20,
222 ADDRESS_SIZE => 20,
223 USES_IAP_MEMCTRLR => 0)
223 USES_IAP_MEMCTRLR => 0)
224 PORT MAP (
224 PORT MAP (
225 clk => clk_25,
225 clk => clk_25,
226 reset => rstn,
226 reset => rstn,
227 errorn => OPEN,
227 errorn => OPEN,
228
228
229 ahbrxd => TAG1,
229 ahbrxd => TAG1,
230 ahbtxd => TAG3,
230 ahbtxd => TAG3,
231 urxd1 => TAG2,
231 urxd1 => TAG2,
232 utxd1 => TAG4,
232 utxd1 => TAG4,
233
233
234 address => address,
234 address => address,
235 data => data,
235 data => data,
236 nSRAM_BE0 => nSRAM_BE0,
236 nSRAM_BE0 => nSRAM_BE0,
237 nSRAM_BE1 => nSRAM_BE1,
237 nSRAM_BE1 => nSRAM_BE1,
238 nSRAM_BE2 => nSRAM_BE2,
238 nSRAM_BE2 => nSRAM_BE2,
239 nSRAM_BE3 => nSRAM_BE3,
239 nSRAM_BE3 => nSRAM_BE3,
240 nSRAM_WE => nSRAM_WE,
240 nSRAM_WE => nSRAM_WE,
241 nSRAM_CE => nSRAM_CE_s,
241 nSRAM_CE => nSRAM_CE_s,
242 nSRAM_OE => nSRAM_OE,
242 nSRAM_OE => nSRAM_OE,
243 nSRAM_READY => '0',
243 nSRAM_READY => '0',
244 SRAM_MBE => OPEN,
244 SRAM_MBE => OPEN,
245
245
246 apbi_ext => apbi_ext,
246 apbi_ext => apbi_ext,
247 apbo_ext => apbo_ext,
247 apbo_ext => apbo_ext,
248 ahbi_s_ext => ahbi_s_ext,
248 ahbi_s_ext => ahbi_s_ext,
249 ahbo_s_ext => ahbo_s_ext,
249 ahbo_s_ext => ahbo_s_ext,
250 ahbi_m_ext => ahbi_m_ext,
250 ahbi_m_ext => ahbi_m_ext,
251 ahbo_m_ext => ahbo_m_ext);
251 ahbo_m_ext => ahbo_m_ext);
252
252
253
253
254 nSRAM_CE <= nSRAM_CE_s(0);
254 nSRAM_CE <= nSRAM_CE_s(0);
255
255
256 -------------------------------------------------------------------------------
256 -------------------------------------------------------------------------------
257 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
257 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
258 -------------------------------------------------------------------------------
258 -------------------------------------------------------------------------------
259 apb_lfr_management_1 : apb_lfr_management
259 apb_lfr_management_1 : apb_lfr_management
260 GENERIC MAP (
260 GENERIC MAP (
261 tech => apa3e,
261 tech => apa3e,
262 pindex => 6,
262 pindex => 6,
263 paddr => 6,
263 paddr => 6,
264 pmask => 16#fff#,
264 pmask => 16#fff#,
265 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
265 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
266 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
266 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
267 PORT MAP (
267 PORT MAP (
268 clk25MHz => clk_25,
268 clk25MHz => clk_25,
269 clk24_576MHz => clk_24, -- 49.152MHz/2
269 clk24_576MHz => clk_24, -- 49.152MHz/2
270 resetn => rstn,
270 resetn => rstn,
271 grspw_tick => swno.tickout,
271 grspw_tick => swno.tickout,
272 apbi => apbi_ext,
272 apbi => apbi_ext,
273 apbo => apbo_ext(6),
273 apbo => apbo_ext(6),
274
274
275 HK_sample => sample_s(8),
275 HK_sample => sample_s(8),
276 HK_val => sample_val,
276 HK_val => sample_val,
277 HK_sel => HK_SEL,
277 HK_sel => HK_SEL,
278
278
279 DAC_SDO => DAC_SDO,
279 DAC_SDO => DAC_SDO,
280 DAC_SCK => DAC_SCK,
280 DAC_SCK => DAC_SCK,
281 DAC_SYNC => DAC_SYNC,
281 DAC_SYNC => DAC_SYNC,
282 DAC_CAL_EN => DAC_CAL_EN,
282 DAC_CAL_EN => DAC_CAL_EN,
283
283
284 coarse_time => coarse_time,
284 coarse_time => coarse_time,
285 fine_time => fine_time,
285 fine_time => fine_time,
286 LFR_soft_rstn => LFR_soft_rstn
286 LFR_soft_rstn => LFR_soft_rstn
287 );
287 );
288
288
289 -----------------------------------------------------------------------
289 -----------------------------------------------------------------------
290 --- SpaceWire --------------------------------------------------------
290 --- SpaceWire --------------------------------------------------------
291 -----------------------------------------------------------------------
291 -----------------------------------------------------------------------
292
292
293 -- SPW_EN <= '1';
293 -- SPW_EN <= '1';
294
294
295 spw_clk <= clk_50_s;
295 spw_clk <= clk_50_s;
296 spw_rxtxclk <= spw_clk;
296 spw_rxtxclk <= spw_clk;
297 spw_rxclkn <= NOT spw_rxtxclk;
297 spw_rxclkn <= NOT spw_rxtxclk;
298
298
299 -- PADS for SPW1
299 -- PADS for SPW1
300 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
300 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
301 PORT MAP (spw1_din, dtmp(0));
301 PORT MAP (spw1_din, dtmp(0));
302 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
302 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
303 PORT MAP (spw1_sin, stmp(0));
303 PORT MAP (spw1_sin, stmp(0));
304 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
304 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
305 PORT MAP (spw1_dout, swno.d(0));
305 PORT MAP (spw1_dout, swno.d(0));
306 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
306 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
307 PORT MAP (spw1_sout, swno.s(0));
307 PORT MAP (spw1_sout, swno.s(0));
308 -- PADS FOR SPW2
308 -- PADS FOR SPW2
309 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
309 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
310 PORT MAP (spw2_din, dtmp(1));
310 PORT MAP (spw2_din, dtmp(1));
311 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
311 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
312 PORT MAP (spw2_sin, stmp(1));
312 PORT MAP (spw2_sin, stmp(1));
313 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
313 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
314 PORT MAP (spw2_dout, swno.d(1));
314 PORT MAP (spw2_dout, swno.d(1));
315 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
315 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
316 PORT MAP (spw2_sout, swno.s(1));
316 PORT MAP (spw2_sout, swno.s(1));
317
317
318 -- GRSPW PHY
318 -- GRSPW PHY
319 --spw1_input: if CFG_SPW_GRSPW = 1 generate
319 --spw1_input: if CFG_SPW_GRSPW = 1 generate
320 spw_inputloop : FOR j IN 0 TO 1 GENERATE
320 spw_inputloop : FOR j IN 0 TO 1 GENERATE
321 spw_phy0 : grspw_phy
321 spw_phy0 : grspw_phy
322 GENERIC MAP(
322 GENERIC MAP(
323 tech => apa3e,
323 tech => apa3e,
324 rxclkbuftype => 1,
324 rxclkbuftype => 1,
325 scantest => 0)
325 scantest => 0)
326 PORT MAP(
326 PORT MAP(
327 rxrst => swno.rxrst,
327 rxrst => swno.rxrst,
328 di => dtmp(j),
328 di => dtmp(j),
329 si => stmp(j),
329 si => stmp(j),
330 rxclko => spw_rxclk(j),
330 rxclko => spw_rxclk(j),
331 do => swni.d(j),
331 do => swni.d(j),
332 ndo => swni.nd(j*5+4 DOWNTO j*5),
332 ndo => swni.nd(j*5+4 DOWNTO j*5),
333 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
333 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
334 END GENERATE spw_inputloop;
334 END GENERATE spw_inputloop;
335
335
336 -- SPW core
336 -- SPW core
337 sw0 : grspwm GENERIC MAP(
337 sw0 : grspwm GENERIC MAP(
338 tech => apa3e,
338 tech => apa3e,
339 hindex => 1,
339 hindex => 1,
340 pindex => 5,
340 pindex => 5,
341 paddr => 5,
341 paddr => 5,
342 pirq => 11,
342 pirq => 11,
343 sysfreq => 25000, -- CPU_FREQ
343 sysfreq => 25000, -- CPU_FREQ
344 rmap => 1,
344 rmap => 1,
345 rmapcrc => 1,
345 rmapcrc => 1,
346 fifosize1 => 16,
346 fifosize1 => 16,
347 fifosize2 => 16,
347 fifosize2 => 16,
348 rxclkbuftype => 1,
348 rxclkbuftype => 1,
349 rxunaligned => 0,
349 rxunaligned => 0,
350 rmapbufs => 4,
350 rmapbufs => 4,
351 ft => 0,
351 ft => 0,
352 netlist => 0,
352 netlist => 0,
353 ports => 2,
353 ports => 2,
354 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
354 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
355 memtech => apa3e,
355 memtech => apa3e,
356 destkey => 2,
356 destkey => 2,
357 spwcore => 1
357 spwcore => 1
358 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
358 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
359 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
359 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
360 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
360 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
361 )
361 )
362 PORT MAP(rstn, clk_25, spw_rxclk(0),
362 PORT MAP(rstn, clk_25, spw_rxclk(0),
363 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
363 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
364 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
364 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
365 swni, swno);
365 swni, swno);
366
366
367 swni.tickin <= '0';
367 swni.tickin <= '0';
368 swni.rmapen <= '1';
368 swni.rmapen <= '1';
369 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
369 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
370 swni.tickinraw <= '0';
370 swni.tickinraw <= '0';
371 swni.timein <= (OTHERS => '0');
371 swni.timein <= (OTHERS => '0');
372 swni.dcrstval <= (OTHERS => '0');
372 swni.dcrstval <= (OTHERS => '0');
373 swni.timerrstval <= (OTHERS => '0');
373 swni.timerrstval <= (OTHERS => '0');
374
374
375 -------------------------------------------------------------------------------
375 -------------------------------------------------------------------------------
376 -- LFR ------------------------------------------------------------------------
376 -- LFR ------------------------------------------------------------------------
377 -------------------------------------------------------------------------------
377 -------------------------------------------------------------------------------
378 LFR_rstn <= LFR_soft_rstn AND rstn;
378 LFR_rstn <= LFR_soft_rstn AND rstn;
379
379
380 lpp_lfr_1 : lpp_lfr
380 lpp_lfr_1 : lpp_lfr
381 GENERIC MAP (
381 GENERIC MAP (
382 Mem_use => use_RAM,
382 Mem_use => use_RAM,
383 nb_data_by_buffer_size => 32,
383 nb_data_by_buffer_size => 32,
384 --nb_word_by_buffer_size => 30,
384 --nb_word_by_buffer_size => 30,
385 nb_snapshot_param_size => 32,
385 nb_snapshot_param_size => 32,
386 delta_vector_size => 32,
386 delta_vector_size => 32,
387 delta_vector_size_f0_2 => 7, -- log2(96)
387 delta_vector_size_f0_2 => 7, -- log2(96)
388 pindex => 15,
388 pindex => 15,
389 paddr => 15,
389 paddr => 15,
390 pmask => 16#fff#,
390 pmask => 16#fff#,
391 pirq_ms => 6,
391 pirq_ms => 6,
392 pirq_wfp => 14,
392 pirq_wfp => 14,
393 hindex => 2,
393 hindex => 2,
394 top_lfr_version => X"010140") -- aa.bb.cc version
394 top_lfr_version => X"010143") -- aa.bb.cc version
395 -- AA : BOARD NUMBER
395 -- AA : BOARD NUMBER
396 -- 0 => MINI_LFR
396 -- 0 => MINI_LFR
397 -- 1 => EM
397 -- 1 => EM
398 PORT MAP (
398 PORT MAP (
399 clk => clk_25,
399 clk => clk_25,
400 rstn => LFR_rstn,
400 rstn => LFR_rstn,
401 sample_B => sample_s(2 DOWNTO 0),
401 sample_B => sample_s(2 DOWNTO 0),
402 sample_E => sample_s(7 DOWNTO 3),
402 sample_E => sample_s(7 DOWNTO 3),
403 sample_val => sample_val,
403 sample_val => sample_val,
404 apbi => apbi_ext,
404 apbi => apbi_ext,
405 apbo => apbo_ext(15),
405 apbo => apbo_ext(15),
406 ahbi => ahbi_m_ext,
406 ahbi => ahbi_m_ext,
407 ahbo => ahbo_m_ext(2),
407 ahbo => ahbo_m_ext(2),
408 coarse_time => coarse_time,
408 coarse_time => coarse_time,
409 fine_time => fine_time,
409 fine_time => fine_time,
410 data_shaping_BW => bias_fail_sw,
410 data_shaping_BW => bias_fail_sw,
411 debug_vector => OPEN,
411 debug_vector => OPEN,
412 debug_vector_ms => OPEN); --,
412 debug_vector_ms => OPEN); --,
413 --observation_vector_0 => OPEN,
413 --observation_vector_0 => OPEN,
414 --observation_vector_1 => OPEN,
414 --observation_vector_1 => OPEN,
415 --observation_reg => observation_reg);
415 --observation_reg => observation_reg);
416
416
417
417
418 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
418 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
419 sample_s(I) <= sample(I) & '0' & '0';
419 sample_s(I) <= sample(I) & '0' & '0';
420 END GENERATE all_sample;
420 END GENERATE all_sample;
421 sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8);
421 sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8);
422
422
423 -----------------------------------------------------------------------------
423 -----------------------------------------------------------------------------
424 --
424 --
425 -----------------------------------------------------------------------------
425 -----------------------------------------------------------------------------
426 top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
426 top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
427 GENERIC MAP (
427 GENERIC MAP (
428 ChanelCount => 9,
428 ChanelCount => 9,
429 ncycle_cnv_high => 13,
429 ncycle_cnv_high => 13,
430 ncycle_cnv => 25,
430 ncycle_cnv => 25,
431 FILTER_ENABLED => 16#FF#)
431 FILTER_ENABLED => 16#FF#)
432 PORT MAP (
432 PORT MAP (
433 cnv_clk => clk_24,
433 cnv_clk => clk_24,
434 cnv_rstn => rstn,
434 cnv_rstn => rstn,
435 cnv => ADC_smpclk_s,
435 cnv => ADC_smpclk_s,
436 clk => clk_25,
436 clk => clk_25,
437 rstn => rstn,
437 rstn => rstn,
438 ADC_data => ADC_data,
438 ADC_data => ADC_data,
439 ADC_nOE => ADC_OEB_bar_CH_s,
439 ADC_nOE => ADC_OEB_bar_CH_s,
440 sample => sample,
440 sample => sample,
441 sample_val => sample_val);
441 sample_val => sample_val);
442
442
443 ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0);
443 ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0);
444
444
445 ADC_smpclk <= ADC_smpclk_s;
445 ADC_smpclk <= ADC_smpclk_s;
446 HK_smpclk <= ADC_smpclk_s;
446 HK_smpclk <= ADC_smpclk_s;
447
447
448 TAG8 <= ADC_smpclk_s;
448 TAG8 <= ADC_smpclk_s;
449
449
450 -----------------------------------------------------------------------------
450 -----------------------------------------------------------------------------
451 -- HK
451 -- HK
452 -----------------------------------------------------------------------------
452 -----------------------------------------------------------------------------
453 ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8);
453 ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8);
454
454
455 END beh;
455 END beh;
Show file before | Show file after | Hide comments
@@ -1,737 +1,737
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
29 USE techmap.gencomp.ALL;
30 LIBRARY gaisler;
30 LIBRARY gaisler;
31 USE gaisler.memctrl.ALL;
31 USE gaisler.memctrl.ALL;
32 USE gaisler.leon3.ALL;
32 USE gaisler.leon3.ALL;
33 USE gaisler.uart.ALL;
33 USE gaisler.uart.ALL;
34 USE gaisler.misc.ALL;
34 USE gaisler.misc.ALL;
35 USE gaisler.spacewire.ALL;
35 USE gaisler.spacewire.ALL;
36 LIBRARY esa;
36 LIBRARY esa;
37 USE esa.memoryctrl.ALL;
37 USE esa.memoryctrl.ALL;
38 LIBRARY lpp;
38 LIBRARY lpp;
39 USE lpp.lpp_memory.ALL;
39 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_ad_conv.ALL;
40 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 USE lpp.iir_filter.ALL;
43 USE lpp.iir_filter.ALL;
44 USE lpp.general_purpose.ALL;
44 USE lpp.general_purpose.ALL;
45 USE lpp.lpp_lfr_management.ALL;
45 USE lpp.lpp_lfr_management.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
47
47
48 ENTITY MINI_LFR_top IS
48 ENTITY MINI_LFR_top IS
49
49
50 PORT (
50 PORT (
51 clk_50 : IN STD_LOGIC;
51 clk_50 : IN STD_LOGIC;
52 clk_49 : IN STD_LOGIC;
52 clk_49 : IN STD_LOGIC;
53 reset : IN STD_LOGIC;
53 reset : IN STD_LOGIC;
54 --BPs
54 --BPs
55 BP0 : IN STD_LOGIC;
55 BP0 : IN STD_LOGIC;
56 BP1 : IN STD_LOGIC;
56 BP1 : IN STD_LOGIC;
57 --LEDs
57 --LEDs
58 LED0 : OUT STD_LOGIC;
58 LED0 : OUT STD_LOGIC;
59 LED1 : OUT STD_LOGIC;
59 LED1 : OUT STD_LOGIC;
60 LED2 : OUT STD_LOGIC;
60 LED2 : OUT STD_LOGIC;
61 --UARTs
61 --UARTs
62 TXD1 : IN STD_LOGIC;
62 TXD1 : IN STD_LOGIC;
63 RXD1 : OUT STD_LOGIC;
63 RXD1 : OUT STD_LOGIC;
64 nCTS1 : OUT STD_LOGIC;
64 nCTS1 : OUT STD_LOGIC;
65 nRTS1 : IN STD_LOGIC;
65 nRTS1 : IN STD_LOGIC;
66
66
67 TXD2 : IN STD_LOGIC;
67 TXD2 : IN STD_LOGIC;
68 RXD2 : OUT STD_LOGIC;
68 RXD2 : OUT STD_LOGIC;
69 nCTS2 : OUT STD_LOGIC;
69 nCTS2 : OUT STD_LOGIC;
70 nDTR2 : IN STD_LOGIC;
70 nDTR2 : IN STD_LOGIC;
71 nRTS2 : IN STD_LOGIC;
71 nRTS2 : IN STD_LOGIC;
72 nDCD2 : OUT STD_LOGIC;
72 nDCD2 : OUT STD_LOGIC;
73
73
74 --EXT CONNECTOR
74 --EXT CONNECTOR
75 IO0 : INOUT STD_LOGIC;
75 IO0 : INOUT STD_LOGIC;
76 IO1 : INOUT STD_LOGIC;
76 IO1 : INOUT STD_LOGIC;
77 IO2 : INOUT STD_LOGIC;
77 IO2 : INOUT STD_LOGIC;
78 IO3 : INOUT STD_LOGIC;
78 IO3 : INOUT STD_LOGIC;
79 IO4 : INOUT STD_LOGIC;
79 IO4 : INOUT STD_LOGIC;
80 IO5 : INOUT STD_LOGIC;
80 IO5 : INOUT STD_LOGIC;
81 IO6 : INOUT STD_LOGIC;
81 IO6 : INOUT STD_LOGIC;
82 IO7 : INOUT STD_LOGIC;
82 IO7 : INOUT STD_LOGIC;
83 IO8 : INOUT STD_LOGIC;
83 IO8 : INOUT STD_LOGIC;
84 IO9 : INOUT STD_LOGIC;
84 IO9 : INOUT STD_LOGIC;
85 IO10 : INOUT STD_LOGIC;
85 IO10 : INOUT STD_LOGIC;
86 IO11 : INOUT STD_LOGIC;
86 IO11 : INOUT STD_LOGIC;
87
87
88 --SPACE WIRE
88 --SPACE WIRE
89 SPW_EN : OUT STD_LOGIC; -- 0 => off
89 SPW_EN : OUT STD_LOGIC; -- 0 => off
90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
91 SPW_NOM_SIN : IN STD_LOGIC;
91 SPW_NOM_SIN : IN STD_LOGIC;
92 SPW_NOM_DOUT : OUT STD_LOGIC;
92 SPW_NOM_DOUT : OUT STD_LOGIC;
93 SPW_NOM_SOUT : OUT STD_LOGIC;
93 SPW_NOM_SOUT : OUT STD_LOGIC;
94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
95 SPW_RED_SIN : IN STD_LOGIC;
95 SPW_RED_SIN : IN STD_LOGIC;
96 SPW_RED_DOUT : OUT STD_LOGIC;
96 SPW_RED_DOUT : OUT STD_LOGIC;
97 SPW_RED_SOUT : OUT STD_LOGIC;
97 SPW_RED_SOUT : OUT STD_LOGIC;
98 -- MINI LFR ADC INPUTS
98 -- MINI LFR ADC INPUTS
99 ADC_nCS : OUT STD_LOGIC;
99 ADC_nCS : OUT STD_LOGIC;
100 ADC_CLK : OUT STD_LOGIC;
100 ADC_CLK : OUT STD_LOGIC;
101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
102
102
103 -- SRAM
103 -- SRAM
104 SRAM_nWE : OUT STD_LOGIC;
104 SRAM_nWE : OUT STD_LOGIC;
105 SRAM_CE : OUT STD_LOGIC;
105 SRAM_CE : OUT STD_LOGIC;
106 SRAM_nOE : OUT STD_LOGIC;
106 SRAM_nOE : OUT STD_LOGIC;
107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
110 );
110 );
111
111
112 END MINI_LFR_top;
112 END MINI_LFR_top;
113
113
114
114
115 ARCHITECTURE beh OF MINI_LFR_top IS
115 ARCHITECTURE beh OF MINI_LFR_top IS
116 SIGNAL clk_50_s : STD_LOGIC := '0';
116 SIGNAL clk_50_s : STD_LOGIC := '0';
117 SIGNAL clk_25 : STD_LOGIC := '0';
117 SIGNAL clk_25 : STD_LOGIC := '0';
118 SIGNAL clk_24 : STD_LOGIC := '0';
118 SIGNAL clk_24 : STD_LOGIC := '0';
119 -----------------------------------------------------------------------------
119 -----------------------------------------------------------------------------
120 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
120 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
121 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
121 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
122 --
122 --
123 SIGNAL errorn : STD_LOGIC;
123 SIGNAL errorn : STD_LOGIC;
124 -- UART AHB ---------------------------------------------------------------
124 -- UART AHB ---------------------------------------------------------------
125 -- SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
125 -- SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
126 -- SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
126 -- SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
127
127
128 -- UART APB ---------------------------------------------------------------
128 -- UART APB ---------------------------------------------------------------
129 -- SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
129 -- SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
130 -- SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
130 -- SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
131 --
131 --
132 SIGNAL I00_s : STD_LOGIC;
132 SIGNAL I00_s : STD_LOGIC;
133
133
134 -- CONSTANTS
134 -- CONSTANTS
135 CONSTANT CFG_PADTECH : INTEGER := inferred;
135 CONSTANT CFG_PADTECH : INTEGER := inferred;
136 --
136 --
137 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
137 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
138 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
138 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
139 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
139 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
140
140
141 SIGNAL apbi_ext : apb_slv_in_type;
141 SIGNAL apbi_ext : apb_slv_in_type;
142 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5); -- := (OTHERS => apb_none);
142 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5); -- := (OTHERS => apb_none);
143 SIGNAL ahbi_s_ext : ahb_slv_in_type;
143 SIGNAL ahbi_s_ext : ahb_slv_in_type;
144 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3); -- := (OTHERS => ahbs_none);
144 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3); -- := (OTHERS => ahbs_none);
145 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
145 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
146 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1); -- := (OTHERS => ahbm_none);
146 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1); -- := (OTHERS => ahbm_none);
147
147
148 -- Spacewire signals
148 -- Spacewire signals
149 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
149 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
151 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
151 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
152 SIGNAL spw_rxtxclk : STD_ULOGIC;
152 SIGNAL spw_rxtxclk : STD_ULOGIC;
153 SIGNAL spw_rxclkn : STD_ULOGIC;
153 SIGNAL spw_rxclkn : STD_ULOGIC;
154 SIGNAL spw_clk : STD_LOGIC;
154 SIGNAL spw_clk : STD_LOGIC;
155 SIGNAL swni : grspw_in_type;
155 SIGNAL swni : grspw_in_type;
156 SIGNAL swno : grspw_out_type;
156 SIGNAL swno : grspw_out_type;
157 -- SIGNAL clkmn : STD_ULOGIC;
157 -- SIGNAL clkmn : STD_ULOGIC;
158 -- SIGNAL txclk : STD_ULOGIC;
158 -- SIGNAL txclk : STD_ULOGIC;
159
159
160 --GPIO
160 --GPIO
161 SIGNAL gpioi : gpio_in_type;
161 SIGNAL gpioi : gpio_in_type;
162 SIGNAL gpioo : gpio_out_type;
162 SIGNAL gpioo : gpio_out_type;
163
163
164 -- AD Converter ADS7886
164 -- AD Converter ADS7886
165 SIGNAL sample : Samples14v(7 DOWNTO 0);
165 SIGNAL sample : Samples14v(7 DOWNTO 0);
166 SIGNAL sample_s : Samples(7 DOWNTO 0);
166 SIGNAL sample_s : Samples(7 DOWNTO 0);
167 SIGNAL sample_val : STD_LOGIC;
167 SIGNAL sample_val : STD_LOGIC;
168 SIGNAL ADC_nCS_sig : STD_LOGIC;
168 SIGNAL ADC_nCS_sig : STD_LOGIC;
169 SIGNAL ADC_CLK_sig : STD_LOGIC;
169 SIGNAL ADC_CLK_sig : STD_LOGIC;
170 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
170 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
171
171
172 SIGNAL bias_fail_sw_sig : STD_LOGIC;
172 SIGNAL bias_fail_sw_sig : STD_LOGIC;
173
173
174 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
174 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
175 SIGNAL observation_vector_0 : STD_LOGIC_VECTOR(11 DOWNTO 0);
175 SIGNAL observation_vector_0 : STD_LOGIC_VECTOR(11 DOWNTO 0);
176 SIGNAL observation_vector_1 : STD_LOGIC_VECTOR(11 DOWNTO 0);
176 SIGNAL observation_vector_1 : STD_LOGIC_VECTOR(11 DOWNTO 0);
177 -----------------------------------------------------------------------------
177 -----------------------------------------------------------------------------
178
178
179 SIGNAL LFR_soft_rstn : STD_LOGIC;
179 SIGNAL LFR_soft_rstn : STD_LOGIC;
180 SIGNAL LFR_rstn : STD_LOGIC;
180 SIGNAL LFR_rstn : STD_LOGIC;
181
181
182
182
183 SIGNAL rstn_25 : STD_LOGIC;
183 SIGNAL rstn_25 : STD_LOGIC;
184 SIGNAL rstn_25_d1 : STD_LOGIC;
184 SIGNAL rstn_25_d1 : STD_LOGIC;
185 SIGNAL rstn_25_d2 : STD_LOGIC;
185 SIGNAL rstn_25_d2 : STD_LOGIC;
186 SIGNAL rstn_25_d3 : STD_LOGIC;
186 SIGNAL rstn_25_d3 : STD_LOGIC;
187
187
188 SIGNAL rstn_50 : STD_LOGIC;
188 SIGNAL rstn_50 : STD_LOGIC;
189 SIGNAL rstn_50_d1 : STD_LOGIC;
189 SIGNAL rstn_50_d1 : STD_LOGIC;
190 SIGNAL rstn_50_d2 : STD_LOGIC;
190 SIGNAL rstn_50_d2 : STD_LOGIC;
191 SIGNAL rstn_50_d3 : STD_LOGIC;
191 SIGNAL rstn_50_d3 : STD_LOGIC;
192
192
193 SIGNAL lfr_debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
193 SIGNAL lfr_debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
194 SIGNAL lfr_debug_vector_ms : STD_LOGIC_VECTOR(11 DOWNTO 0);
194 SIGNAL lfr_debug_vector_ms : STD_LOGIC_VECTOR(11 DOWNTO 0);
195
195
196 --
196 --
197 SIGNAL SRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
197 SIGNAL SRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
198
198
199 --
199 --
200 SIGNAL sample_hk : STD_LOGIC_VECTOR(15 DOWNTO 0);
200 SIGNAL sample_hk : STD_LOGIC_VECTOR(15 DOWNTO 0);
201 SIGNAL HK_SEL : STD_LOGIC_VECTOR( 1 DOWNTO 0);
201 SIGNAL HK_SEL : STD_LOGIC_VECTOR( 1 DOWNTO 0);
202
202
203 BEGIN -- beh
203 BEGIN -- beh
204
204
205 -----------------------------------------------------------------------------
205 -----------------------------------------------------------------------------
206 -- CLK
206 -- CLK
207 -----------------------------------------------------------------------------
207 -----------------------------------------------------------------------------
208
208
209 --PROCESS(clk_50)
209 --PROCESS(clk_50)
210 --BEGIN
210 --BEGIN
211 -- IF clk_50'EVENT AND clk_50 = '1' THEN
211 -- IF clk_50'EVENT AND clk_50 = '1' THEN
212 -- clk_50_s <= NOT clk_50_s;
212 -- clk_50_s <= NOT clk_50_s;
213 -- END IF;
213 -- END IF;
214 --END PROCESS;
214 --END PROCESS;
215
215
216 --PROCESS(clk_50_s)
216 --PROCESS(clk_50_s)
217 --BEGIN
217 --BEGIN
218 -- IF clk_50_s'EVENT AND clk_50_s = '1' THEN
218 -- IF clk_50_s'EVENT AND clk_50_s = '1' THEN
219 -- clk_25 <= NOT clk_25;
219 -- clk_25 <= NOT clk_25;
220 -- END IF;
220 -- END IF;
221 --END PROCESS;
221 --END PROCESS;
222
222
223 --PROCESS(clk_49)
223 --PROCESS(clk_49)
224 --BEGIN
224 --BEGIN
225 -- IF clk_49'EVENT AND clk_49 = '1' THEN
225 -- IF clk_49'EVENT AND clk_49 = '1' THEN
226 -- clk_24 <= NOT clk_24;
226 -- clk_24 <= NOT clk_24;
227 -- END IF;
227 -- END IF;
228 --END PROCESS;
228 --END PROCESS;
229
229
230 --PROCESS(clk_25)
230 --PROCESS(clk_25)
231 --BEGIN
231 --BEGIN
232 -- IF clk_25'EVENT AND clk_25 = '1' THEN
232 -- IF clk_25'EVENT AND clk_25 = '1' THEN
233 -- rstn_25 <= reset;
233 -- rstn_25 <= reset;
234 -- END IF;
234 -- END IF;
235 --END PROCESS;
235 --END PROCESS;
236
236
237 PROCESS (clk_50, reset)
237 PROCESS (clk_50, reset)
238 BEGIN -- PROCESS
238 BEGIN -- PROCESS
239 IF reset = '0' THEN -- asynchronous reset (active low)
239 IF reset = '0' THEN -- asynchronous reset (active low)
240 clk_50_s <= '0';
240 clk_50_s <= '0';
241 rstn_50 <= '0';
241 rstn_50 <= '0';
242 rstn_50_d1 <= '0';
242 rstn_50_d1 <= '0';
243 rstn_50_d2 <= '0';
243 rstn_50_d2 <= '0';
244 rstn_50_d3 <= '0';
244 rstn_50_d3 <= '0';
245
245
246 ELSIF clk_50'EVENT AND clk_50 = '1' THEN -- rising clock edge
246 ELSIF clk_50'EVENT AND clk_50 = '1' THEN -- rising clock edge
247 clk_50_s <= NOT clk_50_s;
247 clk_50_s <= NOT clk_50_s;
248 rstn_50_d1 <= '1';
248 rstn_50_d1 <= '1';
249 rstn_50_d2 <= rstn_50_d1;
249 rstn_50_d2 <= rstn_50_d1;
250 rstn_50_d3 <= rstn_50_d2;
250 rstn_50_d3 <= rstn_50_d2;
251 rstn_50 <= rstn_50_d3;
251 rstn_50 <= rstn_50_d3;
252 END IF;
252 END IF;
253 END PROCESS;
253 END PROCESS;
254
254
255 PROCESS (clk_50_s, rstn_50)
255 PROCESS (clk_50_s, rstn_50)
256 BEGIN -- PROCESS
256 BEGIN -- PROCESS
257 IF rstn_50 = '0' THEN -- asynchronous reset (active low)
257 IF rstn_50 = '0' THEN -- asynchronous reset (active low)
258 clk_25 <= '0';
258 clk_25 <= '0';
259 rstn_25 <= '0';
259 rstn_25 <= '0';
260 rstn_25_d1 <= '0';
260 rstn_25_d1 <= '0';
261 rstn_25_d2 <= '0';
261 rstn_25_d2 <= '0';
262 rstn_25_d3 <= '0';
262 rstn_25_d3 <= '0';
263 ELSIF clk_50_s'EVENT AND clk_50_s = '1' THEN -- rising clock edge
263 ELSIF clk_50_s'EVENT AND clk_50_s = '1' THEN -- rising clock edge
264 clk_25 <= NOT clk_25;
264 clk_25 <= NOT clk_25;
265 rstn_25_d1 <= '1';
265 rstn_25_d1 <= '1';
266 rstn_25_d2 <= rstn_25_d1;
266 rstn_25_d2 <= rstn_25_d1;
267 rstn_25_d3 <= rstn_25_d2;
267 rstn_25_d3 <= rstn_25_d2;
268 rstn_25 <= rstn_25_d3;
268 rstn_25 <= rstn_25_d3;
269 END IF;
269 END IF;
270 END PROCESS;
270 END PROCESS;
271
271
272 PROCESS (clk_49, reset)
272 PROCESS (clk_49, reset)
273 BEGIN -- PROCESS
273 BEGIN -- PROCESS
274 IF reset = '0' THEN -- asynchronous reset (active low)
274 IF reset = '0' THEN -- asynchronous reset (active low)
275 clk_24 <= '0';
275 clk_24 <= '0';
276 ELSIF clk_49'EVENT AND clk_49 = '1' THEN -- rising clock edge
276 ELSIF clk_49'EVENT AND clk_49 = '1' THEN -- rising clock edge
277 clk_24 <= NOT clk_24;
277 clk_24 <= NOT clk_24;
278 END IF;
278 END IF;
279 END PROCESS;
279 END PROCESS;
280
280
281 -----------------------------------------------------------------------------
281 -----------------------------------------------------------------------------
282
282
283 PROCESS (clk_25, rstn_25)
283 PROCESS (clk_25, rstn_25)
284 BEGIN -- PROCESS
284 BEGIN -- PROCESS
285 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
285 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
286 LED0 <= '0';
286 LED0 <= '0';
287 LED1 <= '0';
287 LED1 <= '0';
288 LED2 <= '0';
288 LED2 <= '0';
289 --IO1 <= '0';
289 --IO1 <= '0';
290 --IO2 <= '1';
290 --IO2 <= '1';
291 --IO3 <= '0';
291 --IO3 <= '0';
292 --IO4 <= '0';
292 --IO4 <= '0';
293 --IO5 <= '0';
293 --IO5 <= '0';
294 --IO6 <= '0';
294 --IO6 <= '0';
295 --IO7 <= '0';
295 --IO7 <= '0';
296 --IO8 <= '0';
296 --IO8 <= '0';
297 --IO9 <= '0';
297 --IO9 <= '0';
298 --IO10 <= '0';
298 --IO10 <= '0';
299 --IO11 <= '0';
299 --IO11 <= '0';
300 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
300 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
301 LED0 <= '0';
301 LED0 <= '0';
302 LED1 <= '1';
302 LED1 <= '1';
303 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
303 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
304 --IO1 <= '1';
304 --IO1 <= '1';
305 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
305 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
306 --IO3 <= ADC_SDO(0);
306 --IO3 <= ADC_SDO(0);
307 --IO4 <= ADC_SDO(1);
307 --IO4 <= ADC_SDO(1);
308 --IO5 <= ADC_SDO(2);
308 --IO5 <= ADC_SDO(2);
309 --IO6 <= ADC_SDO(3);
309 --IO6 <= ADC_SDO(3);
310 --IO7 <= ADC_SDO(4);
310 --IO7 <= ADC_SDO(4);
311 --IO8 <= ADC_SDO(5);
311 --IO8 <= ADC_SDO(5);
312 --IO9 <= ADC_SDO(6);
312 --IO9 <= ADC_SDO(6);
313 --IO10 <= ADC_SDO(7);
313 --IO10 <= ADC_SDO(7);
314 --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
314 --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
315 END IF;
315 END IF;
316 END PROCESS;
316 END PROCESS;
317
317
318 PROCESS (clk_24, rstn_25)
318 PROCESS (clk_24, rstn_25)
319 BEGIN -- PROCESS
319 BEGIN -- PROCESS
320 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
320 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
321 I00_s <= '0';
321 I00_s <= '0';
322 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
322 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
323 I00_s <= NOT I00_s;
323 I00_s <= NOT I00_s;
324 END IF;
324 END IF;
325 END PROCESS;
325 END PROCESS;
326 -- IO0 <= I00_s;
326 -- IO0 <= I00_s;
327
327
328 --UARTs
328 --UARTs
329 nCTS1 <= '1';
329 nCTS1 <= '1';
330 nCTS2 <= '1';
330 nCTS2 <= '1';
331 nDCD2 <= '1';
331 nDCD2 <= '1';
332
332
333 --
333 --
334
334
335 leon3_soc_1 : leon3_soc
335 leon3_soc_1 : leon3_soc
336 GENERIC MAP (
336 GENERIC MAP (
337 fabtech => apa3e,
337 fabtech => apa3e,
338 memtech => apa3e,
338 memtech => apa3e,
339 padtech => inferred,
339 padtech => inferred,
340 clktech => inferred,
340 clktech => inferred,
341 disas => 0,
341 disas => 0,
342 dbguart => 0,
342 dbguart => 0,
343 pclow => 2,
343 pclow => 2,
344 clk_freq => 25000,
344 clk_freq => 25000,
345 IS_RADHARD => 0,
345 IS_RADHARD => 0,
346 NB_CPU => 1,
346 NB_CPU => 1,
347 ENABLE_FPU => 1,
347 ENABLE_FPU => 1,
348 FPU_NETLIST => 0,
348 FPU_NETLIST => 0,
349 ENABLE_DSU => 1,
349 ENABLE_DSU => 1,
350 ENABLE_AHB_UART => 1,
350 ENABLE_AHB_UART => 1,
351 ENABLE_APB_UART => 1,
351 ENABLE_APB_UART => 1,
352 ENABLE_IRQMP => 1,
352 ENABLE_IRQMP => 1,
353 ENABLE_GPT => 1,
353 ENABLE_GPT => 1,
354 NB_AHB_MASTER => NB_AHB_MASTER,
354 NB_AHB_MASTER => NB_AHB_MASTER,
355 NB_AHB_SLAVE => NB_AHB_SLAVE,
355 NB_AHB_SLAVE => NB_AHB_SLAVE,
356 NB_APB_SLAVE => NB_APB_SLAVE,
356 NB_APB_SLAVE => NB_APB_SLAVE,
357 ADDRESS_SIZE => 20,
357 ADDRESS_SIZE => 20,
358 USES_IAP_MEMCTRLR => 0)
358 USES_IAP_MEMCTRLR => 0)
359 PORT MAP (
359 PORT MAP (
360 clk => clk_25,
360 clk => clk_25,
361 reset => rstn_25,
361 reset => rstn_25,
362 errorn => errorn,
362 errorn => errorn,
363 ahbrxd => TXD1,
363 ahbrxd => TXD1,
364 ahbtxd => RXD1,
364 ahbtxd => RXD1,
365 urxd1 => TXD2,
365 urxd1 => TXD2,
366 utxd1 => RXD2,
366 utxd1 => RXD2,
367 address => SRAM_A,
367 address => SRAM_A,
368 data => SRAM_DQ,
368 data => SRAM_DQ,
369 nSRAM_BE0 => SRAM_nBE(0),
369 nSRAM_BE0 => SRAM_nBE(0),
370 nSRAM_BE1 => SRAM_nBE(1),
370 nSRAM_BE1 => SRAM_nBE(1),
371 nSRAM_BE2 => SRAM_nBE(2),
371 nSRAM_BE2 => SRAM_nBE(2),
372 nSRAM_BE3 => SRAM_nBE(3),
372 nSRAM_BE3 => SRAM_nBE(3),
373 nSRAM_WE => SRAM_nWE,
373 nSRAM_WE => SRAM_nWE,
374 nSRAM_CE => SRAM_CE_s,
374 nSRAM_CE => SRAM_CE_s,
375 nSRAM_OE => SRAM_nOE,
375 nSRAM_OE => SRAM_nOE,
376 nSRAM_READY => '0',
376 nSRAM_READY => '0',
377 SRAM_MBE => OPEN,
377 SRAM_MBE => OPEN,
378 apbi_ext => apbi_ext,
378 apbi_ext => apbi_ext,
379 apbo_ext => apbo_ext,
379 apbo_ext => apbo_ext,
380 ahbi_s_ext => ahbi_s_ext,
380 ahbi_s_ext => ahbi_s_ext,
381 ahbo_s_ext => ahbo_s_ext,
381 ahbo_s_ext => ahbo_s_ext,
382 ahbi_m_ext => ahbi_m_ext,
382 ahbi_m_ext => ahbi_m_ext,
383 ahbo_m_ext => ahbo_m_ext);
383 ahbo_m_ext => ahbo_m_ext);
384
384
385 SRAM_CE <= SRAM_CE_s(0);
385 SRAM_CE <= SRAM_CE_s(0);
386 -------------------------------------------------------------------------------
386 -------------------------------------------------------------------------------
387 -- APB_LFR_MANAGEMENT ---------------------------------------------------------
387 -- APB_LFR_MANAGEMENT ---------------------------------------------------------
388 -------------------------------------------------------------------------------
388 -------------------------------------------------------------------------------
389 apb_lfr_management_1 : apb_lfr_management
389 apb_lfr_management_1 : apb_lfr_management
390 GENERIC MAP (
390 GENERIC MAP (
391 tech => apa3e,
391 tech => apa3e,
392 pindex => 6,
392 pindex => 6,
393 paddr => 6,
393 paddr => 6,
394 pmask => 16#fff#,
394 pmask => 16#fff#,
395 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
395 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
396 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
396 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
397 PORT MAP (
397 PORT MAP (
398 clk25MHz => clk_25,
398 clk25MHz => clk_25,
399 clk24_576MHz => clk_24, -- 49.152MHz/2
399 clk24_576MHz => clk_24, -- 49.152MHz/2
400 resetn => rstn_25,
400 resetn => rstn_25,
401 grspw_tick => swno.tickout,
401 grspw_tick => swno.tickout,
402 apbi => apbi_ext,
402 apbi => apbi_ext,
403 apbo => apbo_ext(6),
403 apbo => apbo_ext(6),
404 HK_sample => sample_hk,
404 HK_sample => sample_hk,
405 HK_val => sample_val,
405 HK_val => sample_val,
406 HK_sel => HK_SEL,
406 HK_sel => HK_SEL,
407 DAC_SDO => OPEN,
407 DAC_SDO => OPEN,
408 DAC_SCK => OPEN,
408 DAC_SCK => OPEN,
409 DAC_SYNC => OPEN,
409 DAC_SYNC => OPEN,
410 DAC_CAL_EN => OPEN,
410 DAC_CAL_EN => OPEN,
411 coarse_time => coarse_time,
411 coarse_time => coarse_time,
412 fine_time => fine_time,
412 fine_time => fine_time,
413 LFR_soft_rstn => LFR_soft_rstn
413 LFR_soft_rstn => LFR_soft_rstn
414 );
414 );
415
415
416 -----------------------------------------------------------------------
416 -----------------------------------------------------------------------
417 --- SpaceWire --------------------------------------------------------
417 --- SpaceWire --------------------------------------------------------
418 -----------------------------------------------------------------------
418 -----------------------------------------------------------------------
419
419
420 SPW_EN <= '1';
420 SPW_EN <= '1';
421
421
422 spw_clk <= clk_50_s;
422 spw_clk <= clk_50_s;
423 spw_rxtxclk <= spw_clk;
423 spw_rxtxclk <= spw_clk;
424 spw_rxclkn <= NOT spw_rxtxclk;
424 spw_rxclkn <= NOT spw_rxtxclk;
425
425
426 -- PADS for SPW1
426 -- PADS for SPW1
427 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
427 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
428 PORT MAP (SPW_NOM_DIN, dtmp(0));
428 PORT MAP (SPW_NOM_DIN, dtmp(0));
429 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
429 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
430 PORT MAP (SPW_NOM_SIN, stmp(0));
430 PORT MAP (SPW_NOM_SIN, stmp(0));
431 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
431 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
432 PORT MAP (SPW_NOM_DOUT, swno.d(0));
432 PORT MAP (SPW_NOM_DOUT, swno.d(0));
433 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
433 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
434 PORT MAP (SPW_NOM_SOUT, swno.s(0));
434 PORT MAP (SPW_NOM_SOUT, swno.s(0));
435 -- PADS FOR SPW2
435 -- PADS FOR SPW2
436 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
436 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
437 PORT MAP (SPW_RED_SIN, dtmp(1));
437 PORT MAP (SPW_RED_SIN, dtmp(1));
438 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
438 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
439 PORT MAP (SPW_RED_DIN, stmp(1));
439 PORT MAP (SPW_RED_DIN, stmp(1));
440 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
440 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
441 PORT MAP (SPW_RED_DOUT, swno.d(1));
441 PORT MAP (SPW_RED_DOUT, swno.d(1));
442 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
442 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
443 PORT MAP (SPW_RED_SOUT, swno.s(1));
443 PORT MAP (SPW_RED_SOUT, swno.s(1));
444
444
445 -- GRSPW PHY
445 -- GRSPW PHY
446 --spw1_input: if CFG_SPW_GRSPW = 1 generate
446 --spw1_input: if CFG_SPW_GRSPW = 1 generate
447 spw_inputloop : FOR j IN 0 TO 1 GENERATE
447 spw_inputloop : FOR j IN 0 TO 1 GENERATE
448 spw_phy0 : grspw_phy
448 spw_phy0 : grspw_phy
449 GENERIC MAP(
449 GENERIC MAP(
450 tech => apa3e,
450 tech => apa3e,
451 rxclkbuftype => 1,
451 rxclkbuftype => 1,
452 scantest => 0)
452 scantest => 0)
453 PORT MAP(
453 PORT MAP(
454 rxrst => swno.rxrst,
454 rxrst => swno.rxrst,
455 di => dtmp(j),
455 di => dtmp(j),
456 si => stmp(j),
456 si => stmp(j),
457 rxclko => spw_rxclk(j),
457 rxclko => spw_rxclk(j),
458 do => swni.d(j),
458 do => swni.d(j),
459 ndo => swni.nd(j*5+4 DOWNTO j*5),
459 ndo => swni.nd(j*5+4 DOWNTO j*5),
460 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
460 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
461 END GENERATE spw_inputloop;
461 END GENERATE spw_inputloop;
462
462
463 swni.rmapnodeaddr <= (OTHERS => '0');
463 swni.rmapnodeaddr <= (OTHERS => '0');
464
464
465 -- SPW core
465 -- SPW core
466 sw0 : grspwm GENERIC MAP(
466 sw0 : grspwm GENERIC MAP(
467 tech => apa3e,
467 tech => apa3e,
468 hindex => 1,
468 hindex => 1,
469 pindex => 5,
469 pindex => 5,
470 paddr => 5,
470 paddr => 5,
471 pirq => 11,
471 pirq => 11,
472 sysfreq => 25000, -- CPU_FREQ
472 sysfreq => 25000, -- CPU_FREQ
473 rmap => 1,
473 rmap => 1,
474 rmapcrc => 1,
474 rmapcrc => 1,
475 fifosize1 => 16,
475 fifosize1 => 16,
476 fifosize2 => 16,
476 fifosize2 => 16,
477 rxclkbuftype => 1,
477 rxclkbuftype => 1,
478 rxunaligned => 0,
478 rxunaligned => 0,
479 rmapbufs => 4,
479 rmapbufs => 4,
480 ft => 0,
480 ft => 0,
481 netlist => 0,
481 netlist => 0,
482 ports => 2,
482 ports => 2,
483 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
483 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
484 memtech => apa3e,
484 memtech => apa3e,
485 destkey => 2,
485 destkey => 2,
486 spwcore => 1
486 spwcore => 1
487 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
487 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
488 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
488 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
489 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
489 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
490 )
490 )
491 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
491 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
492 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
492 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
493 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
493 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
494 swni, swno);
494 swni, swno);
495
495
496 swni.tickin <= '0';
496 swni.tickin <= '0';
497 swni.rmapen <= '1';
497 swni.rmapen <= '1';
498 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
498 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
499 swni.tickinraw <= '0';
499 swni.tickinraw <= '0';
500 swni.timein <= (OTHERS => '0');
500 swni.timein <= (OTHERS => '0');
501 swni.dcrstval <= (OTHERS => '0');
501 swni.dcrstval <= (OTHERS => '0');
502 swni.timerrstval <= (OTHERS => '0');
502 swni.timerrstval <= (OTHERS => '0');
503
503
504 -------------------------------------------------------------------------------
504 -------------------------------------------------------------------------------
505 -- LFR ------------------------------------------------------------------------
505 -- LFR ------------------------------------------------------------------------
506 -------------------------------------------------------------------------------
506 -------------------------------------------------------------------------------
507
507
508
508
509 LFR_rstn <= LFR_soft_rstn AND rstn_25;
509 LFR_rstn <= LFR_soft_rstn AND rstn_25;
510 --LFR_rstn <= rstn_25;
510 --LFR_rstn <= rstn_25;
511
511
512 lpp_lfr_1 : lpp_lfr
512 lpp_lfr_1 : lpp_lfr
513 GENERIC MAP (
513 GENERIC MAP (
514 Mem_use => use_RAM,
514 Mem_use => use_RAM,
515 nb_data_by_buffer_size => 32,
515 nb_data_by_buffer_size => 32,
516 nb_snapshot_param_size => 32,
516 nb_snapshot_param_size => 32,
517 delta_vector_size => 32,
517 delta_vector_size => 32,
518 delta_vector_size_f0_2 => 7, -- log2(96)
518 delta_vector_size_f0_2 => 7, -- log2(96)
519 pindex => 15,
519 pindex => 15,
520 paddr => 15,
520 paddr => 15,
521 pmask => 16#fff#,
521 pmask => 16#fff#,
522 pirq_ms => 6,
522 pirq_ms => 6,
523 pirq_wfp => 14,
523 pirq_wfp => 14,
524 hindex => 2,
524 hindex => 2,
525 top_lfr_version => X"000142") -- aa.bb.cc version
525 top_lfr_version => X"000143") -- aa.bb.cc version
526 PORT MAP (
526 PORT MAP (
527 clk => clk_25,
527 clk => clk_25,
528 rstn => LFR_rstn,
528 rstn => LFR_rstn,
529 sample_B => sample_s(2 DOWNTO 0),
529 sample_B => sample_s(2 DOWNTO 0),
530 sample_E => sample_s(7 DOWNTO 3),
530 sample_E => sample_s(7 DOWNTO 3),
531 sample_val => sample_val,
531 sample_val => sample_val,
532 apbi => apbi_ext,
532 apbi => apbi_ext,
533 apbo => apbo_ext(15),
533 apbo => apbo_ext(15),
534 ahbi => ahbi_m_ext,
534 ahbi => ahbi_m_ext,
535 ahbo => ahbo_m_ext(2),
535 ahbo => ahbo_m_ext(2),
536 coarse_time => coarse_time,
536 coarse_time => coarse_time,
537 fine_time => fine_time,
537 fine_time => fine_time,
538 data_shaping_BW => bias_fail_sw_sig,
538 data_shaping_BW => bias_fail_sw_sig,
539 debug_vector => lfr_debug_vector,
539 debug_vector => lfr_debug_vector,
540 debug_vector_ms => lfr_debug_vector_ms
540 debug_vector_ms => lfr_debug_vector_ms
541 );
541 );
542
542
543 observation_reg(11 DOWNTO 0) <= lfr_debug_vector;
543 observation_reg(11 DOWNTO 0) <= lfr_debug_vector;
544 observation_reg(31 DOWNTO 12) <= (OTHERS => '0');
544 observation_reg(31 DOWNTO 12) <= (OTHERS => '0');
545 observation_vector_0(11 DOWNTO 0) <= lfr_debug_vector;
545 observation_vector_0(11 DOWNTO 0) <= lfr_debug_vector;
546 observation_vector_1(11 DOWNTO 0) <= lfr_debug_vector;
546 observation_vector_1(11 DOWNTO 0) <= lfr_debug_vector;
547 IO0 <= rstn_25;
547 IO0 <= rstn_25;
548 IO1 <= lfr_debug_vector_ms(0); -- LFR MS FFT data_valid
548 IO1 <= lfr_debug_vector_ms(0); -- LFR MS FFT data_valid
549 IO2 <= lfr_debug_vector_ms(0); -- LFR MS FFT ready
549 IO2 <= lfr_debug_vector_ms(0); -- LFR MS FFT ready
550 IO3 <= lfr_debug_vector(0); -- LFR APBREG error_buffer_full
550 IO3 <= lfr_debug_vector(0); -- LFR APBREG error_buffer_full
551 IO4 <= lfr_debug_vector(1); -- LFR APBREG reg_sp.status_error_buffer_full
551 IO4 <= lfr_debug_vector(1); -- LFR APBREG reg_sp.status_error_buffer_full
552 IO5 <= lfr_debug_vector(8); -- LFR APBREG ready_matrix_f2
552 IO5 <= lfr_debug_vector(8); -- LFR APBREG ready_matrix_f2
553 IO6 <= lfr_debug_vector(9); -- LFR APBREG reg0_ready_matrix_f2
553 IO6 <= lfr_debug_vector(9); -- LFR APBREG reg0_ready_matrix_f2
554 IO7 <= lfr_debug_vector(10); -- LFR APBREG reg0_ready_matrix_f2
554 IO7 <= lfr_debug_vector(10); -- LFR APBREG reg0_ready_matrix_f2
555
555
556 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
556 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
557 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
557 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
558 END GENERATE all_sample;
558 END GENERATE all_sample;
559
559
560 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
560 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
561 GENERIC MAP(
561 GENERIC MAP(
562 ChannelCount => 8,
562 ChannelCount => 8,
563 SampleNbBits => 14,
563 SampleNbBits => 14,
564 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
564 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
565 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
565 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
566 PORT MAP (
566 PORT MAP (
567 -- CONV
567 -- CONV
568 cnv_clk => clk_24,
568 cnv_clk => clk_24,
569 cnv_rstn => rstn_25,
569 cnv_rstn => rstn_25,
570 cnv => ADC_nCS_sig,
570 cnv => ADC_nCS_sig,
571 -- DATA
571 -- DATA
572 clk => clk_25,
572 clk => clk_25,
573 rstn => rstn_25,
573 rstn => rstn_25,
574 sck => ADC_CLK_sig,
574 sck => ADC_CLK_sig,
575 sdo => ADC_SDO_sig,
575 sdo => ADC_SDO_sig,
576 -- SAMPLE
576 -- SAMPLE
577 sample => sample,
577 sample => sample,
578 sample_val => sample_val);
578 sample_val => sample_val);
579
579
580 --IO10 <= ADC_SDO_sig(5);
580 --IO10 <= ADC_SDO_sig(5);
581 --IO9 <= ADC_SDO_sig(4);
581 --IO9 <= ADC_SDO_sig(4);
582 --IO8 <= ADC_SDO_sig(3);
582 --IO8 <= ADC_SDO_sig(3);
583
583
584 ADC_nCS <= ADC_nCS_sig;
584 ADC_nCS <= ADC_nCS_sig;
585 ADC_CLK <= ADC_CLK_sig;
585 ADC_CLK <= ADC_CLK_sig;
586 ADC_SDO_sig <= ADC_SDO;
586 ADC_SDO_sig <= ADC_SDO;
587
587
588 sample_hk <= "0001000100010001" WHEN HK_SEL = "00" ELSE
588 sample_hk <= "0001000100010001" WHEN HK_SEL = "00" ELSE
589 "0010001000100010" WHEN HK_SEL = "01" ELSE
589 "0010001000100010" WHEN HK_SEL = "01" ELSE
590 "0100010001000100" WHEN HK_SEL = "10" ELSE
590 "0100010001000100" WHEN HK_SEL = "10" ELSE
591 (OTHERS => '0');
591 (OTHERS => '0');
592
592
593
593
594 ----------------------------------------------------------------------
594 ----------------------------------------------------------------------
595 --- GPIO -----------------------------------------------------------
595 --- GPIO -----------------------------------------------------------
596 ----------------------------------------------------------------------
596 ----------------------------------------------------------------------
597
597
598 grgpio0 : grgpio
598 grgpio0 : grgpio
599 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
599 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
600 PORT MAP(rstn_25, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
600 PORT MAP(rstn_25, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
601
601
602 gpioi.sig_en <= (OTHERS => '0');
602 gpioi.sig_en <= (OTHERS => '0');
603 gpioi.sig_in <= (OTHERS => '0');
603 gpioi.sig_in <= (OTHERS => '0');
604 gpioi.din <= (OTHERS => '0');
604 gpioi.din <= (OTHERS => '0');
605 --pio_pad_0 : iopad
605 --pio_pad_0 : iopad
606 -- GENERIC MAP (tech => CFG_PADTECH)
606 -- GENERIC MAP (tech => CFG_PADTECH)
607 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
607 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
608 --pio_pad_1 : iopad
608 --pio_pad_1 : iopad
609 -- GENERIC MAP (tech => CFG_PADTECH)
609 -- GENERIC MAP (tech => CFG_PADTECH)
610 -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
610 -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
611 --pio_pad_2 : iopad
611 --pio_pad_2 : iopad
612 -- GENERIC MAP (tech => CFG_PADTECH)
612 -- GENERIC MAP (tech => CFG_PADTECH)
613 -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
613 -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
614 --pio_pad_3 : iopad
614 --pio_pad_3 : iopad
615 -- GENERIC MAP (tech => CFG_PADTECH)
615 -- GENERIC MAP (tech => CFG_PADTECH)
616 -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
616 -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
617 --pio_pad_4 : iopad
617 --pio_pad_4 : iopad
618 -- GENERIC MAP (tech => CFG_PADTECH)
618 -- GENERIC MAP (tech => CFG_PADTECH)
619 -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
619 -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
620 --pio_pad_5 : iopad
620 --pio_pad_5 : iopad
621 -- GENERIC MAP (tech => CFG_PADTECH)
621 -- GENERIC MAP (tech => CFG_PADTECH)
622 -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
622 -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
623 --pio_pad_6 : iopad
623 --pio_pad_6 : iopad
624 -- GENERIC MAP (tech => CFG_PADTECH)
624 -- GENERIC MAP (tech => CFG_PADTECH)
625 -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
625 -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
626 --pio_pad_7 : iopad
626 --pio_pad_7 : iopad
627 -- GENERIC MAP (tech => CFG_PADTECH)
627 -- GENERIC MAP (tech => CFG_PADTECH)
628 -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
628 -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
629
629
630 PROCESS (clk_25, rstn_25)
630 PROCESS (clk_25, rstn_25)
631 BEGIN -- PROCESS
631 BEGIN -- PROCESS
632 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
632 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
633 -- --IO0 <= '0';
633 -- --IO0 <= '0';
634 -- IO1 <= '0';
634 -- IO1 <= '0';
635 -- IO2 <= '0';
635 -- IO2 <= '0';
636 -- IO3 <= '0';
636 -- IO3 <= '0';
637 -- IO4 <= '0';
637 -- IO4 <= '0';
638 -- IO5 <= '0';
638 -- IO5 <= '0';
639 -- IO6 <= '0';
639 -- IO6 <= '0';
640 -- IO7 <= '0';
640 -- IO7 <= '0';
641 IO8 <= '0';
641 IO8 <= '0';
642 IO9 <= '0';
642 IO9 <= '0';
643 IO10 <= '0';
643 IO10 <= '0';
644 IO11 <= '0';
644 IO11 <= '0';
645 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
645 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
646 CASE gpioo.dout(2 DOWNTO 0) IS
646 CASE gpioo.dout(2 DOWNTO 0) IS
647 WHEN "011" =>
647 WHEN "011" =>
648 -- --IO0 <= observation_reg(0 );
648 -- --IO0 <= observation_reg(0 );
649 -- IO1 <= observation_reg(1 );
649 -- IO1 <= observation_reg(1 );
650 -- IO2 <= observation_reg(2 );
650 -- IO2 <= observation_reg(2 );
651 -- IO3 <= observation_reg(3 );
651 -- IO3 <= observation_reg(3 );
652 -- IO4 <= observation_reg(4 );
652 -- IO4 <= observation_reg(4 );
653 -- IO5 <= observation_reg(5 );
653 -- IO5 <= observation_reg(5 );
654 -- IO6 <= observation_reg(6 );
654 -- IO6 <= observation_reg(6 );
655 -- IO7 <= observation_reg(7 );
655 -- IO7 <= observation_reg(7 );
656 IO8 <= observation_reg(8);
656 IO8 <= observation_reg(8);
657 IO9 <= observation_reg(9);
657 IO9 <= observation_reg(9);
658 IO10 <= observation_reg(10);
658 IO10 <= observation_reg(10);
659 IO11 <= observation_reg(11);
659 IO11 <= observation_reg(11);
660 WHEN "001" =>
660 WHEN "001" =>
661 -- --IO0 <= observation_reg(0 + 12);
661 -- --IO0 <= observation_reg(0 + 12);
662 -- IO1 <= observation_reg(1 + 12);
662 -- IO1 <= observation_reg(1 + 12);
663 -- IO2 <= observation_reg(2 + 12);
663 -- IO2 <= observation_reg(2 + 12);
664 -- IO3 <= observation_reg(3 + 12);
664 -- IO3 <= observation_reg(3 + 12);
665 -- IO4 <= observation_reg(4 + 12);
665 -- IO4 <= observation_reg(4 + 12);
666 -- IO5 <= observation_reg(5 + 12);
666 -- IO5 <= observation_reg(5 + 12);
667 -- IO6 <= observation_reg(6 + 12);
667 -- IO6 <= observation_reg(6 + 12);
668 -- IO7 <= observation_reg(7 + 12);
668 -- IO7 <= observation_reg(7 + 12);
669 IO8 <= observation_reg(8 + 12);
669 IO8 <= observation_reg(8 + 12);
670 IO9 <= observation_reg(9 + 12);
670 IO9 <= observation_reg(9 + 12);
671 IO10 <= observation_reg(10 + 12);
671 IO10 <= observation_reg(10 + 12);
672 IO11 <= observation_reg(11 + 12);
672 IO11 <= observation_reg(11 + 12);
673 WHEN "010" =>
673 WHEN "010" =>
674 -- --IO0 <= observation_reg(0 + 12 + 12);
674 -- --IO0 <= observation_reg(0 + 12 + 12);
675 -- IO1 <= observation_reg(1 + 12 + 12);
675 -- IO1 <= observation_reg(1 + 12 + 12);
676 -- IO2 <= observation_reg(2 + 12 + 12);
676 -- IO2 <= observation_reg(2 + 12 + 12);
677 -- IO3 <= observation_reg(3 + 12 + 12);
677 -- IO3 <= observation_reg(3 + 12 + 12);
678 -- IO4 <= observation_reg(4 + 12 + 12);
678 -- IO4 <= observation_reg(4 + 12 + 12);
679 -- IO5 <= observation_reg(5 + 12 + 12);
679 -- IO5 <= observation_reg(5 + 12 + 12);
680 -- IO6 <= observation_reg(6 + 12 + 12);
680 -- IO6 <= observation_reg(6 + 12 + 12);
681 -- IO7 <= observation_reg(7 + 12 + 12);
681 -- IO7 <= observation_reg(7 + 12 + 12);
682 IO8 <= '0';
682 IO8 <= '0';
683 IO9 <= '0';
683 IO9 <= '0';
684 IO10 <= '0';
684 IO10 <= '0';
685 IO11 <= '0';
685 IO11 <= '0';
686 WHEN "000" =>
686 WHEN "000" =>
687 -- --IO0 <= observation_vector_0(0 );
687 -- --IO0 <= observation_vector_0(0 );
688 -- IO1 <= observation_vector_0(1 );
688 -- IO1 <= observation_vector_0(1 );
689 -- IO2 <= observation_vector_0(2 );
689 -- IO2 <= observation_vector_0(2 );
690 -- IO3 <= observation_vector_0(3 );
690 -- IO3 <= observation_vector_0(3 );
691 -- IO4 <= observation_vector_0(4 );
691 -- IO4 <= observation_vector_0(4 );
692 -- IO5 <= observation_vector_0(5 );
692 -- IO5 <= observation_vector_0(5 );
693 -- IO6 <= observation_vector_0(6 );
693 -- IO6 <= observation_vector_0(6 );
694 -- IO7 <= observation_vector_0(7 );
694 -- IO7 <= observation_vector_0(7 );
695 IO8 <= observation_vector_0(8);
695 IO8 <= observation_vector_0(8);
696 IO9 <= observation_vector_0(9);
696 IO9 <= observation_vector_0(9);
697 IO10 <= observation_vector_0(10);
697 IO10 <= observation_vector_0(10);
698 IO11 <= observation_vector_0(11);
698 IO11 <= observation_vector_0(11);
699 WHEN "100" =>
699 WHEN "100" =>
700 -- --IO0 <= observation_vector_1(0 );
700 -- --IO0 <= observation_vector_1(0 );
701 -- IO1 <= observation_vector_1(1 );
701 -- IO1 <= observation_vector_1(1 );
702 -- IO2 <= observation_vector_1(2 );
702 -- IO2 <= observation_vector_1(2 );
703 -- IO3 <= observation_vector_1(3 );
703 -- IO3 <= observation_vector_1(3 );
704 -- IO4 <= observation_vector_1(4 );
704 -- IO4 <= observation_vector_1(4 );
705 -- IO5 <= observation_vector_1(5 );
705 -- IO5 <= observation_vector_1(5 );
706 -- IO6 <= observation_vector_1(6 );
706 -- IO6 <= observation_vector_1(6 );
707 -- IO7 <= observation_vector_1(7 );
707 -- IO7 <= observation_vector_1(7 );
708 IO8 <= observation_vector_1(8);
708 IO8 <= observation_vector_1(8);
709 IO9 <= observation_vector_1(9);
709 IO9 <= observation_vector_1(9);
710 IO10 <= observation_vector_1(10);
710 IO10 <= observation_vector_1(10);
711 IO11 <= observation_vector_1(11);
711 IO11 <= observation_vector_1(11);
712 WHEN OTHERS => NULL;
712 WHEN OTHERS => NULL;
713 END CASE;
713 END CASE;
714
714
715 END IF;
715 END IF;
716 END PROCESS;
716 END PROCESS;
717 -----------------------------------------------------------------------------
717 -----------------------------------------------------------------------------
718 --
718 --
719 -----------------------------------------------------------------------------
719 -----------------------------------------------------------------------------
720 all_apbo_ext : FOR I IN NB_APB_SLAVE-1+5 DOWNTO 5 GENERATE
720 all_apbo_ext : FOR I IN NB_APB_SLAVE-1+5 DOWNTO 5 GENERATE
721 apbo_ext_not_used : IF I /= 5 AND I /= 6 AND I /= 11 AND I /= 15 GENERATE
721 apbo_ext_not_used : IF I /= 5 AND I /= 6 AND I /= 11 AND I /= 15 GENERATE
722 apbo_ext(I) <= apb_none;
722 apbo_ext(I) <= apb_none;
723 END GENERATE apbo_ext_not_used;
723 END GENERATE apbo_ext_not_used;
724 END GENERATE all_apbo_ext;
724 END GENERATE all_apbo_ext;
725
725
726
726
727 all_ahbo_ext : FOR I IN NB_AHB_SLAVE-1+3 DOWNTO 3 GENERATE
727 all_ahbo_ext : FOR I IN NB_AHB_SLAVE-1+3 DOWNTO 3 GENERATE
728 ahbo_s_ext(I) <= ahbs_none;
728 ahbo_s_ext(I) <= ahbs_none;
729 END GENERATE all_ahbo_ext;
729 END GENERATE all_ahbo_ext;
730
730
731 all_ahbo_m_ext : FOR I IN NB_AHB_MASTER-1+1 DOWNTO 1 GENERATE
731 all_ahbo_m_ext : FOR I IN NB_AHB_MASTER-1+1 DOWNTO 1 GENERATE
732 ahbo_m_ext_not_used : IF I /= 1 AND I /= 2 GENERATE
732 ahbo_m_ext_not_used : IF I /= 1 AND I /= 2 GENERATE
733 ahbo_m_ext(I) <= ahbm_none;
733 ahbo_m_ext(I) <= ahbm_none;
734 END GENERATE ahbo_m_ext_not_used;
734 END GENERATE ahbo_m_ext_not_used;
735 END GENERATE all_ahbo_m_ext;
735 END GENERATE all_ahbo_m_ext;
736
736
737 END beh;
737 END beh;
Show file before | Show file after | Hide comments
@@ -1,214 +1,214
1 onerror {resume}
1 onerror {resume}
2 quietly virtual signal -install /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix { /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/rdata(31 downto 0)} data_0
2 quietly virtual signal -install /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix { /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/rdata(31 downto 0)} data_0
3 quietly virtual signal -install /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix { /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/rdata(63 downto 32)} data_1
3 quietly virtual signal -install /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix { /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/rdata(63 downto 32)} data_1
4 quietly virtual signal -install /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix { /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/rdata(95 downto 64)} data_2
4 quietly virtual signal -install /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix { /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/rdata(95 downto 64)} data_2
5 quietly virtual signal -install /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix { /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/rdata(127 downto 96)} data_3
5 quietly virtual signal -install /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix { /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/rdata(127 downto 96)} data_3
6 quietly virtual signal -install /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix { /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/rdata(159 downto 128)} data_4
6 quietly virtual signal -install /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix { /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/rdata(159 downto 128)} data_4
7 quietly virtual signal -install /testbench/data_read_with_timer_f0 { /testbench/data_read_with_timer_f0/data_out(15 downto 0)} f0_0
7 quietly virtual signal -install /testbench/data_read_with_timer_f0 { /testbench/data_read_with_timer_f0/data_out(15 downto 0)} f0_0
8 quietly virtual signal -install /testbench/data_read_with_timer_f0 { /testbench/data_read_with_timer_f0/data_out(31 downto 16)} f0_1
8 quietly virtual signal -install /testbench/data_read_with_timer_f0 { /testbench/data_read_with_timer_f0/data_out(31 downto 16)} f0_1
9 quietly virtual signal -install /testbench/data_read_with_timer_f0 { /testbench/data_read_with_timer_f0/data_out(47 downto 32)} f0_2
9 quietly virtual signal -install /testbench/data_read_with_timer_f0 { /testbench/data_read_with_timer_f0/data_out(47 downto 32)} f0_2
10 quietly virtual signal -install /testbench/data_read_with_timer_f0 { /testbench/data_read_with_timer_f0/data_out(63 downto 48)} f0_4
10 quietly virtual signal -install /testbench/data_read_with_timer_f0 { /testbench/data_read_with_timer_f0/data_out(63 downto 48)} f0_4
11 quietly virtual signal -install /testbench/data_read_with_timer_f0 { /testbench/data_read_with_timer_f0/data_out(79 downto 64)} f0_4001
11 quietly virtual signal -install /testbench/data_read_with_timer_f0 { /testbench/data_read_with_timer_f0/data_out(79 downto 64)} f0_4001
12 quietly WaveActivateNextPane {} 0
12 quietly WaveActivateNextPane {} 0
13 add wave -noupdate -expand -group DATA_GEN_F0 /testbench/data_read_with_timer_f0/data_out_val
13 add wave -noupdate -expand -group DATA_GEN_F0 /testbench/data_read_with_timer_f0/data_out_val
14 add wave -noupdate -expand -group DATA_GEN_F0 /testbench/data_read_with_timer_f0/end_of_file
14 add wave -noupdate -expand -group DATA_GEN_F0 /testbench/data_read_with_timer_f0/end_of_file
15 add wave -noupdate -expand -group DATA_GEN_F0 -label f0_0 -radix decimal /testbench/data_read_with_timer_f0/f0_0
15 add wave -noupdate -expand -group DATA_GEN_F0 -label f0_0 -radix decimal /testbench/data_read_with_timer_f0/f0_0
16 add wave -noupdate -expand -group DATA_GEN_F0 -label f0_1 -radix decimal /testbench/data_read_with_timer_f0/f0_1
16 add wave -noupdate -expand -group DATA_GEN_F0 -label f0_1 -radix decimal /testbench/data_read_with_timer_f0/f0_1
17 add wave -noupdate -expand -group DATA_GEN_F0 -label f0_2 -radix decimal /testbench/data_read_with_timer_f0/f0_2
17 add wave -noupdate -expand -group DATA_GEN_F0 -label f0_2 -radix decimal /testbench/data_read_with_timer_f0/f0_2
18 add wave -noupdate -expand -group DATA_GEN_F0 -label f0_3 -radix decimal /testbench/data_read_with_timer_f0/f0_4
18 add wave -noupdate -expand -group DATA_GEN_F0 -label f0_3 -radix decimal /testbench/data_read_with_timer_f0/f0_4
19 add wave -noupdate -expand -group DATA_GEN_F0 -label f0_4 -radix decimal /testbench/data_read_with_timer_f0/f0_4001
19 add wave -noupdate -expand -group DATA_GEN_F0 -label f0_4 -radix decimal /testbench/data_read_with_timer_f0/f0_4001
20 add wave -noupdate -expand -group DATA_GEN_F0 /testbench/data_read_with_timer_f0/data_out
20 add wave -noupdate -expand -group DATA_GEN_F0 /testbench/data_read_with_timer_f0/data_out
21 add wave -noupdate -expand -group DATA_GEN_F1 /testbench/data_read_with_timer_f1/data_out_val
21 add wave -noupdate -expand -group DATA_GEN_F1 /testbench/data_read_with_timer_f1/data_out_val
22 add wave -noupdate -expand -group DATA_GEN_F1 /testbench/data_read_with_timer_f1/end_of_file
22 add wave -noupdate -expand -group DATA_GEN_F1 /testbench/data_read_with_timer_f1/end_of_file
23 add wave -noupdate -expand -group DATA_GEN_F1 /testbench/data_read_with_timer_f1/data_out
23 add wave -noupdate -expand -group DATA_GEN_F1 /testbench/data_read_with_timer_f1/data_out
24 add wave -noupdate -expand -group DATA_GEN_F2 /testbench/data_read_with_timer_f2/data_out_val
24 add wave -noupdate -expand -group DATA_GEN_F2 /testbench/data_read_with_timer_f2/data_out_val
25 add wave -noupdate -expand -group DATA_GEN_F2 /testbench/data_read_with_timer_f2/end_of_file
25 add wave -noupdate -expand -group DATA_GEN_F2 /testbench/data_read_with_timer_f2/end_of_file
26 add wave -noupdate -expand -group DATA_GEN_F2 /testbench/data_read_with_timer_f2/data_out
26 add wave -noupdate -expand -group DATA_GEN_F2 /testbench/data_read_with_timer_f2/data_out
27 add wave -noupdate -expand -group DMA_interface /testbench/lpp_lfr_ms_1/dma_buffer_addr
27 add wave -noupdate -expand -group DMA_interface /testbench/lpp_lfr_ms_1/dma_buffer_addr
28 add wave -noupdate -expand -group DMA_interface /testbench/lpp_lfr_ms_1/dma_buffer_full
28 add wave -noupdate -expand -group DMA_interface /testbench/lpp_lfr_ms_1/dma_buffer_full
29 add wave -noupdate -expand -group DMA_interface /testbench/lpp_lfr_ms_1/dma_buffer_full_err
29 add wave -noupdate -expand -group DMA_interface /testbench/lpp_lfr_ms_1/dma_buffer_full_err
30 add wave -noupdate -expand -group DMA_interface /testbench/lpp_lfr_ms_1/dma_buffer_length
30 add wave -noupdate -expand -group DMA_interface /testbench/lpp_lfr_ms_1/dma_buffer_length
31 add wave -noupdate -expand -group DMA_interface /testbench/lpp_lfr_ms_1/dma_buffer_new
31 add wave -noupdate -expand -group DMA_interface /testbench/lpp_lfr_ms_1/dma_buffer_new
32 add wave -noupdate -expand -group DMA_interface /testbench/lpp_lfr_ms_1/dma_fifo_burst_valid
32 add wave -noupdate -expand -group DMA_interface /testbench/lpp_lfr_ms_1/dma_fifo_burst_valid
33 add wave -noupdate -expand -group DMA_interface /testbench/lpp_lfr_ms_1/dma_fifo_data
33 add wave -noupdate -expand -group DMA_interface /testbench/lpp_lfr_ms_1/dma_fifo_data
34 add wave -noupdate -expand -group DMA_interface /testbench/lpp_lfr_ms_1/dma_fifo_ren
34 add wave -noupdate -expand -group DMA_interface /testbench/lpp_lfr_ms_1/dma_fifo_ren
35 add wave -noupdate /testbench/dma_ren_counter
35 add wave -noupdate /testbench/dma_ren_counter
36 add wave -noupdate /testbench/dma_output_counter
36 add wave -noupdate /testbench/dma_output_counter
37 add wave -noupdate -expand -group MEM_IN_MS -radix hexadecimal -childformat {{/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(0) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(1) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(2) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(3) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(4) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(5) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(6) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(7) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(8) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(9) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(10) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(11) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(12) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(13) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(14) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(15) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(16) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(17) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(18) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(19) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(20) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(21) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(22) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(23) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(24) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(25) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(26) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(27) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(28) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(29) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(30) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(31) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(32) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(33) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(34) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(35) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(36) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(37) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(38) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(39) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(40) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(41) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(42) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(43) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(44) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(45) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(46) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(47) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(48) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(49) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(50) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(51) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(52) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(53) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(54) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(55) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(56) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(57) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(58) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(59) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(60) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(61) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(62) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(63) -radix hexadecimal} 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{/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(72) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(73) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(74) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(75) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(76) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(77) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(78) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(79) -radix hexadecimal} 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hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(104) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(105) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(106) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(107) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(108) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(109) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(110) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(111) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(112) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(113) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(114) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(115) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(116) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(117) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(118) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(119) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(120) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(121) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(122) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(123) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(124) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(125) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(126) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(127) {-height 15 -radix hexadecimal}} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd
42 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/data_0
42 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/data_0
43 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/ren(0)
43 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/ren(0)
44 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/wen(0)
44 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/wen(0)
45 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/full(0)
45 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/full(0)
46 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/empty(0)
46 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/empty(0)
47 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/ReUse(0)
47 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/ReUse(0)
48 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group fif0_1 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/data_1
48 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group fif0_1 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/data_1
49 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group fif0_1 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/ren(1)
49 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group fif0_1 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/ren(1)
50 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group fif0_1 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/wen(1)
50 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group fif0_1 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/wen(1)
51 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group fif0_1 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/full(1)
51 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group fif0_1 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/full(1)
52 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group fif0_1 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/empty(1)
52 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group fif0_1 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/empty(1)
53 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group fif0_1 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/ReUse(1)
53 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group fif0_1 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/ReUse(1)
54 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_2 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/data_2
54 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_2 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/data_2
55 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_2 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/ren(2)
55 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_2 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/ren(2)
56 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_2 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/wen(2)
56 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_2 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/wen(2)
57 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_2 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/full(2)
57 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_2 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/full(2)
58 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_2 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/empty(2)
58 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_2 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/empty(2)
59 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_2 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/ReUse(2)
59 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_2 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/ReUse(2)
60 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_3 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/data_3
60 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_3 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/data_3
61 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_3 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/ren(3)
61 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_3 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/ren(3)
62 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_3 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/wen(3)
62 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_3 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/wen(3)
63 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_3 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/full(3)
63 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_3 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/full(3)
64 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_3 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/empty(3)
64 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_3 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/empty(3)
65 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_3 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/ReUse(3)
65 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_3 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/ReUse(3)
66 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_4 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/data_4
66 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_4 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/data_4
67 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_4 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/ren(4)
67 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_4 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/ren(4)
68 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_4 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/wen(4)
68 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_4 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/wen(4)
69 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_4 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/full(4)
69 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_4 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/full(4)
70 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_4 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/empty(4)
70 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_4 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/empty(4)
71 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_4 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/ReUse(4)
71 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_4 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/ReUse(4)
72 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(0)/Mem_Out_SpectralMatrix_I/full_threshold
72 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(0)/Mem_Out_SpectralMatrix_I/full_threshold
73 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(0)/Mem_Out_SpectralMatrix_I/full
73 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(0)/Mem_Out_SpectralMatrix_I/full
74 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(0)/Mem_Out_SpectralMatrix_I/empty
74 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(0)/Mem_Out_SpectralMatrix_I/empty
75 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(0)/Mem_Out_SpectralMatrix_I/full_almost
75 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(0)/Mem_Out_SpectralMatrix_I/full_almost
76 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(0)/Mem_Out_SpectralMatrix_I/empty_threshold
76 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(0)/Mem_Out_SpectralMatrix_I/empty_threshold
77 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(0)/Mem_Out_SpectralMatrix_I/wen
77 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(0)/Mem_Out_SpectralMatrix_I/wen
78 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(0)/Mem_Out_SpectralMatrix_I/wdata
78 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(0)/Mem_Out_SpectralMatrix_I/wdata
79 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(0)/Mem_Out_SpectralMatrix_I/ren
79 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(0)/Mem_Out_SpectralMatrix_I/ren
80 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(0)/Mem_Out_SpectralMatrix_I/rdata
80 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(0)/Mem_Out_SpectralMatrix_I/rdata
81 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(0)/Mem_Out_SpectralMatrix_I/run
81 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(0)/Mem_Out_SpectralMatrix_I/run
82 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(0)/Mem_Out_SpectralMatrix_I/reUse
82 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(0)/Mem_Out_SpectralMatrix_I/reUse
83 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_1 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/full_threshold
83 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_1 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/full_threshold
84 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_1 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/full
84 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_1 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/full
85 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_1 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/empty
85 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_1 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/empty
86 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_1 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/full_almost
86 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_1 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/full_almost
87 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_1 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/empty_threshold
87 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_1 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/empty_threshold
88 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_1 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/wen
88 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_1 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/wen
89 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_1 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/wdata
89 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_1 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/wdata
90 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_1 -radix decimal -childformat {{/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(31) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(30) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(29) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(28) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(27) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(26) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(25) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(24) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(23) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(22) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(21) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(20) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(19) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(18) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(17) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(16) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(15) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(14) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(13) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(12) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(11) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(10) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(9) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(8) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(7) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(6) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(5) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(4) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(3) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(2) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(1) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(0) -radix hexadecimal}} -subitemconfig {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(31) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(30) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(29) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(28) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(27) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(26) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(25) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(24) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(23) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(22) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(21) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(20) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(19) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(18) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(17) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(16) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(15) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(14) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(13) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(12) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(11) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(10) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(9) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(8) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(7) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(6) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(5) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(4) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(3) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(2) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(1) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(0) {-height 15 -radix hexadecimal}} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata
90 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_1 -radix decimal -childformat {{/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(31) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(30) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(29) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(28) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(27) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(26) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(25) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(24) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(23) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(22) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(21) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(20) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(19) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(18) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(17) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(16) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(15) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(14) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(13) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(12) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(11) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(10) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(9) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(8) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(7) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(6) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(5) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(4) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(3) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(2) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(1) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(0) -radix hexadecimal}} -subitemconfig {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(31) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(30) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(29) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(28) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(27) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(26) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(25) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(24) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(23) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(22) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(21) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(20) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(19) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(18) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(17) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(16) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(15) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(14) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(13) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(12) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(11) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(10) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(9) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(8) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(7) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(6) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(5) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(4) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(3) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(2) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(1) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(0) {-height 15 -radix hexadecimal}} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata
91 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_1 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/ren
91 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_1 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/ren
92 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_1 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/run
92 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_1 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/run
93 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_1 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/reUse
93 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_1 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/reUse
94 add wave -noupdate -radix hexadecimal /testbench/lpp_lfr_ms_1/dma_fifo_data
94 add wave -noupdate -radix hexadecimal /testbench/lpp_lfr_ms_1/dma_fifo_data
95 add wave -noupdate -expand -group ALU_MS -radix decimal /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/RES
95 add wave -noupdate -expand -group ALU_MS -radix decimal /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/RES
96 add wave -noupdate -expand -group ALU_MS -radix decimal -childformat {{/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(15) -radix decimal} {/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(14) -radix decimal} {/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(13) -radix decimal} {/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(12) -radix decimal} {/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(11) -radix decimal} {/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(10) -radix decimal} {/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(9) -radix decimal} {/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(8) -radix decimal} {/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(7) -radix decimal} {/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(6) -radix decimal} {/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(5) -radix decimal} {/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(4) -radix decimal} {/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(3) -radix decimal} {/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(2) -radix decimal} {/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(1) -radix decimal} {/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(0) -radix decimal}} -subitemconfig {/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(15) {-height 15 -radix decimal} /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(14) {-height 15 -radix decimal} /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(13) {-height 15 -radix decimal} /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(12) {-height 15 -radix decimal} /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(11) {-height 15 -radix decimal} /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(10) {-height 15 -radix decimal} /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(9) {-height 15 -radix decimal} /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(8) {-height 15 -radix decimal} /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(7) {-height 15 -radix decimal} /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(6) {-height 15 -radix decimal} /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(5) {-height 15 -radix decimal} /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(4) {-height 15 -radix decimal} /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(3) {-height 15 -radix decimal} /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(2) {-height 15 -radix decimal} /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(1) {-height 15 -radix decimal} /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(0) {-height 15 -radix decimal}} /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2
96 add wave -noupdate -expand -group ALU_MS -radix decimal -childformat {{/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(15) -radix decimal} {/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(14) -radix decimal} {/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(13) -radix decimal} {/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(12) -radix decimal} {/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(11) -radix decimal} {/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(10) -radix decimal} {/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(9) -radix decimal} {/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(8) -radix decimal} {/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(7) -radix decimal} {/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(6) -radix decimal} {/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(5) -radix decimal} {/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(4) -radix decimal} {/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(3) -radix decimal} {/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(2) -radix decimal} {/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(1) -radix decimal} {/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(0) -radix decimal}} -subitemconfig {/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(15) {-height 15 -radix decimal} /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(14) {-height 15 -radix decimal} /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(13) {-height 15 -radix decimal} /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(12) {-height 15 -radix decimal} /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(11) {-height 15 -radix decimal} /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(10) {-height 15 -radix decimal} /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(9) {-height 15 -radix decimal} /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(8) {-height 15 -radix decimal} /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(7) {-height 15 -radix decimal} /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(6) {-height 15 -radix decimal} /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(5) {-height 15 -radix decimal} /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(4) {-height 15 -radix decimal} /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(3) {-height 15 -radix decimal} /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(2) {-height 15 -radix decimal} /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(1) {-height 15 -radix decimal} /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(0) {-height 15 -radix decimal}} /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2
97 add wave -noupdate -expand -group ALU_MS -radix decimal /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP1
97 add wave -noupdate -expand -group ALU_MS -radix decimal /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP1
98 add wave -noupdate -expand -group ALU_MS -radix hexadecimal /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/comp
98 add wave -noupdate -expand -group ALU_MS -radix hexadecimal /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/comp
99 add wave -noupdate -expand -group ALU_MS -radix hexadecimal /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/ctrl
99 add wave -noupdate -expand -group ALU_MS -radix hexadecimal /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/ctrl
100 add wave -noupdate /testbench/lpp_lfr_ms_1/MS_control_1/state
100 add wave -noupdate /testbench/lpp_lfr_ms_1/MS_control_1/state
101 add wave -noupdate /testbench/lpp_lfr_ms_1/MS_calculation_1/state
101 add wave -noupdate /testbench/lpp_lfr_ms_1/MS_calculation_1/state
102 add wave -noupdate -radix hexadecimal /testbench/lpp_lfr_ms_1/MS_calculation_1/fifo_in_data
102 add wave -noupdate -radix hexadecimal /testbench/lpp_lfr_ms_1/MS_calculation_1/fifo_in_data
103 add wave -noupdate /testbench/lpp_lfr_ms_1/MS_calculation_1/fifo_in_ren
103 add wave -noupdate /testbench/lpp_lfr_ms_1/MS_calculation_1/fifo_in_ren
104 add wave -noupdate /testbench/lpp_lfr_ms_1/MEM_OUT_SM_Full
104 add wave -noupdate /testbench/lpp_lfr_ms_1/MEM_OUT_SM_Full
105 add wave -noupdate /testbench/lpp_lfr_ms_1/MEM_OUT_SM_Full_s
105 add wave -noupdate /testbench/lpp_lfr_ms_1/MEM_OUT_SM_Full_s
106 add wave -noupdate /testbench/lpp_lfr_ms_1/SM_correlation_done
106 add wave -noupdate /testbench/lpp_lfr_ms_1/SM_correlation_done
107 add wave -noupdate /testbench/lpp_lfr_ms_1/SM_correlation_done_reg1
107 add wave -noupdate /testbench/lpp_lfr_ms_1/SM_correlation_done_reg1
108 add wave -noupdate /testbench/lpp_lfr_ms_1/SM_correlation_done_reg2
108 add wave -noupdate /testbench/lpp_lfr_ms_1/SM_correlation_done_reg2
109 add wave -noupdate /testbench/lpp_lfr_ms_1/SM_correlation_done_reg3
109 add wave -noupdate /testbench/lpp_lfr_ms_1/SM_correlation_done_reg3
110 add wave -noupdate /testbench/lpp_lfr_ms_1/current_matrix_wait_empty
110 add wave -noupdate /testbench/lpp_lfr_ms_1/current_matrix_wait_empty
111 add wave -noupdate /testbench/lpp_lfr_ms_1/current_matrix_write
111 add wave -noupdate /testbench/lpp_lfr_ms_1/current_matrix_write
112 add wave -noupdate /testbench/lpp_lfr_ms_1/MEM_OUT_SM_Empty
112 add wave -noupdate /testbench/lpp_lfr_ms_1/MEM_OUT_SM_Empty
113 add wave -noupdate /testbench/lpp_lfr_ms_1/dma_fifo_ren
113 add wave -noupdate /testbench/lpp_lfr_ms_1/dma_fifo_ren
114 add wave -noupdate /testbench/lpp_lfr_ms_1/addr_matrix_f2
114 add wave -noupdate /testbench/lpp_lfr_ms_1/addr_matrix_f2
115 add wave -noupdate /testbench/lpp_lfr_ms_1/addr_matrix_f1
115 add wave -noupdate /testbench/lpp_lfr_ms_1/addr_matrix_f1
116 add wave -noupdate /testbench/lpp_lfr_ms_1/length_matrix_f2
116 add wave -noupdate /testbench/lpp_lfr_ms_1/length_matrix_f2
117 add wave -noupdate /testbench/lpp_lfr_ms_1/dma_buffer_full
117 add wave -noupdate /testbench/lpp_lfr_ms_1/dma_buffer_full
118 add wave -noupdate /testbench/lpp_lfr_ms_1/dma_buffer_full_err
118 add wave -noupdate /testbench/lpp_lfr_ms_1/dma_buffer_full_err
119 add wave -noupdate /testbench/lpp_lfr_ms_1/addr_matrix_f0
119 add wave -noupdate /testbench/lpp_lfr_ms_1/addr_matrix_f0
120 add wave -noupdate /testbench/lpp_lfr_ms_1/status_ready_matrix_f2
120 add wave -noupdate /testbench/lpp_lfr_ms_1/status_ready_matrix_f2
121 add wave -noupdate /testbench/lpp_lfr_ms_1/status_ready_matrix_f1
121 add wave -noupdate /testbench/lpp_lfr_ms_1/status_ready_matrix_f1
122 add wave -noupdate /testbench/lpp_lfr_ms_1/status_ready_matrix_f0
122 add wave -noupdate /testbench/lpp_lfr_ms_1/status_ready_matrix_f0
123 add wave -noupdate /testbench/lpp_lfr_ms_1/current_matrix_write
123 add wave -noupdate /testbench/lpp_lfr_ms_1/current_matrix_write
124 add wave -noupdate /testbench/lpp_lfr_ms_1/matrix_time_f2
124 add wave -noupdate /testbench/lpp_lfr_ms_1/matrix_time_f2
125 add wave -noupdate /testbench/lpp_lfr_ms_1/matrix_time_f1
125 add wave -noupdate /testbench/lpp_lfr_ms_1/matrix_time_f1
126 add wave -noupdate /testbench/lpp_lfr_ms_1/matrix_time_f0
126 add wave -noupdate /testbench/lpp_lfr_ms_1/matrix_time_f0
127 add wave -noupdate /testbench/lpp_lfr_ms_1/error_input_fifo_write
127 add wave -noupdate /testbench/lpp_lfr_ms_1/error_input_fifo_write
128 add wave -noupdate /testbench/lpp_lfr_ms_1/error_buffer_full
128 add wave -noupdate /testbench/lpp_lfr_ms_1/error_buffer_full
129 add wave -noupdate /testbench/lpp_lfr_ms_1/ready_matrix_f2
129 add wave -noupdate /testbench/lpp_lfr_ms_1/ready_matrix_f2
130 add wave -noupdate /testbench/lpp_lfr_ms_1/ready_matrix_f1
130 add wave -noupdate /testbench/lpp_lfr_ms_1/ready_matrix_f1
131 add wave -noupdate /testbench/lpp_lfr_ms_1/ready_matrix_f0
131 add wave -noupdate /testbench/lpp_lfr_ms_1/ready_matrix_f0
132 add wave -noupdate /testbench/lpp_lfr_ms_1/dma_buffer_length
132 add wave -noupdate /testbench/lpp_lfr_ms_1/dma_buffer_length
133 add wave -noupdate /testbench/lpp_lfr_ms_1/dma_buffer_addr
133 add wave -noupdate /testbench/lpp_lfr_ms_1/dma_buffer_addr
134 add wave -noupdate /testbench/lpp_lfr_ms_1/dma_buffer_new
134 add wave -noupdate /testbench/lpp_lfr_ms_1/dma_buffer_new
135 add wave -noupdate /testbench/lpp_lfr_ms_1/dma_fifo_data
135 add wave -noupdate /testbench/lpp_lfr_ms_1/dma_fifo_data
136 add wave -noupdate /testbench/lpp_lfr_ms_1/dma_fifo_burst_valid
136 add wave -noupdate /testbench/lpp_lfr_ms_1/dma_fifo_burst_valid
137 add wave -noupdate /testbench/lpp_lfr_ms_1/debug_vector
137 add wave -noupdate /testbench/lpp_lfr_ms_1/debug_vector
138 add wave -noupdate /testbench/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/state
138 add wave -noupdate /testbench/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/state
139 add wave -noupdate /testbench/lpp_lfr_ms_1/fifo_0_ready
139 add wave -noupdate /testbench/lpp_lfr_ms_1/fifo_0_ready
140 add wave -noupdate /testbench/lpp_lfr_ms_1/fifo_1_ready
140 add wave -noupdate /testbench/lpp_lfr_ms_1/fifo_1_ready
141 add wave -noupdate /testbench/lpp_lfr_ms_1/fifo_ongoing
141 add wave -noupdate /testbench/lpp_lfr_ms_1/fifo_ongoing
142 add wave -noupdate /testbench/lpp_lfr_ms_1/status_component_fifo_0
142 add wave -noupdate /testbench/lpp_lfr_ms_1/status_component_fifo_0
143 add wave -noupdate /testbench/lpp_lfr_ms_1/status_component_fifo_1
143 add wave -noupdate /testbench/lpp_lfr_ms_1/status_component_fifo_1
144 add wave -noupdate /testbench/lpp_lfr_ms_1/status_component_fifo_0_end
144 add wave -noupdate /testbench/lpp_lfr_ms_1/status_component_fifo_0_end
145 add wave -noupdate /testbench/lpp_lfr_ms_1/status_component_fifo_1_end
145 add wave -noupdate /testbench/lpp_lfr_ms_1/status_component_fifo_1_end
146 add wave -noupdate /testbench/lpp_lfr_ms_1/MS_calculation_1/state
146 add wave -noupdate /testbench/lpp_lfr_ms_1/MS_calculation_1/state
147 add wave -noupdate /testbench/lpp_lfr_ms_1/MS_calculation_1/fifo_in_empty
147 add wave -noupdate /testbench/lpp_lfr_ms_1/MS_calculation_1/fifo_in_empty
148 add wave -noupdate /testbench/lpp_lfr_ms_1/MS_calculation_1/fifo_in_empty_reg
148 add wave -noupdate /testbench/lpp_lfr_ms_1/MS_calculation_1/fifo_in_empty_reg
149 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/start_date
149 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/start_date
150 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/coarse_time
150 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/coarse_time
151 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/sample_f0_wen
151 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/sample_f0_wen
152 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/sample_f0_wdata
152 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/sample_f0_wdata
153 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/sample_f1_wen
153 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/sample_f1_wen
154 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/sample_f1_wdata
154 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/sample_f1_wdata
155 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/sample_f2_wen
155 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/sample_f2_wen
156 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/sample_f2_wdata
156 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/sample_f2_wdata
157 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/length_matrix_f1
157 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/length_matrix_f1
158 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/length_matrix_f0
158 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/length_matrix_f0
159 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/dma_fifo_ren
159 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/dma_fifo_ren
160 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/addr_matrix_f2
160 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/addr_matrix_f2
161 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/addr_matrix_f1
161 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/addr_matrix_f1
162 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/length_matrix_f2
162 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/length_matrix_f2
163 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/dma_buffer_full
163 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/dma_buffer_full
164 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/dma_buffer_full_err
164 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/dma_buffer_full_err
165 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/addr_matrix_f0
165 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/addr_matrix_f0
166 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/status_ready_matrix_f2
166 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/status_ready_matrix_f2
167 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/status_ready_matrix_f1
167 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/status_ready_matrix_f1
168 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/status_ready_matrix_f0
168 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/status_ready_matrix_f0
169 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/matrix_time_f2
169 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/matrix_time_f2
170 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/matrix_time_f1
170 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/matrix_time_f1
171 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/matrix_time_f0
171 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/matrix_time_f0
172 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/error_input_fifo_write
172 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/error_input_fifo_write
173 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/error_buffer_full
173 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/error_buffer_full
174 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/ready_matrix_f2
174 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/ready_matrix_f2
175 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/ready_matrix_f1
175 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/ready_matrix_f1
176 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/ready_matrix_f0
176 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/ready_matrix_f0
177 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/dma_buffer_length
177 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/dma_buffer_length
178 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/dma_buffer_addr
178 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/dma_buffer_addr
179 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/dma_buffer_new
179 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/dma_buffer_new
180 add wave -noupdate -expand -group TOP_IN_OUT -radix decimal /testbench/lpp_lfr_ms_1/dma_fifo_data
180 add wave -noupdate -expand -group TOP_IN_OUT -radix decimal /testbench/lpp_lfr_ms_1/dma_fifo_data
181 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/dma_fifo_burst_valid
181 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/dma_fifo_burst_valid
182 add wave -noupdate -expand -group FFT /testbench/lpp_lfr_ms_1/lpp_lfr_ms_FFT_1/fft_pong
182 add wave -noupdate -expand -group FFT /testbench/lpp_lfr_ms_1/lpp_lfr_ms_FFT_1/fft_pong
183 add wave -noupdate -expand -group FFT /testbench/lpp_lfr_ms_1/lpp_lfr_ms_FFT_1/fft_ready
183 add wave -noupdate -expand -group FFT /testbench/lpp_lfr_ms_1/lpp_lfr_ms_FFT_1/fft_ready
184 add wave -noupdate -expand -group FFT -expand -group IN -format Analog-Step -height 74 -max 4096.0 -min -1800.0 -radix decimal /testbench/lpp_lfr_ms_1/lpp_lfr_ms_FFT_1/sample_data
184 add wave -noupdate -expand -group FFT -expand -group IN -format Analog-Step -height 74 -max 4096.0 -min -1800.0 -radix decimal /testbench/lpp_lfr_ms_1/lpp_lfr_ms_FFT_1/sample_data
185 add wave -noupdate -expand -group FFT -expand -group IN /testbench/lpp_lfr_ms_1/lpp_lfr_ms_FFT_1/sample_load
185 add wave -noupdate -expand -group FFT -expand -group IN /testbench/lpp_lfr_ms_1/lpp_lfr_ms_FFT_1/sample_load
186 add wave -noupdate -expand -group FFT -expand -group IN /testbench/lpp_lfr_ms_1/lpp_lfr_ms_FFT_1/fft_read
186 add wave -noupdate -expand -group FFT -expand -group IN /testbench/lpp_lfr_ms_1/lpp_lfr_ms_FFT_1/fft_read
187 add wave -noupdate -expand -group FFT -expand -group IN /testbench/lpp_lfr_ms_1/lpp_lfr_ms_FFT_1/sample_valid
187 add wave -noupdate -expand -group FFT -expand -group IN /testbench/lpp_lfr_ms_1/lpp_lfr_ms_FFT_1/sample_valid
188 add wave -noupdate -expand -group FFT -expand -group OUT -radix decimal /testbench/lpp_lfr_ms_1/lpp_lfr_ms_FFT_1/fft_data_im
188 add wave -noupdate -expand -group FFT -expand -group OUT -format Analog-Step -height 74 -max 17.0 -min -17.0 -radix decimal /testbench/lpp_lfr_ms_1/lpp_lfr_ms_FFT_1/fft_data_im
189 add wave -noupdate -expand -group FFT -expand -group OUT -radix decimal /testbench/lpp_lfr_ms_1/lpp_lfr_ms_FFT_1/fft_data_re
189 add wave -noupdate -expand -group FFT -expand -group OUT -format Analog-Step -height 74 -max 4660.0 -min -1.0 -radix decimal /testbench/lpp_lfr_ms_1/lpp_lfr_ms_FFT_1/fft_data_re
190 add wave -noupdate -expand -group FFT -expand -group OUT /testbench/lpp_lfr_ms_1/lpp_lfr_ms_FFT_1/fft_data_valid
190 add wave -noupdate -expand -group FFT -expand -group OUT /testbench/lpp_lfr_ms_1/lpp_lfr_ms_FFT_1/fft_data_valid
191 add wave -noupdate /testbench/lpp_lfr_ms_1/sample_valid
191 add wave -noupdate /testbench/lpp_lfr_ms_1/sample_valid
192 add wave -noupdate /testbench/lpp_lfr_ms_1/sample_valid_delay
192 add wave -noupdate /testbench/lpp_lfr_ms_1/sample_valid_delay
193 add wave -noupdate /testbench/lpp_lfr_ms_1/sample_valid_r
193 add wave -noupdate /testbench/lpp_lfr_ms_1/sample_valid_r
194 add wave -noupdate /testbench/lpp_lfr_ms_1/state_fsm_load_FFT
194 add wave -noupdate /testbench/lpp_lfr_ms_1/state_fsm_load_FFT
195 add wave -noupdate -expand /testbench/lpp_lfr_ms_1/sample_f0_A_ren
195 add wave -noupdate /testbench/lpp_lfr_ms_1/sample_f0_A_ren
196 add wave -noupdate /testbench/lpp_lfr_ms_1/sample_f0_B_ren
196 add wave -noupdate /testbench/lpp_lfr_ms_1/sample_f0_B_ren
197 TreeUpdate [SetDefaultTree]
197 TreeUpdate [SetDefaultTree]
198 WaveRestoreCursors {WDATA_1 {10541340000 ps} 1} {WDATA_2 {10541500000 ps} 1} {WDATA_8 {10542460000 ps} 1} {WDATA_16 {10543740000 ps} 1} {{Cursor 9} {10490580000 ps} 0} {{Cursor 10} {6346220000 ps} 0}
198 WaveRestoreCursors {WDATA_1 {10541340000 ps} 1} {WDATA_2 {10541500000 ps} 1} {WDATA_8 {10542460000 ps} 1} {WDATA_16 {10543740000 ps} 1} {{Cursor 9} {91072272990 ps} 0} {{Cursor 10} {62824940000 ps} 0} {{Cursor 7} {62825020000 ps} 0}
199 quietly wave cursor active 5
199 quietly wave cursor active 7
200 configure wave -namecolwidth 573
200 configure wave -namecolwidth 573
201 configure wave -valuecolwidth 108
201 configure wave -valuecolwidth 108
202 configure wave -justifyvalue left
202 configure wave -justifyvalue left
203 configure wave -signalnamewidth 0
203 configure wave -signalnamewidth 0
204 configure wave -snapdistance 10
204 configure wave -snapdistance 10
205 configure wave -datasetprefix 0
205 configure wave -datasetprefix 0
206 configure wave -rowmargin 4
206 configure wave -rowmargin 4
207 configure wave -childrowmargin 2
207 configure wave -childrowmargin 2
208 configure wave -gridoffset 0
208 configure wave -gridoffset 0
209 configure wave -gridperiod 1
209 configure wave -gridperiod 1
210 configure wave -griddelta 40
210 configure wave -griddelta 40
211 configure wave -timeline 0
211 configure wave -timeline 0
212 configure wave -timelineunits ns
212 configure wave -timelineunits ns
213 update
213 update
214 WaveRestoreZoom {10489250172 ps} {10491702980 ps}
214 WaveRestoreZoom {62467271961 ps} {63182321178 ps}
Show file before | Show file after | Hide comments
@@ -1,1248 +1,1250
1 LIBRARY ieee;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
2 USE ieee.std_logic_1164.ALL;
3 USE ieee.numeric_std.ALL;
3 USE ieee.numeric_std.ALL;
4
4
5
5
6 LIBRARY lpp;
6 LIBRARY lpp;
7 USE lpp.lpp_memory.ALL;
7 USE lpp.lpp_memory.ALL;
8 USE lpp.iir_filter.ALL;
8 USE lpp.iir_filter.ALL;
9 USE lpp.spectral_matrix_package.ALL;
9 USE lpp.spectral_matrix_package.ALL;
10 USE lpp.lpp_dma_pkg.ALL;
10 USE lpp.lpp_dma_pkg.ALL;
11 USE lpp.lpp_Header.ALL;
11 USE lpp.lpp_Header.ALL;
12 USE lpp.lpp_matrix.ALL;
12 USE lpp.lpp_matrix.ALL;
13 USE lpp.lpp_matrix.ALL;
13 USE lpp.lpp_matrix.ALL;
14 USE lpp.lpp_lfr_pkg.ALL;
14 USE lpp.lpp_lfr_pkg.ALL;
15 USE lpp.lpp_fft.ALL;
15 USE lpp.lpp_fft.ALL;
16 USE lpp.fft_components.ALL;
16 USE lpp.fft_components.ALL;
17
17
18 ENTITY lpp_lfr_ms IS
18 ENTITY lpp_lfr_ms IS
19 GENERIC (
19 GENERIC (
20 Mem_use : INTEGER := use_RAM
20 Mem_use : INTEGER := use_RAM
21 );
21 );
22 PORT (
22 PORT (
23 clk : IN STD_LOGIC;
23 clk : IN STD_LOGIC;
24 rstn : IN STD_LOGIC;
24 rstn : IN STD_LOGIC;
25 run : IN STD_LOGIC;
25 run : IN STD_LOGIC;
26
26
27 ---------------------------------------------------------------------------
27 ---------------------------------------------------------------------------
28 -- DATA INPUT
28 -- DATA INPUT
29 ---------------------------------------------------------------------------
29 ---------------------------------------------------------------------------
30 start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
30 start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
31 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
31 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
32 --fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
32 --fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
33 --
33 --
34 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
34 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
35 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
35 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
36 sample_f0_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
36 sample_f0_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
37 --
37 --
38 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
38 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
39 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
39 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
40 sample_f1_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
40 sample_f1_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
41 --
41 --
42 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
42 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
43 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
43 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
44 sample_f2_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
44 sample_f2_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
45
45
46 ---------------------------------------------------------------------------
46 ---------------------------------------------------------------------------
47 -- DMA
47 -- DMA
48 ---------------------------------------------------------------------------
48 ---------------------------------------------------------------------------
49 dma_fifo_burst_valid: OUT STD_LOGIC; --TODO
49 dma_fifo_burst_valid: OUT STD_LOGIC; --TODO
50 dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --TODO
50 dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --TODO
51 dma_fifo_ren : IN STD_LOGIC; --TODO
51 dma_fifo_ren : IN STD_LOGIC; --TODO
52 dma_buffer_new : OUT STD_LOGIC; --TODOx
52 dma_buffer_new : OUT STD_LOGIC; --TODOx
53 dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --TODO
53 dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --TODO
54 dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); --TODO
54 dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); --TODO
55 dma_buffer_full : IN STD_LOGIC; --TODO
55 dma_buffer_full : IN STD_LOGIC; --TODO
56 dma_buffer_full_err : IN STD_LOGIC; --TODO
56 dma_buffer_full_err : IN STD_LOGIC; --TODO
57
57
58 -- Reg out
58 -- Reg out
59 ready_matrix_f0 : OUT STD_LOGIC; -- TODO
59 ready_matrix_f0 : OUT STD_LOGIC; -- TODO
60 ready_matrix_f1 : OUT STD_LOGIC; -- TODO
60 ready_matrix_f1 : OUT STD_LOGIC; -- TODO
61 ready_matrix_f2 : OUT STD_LOGIC; -- TODO
61 ready_matrix_f2 : OUT STD_LOGIC; -- TODO
62 -- error_bad_component_error : OUT STD_LOGIC; -- TODO
62 -- error_bad_component_error : OUT STD_LOGIC; -- TODO
63 error_buffer_full : OUT STD_LOGIC; -- TODO
63 error_buffer_full : OUT STD_LOGIC; -- TODO
64 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
64 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
65
65
66 -- Reg In
66 -- Reg In
67 status_ready_matrix_f0 : IN STD_LOGIC; -- TODO
67 status_ready_matrix_f0 : IN STD_LOGIC; -- TODO
68 status_ready_matrix_f1 : IN STD_LOGIC; -- TODO
68 status_ready_matrix_f1 : IN STD_LOGIC; -- TODO
69 status_ready_matrix_f2 : IN STD_LOGIC; -- TODO
69 status_ready_matrix_f2 : IN STD_LOGIC; -- TODO
70
70
71 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
71 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
72 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
72 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
73 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
73 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
74
74
75 length_matrix_f0 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); -- TODO
75 length_matrix_f0 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); -- TODO
76 length_matrix_f1 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); -- TODO
76 length_matrix_f1 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); -- TODO
77 length_matrix_f2 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); -- TODO
77 length_matrix_f2 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); -- TODO
78
78
79 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
79 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
80 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
80 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
81 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
81 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
82 ---------------------------------------------------------------------------
82 ---------------------------------------------------------------------------
83 debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
83 debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
84 );
84 );
85 END;
85 END;
86
86
87 ARCHITECTURE Behavioral OF lpp_lfr_ms IS
87 ARCHITECTURE Behavioral OF lpp_lfr_ms IS
88
88
89 SIGNAL sample_f0_A_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
89 SIGNAL sample_f0_A_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
90 SIGNAL sample_f0_A_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
90 SIGNAL sample_f0_A_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
91 SIGNAL sample_f0_A_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
91 SIGNAL sample_f0_A_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
92 SIGNAL sample_f0_A_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
92 SIGNAL sample_f0_A_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
93 SIGNAL sample_f0_A_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
93 SIGNAL sample_f0_A_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
94
94
95 SIGNAL sample_f0_B_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
95 SIGNAL sample_f0_B_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
96 SIGNAL sample_f0_B_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
96 SIGNAL sample_f0_B_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
97 SIGNAL sample_f0_B_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
97 SIGNAL sample_f0_B_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
98 SIGNAL sample_f0_B_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
98 SIGNAL sample_f0_B_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
99 SIGNAL sample_f0_B_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
99 SIGNAL sample_f0_B_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
100
100
101 SIGNAL sample_f1_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
101 SIGNAL sample_f1_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
102 SIGNAL sample_f1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
102 SIGNAL sample_f1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
103 SIGNAL sample_f1_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
103 SIGNAL sample_f1_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
104 SIGNAL sample_f1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
104 SIGNAL sample_f1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
105
105
106 SIGNAL sample_f1_almost_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
106 SIGNAL sample_f1_almost_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
107
107
108 SIGNAL sample_f2_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
108 SIGNAL sample_f2_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
109 SIGNAL sample_f2_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
109 SIGNAL sample_f2_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
110 SIGNAL sample_f2_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
110 SIGNAL sample_f2_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
111 SIGNAL sample_f2_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
111 SIGNAL sample_f2_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
112
112
113 SIGNAL error_wen_f0 : STD_LOGIC;
113 SIGNAL error_wen_f0 : STD_LOGIC;
114 SIGNAL error_wen_f1 : STD_LOGIC;
114 SIGNAL error_wen_f1 : STD_LOGIC;
115 SIGNAL error_wen_f2 : STD_LOGIC;
115 SIGNAL error_wen_f2 : STD_LOGIC;
116
116
117 SIGNAL one_sample_f1_full : STD_LOGIC;
117 SIGNAL one_sample_f1_full : STD_LOGIC;
118 SIGNAL one_sample_f1_wen : STD_LOGIC;
118 SIGNAL one_sample_f1_wen : STD_LOGIC;
119 SIGNAL one_sample_f2_full : STD_LOGIC;
119 SIGNAL one_sample_f2_full : STD_LOGIC;
120 SIGNAL one_sample_f2_wen : STD_LOGIC;
120 SIGNAL one_sample_f2_wen : STD_LOGIC;
121
121
122 -----------------------------------------------------------------------------
122 -----------------------------------------------------------------------------
123 -- FSM / SWITCH SELECT CHANNEL
123 -- FSM / SWITCH SELECT CHANNEL
124 -----------------------------------------------------------------------------
124 -----------------------------------------------------------------------------
125 TYPE fsm_select_channel IS (IDLE, SWITCH_F0_A, SWITCH_F0_B, SWITCH_F1, SWITCH_F2);
125 TYPE fsm_select_channel IS (IDLE, SWITCH_F0_A, SWITCH_F0_B, SWITCH_F1, SWITCH_F2);
126 SIGNAL state_fsm_select_channel : fsm_select_channel;
126 SIGNAL state_fsm_select_channel : fsm_select_channel;
127 -- SIGNAL pre_state_fsm_select_channel : fsm_select_channel;
127 -- SIGNAL pre_state_fsm_select_channel : fsm_select_channel;
128 SIGNAL select_channel : STD_LOGIC_VECTOR(1 DOWNTO 0);
128 SIGNAL select_channel : STD_LOGIC_VECTOR(1 DOWNTO 0);
129 SIGNAL select_channel_reg : STD_LOGIC_VECTOR(1 DOWNTO 0);
129 SIGNAL select_channel_reg : STD_LOGIC_VECTOR(1 DOWNTO 0);
130
130
131 SIGNAL sample_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
131 SIGNAL sample_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
132 SIGNAL sample_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
132 SIGNAL sample_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
133 SIGNAL sample_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
133 SIGNAL sample_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
134 SIGNAL sample_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
134 SIGNAL sample_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
135
135
136 -----------------------------------------------------------------------------
136 -----------------------------------------------------------------------------
137 -- FSM LOAD FFT
137 -- FSM LOAD FFT
138 -----------------------------------------------------------------------------
138 -----------------------------------------------------------------------------
139 TYPE fsm_load_FFT IS (IDLE, FIFO_1, FIFO_2, FIFO_3, FIFO_4, FIFO_5, WAIT_STATE, WAIT_STATE_2);
139 TYPE fsm_load_FFT IS (IDLE, FIFO_1, FIFO_2, FIFO_3, FIFO_4, FIFO_5, WAIT_STATE, WAIT_STATE_2);
140 SIGNAL state_fsm_load_FFT : fsm_load_FFT;
140 SIGNAL state_fsm_load_FFT : fsm_load_FFT;
141 SIGNAL next_state_fsm_load_FFT : fsm_load_FFT;
141 SIGNAL next_state_fsm_load_FFT : fsm_load_FFT;
142 SIGNAL select_fifo : STD_LOGIC_VECTOR(2 DOWNTO 0);
142 SIGNAL select_fifo : STD_LOGIC_VECTOR(2 DOWNTO 0);
143 SIGNAL select_fifo_reg : STD_LOGIC_VECTOR(2 DOWNTO 0);
143 SIGNAL select_fifo_reg : STD_LOGIC_VECTOR(2 DOWNTO 0);
144
144
145 SIGNAL sample_ren_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
145 SIGNAL sample_ren_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
146 SIGNAL sample_load : STD_LOGIC;
146 SIGNAL sample_load : STD_LOGIC;
147 SIGNAL sample_valid : STD_LOGIC;
147 SIGNAL sample_valid : STD_LOGIC;
148 SIGNAL sample_valid_r : STD_LOGIC;
148 SIGNAL sample_valid_r : STD_LOGIC;
149 SIGNAL sample_data : STD_LOGIC_VECTOR(15 DOWNTO 0);
149 SIGNAL sample_data : STD_LOGIC_VECTOR(15 DOWNTO 0);
150
150
151
151
152 -----------------------------------------------------------------------------
152 -----------------------------------------------------------------------------
153 -- FFT
153 -- FFT
154 -----------------------------------------------------------------------------
154 -----------------------------------------------------------------------------
155 SIGNAL fft_read : STD_LOGIC;
155 SIGNAL fft_read : STD_LOGIC;
156 SIGNAL fft_pong : STD_LOGIC;
156 SIGNAL fft_pong : STD_LOGIC;
157 SIGNAL fft_data_im : STD_LOGIC_VECTOR(15 DOWNTO 0);
157 SIGNAL fft_data_im : STD_LOGIC_VECTOR(15 DOWNTO 0);
158 SIGNAL fft_data_re : STD_LOGIC_VECTOR(15 DOWNTO 0);
158 SIGNAL fft_data_re : STD_LOGIC_VECTOR(15 DOWNTO 0);
159 SIGNAL fft_data_valid : STD_LOGIC;
159 SIGNAL fft_data_valid : STD_LOGIC;
160 SIGNAL fft_data_valid_pre : STD_LOGIC;
160 SIGNAL fft_data_valid_pre : STD_LOGIC;
161 SIGNAL fft_ready : STD_LOGIC;
161 SIGNAL fft_ready : STD_LOGIC;
162 -----------------------------------------------------------------------------
162 -----------------------------------------------------------------------------
163 -- SIGNAL fft_linker_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
163 -- SIGNAL fft_linker_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
164 -----------------------------------------------------------------------------
164 -----------------------------------------------------------------------------
165 TYPE fsm_load_MS_memory IS (IDLE, LOAD_FIFO, TRASH_FFT);
165 TYPE fsm_load_MS_memory IS (IDLE, LOAD_FIFO, TRASH_FFT);
166 SIGNAL state_fsm_load_MS_memory : fsm_load_MS_memory;
166 SIGNAL state_fsm_load_MS_memory : fsm_load_MS_memory;
167 SIGNAL current_fifo_load : STD_LOGIC_VECTOR(4 DOWNTO 0);
167 SIGNAL current_fifo_load : STD_LOGIC_VECTOR(4 DOWNTO 0);
168 SIGNAL current_fifo_empty : STD_LOGIC;
168 SIGNAL current_fifo_empty : STD_LOGIC;
169 SIGNAL current_fifo_locked : STD_LOGIC;
169 SIGNAL current_fifo_locked : STD_LOGIC;
170 SIGNAL current_fifo_full : STD_LOGIC;
170 SIGNAL current_fifo_full : STD_LOGIC;
171 SIGNAL MEM_IN_SM_locked : STD_LOGIC_VECTOR(4 DOWNTO 0);
171 SIGNAL MEM_IN_SM_locked : STD_LOGIC_VECTOR(4 DOWNTO 0);
172
172
173 -----------------------------------------------------------------------------
173 -----------------------------------------------------------------------------
174 SIGNAL MEM_IN_SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
174 SIGNAL MEM_IN_SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
175 SIGNAL MEM_IN_SM_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
175 SIGNAL MEM_IN_SM_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
176 SIGNAL MEM_IN_SM_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
176 SIGNAL MEM_IN_SM_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
177 SIGNAL MEM_IN_SM_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
177 SIGNAL MEM_IN_SM_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
178 SIGNAL MEM_IN_SM_wData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
178 SIGNAL MEM_IN_SM_wData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
179 SIGNAL MEM_IN_SM_rData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
179 SIGNAL MEM_IN_SM_rData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
180 SIGNAL MEM_IN_SM_Full : STD_LOGIC_VECTOR(4 DOWNTO 0);
180 SIGNAL MEM_IN_SM_Full : STD_LOGIC_VECTOR(4 DOWNTO 0);
181 SIGNAL MEM_IN_SM_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
181 SIGNAL MEM_IN_SM_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
182 -----------------------------------------------------------------------------
182 -----------------------------------------------------------------------------
183 SIGNAL SM_in_data : STD_LOGIC_VECTOR(32*2-1 DOWNTO 0);
183 SIGNAL SM_in_data : STD_LOGIC_VECTOR(32*2-1 DOWNTO 0);
184 SIGNAL SM_in_ren : STD_LOGIC_VECTOR(1 DOWNTO 0);
184 SIGNAL SM_in_ren : STD_LOGIC_VECTOR(1 DOWNTO 0);
185 SIGNAL SM_in_empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
185 SIGNAL SM_in_empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
186
186
187 SIGNAL SM_correlation_start : STD_LOGIC;
187 SIGNAL SM_correlation_start : STD_LOGIC;
188 SIGNAL SM_correlation_auto : STD_LOGIC;
188 SIGNAL SM_correlation_auto : STD_LOGIC;
189 SIGNAL SM_correlation_done : STD_LOGIC;
189 SIGNAL SM_correlation_done : STD_LOGIC;
190 SIGNAL SM_correlation_done_reg1 : STD_LOGIC;
190 SIGNAL SM_correlation_done_reg1 : STD_LOGIC;
191 SIGNAL SM_correlation_done_reg2 : STD_LOGIC;
191 SIGNAL SM_correlation_done_reg2 : STD_LOGIC;
192 SIGNAL SM_correlation_done_reg3 : STD_LOGIC;
192 SIGNAL SM_correlation_done_reg3 : STD_LOGIC;
193 SIGNAL SM_correlation_begin : STD_LOGIC;
193 SIGNAL SM_correlation_begin : STD_LOGIC;
194
194
195 SIGNAL MEM_OUT_SM_Full_s : STD_LOGIC;
195 SIGNAL MEM_OUT_SM_Full_s : STD_LOGIC;
196 SIGNAL MEM_OUT_SM_Data_in_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
196 SIGNAL MEM_OUT_SM_Data_in_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
197 SIGNAL MEM_OUT_SM_Write_s : STD_LOGIC;
197 SIGNAL MEM_OUT_SM_Write_s : STD_LOGIC;
198
198
199 SIGNAL current_matrix_write : STD_LOGIC;
199 SIGNAL current_matrix_write : STD_LOGIC;
200 SIGNAL current_matrix_wait_empty : STD_LOGIC;
200 SIGNAL current_matrix_wait_empty : STD_LOGIC;
201 -----------------------------------------------------------------------------
201 -----------------------------------------------------------------------------
202 SIGNAL fifo_0_ready : STD_LOGIC;
202 SIGNAL fifo_0_ready : STD_LOGIC;
203 SIGNAL fifo_1_ready : STD_LOGIC;
203 SIGNAL fifo_1_ready : STD_LOGIC;
204 SIGNAL fifo_ongoing : STD_LOGIC;
204 SIGNAL fifo_ongoing : STD_LOGIC;
205 SIGNAL fifo_ongoing_reg : STD_LOGIC;
205 SIGNAL fifo_ongoing_reg : STD_LOGIC;
206
206
207 SIGNAL FSM_DMA_fifo_ren : STD_LOGIC;
207 SIGNAL FSM_DMA_fifo_ren : STD_LOGIC;
208 SIGNAL FSM_DMA_fifo_empty : STD_LOGIC;
208 SIGNAL FSM_DMA_fifo_empty : STD_LOGIC;
209 SIGNAL FSM_DMA_fifo_empty_threshold : STD_LOGIC;
209 SIGNAL FSM_DMA_fifo_empty_threshold : STD_LOGIC;
210 SIGNAL FSM_DMA_fifo_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
210 SIGNAL FSM_DMA_fifo_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
211 SIGNAL FSM_DMA_fifo_status : STD_LOGIC_VECTOR(53 DOWNTO 4);
211 SIGNAL FSM_DMA_fifo_status : STD_LOGIC_VECTOR(53 DOWNTO 4);
212 -----------------------------------------------------------------------------
212 -----------------------------------------------------------------------------
213 SIGNAL MEM_OUT_SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0);
213 SIGNAL MEM_OUT_SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0);
214 SIGNAL MEM_OUT_SM_Read : STD_LOGIC_VECTOR(1 DOWNTO 0);
214 SIGNAL MEM_OUT_SM_Read : STD_LOGIC_VECTOR(1 DOWNTO 0);
215 SIGNAL MEM_OUT_SM_Data_in : STD_LOGIC_VECTOR(63 DOWNTO 0);
215 SIGNAL MEM_OUT_SM_Data_in : STD_LOGIC_VECTOR(63 DOWNTO 0);
216 SIGNAL MEM_OUT_SM_Data_out : STD_LOGIC_VECTOR(63 DOWNTO 0);
216 SIGNAL MEM_OUT_SM_Data_out : STD_LOGIC_VECTOR(63 DOWNTO 0);
217 SIGNAL MEM_OUT_SM_Full : STD_LOGIC_VECTOR(1 DOWNTO 0);
217 SIGNAL MEM_OUT_SM_Full : STD_LOGIC_VECTOR(1 DOWNTO 0);
218 SIGNAL MEM_OUT_SM_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
218 SIGNAL MEM_OUT_SM_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
219 SIGNAL MEM_OUT_SM_Empty_Threshold : STD_LOGIC_VECTOR(1 DOWNTO 0);
219 SIGNAL MEM_OUT_SM_Empty_Threshold : STD_LOGIC_VECTOR(1 DOWNTO 0);
220
220
221 -----------------------------------------------------------------------------
221 -----------------------------------------------------------------------------
222 -- TIME REG & INFOs
222 -- TIME REG & INFOs
223 -----------------------------------------------------------------------------
223 -----------------------------------------------------------------------------
224 SIGNAL all_time : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
224 SIGNAL all_time : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
225
225
226 SIGNAL f_empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
226 SIGNAL f_empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
227 SIGNAL f_empty_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
227 SIGNAL f_empty_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
228 SIGNAL time_update_f : STD_LOGIC_VECTOR(3 DOWNTO 0);
228 SIGNAL time_update_f : STD_LOGIC_VECTOR(3 DOWNTO 0);
229 SIGNAL time_reg_f : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
229 SIGNAL time_reg_f : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
230
230
231 SIGNAL time_reg_f0_A : STD_LOGIC_VECTOR(47 DOWNTO 0);
231 SIGNAL time_reg_f0_A : STD_LOGIC_VECTOR(47 DOWNTO 0);
232 SIGNAL time_reg_f0_B : STD_LOGIC_VECTOR(47 DOWNTO 0);
232 SIGNAL time_reg_f0_B : STD_LOGIC_VECTOR(47 DOWNTO 0);
233 SIGNAL time_reg_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
233 SIGNAL time_reg_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
234 SIGNAL time_reg_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
234 SIGNAL time_reg_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
235
235
236 --SIGNAL time_update_f0_A : STD_LOGIC;
236 --SIGNAL time_update_f0_A : STD_LOGIC;
237 --SIGNAL time_update_f0_B : STD_LOGIC;
237 --SIGNAL time_update_f0_B : STD_LOGIC;
238 --SIGNAL time_update_f1 : STD_LOGIC;
238 --SIGNAL time_update_f1 : STD_LOGIC;
239 --SIGNAL time_update_f2 : STD_LOGIC;
239 --SIGNAL time_update_f2 : STD_LOGIC;
240 --
240 --
241 SIGNAL status_channel : STD_LOGIC_VECTOR(49 DOWNTO 0);
241 SIGNAL status_channel : STD_LOGIC_VECTOR(49 DOWNTO 0);
242 SIGNAL status_MS_input : STD_LOGIC_VECTOR(49 DOWNTO 0);
242 SIGNAL status_MS_input : STD_LOGIC_VECTOR(49 DOWNTO 0);
243 SIGNAL status_component : STD_LOGIC_VECTOR(53 DOWNTO 0);
243 SIGNAL status_component : STD_LOGIC_VECTOR(53 DOWNTO 0);
244
244
245 SIGNAL status_component_fifo_0 : STD_LOGIC_VECTOR(53 DOWNTO 4);
245 SIGNAL status_component_fifo_0 : STD_LOGIC_VECTOR(53 DOWNTO 4);
246 SIGNAL status_component_fifo_1 : STD_LOGIC_VECTOR(53 DOWNTO 4);
246 SIGNAL status_component_fifo_1 : STD_LOGIC_VECTOR(53 DOWNTO 4);
247 SIGNAL status_component_fifo_0_end : STD_LOGIC;
247 SIGNAL status_component_fifo_0_end : STD_LOGIC;
248 SIGNAL status_component_fifo_1_end : STD_LOGIC;
248 SIGNAL status_component_fifo_1_end : STD_LOGIC;
249 -----------------------------------------------------------------------------
249 -----------------------------------------------------------------------------
250 SIGNAL fft_ongoing_counter : STD_LOGIC;--_VECTOR(1 DOWNTO 0);
250 SIGNAL fft_ongoing_counter : STD_LOGIC;--_VECTOR(1 DOWNTO 0);
251
251
252 SIGNAL fft_ready_reg : STD_LOGIC;
252 SIGNAL fft_ready_reg : STD_LOGIC;
253 SIGNAL fft_ready_rising_down : STD_LOGIC;
253 SIGNAL fft_ready_rising_down : STD_LOGIC;
254
254
255 SIGNAL sample_load_reg : STD_LOGIC;
255 SIGNAL sample_load_reg : STD_LOGIC;
256 SIGNAL sample_load_rising_down : STD_LOGIC;
256 SIGNAL sample_load_rising_down : STD_LOGIC;
257
257
258 -----------------------------------------------------------------------------
258 -----------------------------------------------------------------------------
259 SIGNAL sample_f1_wen_head : STD_LOGIC_VECTOR(4 DOWNTO 0);
259 SIGNAL sample_f1_wen_head : STD_LOGIC_VECTOR(4 DOWNTO 0);
260 SIGNAL sample_f1_wen_head_in : STD_LOGIC;
260 SIGNAL sample_f1_wen_head_in : STD_LOGIC;
261 SIGNAL sample_f1_wen_head_out : STD_LOGIC;
261 SIGNAL sample_f1_wen_head_out : STD_LOGIC;
262 SIGNAL sample_f1_full_head_in : STD_LOGIC;
262 SIGNAL sample_f1_full_head_in : STD_LOGIC;
263 SIGNAL sample_f1_full_head_out : STD_LOGIC;
263 SIGNAL sample_f1_full_head_out : STD_LOGIC;
264 SIGNAL sample_f1_empty_head_in : STD_LOGIC;
264 SIGNAL sample_f1_empty_head_in : STD_LOGIC;
265
265
266 SIGNAL sample_f1_wdata_head : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
266 SIGNAL sample_f1_wdata_head : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
267 -----------------------------------------------------------------------------
267 -----------------------------------------------------------------------------
268 SIGNAL sample_f0_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
268 SIGNAL sample_f0_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
269 SIGNAL sample_f1_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
269 SIGNAL sample_f1_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
270 SIGNAL sample_f2_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
270 SIGNAL sample_f2_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
271 SIGNAL ongoing : STD_LOGIC;
271 SIGNAL ongoing : STD_LOGIC;
272
272
273 BEGIN
273 BEGIN
274
274
275 PROCESS (clk, rstn)
275 PROCESS (clk, rstn)
276 BEGIN -- PROCESS
276 BEGIN -- PROCESS
277 IF rstn = '0' THEN -- asynchronous reset (active low)
277 IF rstn = '0' THEN -- asynchronous reset (active low)
278 sample_f0_wen_s <= (OTHERS => '1');
278 sample_f0_wen_s <= (OTHERS => '1');
279 sample_f1_wen_s <= (OTHERS => '1');
279 sample_f1_wen_s <= (OTHERS => '1');
280 sample_f2_wen_s <= (OTHERS => '1');
280 sample_f2_wen_s <= (OTHERS => '1');
281 ongoing <= '0';
281 ongoing <= '0';
282 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
282 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
283 IF ongoing = '1' THEN
283 IF ongoing = '1' THEN
284 sample_f0_wen_s <= sample_f0_wen;
284 sample_f0_wen_s <= sample_f0_wen;
285 sample_f1_wen_s <= sample_f1_wen;
285 sample_f1_wen_s <= sample_f1_wen;
286 sample_f2_wen_s <= sample_f2_wen;
286 sample_f2_wen_s <= sample_f2_wen;
287 ELSE
287 ELSE
288 IF start_date = coarse_time(30 DOWNTO 0) THEN
288 IF start_date = coarse_time(30 DOWNTO 0) THEN
289 ongoing <= '1';
289 ongoing <= '1';
290 END IF;
290 END IF;
291 sample_f0_wen_s <= (OTHERS => '1');
291 sample_f0_wen_s <= (OTHERS => '1');
292 sample_f1_wen_s <= (OTHERS => '1');
292 sample_f1_wen_s <= (OTHERS => '1');
293 sample_f2_wen_s <= (OTHERS => '1');
293 sample_f2_wen_s <= (OTHERS => '1');
294 END IF;
294 END IF;
295 END IF;
295 END IF;
296 END PROCESS;
296 END PROCESS;
297
297
298
298
299 error_input_fifo_write <= error_wen_f2 & error_wen_f1 & error_wen_f0;
299 error_input_fifo_write <= error_wen_f2 & error_wen_f1 & error_wen_f0;
300
300
301
301
302 switch_f0_inst : spectral_matrix_switch_f0
302 switch_f0_inst : spectral_matrix_switch_f0
303 PORT MAP (
303 PORT MAP (
304 clk => clk,
304 clk => clk,
305 rstn => rstn,
305 rstn => rstn,
306
306
307 sample_wen => sample_f0_wen_s,
307 sample_wen => sample_f0_wen_s,
308
308
309 fifo_A_empty => sample_f0_A_empty,
309 fifo_A_empty => sample_f0_A_empty,
310 fifo_A_full => sample_f0_A_full,
310 fifo_A_full => sample_f0_A_full,
311 fifo_A_wen => sample_f0_A_wen,
311 fifo_A_wen => sample_f0_A_wen,
312
312
313 fifo_B_empty => sample_f0_B_empty,
313 fifo_B_empty => sample_f0_B_empty,
314 fifo_B_full => sample_f0_B_full,
314 fifo_B_full => sample_f0_B_full,
315 fifo_B_wen => sample_f0_B_wen,
315 fifo_B_wen => sample_f0_B_wen,
316
316
317 error_wen => error_wen_f0); -- TODO
317 error_wen => error_wen_f0); -- TODO
318
318
319 -----------------------------------------------------------------------------
319 -----------------------------------------------------------------------------
320 -- FIFO IN
320 -- FIFO IN
321 -----------------------------------------------------------------------------
321 -----------------------------------------------------------------------------
322 lppFIFOxN_f0_a : lppFIFOxN
322 lppFIFOxN_f0_a : lppFIFOxN
323 GENERIC MAP (
323 GENERIC MAP (
324 tech => 0,
324 tech => 0,
325 Mem_use => Mem_use,
325 Mem_use => Mem_use,
326 Data_sz => 16,
326 Data_sz => 16,
327 Addr_sz => 8,
327 Addr_sz => 8,
328 FifoCnt => 5)
328 FifoCnt => 5)
329 PORT MAP (
329 PORT MAP (
330 clk => clk,
330 clk => clk,
331 rstn => rstn,
331 rstn => rstn,
332
332
333 ReUse => (OTHERS => '0'),
333 ReUse => (OTHERS => '0'),
334
334
335 run => (OTHERS => '1'),
335 run => (OTHERS => '1'),
336
336
337 wen => sample_f0_A_wen,
337 wen => sample_f0_A_wen,
338 wdata => sample_f0_wdata,
338 wdata => sample_f0_wdata,
339
339
340 ren => sample_f0_A_ren,
340 ren => sample_f0_A_ren,
341 rdata => sample_f0_A_rdata,
341 rdata => sample_f0_A_rdata,
342
342
343 empty => sample_f0_A_empty,
343 empty => sample_f0_A_empty,
344 full => sample_f0_A_full,
344 full => sample_f0_A_full,
345 almost_full => OPEN);
345 almost_full => OPEN);
346
346
347 lppFIFOxN_f0_b : lppFIFOxN
347 lppFIFOxN_f0_b : lppFIFOxN
348 GENERIC MAP (
348 GENERIC MAP (
349 tech => 0,
349 tech => 0,
350 Mem_use => Mem_use,
350 Mem_use => Mem_use,
351 Data_sz => 16,
351 Data_sz => 16,
352 Addr_sz => 8,
352 Addr_sz => 8,
353 FifoCnt => 5)
353 FifoCnt => 5)
354 PORT MAP (
354 PORT MAP (
355 clk => clk,
355 clk => clk,
356 rstn => rstn,
356 rstn => rstn,
357
357
358 ReUse => (OTHERS => '0'),
358 ReUse => (OTHERS => '0'),
359 run => (OTHERS => '1'),
359 run => (OTHERS => '1'),
360
360
361 wen => sample_f0_B_wen,
361 wen => sample_f0_B_wen,
362 wdata => sample_f0_wdata,
362 wdata => sample_f0_wdata,
363 ren => sample_f0_B_ren,
363 ren => sample_f0_B_ren,
364 rdata => sample_f0_B_rdata,
364 rdata => sample_f0_B_rdata,
365 empty => sample_f0_B_empty,
365 empty => sample_f0_B_empty,
366 full => sample_f0_B_full,
366 full => sample_f0_B_full,
367 almost_full => OPEN);
367 almost_full => OPEN);
368
368
369 -----------------------------------------------------------------------------
369 -----------------------------------------------------------------------------
370 -- sample_f1_wen in
370 -- sample_f1_wen in
371 -- sample_f1_wdata in
371 -- sample_f1_wdata in
372 -- sample_f1_full OUT
372 -- sample_f1_full OUT
373
373
374 sample_f1_wen_head_in <= '0' WHEN sample_f1_wen_s = "00000" ELSE '1';
374 sample_f1_wen_head_in <= '0' WHEN sample_f1_wen_s = "00000" ELSE '1';
375 sample_f1_full_head_in <= '0' WHEN sample_f1_full = "00000" ELSE '1';
375 sample_f1_full_head_in <= '0' WHEN sample_f1_full = "00000" ELSE '1';
376 sample_f1_empty_head_in <= '1' WHEN sample_f1_empty = "11111" ELSE '0';
376 sample_f1_empty_head_in <= '1' WHEN sample_f1_empty = "11111" ELSE '0';
377
377
378 lpp_lfr_ms_reg_head_1:lpp_lfr_ms_reg_head
378 lpp_lfr_ms_reg_head_1:lpp_lfr_ms_reg_head
379 PORT MAP (
379 PORT MAP (
380 clk => clk,
380 clk => clk,
381 rstn => rstn,
381 rstn => rstn,
382 in_wen => sample_f1_wen_head_in,
382 in_wen => sample_f1_wen_head_in,
383 in_data => sample_f1_wdata,
383 in_data => sample_f1_wdata,
384 in_full => sample_f1_full_head_in,
384 in_full => sample_f1_full_head_in,
385 in_empty => sample_f1_empty_head_in,
385 in_empty => sample_f1_empty_head_in,
386 out_write_error => error_wen_f1,
386 out_write_error => error_wen_f1,
387 out_wen => sample_f1_wen_head_out,
387 out_wen => sample_f1_wen_head_out,
388 out_data => sample_f1_wdata_head,
388 out_data => sample_f1_wdata_head,
389 out_full => sample_f1_full_head_out);
389 out_full => sample_f1_full_head_out);
390
390
391 sample_f1_wen_head <= sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out;
391 sample_f1_wen_head <= sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out;
392
392
393
393
394 lppFIFOxN_f1 : lppFIFOxN
394 lppFIFOxN_f1 : lppFIFOxN
395 GENERIC MAP (
395 GENERIC MAP (
396 tech => 0,
396 tech => 0,
397 Mem_use => Mem_use,
397 Mem_use => Mem_use,
398 Data_sz => 16,
398 Data_sz => 16,
399 Addr_sz => 8,
399 Addr_sz => 8,
400 FifoCnt => 5)
400 FifoCnt => 5)
401 PORT MAP (
401 PORT MAP (
402 clk => clk,
402 clk => clk,
403 rstn => rstn,
403 rstn => rstn,
404
404
405 ReUse => (OTHERS => '0'),
405 ReUse => (OTHERS => '0'),
406 run => (OTHERS => '1'),
406 run => (OTHERS => '1'),
407
407
408 wen => sample_f1_wen_head,
408 wen => sample_f1_wen_head,
409 wdata => sample_f1_wdata_head,
409 wdata => sample_f1_wdata_head,
410 ren => sample_f1_ren,
410 ren => sample_f1_ren,
411 rdata => sample_f1_rdata,
411 rdata => sample_f1_rdata,
412 empty => sample_f1_empty,
412 empty => sample_f1_empty,
413 full => sample_f1_full,
413 full => sample_f1_full,
414 almost_full => sample_f1_almost_full);
414 almost_full => sample_f1_almost_full);
415
415
416
416
417 one_sample_f1_wen <= '0' WHEN sample_f1_wen_head = "11111" ELSE '1';
417 one_sample_f1_wen <= '0' WHEN sample_f1_wen_head = "11111" ELSE '1';
418
418
419 PROCESS (clk, rstn)
419 PROCESS (clk, rstn)
420 BEGIN -- PROCESS
420 BEGIN -- PROCESS
421 IF rstn = '0' THEN -- asynchronous reset (active low)
421 IF rstn = '0' THEN -- asynchronous reset (active low)
422 one_sample_f1_full <= '0';
422 one_sample_f1_full <= '0';
423 --error_wen_f1 <= '0';
423 --error_wen_f1 <= '0';
424 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
424 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
425 IF sample_f1_full_head_out = '0' THEN
425 IF sample_f1_full_head_out = '0' THEN
426 one_sample_f1_full <= '0';
426 one_sample_f1_full <= '0';
427 ELSE
427 ELSE
428 one_sample_f1_full <= '1';
428 one_sample_f1_full <= '1';
429 END IF;
429 END IF;
430 --error_wen_f1 <= one_sample_f1_wen AND one_sample_f1_full;
430 --error_wen_f1 <= one_sample_f1_wen AND one_sample_f1_full;
431 END IF;
431 END IF;
432 END PROCESS;
432 END PROCESS;
433
433
434 -----------------------------------------------------------------------------
434 -----------------------------------------------------------------------------
435
435
436
436
437 lppFIFOxN_f2 : lppFIFOxN
437 lppFIFOxN_f2 : lppFIFOxN
438 GENERIC MAP (
438 GENERIC MAP (
439 tech => 0,
439 tech => 0,
440 Mem_use => Mem_use,
440 Mem_use => Mem_use,
441 Data_sz => 16,
441 Data_sz => 16,
442 Addr_sz => 8,
442 Addr_sz => 8,
443 FifoCnt => 5)
443 FifoCnt => 5)
444 PORT MAP (
444 PORT MAP (
445 clk => clk,
445 clk => clk,
446 rstn => rstn,
446 rstn => rstn,
447
447
448 ReUse => (OTHERS => '0'),
448 ReUse => (OTHERS => '0'),
449 run => (OTHERS => '1'),
449 run => (OTHERS => '1'),
450
450
451 wen => sample_f2_wen_s,
451 wen => sample_f2_wen_s,
452 wdata => sample_f2_wdata,
452 wdata => sample_f2_wdata,
453 ren => sample_f2_ren,
453 ren => sample_f2_ren,
454 rdata => sample_f2_rdata,
454 rdata => sample_f2_rdata,
455 empty => sample_f2_empty,
455 empty => sample_f2_empty,
456 full => sample_f2_full,
456 full => sample_f2_full,
457 almost_full => OPEN);
457 almost_full => OPEN);
458
458
459
459
460 one_sample_f2_wen <= '0' WHEN sample_f2_wen_s = "11111" ELSE '1';
460 one_sample_f2_wen <= '0' WHEN sample_f2_wen_s = "11111" ELSE '1';
461
461
462 PROCESS (clk, rstn)
462 PROCESS (clk, rstn)
463 BEGIN -- PROCESS
463 BEGIN -- PROCESS
464 IF rstn = '0' THEN -- asynchronous reset (active low)
464 IF rstn = '0' THEN -- asynchronous reset (active low)
465 one_sample_f2_full <= '0';
465 one_sample_f2_full <= '0';
466 error_wen_f2 <= '0';
466 error_wen_f2 <= '0';
467 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
467 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
468 IF sample_f2_full = "00000" THEN
468 IF sample_f2_full = "00000" THEN
469 one_sample_f2_full <= '0';
469 one_sample_f2_full <= '0';
470 ELSE
470 ELSE
471 one_sample_f2_full <= '1';
471 one_sample_f2_full <= '1';
472 END IF;
472 END IF;
473 error_wen_f2 <= one_sample_f2_wen AND one_sample_f2_full;
473 error_wen_f2 <= one_sample_f2_wen AND one_sample_f2_full;
474 END IF;
474 END IF;
475 END PROCESS;
475 END PROCESS;
476
476
477 -----------------------------------------------------------------------------
477 -----------------------------------------------------------------------------
478 -- FSM SELECT CHANNEL
478 -- FSM SELECT CHANNEL
479 -----------------------------------------------------------------------------
479 -----------------------------------------------------------------------------
480 PROCESS (clk, rstn)
480 PROCESS (clk, rstn)
481 BEGIN
481 BEGIN
482 IF rstn = '0' THEN
482 IF rstn = '0' THEN
483 state_fsm_select_channel <= IDLE;
483 state_fsm_select_channel <= IDLE;
484 select_channel <= (OTHERS => '0');
484 select_channel <= (OTHERS => '0');
485 ELSIF clk'EVENT AND clk = '1' THEN
485 ELSIF clk'EVENT AND clk = '1' THEN
486 CASE state_fsm_select_channel IS
486 CASE state_fsm_select_channel IS
487 WHEN IDLE =>
487 WHEN IDLE =>
488 IF sample_f1_full = "11111" THEN
488 IF sample_f1_full = "11111" THEN
489 state_fsm_select_channel <= SWITCH_F1;
489 state_fsm_select_channel <= SWITCH_F1;
490 select_channel <= "10";
490 select_channel <= "10";
491 ELSIF sample_f1_almost_full = "00000" THEN
491 ELSIF sample_f1_almost_full = "00000" THEN
492 IF sample_f0_A_full = "11111" THEN
492 IF sample_f0_A_full = "11111" THEN
493 state_fsm_select_channel <= SWITCH_F0_A;
493 state_fsm_select_channel <= SWITCH_F0_A;
494 select_channel <= "00";
494 select_channel <= "00";
495 ELSIF sample_f0_B_full = "11111" THEN
495 ELSIF sample_f0_B_full = "11111" THEN
496 state_fsm_select_channel <= SWITCH_F0_B;
496 state_fsm_select_channel <= SWITCH_F0_B;
497 select_channel <= "01";
497 select_channel <= "01";
498 ELSIF sample_f2_full = "11111" THEN
498 ELSIF sample_f2_full = "11111" THEN
499 state_fsm_select_channel <= SWITCH_F2;
499 state_fsm_select_channel <= SWITCH_F2;
500 select_channel <= "11";
500 select_channel <= "11";
501 END IF;
501 END IF;
502 END IF;
502 END IF;
503
503
504 WHEN SWITCH_F0_A =>
504 WHEN SWITCH_F0_A =>
505 IF sample_f0_A_empty = "11111" THEN
505 IF sample_f0_A_empty = "11111" THEN
506 state_fsm_select_channel <= IDLE;
506 state_fsm_select_channel <= IDLE;
507 select_channel <= (OTHERS => '0');
507 select_channel <= (OTHERS => '0');
508 END IF;
508 END IF;
509 WHEN SWITCH_F0_B =>
509 WHEN SWITCH_F0_B =>
510 IF sample_f0_B_empty = "11111" THEN
510 IF sample_f0_B_empty = "11111" THEN
511 state_fsm_select_channel <= IDLE;
511 state_fsm_select_channel <= IDLE;
512 select_channel <= (OTHERS => '0');
512 select_channel <= (OTHERS => '0');
513 END IF;
513 END IF;
514 WHEN SWITCH_F1 =>
514 WHEN SWITCH_F1 =>
515 IF sample_f1_empty = "11111" THEN
515 IF sample_f1_empty = "11111" THEN
516 state_fsm_select_channel <= IDLE;
516 state_fsm_select_channel <= IDLE;
517 select_channel <= (OTHERS => '0');
517 select_channel <= (OTHERS => '0');
518 END IF;
518 END IF;
519 WHEN SWITCH_F2 =>
519 WHEN SWITCH_F2 =>
520 IF sample_f2_empty = "11111" THEN
520 IF sample_f2_empty = "11111" THEN
521 state_fsm_select_channel <= IDLE;
521 state_fsm_select_channel <= IDLE;
522 select_channel <= (OTHERS => '0');
522 select_channel <= (OTHERS => '0');
523 END IF;
523 END IF;
524 WHEN OTHERS => NULL;
524 WHEN OTHERS => NULL;
525 END CASE;
525 END CASE;
526
526
527 END IF;
527 END IF;
528 END PROCESS;
528 END PROCESS;
529
529
530 PROCESS (clk, rstn)
530 PROCESS (clk, rstn)
531 BEGIN
531 BEGIN
532 IF rstn = '0' THEN
532 IF rstn = '0' THEN
533 select_channel_reg <= (OTHERS => '0');
533 select_channel_reg <= (OTHERS => '0');
534 --pre_state_fsm_select_channel <= IDLE;
534 --pre_state_fsm_select_channel <= IDLE;
535 ELSIF clk'EVENT AND clk = '1' THEN
535 ELSIF clk'EVENT AND clk = '1' THEN
536 select_channel_reg <= select_channel;
536 select_channel_reg <= select_channel;
537 --pre_state_fsm_select_channel <= state_fsm_select_channel;
537 --pre_state_fsm_select_channel <= state_fsm_select_channel;
538 END IF;
538 END IF;
539 END PROCESS;
539 END PROCESS;
540
540
541
541
542 -----------------------------------------------------------------------------
542 -----------------------------------------------------------------------------
543 -- SWITCH SELECT CHANNEL
543 -- SWITCH SELECT CHANNEL
544 -----------------------------------------------------------------------------
544 -----------------------------------------------------------------------------
545 sample_empty <= sample_f0_A_empty WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
545 sample_empty <= sample_f0_A_empty WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
546 sample_f0_B_empty WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
546 sample_f0_B_empty WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
547 sample_f1_empty WHEN state_fsm_select_channel = SWITCH_F1 ELSE
547 sample_f1_empty WHEN state_fsm_select_channel = SWITCH_F1 ELSE
548 sample_f2_empty WHEN state_fsm_select_channel = SWITCH_F2 ELSE
548 sample_f2_empty WHEN state_fsm_select_channel = SWITCH_F2 ELSE
549 (OTHERS => '1');
549 (OTHERS => '1');
550
550
551 sample_full <= sample_f0_A_full WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
551 sample_full <= sample_f0_A_full WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
552 sample_f0_B_full WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
552 sample_f0_B_full WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
553 sample_f1_full WHEN state_fsm_select_channel = SWITCH_F1 ELSE
553 sample_f1_full WHEN state_fsm_select_channel = SWITCH_F1 ELSE
554 sample_f2_full WHEN state_fsm_select_channel = SWITCH_F2 ELSE
554 sample_f2_full WHEN state_fsm_select_channel = SWITCH_F2 ELSE
555 (OTHERS => '0');
555 (OTHERS => '0');
556
556
557 --sample_rdata <= sample_f0_A_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_A ELSE
557 --sample_rdata <= sample_f0_A_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_A ELSE
558 -- sample_f0_B_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_B ELSE
558 -- sample_f0_B_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_B ELSE
559 -- sample_f1_rdata WHEN pre_state_fsm_select_channel = SWITCH_F1 ELSE
559 -- sample_f1_rdata WHEN pre_state_fsm_select_channel = SWITCH_F1 ELSE
560 -- sample_f2_rdata; -- WHEN state_fsm_select_channel = SWITCH_F2 ELSE
560 -- sample_f2_rdata; -- WHEN state_fsm_select_channel = SWITCH_F2 ELSE
561 sample_rdata <= sample_f0_A_rdata WHEN select_channel_reg = "00" ELSE
561 sample_rdata <= sample_f0_A_rdata WHEN select_channel_reg = "00" ELSE
562 sample_f0_B_rdata WHEN select_channel_reg = "01" ELSE
562 sample_f0_B_rdata WHEN select_channel_reg = "01" ELSE
563 sample_f1_rdata WHEN select_channel_reg = "10" ELSE
563 sample_f1_rdata WHEN select_channel_reg = "10" ELSE
564 sample_f2_rdata; -- WHEN state_fsm_select_channel = SWITCH_F2 ELSE
564 sample_f2_rdata; -- WHEN state_fsm_select_channel = SWITCH_F2 ELSE
565
565
566
566
567 sample_f0_A_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_A ELSE (OTHERS => '1');
567 sample_f0_A_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_A ELSE (OTHERS => '1');
568 sample_f0_B_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_B ELSE (OTHERS => '1');
568 sample_f0_B_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_B ELSE (OTHERS => '1');
569 sample_f1_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F1 ELSE (OTHERS => '1');
569 sample_f1_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F1 ELSE (OTHERS => '1');
570 sample_f2_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F2 ELSE (OTHERS => '1');
570 sample_f2_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F2 ELSE (OTHERS => '1');
571
571
572
572
573 status_channel <= time_reg_f0_A & "00" WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
573 status_channel <= time_reg_f0_A & "00" WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
574 time_reg_f0_B & "00" WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
574 time_reg_f0_B & "00" WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
575 time_reg_f1 & "01" WHEN state_fsm_select_channel = SWITCH_F1 ELSE
575 time_reg_f1 & "01" WHEN state_fsm_select_channel = SWITCH_F1 ELSE
576 time_reg_f2 & "10"; -- WHEN state_fsm_select_channel = SWITCH_F2
576 time_reg_f2 & "10"; -- WHEN state_fsm_select_channel = SWITCH_F2
577
577
578 -----------------------------------------------------------------------------
578 -----------------------------------------------------------------------------
579 -- FSM LOAD FFT
579 -- FSM LOAD FFT
580 -----------------------------------------------------------------------------
580 -----------------------------------------------------------------------------
581
581
582 sample_ren <= (OTHERS => '1') WHEN fft_ongoing_counter = '1' ELSE
582 sample_ren <= (OTHERS => '1') WHEN fft_ongoing_counter = '1' ELSE
583 sample_ren_s WHEN sample_load = '1' ELSE
583 sample_ren_s WHEN sample_load = '1' ELSE
584 (OTHERS => '1');
584 (OTHERS => '1');
585
585
586 PROCESS (clk, rstn)
586 PROCESS (clk, rstn)
587 BEGIN
587 BEGIN
588 IF rstn = '0' THEN
588 IF rstn = '0' THEN
589 sample_ren_s <= (OTHERS => '1');
589 sample_ren_s <= (OTHERS => '1');
590 state_fsm_load_FFT <= IDLE;
590 state_fsm_load_FFT <= IDLE;
591 status_MS_input <= (OTHERS => '0');
591 status_MS_input <= (OTHERS => '0');
592 select_fifo <= "000";
592 select_fifo <= "000";
593 --next_state_fsm_load_FFT <= IDLE;
593 --next_state_fsm_load_FFT <= IDLE;
594 --sample_valid <= '0';
594 --sample_valid <= '0';
595 ELSIF clk'EVENT AND clk = '1' THEN
595 ELSIF clk'EVENT AND clk = '1' THEN
596 CASE state_fsm_load_FFT IS
596 CASE state_fsm_load_FFT IS
597 WHEN IDLE =>
597 WHEN IDLE =>
598 --sample_valid <= '0';
598 --sample_valid <= '0';
599 sample_ren_s <= (OTHERS => '1');
599 sample_ren_s <= (OTHERS => '1');
600 IF sample_full = "11111" AND sample_load = '1' THEN
600 IF sample_full = "11111" AND sample_load = '1' THEN
601 sample_ren_s <= "11111";
601 sample_ren_s <= "11111";
602 state_fsm_load_FFT <= FIFO_1;
602 state_fsm_load_FFT <= FIFO_1;
603 status_MS_input <= status_channel;
603 status_MS_input <= status_channel;
604 select_fifo <= "000";
604 select_fifo <= "000";
605 END IF;
605 END IF;
606
606
607 WHEN FIFO_1 =>
607 WHEN FIFO_1 =>
608 sample_ren_s <= "1111" & NOT(sample_load);
608 sample_ren_s <= "1111" & NOT(sample_load);
609 IF sample_empty(0) = '1' THEN
609 IF sample_empty(0) = '1' THEN
610 sample_ren_s <= "11111";
610 sample_ren_s <= "11111";
611 state_fsm_load_FFT <= WAIT_STATE;
611 state_fsm_load_FFT <= WAIT_STATE;
612 next_state_fsm_load_FFT <= FIFO_2;
612 next_state_fsm_load_FFT <= FIFO_2;
613 select_fifo <= "001";
613 select_fifo <= "001";
614 END IF;
614 END IF;
615
615
616 WHEN FIFO_2 =>
616 WHEN FIFO_2 =>
617 sample_ren_s <= "111" & NOT(sample_load) & '1';
617 sample_ren_s <= "111" & NOT(sample_load) & '1';
618 IF sample_empty(1) = '1' THEN
618 IF sample_empty(1) = '1' THEN
619 sample_ren_s <= "11111";
619 sample_ren_s <= "11111";
620 state_fsm_load_FFT <= WAIT_STATE;
620 state_fsm_load_FFT <= WAIT_STATE;
621 next_state_fsm_load_FFT <= FIFO_3;
621 next_state_fsm_load_FFT <= FIFO_3;
622 select_fifo <= "010";
622 select_fifo <= "010";
623 END IF;
623 END IF;
624
624
625 WHEN FIFO_3 =>
625 WHEN FIFO_3 =>
626 sample_ren_s <= "11" & NOT(sample_load) & "11";
626 sample_ren_s <= "11" & NOT(sample_load) & "11";
627 IF sample_empty(2) = '1' THEN
627 IF sample_empty(2) = '1' THEN
628 sample_ren_s <= "11111";
628 sample_ren_s <= "11111";
629 state_fsm_load_FFT <= WAIT_STATE;
629 state_fsm_load_FFT <= WAIT_STATE;
630 next_state_fsm_load_FFT <= FIFO_4;
630 next_state_fsm_load_FFT <= FIFO_4;
631 select_fifo <= "011";
631 select_fifo <= "011";
632 END IF;
632 END IF;
633
633
634 WHEN FIFO_4 =>
634 WHEN FIFO_4 =>
635 sample_ren_s <= '1' & NOT(sample_load) & "111";
635 sample_ren_s <= '1' & NOT(sample_load) & "111";
636 IF sample_empty(3) = '1' THEN
636 IF sample_empty(3) = '1' THEN
637 sample_ren_s <= "11111";
637 sample_ren_s <= "11111";
638 state_fsm_load_FFT <= WAIT_STATE;
638 state_fsm_load_FFT <= WAIT_STATE;
639 next_state_fsm_load_FFT <= FIFO_5;
639 next_state_fsm_load_FFT <= FIFO_5;
640 select_fifo <= "100";
640 select_fifo <= "100";
641 END IF;
641 END IF;
642
642
643 WHEN FIFO_5 =>
643 WHEN FIFO_5 =>
644 sample_ren_s <= NOT(sample_load) & "1111";
644 sample_ren_s <= NOT(sample_load) & "1111";
645 IF sample_empty(4) = '1' THEN
645 IF sample_empty(4) = '1' THEN
646 sample_ren_s <= (OTHERS => '1');
646 sample_ren_s <= (OTHERS => '1');
647 state_fsm_load_FFT <= IDLE;
647 state_fsm_load_FFT <= WAIT_STATE;
648 next_state_fsm_load_FFT <= IDLE;
649 --state_fsm_load_FFT <= IDLE;
648 select_fifo <= "000";
650 select_fifo <= "000";
649 END IF;
651 END IF;
650
652
651 WHEN WAIT_STATE =>
653 WHEN WAIT_STATE =>
652 sample_ren_s <= (OTHERS => '1');
654 sample_ren_s <= (OTHERS => '1');
653 IF sample_load = '1' THEN
655 IF sample_load = '1' THEN
654 state_fsm_load_FFT <= WAIT_STATE_2 ;
656 state_fsm_load_FFT <= WAIT_STATE_2 ;
655 END IF;
657 END IF;
656
658
657 WHEN WAIT_STATE_2 =>
659 WHEN WAIT_STATE_2 =>
658 sample_ren_s <= (OTHERS => '1');
660 sample_ren_s <= (OTHERS => '1');
659 IF fft_data_valid = '0' AND fft_data_valid_pre = '1' THEN
661 IF fft_data_valid = '0' AND fft_data_valid_pre = '1' THEN
660 state_fsm_load_FFT <= next_state_fsm_load_FFT;
662 state_fsm_load_FFT <= next_state_fsm_load_FFT;
661 END IF;
663 END IF;
662
664
663 WHEN OTHERS => NULL;
665 WHEN OTHERS => NULL;
664 END CASE;
666 END CASE;
665 END IF;
667 END IF;
666 END PROCESS;
668 END PROCESS;
667
669
668 PROCESS (clk, rstn)
670 PROCESS (clk, rstn)
669 BEGIN -- PROCESS
671 BEGIN -- PROCESS
670 IF rstn = '0' THEN -- asynchronous reset (active low)
672 IF rstn = '0' THEN -- asynchronous reset (active low)
671 fft_data_valid_pre <= '0';
673 fft_data_valid_pre <= '0';
672 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
674 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
673 fft_data_valid_pre <= fft_data_valid;
675 fft_data_valid_pre <= fft_data_valid;
674 END IF;
676 END IF;
675 END PROCESS;
677 END PROCESS;
676
678
677 PROCESS (clk, rstn)
679 PROCESS (clk, rstn)
678 BEGIN
680 BEGIN
679 IF rstn = '0' THEN
681 IF rstn = '0' THEN
680 sample_valid_r <= '0';
682 sample_valid_r <= '0';
681 select_fifo_reg <= (OTHERS => '0');
683 select_fifo_reg <= (OTHERS => '0');
682 --next_state_fsm_load_FFT <= IDLE;
684 --next_state_fsm_load_FFT <= IDLE;
683 ELSIF clk'EVENT AND clk = '1' THEN
685 ELSIF clk'EVENT AND clk = '1' THEN
684 select_fifo_reg <= select_fifo;
686 select_fifo_reg <= select_fifo;
685 --next_state_fsm_load_FFT <= state_fsm_load_FFT;
687 --next_state_fsm_load_FFT <= state_fsm_load_FFT;
686 IF sample_ren_s = "11111" THEN
688 IF sample_ren_s = "11111" THEN
687 sample_valid_r <= '0';
689 sample_valid_r <= '0';
688 ELSE
690 ELSE
689 sample_valid_r <= '1';
691 sample_valid_r <= '1';
690 END IF;
692 END IF;
691 END IF;
693 END IF;
692 END PROCESS;
694 END PROCESS;
693
695
694 sample_valid <= '0' WHEN fft_ongoing_counter = '1' ELSE sample_valid_r AND sample_load;
696 sample_valid <= '0' WHEN fft_ongoing_counter = '1' ELSE sample_valid_r AND sample_load;
695
697
696 --sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN next_state_fsm_load_FFT = FIFO_1 ELSE
698 --sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN next_state_fsm_load_FFT = FIFO_1 ELSE
697 -- sample_rdata(16*2-1 DOWNTO 16*1) WHEN next_state_fsm_load_FFT = FIFO_2 ELSE
699 -- sample_rdata(16*2-1 DOWNTO 16*1) WHEN next_state_fsm_load_FFT = FIFO_2 ELSE
698 -- sample_rdata(16*3-1 DOWNTO 16*2) WHEN next_state_fsm_load_FFT = FIFO_3 ELSE
700 -- sample_rdata(16*3-1 DOWNTO 16*2) WHEN next_state_fsm_load_FFT = FIFO_3 ELSE
699 -- sample_rdata(16*4-1 DOWNTO 16*3) WHEN next_state_fsm_load_FFT = FIFO_4 ELSE
701 -- sample_rdata(16*4-1 DOWNTO 16*3) WHEN next_state_fsm_load_FFT = FIFO_4 ELSE
700 -- sample_rdata(16*5-1 DOWNTO 16*4); --WHEN next_state_fsm_load_FFT = FIFO_5 ELSE
702 -- sample_rdata(16*5-1 DOWNTO 16*4); --WHEN next_state_fsm_load_FFT = FIFO_5 ELSE
701 sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN select_fifo_reg = "000" ELSE
703 sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN select_fifo_reg = "000" ELSE
702 sample_rdata(16*2-1 DOWNTO 16*1) WHEN select_fifo_reg = "001" ELSE
704 sample_rdata(16*2-1 DOWNTO 16*1) WHEN select_fifo_reg = "001" ELSE
703 sample_rdata(16*3-1 DOWNTO 16*2) WHEN select_fifo_reg = "010" ELSE
705 sample_rdata(16*3-1 DOWNTO 16*2) WHEN select_fifo_reg = "010" ELSE
704 sample_rdata(16*4-1 DOWNTO 16*3) WHEN select_fifo_reg = "011" ELSE
706 sample_rdata(16*4-1 DOWNTO 16*3) WHEN select_fifo_reg = "011" ELSE
705 sample_rdata(16*5-1 DOWNTO 16*4); --WHEN next_state_fsm_load_FFT = FIFO_5 ELSE
707 sample_rdata(16*5-1 DOWNTO 16*4); --WHEN next_state_fsm_load_FFT = FIFO_5 ELSE
706
708
707 -----------------------------------------------------------------------------
709 -----------------------------------------------------------------------------
708 -- FFT
710 -- FFT
709 -----------------------------------------------------------------------------
711 -----------------------------------------------------------------------------
710 lpp_lfr_ms_FFT_1 : lpp_lfr_ms_FFT
712 lpp_lfr_ms_FFT_1 : lpp_lfr_ms_FFT
711 PORT MAP (
713 PORT MAP (
712 clk => clk,
714 clk => clk,
713 rstn => rstn,
715 rstn => rstn,
714 sample_valid => sample_valid,
716 sample_valid => sample_valid,
715 fft_read => fft_read,
717 fft_read => fft_read,
716 sample_data => sample_data,
718 sample_data => sample_data,
717 sample_load => sample_load,
719 sample_load => sample_load,
718 fft_pong => fft_pong,
720 fft_pong => fft_pong,
719 fft_data_im => fft_data_im,
721 fft_data_im => fft_data_im,
720 fft_data_re => fft_data_re,
722 fft_data_re => fft_data_re,
721 fft_data_valid => fft_data_valid,
723 fft_data_valid => fft_data_valid,
722 fft_ready => fft_ready);
724 fft_ready => fft_ready);
723
725
724 debug_vector(0) <= fft_data_valid;
726 debug_vector(0) <= fft_data_valid;
725 debug_vector(1) <= fft_ready;
727 debug_vector(1) <= fft_ready;
726 debug_vector(11 DOWNTO 2) <= (OTHERS => '0');
728 debug_vector(11 DOWNTO 2) <= (OTHERS => '0');
727
729
728
730
729 -----------------------------------------------------------------------------
731 -----------------------------------------------------------------------------
730 fft_ready_rising_down <= fft_ready_reg AND NOT fft_ready;
732 fft_ready_rising_down <= fft_ready_reg AND NOT fft_ready;
731 sample_load_rising_down <= sample_load_reg AND NOT sample_load;
733 sample_load_rising_down <= sample_load_reg AND NOT sample_load;
732
734
733 PROCESS (clk, rstn)
735 PROCESS (clk, rstn)
734 BEGIN
736 BEGIN
735 IF rstn = '0' THEN
737 IF rstn = '0' THEN
736 fft_ready_reg <= '0';
738 fft_ready_reg <= '0';
737 sample_load_reg <= '0';
739 sample_load_reg <= '0';
738
740
739 fft_ongoing_counter <= '0';
741 fft_ongoing_counter <= '0';
740 ELSIF clk'event AND clk = '1' THEN
742 ELSIF clk'event AND clk = '1' THEN
741 fft_ready_reg <= fft_ready;
743 fft_ready_reg <= fft_ready;
742 sample_load_reg <= sample_load;
744 sample_load_reg <= sample_load;
743
745
744 IF fft_ready_rising_down = '1' AND sample_load_rising_down = '0' THEN
746 IF fft_ready_rising_down = '1' AND sample_load_rising_down = '0' THEN
745 fft_ongoing_counter <= '0';
747 fft_ongoing_counter <= '0';
746
748
747 -- CASE fft_ongoing_counter IS
749 -- CASE fft_ongoing_counter IS
748 -- WHEN "01" => fft_ongoing_counter <= "00";
750 -- WHEN "01" => fft_ongoing_counter <= "00";
749 ---- WHEN "10" => fft_ongoing_counter <= "01";
751 ---- WHEN "10" => fft_ongoing_counter <= "01";
750 -- WHEN OTHERS => NULL;
752 -- WHEN OTHERS => NULL;
751 -- END CASE;
753 -- END CASE;
752 ELSIF fft_ready_rising_down = '0' AND sample_load_rising_down = '1' THEN
754 ELSIF fft_ready_rising_down = '0' AND sample_load_rising_down = '1' THEN
753 fft_ongoing_counter <= '1';
755 fft_ongoing_counter <= '1';
754 -- CASE fft_ongoing_counter IS
756 -- CASE fft_ongoing_counter IS
755 -- WHEN "00" => fft_ongoing_counter <= "01";
757 -- WHEN "00" => fft_ongoing_counter <= "01";
756 ---- WHEN "01" => fft_ongoing_counter <= "10";
758 ---- WHEN "01" => fft_ongoing_counter <= "10";
757 -- WHEN OTHERS => NULL;
759 -- WHEN OTHERS => NULL;
758 -- END CASE;
760 -- END CASE;
759 END IF;
761 END IF;
760
762
761 END IF;
763 END IF;
762 END PROCESS;
764 END PROCESS;
763
765
764 -----------------------------------------------------------------------------
766 -----------------------------------------------------------------------------
765 PROCESS (clk, rstn)
767 PROCESS (clk, rstn)
766 BEGIN
768 BEGIN
767 IF rstn = '0' THEN
769 IF rstn = '0' THEN
768 state_fsm_load_MS_memory <= IDLE;
770 state_fsm_load_MS_memory <= IDLE;
769 current_fifo_load <= "00001";
771 current_fifo_load <= "00001";
770 ELSIF clk'EVENT AND clk = '1' THEN
772 ELSIF clk'EVENT AND clk = '1' THEN
771 CASE state_fsm_load_MS_memory IS
773 CASE state_fsm_load_MS_memory IS
772 WHEN IDLE =>
774 WHEN IDLE =>
773 IF current_fifo_empty = '1' AND fft_ready = '1' AND current_fifo_locked = '0' THEN
775 IF current_fifo_empty = '1' AND fft_ready = '1' AND current_fifo_locked = '0' THEN
774 state_fsm_load_MS_memory <= LOAD_FIFO;
776 state_fsm_load_MS_memory <= LOAD_FIFO;
775 END IF;
777 END IF;
776 WHEN LOAD_FIFO =>
778 WHEN LOAD_FIFO =>
777 IF current_fifo_full = '1' THEN
779 IF current_fifo_full = '1' THEN
778 state_fsm_load_MS_memory <= TRASH_FFT;
780 state_fsm_load_MS_memory <= TRASH_FFT;
779 END IF;
781 END IF;
780 WHEN TRASH_FFT =>
782 WHEN TRASH_FFT =>
781 IF fft_ready = '0' THEN
783 IF fft_ready = '0' THEN
782 state_fsm_load_MS_memory <= IDLE;
784 state_fsm_load_MS_memory <= IDLE;
783 current_fifo_load <= current_fifo_load(3 DOWNTO 0) & current_fifo_load(4);
785 current_fifo_load <= current_fifo_load(3 DOWNTO 0) & current_fifo_load(4);
784 END IF;
786 END IF;
785 WHEN OTHERS => NULL;
787 WHEN OTHERS => NULL;
786 END CASE;
788 END CASE;
787
789
788 END IF;
790 END IF;
789 END PROCESS;
791 END PROCESS;
790
792
791 current_fifo_empty <= MEM_IN_SM_Empty(0) WHEN current_fifo_load(0) = '1' ELSE
793 current_fifo_empty <= MEM_IN_SM_Empty(0) WHEN current_fifo_load(0) = '1' ELSE
792 MEM_IN_SM_Empty(1) WHEN current_fifo_load(1) = '1' ELSE
794 MEM_IN_SM_Empty(1) WHEN current_fifo_load(1) = '1' ELSE
793 MEM_IN_SM_Empty(2) WHEN current_fifo_load(2) = '1' ELSE
795 MEM_IN_SM_Empty(2) WHEN current_fifo_load(2) = '1' ELSE
794 MEM_IN_SM_Empty(3) WHEN current_fifo_load(3) = '1' ELSE
796 MEM_IN_SM_Empty(3) WHEN current_fifo_load(3) = '1' ELSE
795 MEM_IN_SM_Empty(4); -- WHEN current_fifo_load(3) = '1' ELSE
797 MEM_IN_SM_Empty(4); -- WHEN current_fifo_load(3) = '1' ELSE
796
798
797 current_fifo_full <= MEM_IN_SM_Full(0) WHEN current_fifo_load(0) = '1' ELSE
799 current_fifo_full <= MEM_IN_SM_Full(0) WHEN current_fifo_load(0) = '1' ELSE
798 MEM_IN_SM_Full(1) WHEN current_fifo_load(1) = '1' ELSE
800 MEM_IN_SM_Full(1) WHEN current_fifo_load(1) = '1' ELSE
799 MEM_IN_SM_Full(2) WHEN current_fifo_load(2) = '1' ELSE
801 MEM_IN_SM_Full(2) WHEN current_fifo_load(2) = '1' ELSE
800 MEM_IN_SM_Full(3) WHEN current_fifo_load(3) = '1' ELSE
802 MEM_IN_SM_Full(3) WHEN current_fifo_load(3) = '1' ELSE
801 MEM_IN_SM_Full(4); -- WHEN current_fifo_load(3) = '1' ELSE
803 MEM_IN_SM_Full(4); -- WHEN current_fifo_load(3) = '1' ELSE
802
804
803 current_fifo_locked <= MEM_IN_SM_locked(0) WHEN current_fifo_load(0) = '1' ELSE
805 current_fifo_locked <= MEM_IN_SM_locked(0) WHEN current_fifo_load(0) = '1' ELSE
804 MEM_IN_SM_locked(1) WHEN current_fifo_load(1) = '1' ELSE
806 MEM_IN_SM_locked(1) WHEN current_fifo_load(1) = '1' ELSE
805 MEM_IN_SM_locked(2) WHEN current_fifo_load(2) = '1' ELSE
807 MEM_IN_SM_locked(2) WHEN current_fifo_load(2) = '1' ELSE
806 MEM_IN_SM_locked(3) WHEN current_fifo_load(3) = '1' ELSE
808 MEM_IN_SM_locked(3) WHEN current_fifo_load(3) = '1' ELSE
807 MEM_IN_SM_locked(4); -- WHEN current_fifo_load(3) = '1' ELSE
809 MEM_IN_SM_locked(4); -- WHEN current_fifo_load(3) = '1' ELSE
808
810
809 fft_read <= '0' WHEN state_fsm_load_MS_memory = IDLE ELSE '1';
811 fft_read <= '0' WHEN state_fsm_load_MS_memory = IDLE ELSE '1';
810
812
811 all_fifo : FOR I IN 4 DOWNTO 0 GENERATE
813 all_fifo : FOR I IN 4 DOWNTO 0 GENERATE
812 MEM_IN_SM_wen_s(I) <= '0' WHEN fft_data_valid = '1'
814 MEM_IN_SM_wen_s(I) <= '0' WHEN fft_data_valid = '1'
813 AND state_fsm_load_MS_memory = LOAD_FIFO
815 AND state_fsm_load_MS_memory = LOAD_FIFO
814 AND current_fifo_load(I) = '1'
816 AND current_fifo_load(I) = '1'
815 ELSE '1';
817 ELSE '1';
816 END GENERATE all_fifo;
818 END GENERATE all_fifo;
817
819
818 PROCESS (clk, rstn)
820 PROCESS (clk, rstn)
819 BEGIN
821 BEGIN
820 IF rstn = '0' THEN
822 IF rstn = '0' THEN
821 MEM_IN_SM_wen <= (OTHERS => '1');
823 MEM_IN_SM_wen <= (OTHERS => '1');
822 ELSIF clk'EVENT AND clk = '1' THEN
824 ELSIF clk'EVENT AND clk = '1' THEN
823 MEM_IN_SM_wen <= MEM_IN_SM_wen_s;
825 MEM_IN_SM_wen <= MEM_IN_SM_wen_s;
824 END IF;
826 END IF;
825 END PROCESS;
827 END PROCESS;
826
828
827 MEM_IN_SM_wData <= (fft_data_im & fft_data_re) &
829 MEM_IN_SM_wData <= (fft_data_im & fft_data_re) &
828 (fft_data_im & fft_data_re) &
830 (fft_data_im & fft_data_re) &
829 (fft_data_im & fft_data_re) &
831 (fft_data_im & fft_data_re) &
830 (fft_data_im & fft_data_re) &
832 (fft_data_im & fft_data_re) &
831 (fft_data_im & fft_data_re);
833 (fft_data_im & fft_data_re);
832 -----------------------------------------------------------------------------
834 -----------------------------------------------------------------------------
833
835
834
836
835 -----------------------------------------------------------------------------
837 -----------------------------------------------------------------------------
836 Mem_In_SpectralMatrix : lppFIFOxN
838 Mem_In_SpectralMatrix : lppFIFOxN
837 GENERIC MAP (
839 GENERIC MAP (
838 tech => 0,
840 tech => 0,
839 Mem_use => Mem_use,
841 Mem_use => Mem_use,
840 Data_sz => 32, --16,
842 Data_sz => 32, --16,
841 Addr_sz => 7, --8
843 Addr_sz => 7, --8
842 FifoCnt => 5)
844 FifoCnt => 5)
843 PORT MAP (
845 PORT MAP (
844 clk => clk,
846 clk => clk,
845 rstn => rstn,
847 rstn => rstn,
846
848
847 ReUse => MEM_IN_SM_ReUse,
849 ReUse => MEM_IN_SM_ReUse,
848 run => (OTHERS => '1'),
850 run => (OTHERS => '1'),
849
851
850 wen => MEM_IN_SM_wen,
852 wen => MEM_IN_SM_wen,
851 wdata => MEM_IN_SM_wData,
853 wdata => MEM_IN_SM_wData,
852
854
853 ren => MEM_IN_SM_ren,
855 ren => MEM_IN_SM_ren,
854 rdata => MEM_IN_SM_rData,
856 rdata => MEM_IN_SM_rData,
855 full => MEM_IN_SM_Full,
857 full => MEM_IN_SM_Full,
856 empty => MEM_IN_SM_Empty,
858 empty => MEM_IN_SM_Empty,
857 almost_full => OPEN);
859 almost_full => OPEN);
858
860
859
861
860 -----------------------------------------------------------------------------
862 -----------------------------------------------------------------------------
861 MS_control_1 : MS_control
863 MS_control_1 : MS_control
862 PORT MAP (
864 PORT MAP (
863 clk => clk,
865 clk => clk,
864 rstn => rstn,
866 rstn => rstn,
865
867
866 current_status_ms => status_MS_input,
868 current_status_ms => status_MS_input,
867
869
868 fifo_in_lock => MEM_IN_SM_locked,
870 fifo_in_lock => MEM_IN_SM_locked,
869 fifo_in_data => MEM_IN_SM_rdata,
871 fifo_in_data => MEM_IN_SM_rdata,
870 fifo_in_full => MEM_IN_SM_Full,
872 fifo_in_full => MEM_IN_SM_Full,
871 fifo_in_empty => MEM_IN_SM_Empty,
873 fifo_in_empty => MEM_IN_SM_Empty,
872 fifo_in_ren => MEM_IN_SM_ren,
874 fifo_in_ren => MEM_IN_SM_ren,
873 fifo_in_reuse => MEM_IN_SM_ReUse,
875 fifo_in_reuse => MEM_IN_SM_ReUse,
874
876
875 fifo_out_data => SM_in_data,
877 fifo_out_data => SM_in_data,
876 fifo_out_ren => SM_in_ren,
878 fifo_out_ren => SM_in_ren,
877 fifo_out_empty => SM_in_empty,
879 fifo_out_empty => SM_in_empty,
878
880
879 current_status_component => status_component,
881 current_status_component => status_component,
880
882
881 correlation_start => SM_correlation_start,
883 correlation_start => SM_correlation_start,
882 correlation_auto => SM_correlation_auto,
884 correlation_auto => SM_correlation_auto,
883 correlation_done => SM_correlation_done);
885 correlation_done => SM_correlation_done);
884
886
885
887
886 MS_calculation_1 : MS_calculation
888 MS_calculation_1 : MS_calculation
887 PORT MAP (
889 PORT MAP (
888 clk => clk,
890 clk => clk,
889 rstn => rstn,
891 rstn => rstn,
890
892
891 fifo_in_data => SM_in_data,
893 fifo_in_data => SM_in_data,
892 fifo_in_ren => SM_in_ren,
894 fifo_in_ren => SM_in_ren,
893 fifo_in_empty => SM_in_empty,
895 fifo_in_empty => SM_in_empty,
894
896
895 fifo_out_data => MEM_OUT_SM_Data_in_s, -- TODO
897 fifo_out_data => MEM_OUT_SM_Data_in_s, -- TODO
896 fifo_out_wen => MEM_OUT_SM_Write_s, -- TODO
898 fifo_out_wen => MEM_OUT_SM_Write_s, -- TODO
897 fifo_out_full => MEM_OUT_SM_Full_s, -- TODO
899 fifo_out_full => MEM_OUT_SM_Full_s, -- TODO
898
900
899 correlation_start => SM_correlation_start,
901 correlation_start => SM_correlation_start,
900 correlation_auto => SM_correlation_auto,
902 correlation_auto => SM_correlation_auto,
901 correlation_begin => SM_correlation_begin,
903 correlation_begin => SM_correlation_begin,
902 correlation_done => SM_correlation_done);
904 correlation_done => SM_correlation_done);
903
905
904 -----------------------------------------------------------------------------
906 -----------------------------------------------------------------------------
905 PROCESS (clk, rstn)
907 PROCESS (clk, rstn)
906 BEGIN -- PROCESS
908 BEGIN -- PROCESS
907 IF rstn = '0' THEN -- asynchronous reset (active low)
909 IF rstn = '0' THEN -- asynchronous reset (active low)
908 current_matrix_write <= '0';
910 current_matrix_write <= '0';
909 current_matrix_wait_empty <= '1';
911 current_matrix_wait_empty <= '1';
910 status_component_fifo_0 <= (OTHERS => '0');
912 status_component_fifo_0 <= (OTHERS => '0');
911 status_component_fifo_1 <= (OTHERS => '0');
913 status_component_fifo_1 <= (OTHERS => '0');
912 status_component_fifo_0_end <= '0';
914 status_component_fifo_0_end <= '0';
913 status_component_fifo_1_end <= '0';
915 status_component_fifo_1_end <= '0';
914 SM_correlation_done_reg1 <= '0';
916 SM_correlation_done_reg1 <= '0';
915 SM_correlation_done_reg2 <= '0';
917 SM_correlation_done_reg2 <= '0';
916 SM_correlation_done_reg3 <= '0';
918 SM_correlation_done_reg3 <= '0';
917
919
918 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
920 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
919 SM_correlation_done_reg1 <= SM_correlation_done;
921 SM_correlation_done_reg1 <= SM_correlation_done;
920 SM_correlation_done_reg2 <= SM_correlation_done_reg1;
922 SM_correlation_done_reg2 <= SM_correlation_done_reg1;
921 SM_correlation_done_reg3 <= SM_correlation_done_reg2;
923 SM_correlation_done_reg3 <= SM_correlation_done_reg2;
922 status_component_fifo_0_end <= '0';
924 status_component_fifo_0_end <= '0';
923 status_component_fifo_1_end <= '0';
925 status_component_fifo_1_end <= '0';
924 IF SM_correlation_begin = '1' THEN
926 IF SM_correlation_begin = '1' THEN
925 IF current_matrix_write = '0' THEN
927 IF current_matrix_write = '0' THEN
926 status_component_fifo_0 <= status_component(53 DOWNTO 4);
928 status_component_fifo_0 <= status_component(53 DOWNTO 4);
927 ELSE
929 ELSE
928 status_component_fifo_1 <= status_component(53 DOWNTO 4);
930 status_component_fifo_1 <= status_component(53 DOWNTO 4);
929 END IF;
931 END IF;
930 END IF;
932 END IF;
931
933
932 IF SM_correlation_done_reg3 = '1' THEN
934 IF SM_correlation_done_reg3 = '1' THEN
933 IF current_matrix_write = '0' THEN
935 IF current_matrix_write = '0' THEN
934 status_component_fifo_0_end <= '1';
936 status_component_fifo_0_end <= '1';
935 ELSE
937 ELSE
936 status_component_fifo_1_end <= '1';
938 status_component_fifo_1_end <= '1';
937 END IF;
939 END IF;
938 current_matrix_wait_empty <= '1';
940 current_matrix_wait_empty <= '1';
939 current_matrix_write <= NOT current_matrix_write;
941 current_matrix_write <= NOT current_matrix_write;
940 END IF;
942 END IF;
941
943
942 IF current_matrix_wait_empty <= '1' THEN
944 IF current_matrix_wait_empty <= '1' THEN
943 IF current_matrix_write = '0' THEN
945 IF current_matrix_write = '0' THEN
944 current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(0);
946 current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(0);
945 ELSE
947 ELSE
946 current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(1);
948 current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(1);
947 END IF;
949 END IF;
948 END IF;
950 END IF;
949
951
950 END IF;
952 END IF;
951 END PROCESS;
953 END PROCESS;
952
954
953 MEM_OUT_SM_Full_s <= '1' WHEN SM_correlation_done = '1' ELSE
955 MEM_OUT_SM_Full_s <= '1' WHEN SM_correlation_done = '1' ELSE
954 '1' WHEN SM_correlation_done_reg1 = '1' ELSE
956 '1' WHEN SM_correlation_done_reg1 = '1' ELSE
955 '1' WHEN SM_correlation_done_reg2 = '1' ELSE
957 '1' WHEN SM_correlation_done_reg2 = '1' ELSE
956 '1' WHEN SM_correlation_done_reg3 = '1' ELSE
958 '1' WHEN SM_correlation_done_reg3 = '1' ELSE
957 '1' WHEN current_matrix_wait_empty = '1' ELSE
959 '1' WHEN current_matrix_wait_empty = '1' ELSE
958 MEM_OUT_SM_Full(0) WHEN current_matrix_write = '0' ELSE
960 MEM_OUT_SM_Full(0) WHEN current_matrix_write = '0' ELSE
959 MEM_OUT_SM_Full(1);
961 MEM_OUT_SM_Full(1);
960
962
961 MEM_OUT_SM_Write(0) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '0' ELSE '1';
963 MEM_OUT_SM_Write(0) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '0' ELSE '1';
962 MEM_OUT_SM_Write(1) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '1' ELSE '1';
964 MEM_OUT_SM_Write(1) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '1' ELSE '1';
963
965
964 MEM_OUT_SM_Data_in <= MEM_OUT_SM_Data_in_s & MEM_OUT_SM_Data_in_s;
966 MEM_OUT_SM_Data_in <= MEM_OUT_SM_Data_in_s & MEM_OUT_SM_Data_in_s;
965 -----------------------------------------------------------------------------
967 -----------------------------------------------------------------------------
966
968
967 --Mem_Out_SpectralMatrix : lppFIFOxN
969 --Mem_Out_SpectralMatrix : lppFIFOxN
968 -- GENERIC MAP (
970 -- GENERIC MAP (
969 -- tech => 0,
971 -- tech => 0,
970 -- Mem_use => Mem_use,
972 -- Mem_use => Mem_use,
971 -- Data_sz => 32,
973 -- Data_sz => 32,
972 -- Addr_sz => 8,
974 -- Addr_sz => 8,
973 -- FifoCnt => 2)
975 -- FifoCnt => 2)
974 -- PORT MAP (
976 -- PORT MAP (
975 -- clk => clk,
977 -- clk => clk,
976 -- rstn => rstn,
978 -- rstn => rstn,
977
979
978 -- ReUse => (OTHERS => '0'),
980 -- ReUse => (OTHERS => '0'),
979 -- run => (OTHERS => '1'),
981 -- run => (OTHERS => '1'),
980
982
981 -- wen => MEM_OUT_SM_Write,
983 -- wen => MEM_OUT_SM_Write,
982 -- wdata => MEM_OUT_SM_Data_in,
984 -- wdata => MEM_OUT_SM_Data_in,
983
985
984 -- ren => MEM_OUT_SM_Read,
986 -- ren => MEM_OUT_SM_Read,
985 -- rdata => MEM_OUT_SM_Data_out,
987 -- rdata => MEM_OUT_SM_Data_out,
986
988
987 -- full => MEM_OUT_SM_Full,
989 -- full => MEM_OUT_SM_Full,
988 -- empty => MEM_OUT_SM_Empty,
990 -- empty => MEM_OUT_SM_Empty,
989 -- almost_full => OPEN);
991 -- almost_full => OPEN);
990
992
991
993
992 all_Mem_Out_SpectralMatrix: FOR I IN 1 DOWNTO 0 GENERATE
994 all_Mem_Out_SpectralMatrix: FOR I IN 1 DOWNTO 0 GENERATE
993 Mem_Out_SpectralMatrix_I: lpp_fifo
995 Mem_Out_SpectralMatrix_I: lpp_fifo
994 GENERIC MAP (
996 GENERIC MAP (
995 tech => 0,
997 tech => 0,
996 Mem_use => Mem_use,
998 Mem_use => Mem_use,
997 EMPTY_THRESHOLD_LIMIT => 15,
999 EMPTY_THRESHOLD_LIMIT => 15,
998 FULL_THRESHOLD_LIMIT => 1,
1000 FULL_THRESHOLD_LIMIT => 1,
999 DataSz => 32,
1001 DataSz => 32,
1000 AddrSz => 8)
1002 AddrSz => 8)
1001 PORT MAP (
1003 PORT MAP (
1002 clk => clk,
1004 clk => clk,
1003 rstn => rstn,
1005 rstn => rstn,
1004 reUse => '0',
1006 reUse => '0',
1005 run => run,
1007 run => run,
1006
1008
1007 ren => MEM_OUT_SM_Read(I),
1009 ren => MEM_OUT_SM_Read(I),
1008 rdata => MEM_OUT_SM_Data_out(32*(I+1)-1 DOWNTO 32*i),
1010 rdata => MEM_OUT_SM_Data_out(32*(I+1)-1 DOWNTO 32*i),
1009
1011
1010 wen => MEM_OUT_SM_Write(I),
1012 wen => MEM_OUT_SM_Write(I),
1011 wdata => MEM_OUT_SM_Data_in(32*(I+1)-1 DOWNTO 32*i),
1013 wdata => MEM_OUT_SM_Data_in(32*(I+1)-1 DOWNTO 32*i),
1012
1014
1013 empty => MEM_OUT_SM_Empty(I),
1015 empty => MEM_OUT_SM_Empty(I),
1014 full => MEM_OUT_SM_Full(I),
1016 full => MEM_OUT_SM_Full(I),
1015 full_almost => OPEN,
1017 full_almost => OPEN,
1016 empty_threshold => MEM_OUT_SM_Empty_Threshold(I),
1018 empty_threshold => MEM_OUT_SM_Empty_Threshold(I),
1017
1019
1018 full_threshold => OPEN);
1020 full_threshold => OPEN);
1019
1021
1020 END GENERATE all_Mem_Out_SpectralMatrix;
1022 END GENERATE all_Mem_Out_SpectralMatrix;
1021
1023
1022 -----------------------------------------------------------------------------
1024 -----------------------------------------------------------------------------
1023 -- MEM_OUT_SM_Read <= "00";
1025 -- MEM_OUT_SM_Read <= "00";
1024 PROCESS (clk, rstn)
1026 PROCESS (clk, rstn)
1025 BEGIN
1027 BEGIN
1026 IF rstn = '0' THEN
1028 IF rstn = '0' THEN
1027 fifo_0_ready <= '0';
1029 fifo_0_ready <= '0';
1028 fifo_1_ready <= '0';
1030 fifo_1_ready <= '0';
1029 fifo_ongoing <= '0';
1031 fifo_ongoing <= '0';
1030 fifo_ongoing_reg <= '0';
1032 fifo_ongoing_reg <= '0';
1031 ELSIF clk'EVENT AND clk = '1' THEN
1033 ELSIF clk'EVENT AND clk = '1' THEN
1032 fifo_ongoing_reg <= fifo_ongoing;
1034 fifo_ongoing_reg <= fifo_ongoing;
1033 IF fifo_0_ready = '1' AND MEM_OUT_SM_Empty(0) = '1' THEN
1035 IF fifo_0_ready = '1' AND MEM_OUT_SM_Empty(0) = '1' THEN
1034 fifo_ongoing <= '1';
1036 fifo_ongoing <= '1';
1035 fifo_0_ready <= '0';
1037 fifo_0_ready <= '0';
1036 ELSIF status_component_fifo_0_end = '1' THEN
1038 ELSIF status_component_fifo_0_end = '1' THEN
1037 fifo_0_ready <= '1';
1039 fifo_0_ready <= '1';
1038 END IF;
1040 END IF;
1039
1041
1040 IF fifo_1_ready = '1' AND MEM_OUT_SM_Empty(1) = '1' THEN
1042 IF fifo_1_ready = '1' AND MEM_OUT_SM_Empty(1) = '1' THEN
1041 fifo_ongoing <= '0';
1043 fifo_ongoing <= '0';
1042 fifo_1_ready <= '0';
1044 fifo_1_ready <= '0';
1043 ELSIF status_component_fifo_1_end = '1' THEN
1045 ELSIF status_component_fifo_1_end = '1' THEN
1044 fifo_1_ready <= '1';
1046 fifo_1_ready <= '1';
1045 END IF;
1047 END IF;
1046
1048
1047 END IF;
1049 END IF;
1048 END PROCESS;
1050 END PROCESS;
1049
1051
1050 MEM_OUT_SM_Read(0) <= '1' WHEN fifo_ongoing = '1' ELSE
1052 MEM_OUT_SM_Read(0) <= '1' WHEN fifo_ongoing = '1' ELSE
1051 '1' WHEN fifo_0_ready = '0' ELSE
1053 '1' WHEN fifo_0_ready = '0' ELSE
1052 FSM_DMA_fifo_ren;
1054 FSM_DMA_fifo_ren;
1053
1055
1054 MEM_OUT_SM_Read(1) <= '1' WHEN fifo_ongoing = '0' ELSE
1056 MEM_OUT_SM_Read(1) <= '1' WHEN fifo_ongoing = '0' ELSE
1055 '1' WHEN fifo_1_ready = '0' ELSE
1057 '1' WHEN fifo_1_ready = '0' ELSE
1056 FSM_DMA_fifo_ren;
1058 FSM_DMA_fifo_ren;
1057
1059
1058 FSM_DMA_fifo_empty <= MEM_OUT_SM_Empty(0) WHEN fifo_ongoing = '0' AND fifo_0_ready = '1' ELSE
1060 FSM_DMA_fifo_empty <= MEM_OUT_SM_Empty(0) WHEN fifo_ongoing = '0' AND fifo_0_ready = '1' ELSE
1059 MEM_OUT_SM_Empty(1) WHEN fifo_ongoing = '1' AND fifo_1_ready = '1' ELSE
1061 MEM_OUT_SM_Empty(1) WHEN fifo_ongoing = '1' AND fifo_1_ready = '1' ELSE
1060 '1';
1062 '1';
1061
1063
1062 FSM_DMA_fifo_status <= status_component_fifo_0 WHEN fifo_ongoing = '0' ELSE
1064 FSM_DMA_fifo_status <= status_component_fifo_0 WHEN fifo_ongoing = '0' ELSE
1063 status_component_fifo_1;
1065 status_component_fifo_1;
1064
1066
1065 FSM_DMA_fifo_data <= MEM_OUT_SM_Data_out(31 DOWNTO 0) WHEN fifo_ongoing_reg = '0' ELSE
1067 FSM_DMA_fifo_data <= MEM_OUT_SM_Data_out(31 DOWNTO 0) WHEN fifo_ongoing_reg = '0' ELSE
1066 MEM_OUT_SM_Data_out(63 DOWNTO 32);
1068 MEM_OUT_SM_Data_out(63 DOWNTO 32);
1067
1069
1068
1070
1069 FSM_DMA_fifo_empty_threshold <= MEM_OUT_SM_Empty_Threshold(0) WHEN fifo_ongoing = '0' AND fifo_0_ready = '1' ELSE
1071 FSM_DMA_fifo_empty_threshold <= MEM_OUT_SM_Empty_Threshold(0) WHEN fifo_ongoing = '0' AND fifo_0_ready = '1' ELSE
1070 MEM_OUT_SM_Empty_Threshold(1) WHEN fifo_ongoing = '1' AND fifo_1_ready = '1' ELSE
1072 MEM_OUT_SM_Empty_Threshold(1) WHEN fifo_ongoing = '1' AND fifo_1_ready = '1' ELSE
1071 '1';
1073 '1';
1072
1074
1073 -----------------------------------------------------------------------------
1075 -----------------------------------------------------------------------------
1074 -- fifo_matrix_type => FSM_DMA_fifo_status(5 DOWNTO 4), --IN
1076 -- fifo_matrix_type => FSM_DMA_fifo_status(5 DOWNTO 4), --IN
1075 -- fifo_matrix_component => FSM_DMA_fifo_status(3 DOWNTO 0), --IN
1077 -- fifo_matrix_component => FSM_DMA_fifo_status(3 DOWNTO 0), --IN
1076 -- fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6), --IN
1078 -- fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6), --IN
1077 -- fifo_data => FSM_DMA_fifo_data, --IN
1079 -- fifo_data => FSM_DMA_fifo_data, --IN
1078 -- fifo_empty => FSM_DMA_fifo_empty, --IN
1080 -- fifo_empty => FSM_DMA_fifo_empty, --IN
1079 -- fifo_empty_threshold => FSM_DMA_fifo_empty_threshold, --IN
1081 -- fifo_empty_threshold => FSM_DMA_fifo_empty_threshold, --IN
1080 -- fifo_ren => FSM_DMA_fifo_ren, --OUT
1082 -- fifo_ren => FSM_DMA_fifo_ren, --OUT
1081
1083
1082
1084
1083 lpp_lfr_ms_fsmdma_1: lpp_lfr_ms_fsmdma
1085 lpp_lfr_ms_fsmdma_1: lpp_lfr_ms_fsmdma
1084 PORT MAP (
1086 PORT MAP (
1085 clk => clk,
1087 clk => clk,
1086 rstn => rstn,
1088 rstn => rstn,
1087 run => run,
1089 run => run,
1088
1090
1089 fifo_matrix_type => FSM_DMA_fifo_status(5 DOWNTO 4),
1091 fifo_matrix_type => FSM_DMA_fifo_status(5 DOWNTO 4),
1090 fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6),
1092 fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6),
1091 fifo_data => FSM_DMA_fifo_data,
1093 fifo_data => FSM_DMA_fifo_data,
1092 fifo_empty => FSM_DMA_fifo_empty,
1094 fifo_empty => FSM_DMA_fifo_empty,
1093 fifo_empty_threshold => FSM_DMA_fifo_empty_threshold,
1095 fifo_empty_threshold => FSM_DMA_fifo_empty_threshold,
1094 fifo_ren => FSM_DMA_fifo_ren,
1096 fifo_ren => FSM_DMA_fifo_ren,
1095
1097
1096 dma_fifo_valid_burst => dma_fifo_burst_valid,
1098 dma_fifo_valid_burst => dma_fifo_burst_valid,
1097 dma_fifo_data => dma_fifo_data,
1099 dma_fifo_data => dma_fifo_data,
1098 dma_fifo_ren => dma_fifo_ren,
1100 dma_fifo_ren => dma_fifo_ren,
1099 dma_buffer_new => dma_buffer_new,
1101 dma_buffer_new => dma_buffer_new,
1100 dma_buffer_addr => dma_buffer_addr,
1102 dma_buffer_addr => dma_buffer_addr,
1101 dma_buffer_length => dma_buffer_length,
1103 dma_buffer_length => dma_buffer_length,
1102 dma_buffer_full => dma_buffer_full,
1104 dma_buffer_full => dma_buffer_full,
1103 dma_buffer_full_err => dma_buffer_full_err,
1105 dma_buffer_full_err => dma_buffer_full_err,
1104
1106
1105 status_ready_matrix_f0 => status_ready_matrix_f0,
1107 status_ready_matrix_f0 => status_ready_matrix_f0,
1106 status_ready_matrix_f1 => status_ready_matrix_f1,
1108 status_ready_matrix_f1 => status_ready_matrix_f1,
1107 status_ready_matrix_f2 => status_ready_matrix_f2,
1109 status_ready_matrix_f2 => status_ready_matrix_f2,
1108 addr_matrix_f0 => addr_matrix_f0,
1110 addr_matrix_f0 => addr_matrix_f0,
1109 addr_matrix_f1 => addr_matrix_f1,
1111 addr_matrix_f1 => addr_matrix_f1,
1110 addr_matrix_f2 => addr_matrix_f2,
1112 addr_matrix_f2 => addr_matrix_f2,
1111 length_matrix_f0 => length_matrix_f0,
1113 length_matrix_f0 => length_matrix_f0,
1112 length_matrix_f1 => length_matrix_f1,
1114 length_matrix_f1 => length_matrix_f1,
1113 length_matrix_f2 => length_matrix_f2,
1115 length_matrix_f2 => length_matrix_f2,
1114 ready_matrix_f0 => ready_matrix_f0,
1116 ready_matrix_f0 => ready_matrix_f0,
1115 ready_matrix_f1 => ready_matrix_f1,
1117 ready_matrix_f1 => ready_matrix_f1,
1116 ready_matrix_f2 => ready_matrix_f2,
1118 ready_matrix_f2 => ready_matrix_f2,
1117 matrix_time_f0 => matrix_time_f0,
1119 matrix_time_f0 => matrix_time_f0,
1118 matrix_time_f1 => matrix_time_f1,
1120 matrix_time_f1 => matrix_time_f1,
1119 matrix_time_f2 => matrix_time_f2,
1121 matrix_time_f2 => matrix_time_f2,
1120 error_buffer_full => error_buffer_full);
1122 error_buffer_full => error_buffer_full);
1121
1123
1122
1124
1123
1125
1124
1126
1125
1127
1126 --dma_fifo_burst_valid: OUT STD_LOGIC; --TODO
1128 --dma_fifo_burst_valid: OUT STD_LOGIC; --TODO
1127 --dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --TODO
1129 --dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --TODO
1128 --dma_fifo_ren : IN STD_LOGIC; --TODO
1130 --dma_fifo_ren : IN STD_LOGIC; --TODO
1129 --dma_buffer_new : OUT STD_LOGIC; --TODO
1131 --dma_buffer_new : OUT STD_LOGIC; --TODO
1130 --dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --TODO
1132 --dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --TODO
1131 --dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); --TODO
1133 --dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); --TODO
1132 --dma_buffer_full : IN STD_LOGIC; --TODO
1134 --dma_buffer_full : IN STD_LOGIC; --TODO
1133 --dma_buffer_full_err : IN STD_LOGIC; --TODO
1135 --dma_buffer_full_err : IN STD_LOGIC; --TODO
1134
1136
1135 ---- Reg out
1137 ---- Reg out
1136 --ready_matrix_f0 : OUT STD_LOGIC; -- TODO
1138 --ready_matrix_f0 : OUT STD_LOGIC; -- TODO
1137 --ready_matrix_f1 : OUT STD_LOGIC; -- TODO
1139 --ready_matrix_f1 : OUT STD_LOGIC; -- TODO
1138 --ready_matrix_f2 : OUT STD_LOGIC; -- TODO
1140 --ready_matrix_f2 : OUT STD_LOGIC; -- TODO
1139 --error_bad_component_error : OUT STD_LOGIC; -- TODO
1141 --error_bad_component_error : OUT STD_LOGIC; -- TODO
1140 --error_buffer_full : OUT STD_LOGIC; -- TODO
1142 --error_buffer_full : OUT STD_LOGIC; -- TODO
1141
1143
1142 ---- Reg In
1144 ---- Reg In
1143 --status_ready_matrix_f0 : IN STD_LOGIC; -- TODO
1145 --status_ready_matrix_f0 : IN STD_LOGIC; -- TODO
1144 --status_ready_matrix_f1 : IN STD_LOGIC; -- TODO
1146 --status_ready_matrix_f1 : IN STD_LOGIC; -- TODO
1145 --status_ready_matrix_f2 : IN STD_LOGIC; -- TODO
1147 --status_ready_matrix_f2 : IN STD_LOGIC; -- TODO
1146
1148
1147 --addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
1149 --addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
1148 --addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
1150 --addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
1149 --addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
1151 --addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
1150
1152
1151 --matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
1153 --matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
1152 --matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
1154 --matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
1153 --matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) -- TODO
1155 --matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) -- TODO
1154 -----------------------------------------------------------------------------
1156 -----------------------------------------------------------------------------
1155
1157
1156 -----------------------------------------------------------------------------
1158 -----------------------------------------------------------------------------
1157 --lpp_lfr_ms_fsmdma_1 : lpp_lfr_ms_fsmdma
1159 --lpp_lfr_ms_fsmdma_1 : lpp_lfr_ms_fsmdma
1158 -- PORT MAP (
1160 -- PORT MAP (
1159 -- HCLK => clk,
1161 -- HCLK => clk,
1160 -- HRESETn => rstn,
1162 -- HRESETn => rstn,
1161
1163
1162 -- fifo_matrix_type => FSM_DMA_fifo_status(5 DOWNTO 4),
1164 -- fifo_matrix_type => FSM_DMA_fifo_status(5 DOWNTO 4),
1163 -- fifo_matrix_component => FSM_DMA_fifo_status(3 DOWNTO 0),
1165 -- fifo_matrix_component => FSM_DMA_fifo_status(3 DOWNTO 0),
1164 -- fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6),
1166 -- fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6),
1165 -- fifo_data => FSM_DMA_fifo_data,
1167 -- fifo_data => FSM_DMA_fifo_data,
1166 -- fifo_empty => FSM_DMA_fifo_empty,
1168 -- fifo_empty => FSM_DMA_fifo_empty,
1167 -- fifo_ren => FSM_DMA_fifo_ren,
1169 -- fifo_ren => FSM_DMA_fifo_ren,
1168
1170
1169 -- dma_addr => dma_addr,
1171 -- dma_addr => dma_addr,
1170 -- dma_data => dma_data,
1172 -- dma_data => dma_data,
1171 -- dma_valid => dma_valid,
1173 -- dma_valid => dma_valid,
1172 -- dma_valid_burst => dma_valid_burst,
1174 -- dma_valid_burst => dma_valid_burst,
1173 -- dma_ren => dma_ren,
1175 -- dma_ren => dma_ren,
1174 -- dma_done => dma_done,
1176 -- dma_done => dma_done,
1175
1177
1176 -- ready_matrix_f0 => ready_matrix_f0,
1178 -- ready_matrix_f0 => ready_matrix_f0,
1177 -- ready_matrix_f1 => ready_matrix_f1,
1179 -- ready_matrix_f1 => ready_matrix_f1,
1178 -- ready_matrix_f2 => ready_matrix_f2,
1180 -- ready_matrix_f2 => ready_matrix_f2,
1179
1181
1180 -- error_bad_component_error => error_bad_component_error,
1182 -- error_bad_component_error => error_bad_component_error,
1181 -- error_buffer_full => error_buffer_full,
1183 -- error_buffer_full => error_buffer_full,
1182
1184
1183 -- debug_reg => debug_reg,
1185 -- debug_reg => debug_reg,
1184 -- status_ready_matrix_f0 => status_ready_matrix_f0,
1186 -- status_ready_matrix_f0 => status_ready_matrix_f0,
1185 -- status_ready_matrix_f1 => status_ready_matrix_f1,
1187 -- status_ready_matrix_f1 => status_ready_matrix_f1,
1186 -- status_ready_matrix_f2 => status_ready_matrix_f2,
1188 -- status_ready_matrix_f2 => status_ready_matrix_f2,
1187
1189
1188 -- config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
1190 -- config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
1189 -- config_active_interruption_onError => config_active_interruption_onError,
1191 -- config_active_interruption_onError => config_active_interruption_onError,
1190
1192
1191 -- addr_matrix_f0 => addr_matrix_f0,
1193 -- addr_matrix_f0 => addr_matrix_f0,
1192 -- addr_matrix_f1 => addr_matrix_f1,
1194 -- addr_matrix_f1 => addr_matrix_f1,
1193 -- addr_matrix_f2 => addr_matrix_f2,
1195 -- addr_matrix_f2 => addr_matrix_f2,
1194
1196
1195 -- matrix_time_f0 => matrix_time_f0,
1197 -- matrix_time_f0 => matrix_time_f0,
1196 -- matrix_time_f1 => matrix_time_f1,
1198 -- matrix_time_f1 => matrix_time_f1,
1197 -- matrix_time_f2 => matrix_time_f2
1199 -- matrix_time_f2 => matrix_time_f2
1198 -- );
1200 -- );
1199 -----------------------------------------------------------------------------
1201 -----------------------------------------------------------------------------
1200
1202
1201
1203
1202
1204
1203
1205
1204
1206
1205
1207
1206 -----------------------------------------------------------------------------
1208 -----------------------------------------------------------------------------
1207 -- TIME MANAGMENT
1209 -- TIME MANAGMENT
1208 -----------------------------------------------------------------------------
1210 -----------------------------------------------------------------------------
1209 all_time <= sample_f2_time & sample_f1_time & sample_f0_time & sample_f0_time;
1211 all_time <= sample_f2_time & sample_f1_time & sample_f0_time & sample_f0_time;
1210 --all_time <= coarse_time & fine_time;
1212 --all_time <= coarse_time & fine_time;
1211 --
1213 --
1212 f_empty(0) <= '1' WHEN sample_f0_A_empty = "11111" ELSE '0';
1214 f_empty(0) <= '1' WHEN sample_f0_A_empty = "11111" ELSE '0';
1213 f_empty(1) <= '1' WHEN sample_f0_B_empty = "11111" ELSE '0';
1215 f_empty(1) <= '1' WHEN sample_f0_B_empty = "11111" ELSE '0';
1214 f_empty(2) <= '1' WHEN sample_f1_empty = "11111" ELSE '0';
1216 f_empty(2) <= '1' WHEN sample_f1_empty = "11111" ELSE '0';
1215 f_empty(3) <= '1' WHEN sample_f2_empty = "11111" ELSE '0';
1217 f_empty(3) <= '1' WHEN sample_f2_empty = "11111" ELSE '0';
1216
1218
1217 all_time_reg: FOR I IN 0 TO 3 GENERATE
1219 all_time_reg: FOR I IN 0 TO 3 GENERATE
1218
1220
1219 PROCESS (clk, rstn)
1221 PROCESS (clk, rstn)
1220 BEGIN
1222 BEGIN
1221 IF rstn = '0' THEN
1223 IF rstn = '0' THEN
1222 f_empty_reg(I) <= '1';
1224 f_empty_reg(I) <= '1';
1223 ELSIF clk'event AND clk = '1' THEN
1225 ELSIF clk'event AND clk = '1' THEN
1224 f_empty_reg(I) <= f_empty(I);
1226 f_empty_reg(I) <= f_empty(I);
1225 END IF;
1227 END IF;
1226 END PROCESS;
1228 END PROCESS;
1227
1229
1228 time_update_f(I) <= '1' WHEN f_empty(I) = '0' AND f_empty_reg(I) = '1' ELSE '0';
1230 time_update_f(I) <= '1' WHEN f_empty(I) = '0' AND f_empty_reg(I) = '1' ELSE '0';
1229
1231
1230 s_m_t_m_f0_A : spectral_matrix_time_managment
1232 s_m_t_m_f0_A : spectral_matrix_time_managment
1231 PORT MAP (
1233 PORT MAP (
1232 clk => clk,
1234 clk => clk,
1233 rstn => rstn,
1235 rstn => rstn,
1234 time_in => all_time((I+1)*48-1 DOWNTO I*48),
1236 time_in => all_time((I+1)*48-1 DOWNTO I*48),
1235 update_1 => time_update_f(I),
1237 update_1 => time_update_f(I),
1236 time_out => time_reg_f((I+1)*48-1 DOWNTO I*48)
1238 time_out => time_reg_f((I+1)*48-1 DOWNTO I*48)
1237 );
1239 );
1238
1240
1239 END GENERATE all_time_reg;
1241 END GENERATE all_time_reg;
1240
1242
1241 time_reg_f0_A <= time_reg_f((0+1)*48-1 DOWNTO 0*48);
1243 time_reg_f0_A <= time_reg_f((0+1)*48-1 DOWNTO 0*48);
1242 time_reg_f0_B <= time_reg_f((1+1)*48-1 DOWNTO 1*48);
1244 time_reg_f0_B <= time_reg_f((1+1)*48-1 DOWNTO 1*48);
1243 time_reg_f1 <= time_reg_f((2+1)*48-1 DOWNTO 2*48);
1245 time_reg_f1 <= time_reg_f((2+1)*48-1 DOWNTO 2*48);
1244 time_reg_f2 <= time_reg_f((3+1)*48-1 DOWNTO 3*48);
1246 time_reg_f2 <= time_reg_f((3+1)*48-1 DOWNTO 3*48);
1245
1247
1246 -----------------------------------------------------------------------------
1248 -----------------------------------------------------------------------------
1247
1249
1248 END Behavioral;
1250 END Behavioral;
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