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Update DMA : split IP DMA and Reg AHB.
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
22 -------------------------------------------------------------------------------
23 -- 1.0 - initial version
24 -- 1.1 - (01/11/2013) FIX boundary error (1kB address should not be crossed by BURSTS)
25 -------------------------------------------------------------------------------
26 LIBRARY ieee;
27 USE ieee.std_logic_1164.ALL;
28 USE ieee.numeric_std.ALL;
29 LIBRARY grlib;
30 USE grlib.amba.ALL;
31 USE grlib.stdlib.ALL;
32 USE grlib.devices.ALL;
33 USE GRLIB.DMA2AHB_Package.ALL;
34 --USE GRLIB.DMA2AHB_TestPackage.ALL;
35 LIBRARY lpp;
36 USE lpp.lpp_amba.ALL;
37 USE lpp.apb_devices_list.ALL;
38 USE lpp.lpp_memory.ALL;
39 USE lpp.lpp_dma_pkg.ALL;
40 LIBRARY techmap;
41 USE techmap.gencomp.ALL;
42
43
44 ENTITY lpp_dma_ip IS
45 GENERIC (
46 tech : INTEGER := inferred;
47 hindex : INTEGER := 2;
48 pindex : INTEGER := 4;
49 paddr : INTEGER := 4;
50 pmask : INTEGER := 16#fff#;
51 pirq : INTEGER := 0);
52 PORT (
53 -- AMBA AHB system signals
54 HCLK : IN STD_ULOGIC;
55 HRESETn : IN STD_ULOGIC;
56
57 -- AMBA AHB Master Interface
58 AHB_Master_In : IN AHB_Mst_In_Type;
59 AHB_Master_Out : OUT AHB_Mst_Out_Type;
60
61 -- fifo interface
62 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
63 fifo_empty : IN STD_LOGIC;
64 fifo_ren : OUT STD_LOGIC;
65
66 -- header
67 header : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
68 header_val : IN STD_LOGIC;
69 header_ack : OUT STD_LOGIC;
70
71 -- Reg out
72 ready_matrix_f0_0 : OUT STD_LOGIC;
73 ready_matrix_f0_1 : OUT STD_LOGIC;
74 ready_matrix_f1 : OUT STD_LOGIC;
75 ready_matrix_f2 : OUT STD_LOGIC;
76 error_anticipating_empty_fifo : OUT STD_LOGIC;
77 error_bad_component_error : OUT STD_LOGIC;
78 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
79
80 -- Reg In
81 status_ready_matrix_f0_0 :IN STD_LOGIC;
82 status_ready_matrix_f0_1 :IN STD_LOGIC;
83 status_ready_matrix_f1 :IN STD_LOGIC;
84 status_ready_matrix_f2 :IN STD_LOGIC;
85 status_error_anticipating_empty_fifo :IN STD_LOGIC;
86 status_error_bad_component_error :IN STD_LOGIC;
87
88 config_active_interruption_onNewMatrix : IN STD_LOGIC;
89 config_active_interruption_onError : IN STD_LOGIC;
90 addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
91 addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
92 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
93 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
94 );
95 END;
96
97 ARCHITECTURE Behavioral OF lpp_dma_ip IS
98 -----------------------------------------------------------------------------
99 SIGNAL DMAIn : DMA_In_Type;
100 SIGNAL header_dmai : DMA_In_Type;
101 SIGNAL component_dmai : DMA_In_Type;
102 SIGNAL DMAOut : DMA_OUt_Type;
103 -----------------------------------------------------------------------------
104
105 -----------------------------------------------------------------------------
106 -----------------------------------------------------------------------------
107 TYPE state_DMAWriteBurst IS (IDLE,
108 TRASH_FIFO,
109 WAIT_HEADER_ACK,
110 SEND_DATA,
111 WAIT_DATA_ACK,
112 CHECK_LENGTH
113 );
114 SIGNAL state : state_DMAWriteBurst := IDLE;
115
116 SIGNAL nbSend : INTEGER;
117 SIGNAL matrix_type : STD_LOGIC_VECTOR(1 DOWNTO 0);
118 SIGNAL component_type : STD_LOGIC_VECTOR(3 DOWNTO 0);
119 SIGNAL component_type_pre : STD_LOGIC_VECTOR(3 DOWNTO 0);
120 SIGNAL header_check_ok : STD_LOGIC;
121 SIGNAL address_matrix : STD_LOGIC_VECTOR(31 DOWNTO 0);
122 SIGNAL send_matrix : STD_LOGIC;
123 SIGNAL request : STD_LOGIC;
124 SIGNAL remaining_data_request : INTEGER;
125 SIGNAL Address : STD_LOGIC_VECTOR(31 DOWNTO 0);
126 -----------------------------------------------------------------------------
127 -----------------------------------------------------------------------------
128 SIGNAL header_select : STD_LOGIC;
129
130 SIGNAL header_send : STD_LOGIC;
131 SIGNAL header_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
132 SIGNAL header_send_ok : STD_LOGIC;
133 SIGNAL header_send_ko : STD_LOGIC;
134
135 SIGNAL component_send : STD_LOGIC;
136 SIGNAL component_send_ok : STD_LOGIC;
137 SIGNAL component_send_ko : STD_LOGIC;
138 -----------------------------------------------------------------------------
139 SIGNAL fifo_ren_trash : STD_LOGIC;
140 SIGNAL component_fifo_ren : STD_LOGIC;
141
142 -----------------------------------------------------------------------------
143 SIGNAL debug_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
144
145 BEGIN
146
147 -----------------------------------------------------------------------------
148 -- DMA to AHB interface
149 -----------------------------------------------------------------------------
150
151 DMA2AHB_1 : DMA2AHB
152 GENERIC MAP (
153 hindex => hindex,
154 vendorid => VENDOR_LPP,
155 deviceid => 0,
156 version => 0,
157 syncrst => 1,
158 boundary => 1) -- FIX 11/01/2013
159 PORT MAP (
160 HCLK => HCLK,
161 HRESETn => HRESETn,
162 DMAIn => DMAIn,
163 DMAOut => DMAOut,
164 AHBIn => AHB_Master_In,
165 AHBOut => AHB_Master_Out);
166
167 debug_reg <= debug_reg_s;
168
169 debug_info: PROCESS (HCLK, HRESETn)
170 BEGIN -- PROCESS debug_info
171 IF HRESETn = '0' THEN -- asynchronous reset (active low)
172 debug_reg <= (OTHERS => '0');
173 ELSIF HCLK'event AND HCLK = '1' THEN -- rising clock edge
174 debug_reg_s(0) <= debug_reg_s(0) OR (DMAOut.Retry );
175 debug_reg_s(1) <= debug_reg_s(1) OR (DMAOut.Grant AND DMAOut.Retry) ;
176 IF state = TRASH_FIFO THEN debug_reg(2) <= '1'; END IF;
177 debug_reg_s(3) <= debug_reg_s(3) OR (header_send_ko);
178 debug_reg_s(4) <= debug_reg_s(4) OR (header_send_ok);
179 debug_reg_s(5) <= debug_reg_s(5) OR (component_send_ko);
180 debug_reg_s(6) <= debug_reg_s(6) OR (component_send_ok);
181
182 debug_reg_s(31 DOWNTO 7) <= (OTHERS => '1');
183 END IF;
184 END PROCESS debug_info;
185
186
187 matrix_type <= header(1 DOWNTO 0);
188 component_type <= header(5 DOWNTO 2);
189
190 send_matrix <= '1' WHEN matrix_type = "00" AND status_ready_matrix_f0_0 = '0' ELSE
191 '1' WHEN matrix_type = "01" AND status_ready_matrix_f0_1 = '0' ELSE
192 '1' WHEN matrix_type = "10" AND status_ready_matrix_f1 = '0' ELSE
193 '1' WHEN matrix_type = "11" AND status_ready_matrix_f2 = '0' ELSE
194 '0';
195
196 header_check_ok <= '0' WHEN component_type = "1111" ELSE
197 '1' WHEN component_type = "0000" AND component_type_pre = "1110" ELSE
198 '1' WHEN component_type = component_type_pre + "0001" ELSE
199 '0';
200
201 address_matrix <= addr_matrix_f0_0 WHEN matrix_type = "00" ELSE
202 addr_matrix_f0_1 WHEN matrix_type = "01" ELSE
203 addr_matrix_f1 WHEN matrix_type = "10" ELSE
204 addr_matrix_f2 WHEN matrix_type = "11" ELSE
205 (OTHERS => '0');
206
207 -----------------------------------------------------------------------------
208 -- DMA control
209 -----------------------------------------------------------------------------
210 DMAWriteFSM_p : PROCESS (HCLK, HRESETn)
211 BEGIN -- PROCESS DMAWriteBurst_p
212 IF HRESETn = '0' THEN -- asynchronous reset (active low)
213 state <= IDLE;
214 header_ack <= '0';
215 ready_matrix_f0_0 <= '0';
216 ready_matrix_f0_1 <= '0';
217 ready_matrix_f1 <= '0';
218 ready_matrix_f2 <= '0';
219 error_anticipating_empty_fifo <= '0';
220 error_bad_component_error <= '0';
221 component_type_pre <= "1110";
222 fifo_ren_trash <= '1';
223 component_send <= '0';
224 address <= (OTHERS => '0');
225 header_select <= '0';
226 header_send <= '0';
227 header_data <= (OTHERS => '0');
228 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
229
230 CASE state IS
231 WHEN IDLE =>
232 ready_matrix_f0_0 <= '0';
233 ready_matrix_f0_1 <= '0';
234 ready_matrix_f1 <= '0';
235 ready_matrix_f2 <= '0';
236 error_bad_component_error <= '0';
237 header_select <= '1';
238 IF header_val = '1' AND fifo_empty = '0' AND send_matrix = '1' THEN
239 IF header_check_ok = '1' THEN
240 header_data <= header;
241 component_type_pre <= header(5 DOWNTO 2);
242 header_ack <= '1';
243 --
244 header_send <= '1';
245 IF component_type = "0000" THEN
246 address <= address_matrix;
247 END IF;
248 header_data <= header;
249 --
250 state <= WAIT_HEADER_ACK;
251 ELSE
252 error_bad_component_error <= '1';
253 component_type_pre <= "1110";
254 header_ack <= '1';
255 state <= TRASH_FIFO;
256 END IF;
257 END IF;
258
259 WHEN TRASH_FIFO =>
260 error_bad_component_error <= '0';
261 error_anticipating_empty_fifo <= '0';
262 IF fifo_empty = '1' THEN
263 state <= IDLE;
264 fifo_ren_trash <= '1';
265 ELSE
266 fifo_ren_trash <= '0';
267 END IF;
268
269 WHEN WAIT_HEADER_ACK =>
270 header_send <= '0';
271 IF header_send_ko = '1' THEN
272 state <= TRASH_FIFO;
273 error_anticipating_empty_fifo <= '1';
274 -- TODO : error sending header
275 ELSIF header_send_ok = '1' THEN
276 header_select <= '0';
277 state <= SEND_DATA;
278 address <= address + 4;
279 END IF;
280
281 WHEN SEND_DATA =>
282 IF fifo_empty = '1' THEN
283 state <= IDLE;
284 IF component_type = "1110" THEN
285 CASE matrix_type IS
286 WHEN "00" => ready_matrix_f0_0 <= '1';
287 WHEN "01" => ready_matrix_f0_1 <= '1';
288 WHEN "10" => ready_matrix_f1 <= '1';
289 WHEN "11" => ready_matrix_f2 <= '1';
290 WHEN OTHERS => NULL;
291 END CASE;
292 END IF;
293 ELSE
294 component_send <= '1';
295 address <= address;
296 state <= WAIT_DATA_ACK;
297 END IF;
298
299 WHEN WAIT_DATA_ACK =>
300 component_send <= '0';
301 IF component_send_ok = '1' THEN
302 address <= address + 64;
303 state <= SEND_DATA;
304 ELSIF component_send_ko = '1' THEN
305 error_anticipating_empty_fifo <= '0';
306 state <= TRASH_FIFO;
307 END IF;
308
309 WHEN CHECK_LENGTH =>
310 state <= IDLE;
311 WHEN OTHERS => NULL;
312 END CASE;
313
314 END IF;
315 END PROCESS DMAWriteFSM_p;
316
317 -----------------------------------------------------------------------------
318 -- SEND 1 word by DMA
319 -----------------------------------------------------------------------------
320 lpp_dma_send_1word_1 : lpp_dma_send_1word
321 PORT MAP (
322 HCLK => HCLK,
323 HRESETn => HRESETn,
324 DMAIn => header_dmai,
325 DMAOut => DMAOut,
326
327 send => header_send,
328 address => address,
329 data => header_data,
330 send_ok => header_send_ok,
331 send_ko => header_send_ko
332 );
333
334 -----------------------------------------------------------------------------
335 -- SEND 16 word by DMA (in burst mode)
336 -----------------------------------------------------------------------------
337 lpp_dma_send_16word_1 : lpp_dma_send_16word
338 PORT MAP (
339 HCLK => HCLK,
340 HRESETn => HRESETn,
341 DMAIn => component_dmai,
342 DMAOut => DMAOut,
343
344 send => component_send,
345 address => address,
346 data => fifo_data,
347 ren => component_fifo_ren,
348 send_ok => component_send_ok,
349 send_ko => component_send_ko);
350
351 DMAIn <= header_dmai WHEN header_select = '1' ELSE component_dmai;
352 fifo_ren <= fifo_ren_trash WHEN header_select = '1' ELSE component_fifo_ren;
353
354 END Behavioral;
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