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(MINI-LFR) WFP_MS-0.1-53
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1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -------------------------------------------------------------------------------
22 22 LIBRARY IEEE;
23 23 USE IEEE.numeric_std.ALL;
24 24 USE IEEE.std_logic_1164.ALL;
25 25 LIBRARY grlib;
26 26 USE grlib.amba.ALL;
27 27 USE grlib.stdlib.ALL;
28 28 LIBRARY techmap;
29 29 USE techmap.gencomp.ALL;
30 30 LIBRARY gaisler;
31 31 USE gaisler.memctrl.ALL;
32 32 USE gaisler.leon3.ALL;
33 33 USE gaisler.uart.ALL;
34 34 USE gaisler.misc.ALL;
35 35 USE gaisler.spacewire.ALL;
36 36 LIBRARY esa;
37 37 USE esa.memoryctrl.ALL;
38 38 LIBRARY lpp;
39 39 USE lpp.lpp_memory.ALL;
40 40 USE lpp.lpp_ad_conv.ALL;
41 41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 43 USE lpp.iir_filter.ALL;
44 44 USE lpp.general_purpose.ALL;
45 45 USE lpp.lpp_lfr_management.ALL;
46 46 USE lpp.lpp_leon3_soc_pkg.ALL;
47 47
48 48 ENTITY MINI_LFR_top IS
49 49
50 50 PORT (
51 51 clk_50 : IN STD_LOGIC;
52 52 clk_49 : IN STD_LOGIC;
53 53 reset : IN STD_LOGIC;
54 54 --BPs
55 55 BP0 : IN STD_LOGIC;
56 56 BP1 : IN STD_LOGIC;
57 57 --LEDs
58 58 LED0 : OUT STD_LOGIC;
59 59 LED1 : OUT STD_LOGIC;
60 60 LED2 : OUT STD_LOGIC;
61 61 --UARTs
62 62 TXD1 : IN STD_LOGIC;
63 63 RXD1 : OUT STD_LOGIC;
64 64 nCTS1 : OUT STD_LOGIC;
65 65 nRTS1 : IN STD_LOGIC;
66 66
67 67 TXD2 : IN STD_LOGIC;
68 68 RXD2 : OUT STD_LOGIC;
69 69 nCTS2 : OUT STD_LOGIC;
70 70 nDTR2 : IN STD_LOGIC;
71 71 nRTS2 : IN STD_LOGIC;
72 72 nDCD2 : OUT STD_LOGIC;
73 73
74 74 --EXT CONNECTOR
75 75 IO0 : INOUT STD_LOGIC;
76 76 IO1 : INOUT STD_LOGIC;
77 77 IO2 : INOUT STD_LOGIC;
78 78 IO3 : INOUT STD_LOGIC;
79 79 IO4 : INOUT STD_LOGIC;
80 80 IO5 : INOUT STD_LOGIC;
81 81 IO6 : INOUT STD_LOGIC;
82 82 IO7 : INOUT STD_LOGIC;
83 83 IO8 : INOUT STD_LOGIC;
84 84 IO9 : INOUT STD_LOGIC;
85 85 IO10 : INOUT STD_LOGIC;
86 86 IO11 : INOUT STD_LOGIC;
87 87
88 88 --SPACE WIRE
89 89 SPW_EN : OUT STD_LOGIC; -- 0 => off
90 90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
91 91 SPW_NOM_SIN : IN STD_LOGIC;
92 92 SPW_NOM_DOUT : OUT STD_LOGIC;
93 93 SPW_NOM_SOUT : OUT STD_LOGIC;
94 94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
95 95 SPW_RED_SIN : IN STD_LOGIC;
96 96 SPW_RED_DOUT : OUT STD_LOGIC;
97 97 SPW_RED_SOUT : OUT STD_LOGIC;
98 98 -- MINI LFR ADC INPUTS
99 99 ADC_nCS : OUT STD_LOGIC;
100 100 ADC_CLK : OUT STD_LOGIC;
101 101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
102 102
103 103 -- SRAM
104 104 SRAM_nWE : OUT STD_LOGIC;
105 105 SRAM_CE : OUT STD_LOGIC;
106 106 SRAM_nOE : OUT STD_LOGIC;
107 107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
108 108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
109 109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
110 110 );
111 111
112 112 END MINI_LFR_top;
113 113
114 114
115 115 ARCHITECTURE beh OF MINI_LFR_top IS
116 116 SIGNAL clk_50_s : STD_LOGIC := '0';
117 117 SIGNAL clk_25 : STD_LOGIC := '0';
118 118 SIGNAL clk_24 : STD_LOGIC := '0';
119 119 -----------------------------------------------------------------------------
120 120 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
121 121 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
122 122 --
123 123 SIGNAL errorn : STD_LOGIC;
124 124 -- UART AHB ---------------------------------------------------------------
125 125 -- SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
126 126 -- SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
127 127
128 128 -- UART APB ---------------------------------------------------------------
129 129 -- SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
130 130 -- SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
131 131 --
132 132 SIGNAL I00_s : STD_LOGIC;
133 133
134 134 -- CONSTANTS
135 135 CONSTANT CFG_PADTECH : INTEGER := inferred;
136 136 --
137 137 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
138 138 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
139 139 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
140 140
141 141 SIGNAL apbi_ext : apb_slv_in_type;
142 142 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5); -- := (OTHERS => apb_none);
143 143 SIGNAL ahbi_s_ext : ahb_slv_in_type;
144 144 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3); -- := (OTHERS => ahbs_none);
145 145 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
146 146 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1); -- := (OTHERS => ahbm_none);
147 147
148 148 -- Spacewire signals
149 149 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 150 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
151 151 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
152 152 SIGNAL spw_rxtxclk : STD_ULOGIC;
153 153 SIGNAL spw_rxclkn : STD_ULOGIC;
154 154 SIGNAL spw_clk : STD_LOGIC;
155 155 SIGNAL swni : grspw_in_type;
156 156 SIGNAL swno : grspw_out_type;
157 157 -- SIGNAL clkmn : STD_ULOGIC;
158 158 -- SIGNAL txclk : STD_ULOGIC;
159 159
160 160 --GPIO
161 161 SIGNAL gpioi : gpio_in_type;
162 162 SIGNAL gpioo : gpio_out_type;
163 163
164 164 -- AD Converter ADS7886
165 165 SIGNAL sample : Samples14v(7 DOWNTO 0);
166 166 SIGNAL sample_s : Samples(7 DOWNTO 0);
167 167 SIGNAL sample_val : STD_LOGIC;
168 168 SIGNAL ADC_nCS_sig : STD_LOGIC;
169 169 SIGNAL ADC_CLK_sig : STD_LOGIC;
170 170 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
171 171
172 172 SIGNAL bias_fail_sw_sig : STD_LOGIC;
173 173
174 174 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
175 175 SIGNAL observation_vector_0 : STD_LOGIC_VECTOR(11 DOWNTO 0);
176 176 SIGNAL observation_vector_1 : STD_LOGIC_VECTOR(11 DOWNTO 0);
177 177 -----------------------------------------------------------------------------
178 178
179 179 SIGNAL LFR_soft_rstn : STD_LOGIC;
180 180 SIGNAL LFR_rstn : STD_LOGIC;
181 181
182 182
183 183 SIGNAL rstn_25 : STD_LOGIC;
184 184 SIGNAL rstn_25_d1 : STD_LOGIC;
185 185 SIGNAL rstn_25_d2 : STD_LOGIC;
186 186 SIGNAL rstn_25_d3 : STD_LOGIC;
187 187
188 188 SIGNAL rstn_50 : STD_LOGIC;
189 189 SIGNAL rstn_50_d1 : STD_LOGIC;
190 190 SIGNAL rstn_50_d2 : STD_LOGIC;
191 191 SIGNAL rstn_50_d3 : STD_LOGIC;
192 192
193 193 SIGNAL lfr_debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
194 194 SIGNAL lfr_debug_vector_ms : STD_LOGIC_VECTOR(11 DOWNTO 0);
195 195
196 196 --
197 197 SIGNAL SRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
198 198
199 199 --
200 200 SIGNAL sample_hk : STD_LOGIC_VECTOR(15 DOWNTO 0);
201 201 SIGNAL HK_SEL : STD_LOGIC_VECTOR( 1 DOWNTO 0);
202 202
203 203 BEGIN -- beh
204 204
205 205 -----------------------------------------------------------------------------
206 206 -- CLK
207 207 -----------------------------------------------------------------------------
208 208
209 209 --PROCESS(clk_50)
210 210 --BEGIN
211 211 -- IF clk_50'EVENT AND clk_50 = '1' THEN
212 212 -- clk_50_s <= NOT clk_50_s;
213 213 -- END IF;
214 214 --END PROCESS;
215 215
216 216 --PROCESS(clk_50_s)
217 217 --BEGIN
218 218 -- IF clk_50_s'EVENT AND clk_50_s = '1' THEN
219 219 -- clk_25 <= NOT clk_25;
220 220 -- END IF;
221 221 --END PROCESS;
222 222
223 223 --PROCESS(clk_49)
224 224 --BEGIN
225 225 -- IF clk_49'EVENT AND clk_49 = '1' THEN
226 226 -- clk_24 <= NOT clk_24;
227 227 -- END IF;
228 228 --END PROCESS;
229 229
230 230 --PROCESS(clk_25)
231 231 --BEGIN
232 232 -- IF clk_25'EVENT AND clk_25 = '1' THEN
233 233 -- rstn_25 <= reset;
234 234 -- END IF;
235 235 --END PROCESS;
236 236
237 237 PROCESS (clk_50, reset)
238 238 BEGIN -- PROCESS
239 239 IF reset = '0' THEN -- asynchronous reset (active low)
240 240 clk_50_s <= '0';
241 241 rstn_50 <= '0';
242 242 rstn_50_d1 <= '0';
243 243 rstn_50_d2 <= '0';
244 244 rstn_50_d3 <= '0';
245 245
246 246 ELSIF clk_50'EVENT AND clk_50 = '1' THEN -- rising clock edge
247 247 clk_50_s <= NOT clk_50_s;
248 248 rstn_50_d1 <= '1';
249 249 rstn_50_d2 <= rstn_50_d1;
250 250 rstn_50_d3 <= rstn_50_d2;
251 251 rstn_50 <= rstn_50_d3;
252 252 END IF;
253 253 END PROCESS;
254 254
255 255 PROCESS (clk_50_s, rstn_50)
256 256 BEGIN -- PROCESS
257 257 IF rstn_50 = '0' THEN -- asynchronous reset (active low)
258 258 clk_25 <= '0';
259 259 rstn_25 <= '0';
260 260 rstn_25_d1 <= '0';
261 261 rstn_25_d2 <= '0';
262 262 rstn_25_d3 <= '0';
263 263 ELSIF clk_50_s'EVENT AND clk_50_s = '1' THEN -- rising clock edge
264 264 clk_25 <= NOT clk_25;
265 265 rstn_25_d1 <= '1';
266 266 rstn_25_d2 <= rstn_25_d1;
267 267 rstn_25_d3 <= rstn_25_d2;
268 268 rstn_25 <= rstn_25_d3;
269 269 END IF;
270 270 END PROCESS;
271 271
272 272 PROCESS (clk_49, reset)
273 273 BEGIN -- PROCESS
274 274 IF reset = '0' THEN -- asynchronous reset (active low)
275 275 clk_24 <= '0';
276 276 ELSIF clk_49'EVENT AND clk_49 = '1' THEN -- rising clock edge
277 277 clk_24 <= NOT clk_24;
278 278 END IF;
279 279 END PROCESS;
280 280
281 281 -----------------------------------------------------------------------------
282 282
283 283 PROCESS (clk_25, rstn_25)
284 284 BEGIN -- PROCESS
285 285 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
286 286 LED0 <= '0';
287 287 LED1 <= '0';
288 288 LED2 <= '0';
289 289 --IO1 <= '0';
290 290 --IO2 <= '1';
291 291 --IO3 <= '0';
292 292 --IO4 <= '0';
293 293 --IO5 <= '0';
294 294 --IO6 <= '0';
295 295 --IO7 <= '0';
296 296 --IO8 <= '0';
297 297 --IO9 <= '0';
298 298 --IO10 <= '0';
299 299 --IO11 <= '0';
300 300 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
301 301 LED0 <= '0';
302 302 LED1 <= '1';
303 303 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
304 304 --IO1 <= '1';
305 305 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
306 306 --IO3 <= ADC_SDO(0);
307 307 --IO4 <= ADC_SDO(1);
308 308 --IO5 <= ADC_SDO(2);
309 309 --IO6 <= ADC_SDO(3);
310 310 --IO7 <= ADC_SDO(4);
311 311 --IO8 <= ADC_SDO(5);
312 312 --IO9 <= ADC_SDO(6);
313 313 --IO10 <= ADC_SDO(7);
314 314 --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
315 315 END IF;
316 316 END PROCESS;
317 317
318 318 PROCESS (clk_24, rstn_25)
319 319 BEGIN -- PROCESS
320 320 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
321 321 I00_s <= '0';
322 322 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
323 323 I00_s <= NOT I00_s;
324 324 END IF;
325 325 END PROCESS;
326 326 -- IO0 <= I00_s;
327 327
328 328 --UARTs
329 329 nCTS1 <= '1';
330 330 nCTS2 <= '1';
331 331 nDCD2 <= '1';
332 332
333 333 --EXT CONNECTOR
334 334
335 335 --SPACE WIRE
336 336
337 337 leon3_soc_1 : leon3_soc
338 338 GENERIC MAP (
339 339 fabtech => apa3e,
340 340 memtech => apa3e,
341 341 padtech => inferred,
342 342 clktech => inferred,
343 343 disas => 0,
344 344 dbguart => 0,
345 345 pclow => 2,
346 346 clk_freq => 25000,
347 347 NB_CPU => 1,
348 348 ENABLE_FPU => 1,
349 349 FPU_NETLIST => 0,
350 350 ENABLE_DSU => 1,
351 351 ENABLE_AHB_UART => 1,
352 352 ENABLE_APB_UART => 1,
353 353 ENABLE_IRQMP => 1,
354 354 ENABLE_GPT => 1,
355 355 NB_AHB_MASTER => NB_AHB_MASTER,
356 356 NB_AHB_SLAVE => NB_AHB_SLAVE,
357 357 NB_APB_SLAVE => NB_APB_SLAVE,
358 358 ADDRESS_SIZE => 20,
359 359 USES_IAP_MEMCTRLR => 0)
360 360 PORT MAP (
361 361 clk => clk_25,
362 362 reset => rstn_25,
363 363 errorn => errorn,
364 364 ahbrxd => TXD1,
365 365 ahbtxd => RXD1,
366 366 urxd1 => TXD2,
367 367 utxd1 => RXD2,
368 368 address => SRAM_A,
369 369 data => SRAM_DQ,
370 370 nSRAM_BE0 => SRAM_nBE(0),
371 371 nSRAM_BE1 => SRAM_nBE(1),
372 372 nSRAM_BE2 => SRAM_nBE(2),
373 373 nSRAM_BE3 => SRAM_nBE(3),
374 374 nSRAM_WE => SRAM_nWE,
375 375 nSRAM_CE => SRAM_CE_s,
376 376 nSRAM_OE => SRAM_nOE,
377 377 nSRAM_READY => '0',
378 378 SRAM_MBE => OPEN,
379 379 apbi_ext => apbi_ext,
380 380 apbo_ext => apbo_ext,
381 381 ahbi_s_ext => ahbi_s_ext,
382 382 ahbo_s_ext => ahbo_s_ext,
383 383 ahbi_m_ext => ahbi_m_ext,
384 384 ahbo_m_ext => ahbo_m_ext);
385 385
386 386 SRAM_CE <= SRAM_CE_s(0);
387 387 -------------------------------------------------------------------------------
388 388 -- APB_LFR_MANAGEMENT ---------------------------------------------------------
389 389 -------------------------------------------------------------------------------
390 390 apb_lfr_management_1 : apb_lfr_management
391 391 GENERIC MAP (
392 392 pindex => 6,
393 393 paddr => 6,
394 394 pmask => 16#fff#,
395 395 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
396 396 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
397 397 PORT MAP (
398 398 clk25MHz => clk_25,
399 399 clk24_576MHz => clk_24, -- 49.152MHz/2
400 400 resetn => rstn_25,
401 401 grspw_tick => swno.tickout,
402 402 apbi => apbi_ext,
403 403 apbo => apbo_ext(6),
404 404 HK_sample => sample_hk,
405 405 HK_val => sample_val,
406 406 HK_sel => HK_SEL,
407 407 coarse_time => coarse_time,
408 408 fine_time => fine_time,
409 409 LFR_soft_rstn => LFR_soft_rstn
410 410 );
411 411
412 412 -----------------------------------------------------------------------
413 413 --- SpaceWire --------------------------------------------------------
414 414 -----------------------------------------------------------------------
415 415
416 416 SPW_EN <= '1';
417 417
418 418 spw_clk <= clk_50_s;
419 419 spw_rxtxclk <= spw_clk;
420 420 spw_rxclkn <= NOT spw_rxtxclk;
421 421
422 422 -- PADS for SPW1
423 423 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
424 424 PORT MAP (SPW_NOM_DIN, dtmp(0));
425 425 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
426 426 PORT MAP (SPW_NOM_SIN, stmp(0));
427 427 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
428 428 PORT MAP (SPW_NOM_DOUT, swno.d(0));
429 429 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
430 430 PORT MAP (SPW_NOM_SOUT, swno.s(0));
431 431 -- PADS FOR SPW2
432 432 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
433 433 PORT MAP (SPW_RED_SIN, dtmp(1));
434 434 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
435 435 PORT MAP (SPW_RED_DIN, stmp(1));
436 436 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
437 437 PORT MAP (SPW_RED_DOUT, swno.d(1));
438 438 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
439 439 PORT MAP (SPW_RED_SOUT, swno.s(1));
440 440
441 441 -- GRSPW PHY
442 442 --spw1_input: if CFG_SPW_GRSPW = 1 generate
443 443 spw_inputloop : FOR j IN 0 TO 1 GENERATE
444 444 spw_phy0 : grspw_phy
445 445 GENERIC MAP(
446 446 tech => apa3e,
447 447 rxclkbuftype => 1,
448 448 scantest => 0)
449 449 PORT MAP(
450 450 rxrst => swno.rxrst,
451 451 di => dtmp(j),
452 452 si => stmp(j),
453 453 rxclko => spw_rxclk(j),
454 454 do => swni.d(j),
455 455 ndo => swni.nd(j*5+4 DOWNTO j*5),
456 456 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
457 457 END GENERATE spw_inputloop;
458 458
459 459 swni.rmapnodeaddr <= (OTHERS => '0');
460 460
461 461 -- SPW core
462 462 sw0 : grspwm GENERIC MAP(
463 463 tech => apa3e,
464 464 hindex => 1,
465 465 pindex => 5,
466 466 paddr => 5,
467 467 pirq => 11,
468 468 sysfreq => 25000, -- CPU_FREQ
469 469 rmap => 1,
470 470 rmapcrc => 1,
471 471 fifosize1 => 16,
472 472 fifosize2 => 16,
473 473 rxclkbuftype => 1,
474 474 rxunaligned => 0,
475 475 rmapbufs => 4,
476 476 ft => 0,
477 477 netlist => 0,
478 478 ports => 2,
479 479 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
480 480 memtech => apa3e,
481 481 destkey => 2,
482 482 spwcore => 1
483 483 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
484 484 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
485 485 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
486 486 )
487 487 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
488 488 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
489 489 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
490 490 swni, swno);
491 491
492 492 swni.tickin <= '0';
493 493 swni.rmapen <= '1';
494 494 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
495 495 swni.tickinraw <= '0';
496 496 swni.timein <= (OTHERS => '0');
497 497 swni.dcrstval <= (OTHERS => '0');
498 498 swni.timerrstval <= (OTHERS => '0');
499 499
500 500 -------------------------------------------------------------------------------
501 501 -- LFR ------------------------------------------------------------------------
502 502 -------------------------------------------------------------------------------
503 503
504 504
505 505 LFR_rstn <= LFR_soft_rstn AND rstn_25;
506 506 --LFR_rstn <= rstn_25;
507 507
508 508 lpp_lfr_1 : lpp_lfr
509 509 GENERIC MAP (
510 510 Mem_use => use_RAM,
511 511 nb_data_by_buffer_size => 32,
512 512 nb_snapshot_param_size => 32,
513 513 delta_vector_size => 32,
514 514 delta_vector_size_f0_2 => 7, -- log2(96)
515 515 pindex => 15,
516 516 paddr => 15,
517 517 pmask => 16#fff#,
518 518 pirq_ms => 6,
519 519 pirq_wfp => 14,
520 520 hindex => 2,
521 top_lfr_version => X"000134") -- aa.bb.cc version
521 top_lfr_version => X"000135") -- aa.bb.cc version
522 522 PORT MAP (
523 523 clk => clk_25,
524 524 rstn => LFR_rstn,
525 525 sample_B => sample_s(2 DOWNTO 0),
526 526 sample_E => sample_s(7 DOWNTO 3),
527 527 sample_val => sample_val,
528 528 apbi => apbi_ext,
529 529 apbo => apbo_ext(15),
530 530 ahbi => ahbi_m_ext,
531 531 ahbo => ahbo_m_ext(2),
532 532 coarse_time => coarse_time,
533 533 fine_time => fine_time,
534 534 data_shaping_BW => bias_fail_sw_sig,
535 535 debug_vector => lfr_debug_vector,
536 536 debug_vector_ms => lfr_debug_vector_ms
537 537 );
538 538
539 539 observation_reg(11 DOWNTO 0) <= lfr_debug_vector;
540 540 observation_reg(31 DOWNTO 12) <= (OTHERS => '0');
541 541 observation_vector_0(11 DOWNTO 0) <= lfr_debug_vector;
542 542 observation_vector_1(11 DOWNTO 0) <= lfr_debug_vector;
543 543 IO0 <= rstn_25;
544 544 IO1 <= lfr_debug_vector_ms(0); -- LFR MS FFT data_valid
545 545 IO2 <= lfr_debug_vector_ms(0); -- LFR MS FFT ready
546 546 IO3 <= lfr_debug_vector(0); -- LFR APBREG error_buffer_full
547 547 IO4 <= lfr_debug_vector(1); -- LFR APBREG reg_sp.status_error_buffer_full
548 548 IO5 <= lfr_debug_vector(8); -- LFR APBREG ready_matrix_f2
549 549 IO6 <= lfr_debug_vector(9); -- LFR APBREG reg0_ready_matrix_f2
550 550 IO7 <= lfr_debug_vector(10); -- LFR APBREG reg0_ready_matrix_f2
551 551
552 552 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
553 553 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
554 554 END GENERATE all_sample;
555 555
556 556 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
557 557 GENERIC MAP(
558 558 ChannelCount => 8,
559 559 SampleNbBits => 14,
560 560 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
561 561 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
562 562 PORT MAP (
563 563 -- CONV
564 564 cnv_clk => clk_24,
565 565 cnv_rstn => rstn_25,
566 566 cnv => ADC_nCS_sig,
567 567 -- DATA
568 568 clk => clk_25,
569 569 rstn => rstn_25,
570 570 sck => ADC_CLK_sig,
571 571 sdo => ADC_SDO_sig,
572 572 -- SAMPLE
573 573 sample => sample,
574 574 sample_val => sample_val);
575 575
576 576 --IO10 <= ADC_SDO_sig(5);
577 577 --IO9 <= ADC_SDO_sig(4);
578 578 --IO8 <= ADC_SDO_sig(3);
579 579
580 580 ADC_nCS <= ADC_nCS_sig;
581 581 ADC_CLK <= ADC_CLK_sig;
582 582 ADC_SDO_sig <= ADC_SDO;
583 583
584 584 sample_hk <= "0001000100010001" WHEN HK_SEL = "00" ELSE
585 585 "0010001000100010" WHEN HK_SEL = "10" ELSE
586 "0100010001000100" WHEN HK_SEL = "10" ELSE
586 "0100010001000100" WHEN HK_SEL = "11" ELSE
587 587 (OTHERS => '0');
588 588
589 589
590 590 ----------------------------------------------------------------------
591 591 --- GPIO -----------------------------------------------------------
592 592 ----------------------------------------------------------------------
593 593
594 594 grgpio0 : grgpio
595 595 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
596 596 PORT MAP(rstn_25, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
597 597
598 598 gpioi.sig_en <= (OTHERS => '0');
599 599 gpioi.sig_in <= (OTHERS => '0');
600 600 gpioi.din <= (OTHERS => '0');
601 601 --pio_pad_0 : iopad
602 602 -- GENERIC MAP (tech => CFG_PADTECH)
603 603 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
604 604 --pio_pad_1 : iopad
605 605 -- GENERIC MAP (tech => CFG_PADTECH)
606 606 -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
607 607 --pio_pad_2 : iopad
608 608 -- GENERIC MAP (tech => CFG_PADTECH)
609 609 -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
610 610 --pio_pad_3 : iopad
611 611 -- GENERIC MAP (tech => CFG_PADTECH)
612 612 -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
613 613 --pio_pad_4 : iopad
614 614 -- GENERIC MAP (tech => CFG_PADTECH)
615 615 -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
616 616 --pio_pad_5 : iopad
617 617 -- GENERIC MAP (tech => CFG_PADTECH)
618 618 -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
619 619 --pio_pad_6 : iopad
620 620 -- GENERIC MAP (tech => CFG_PADTECH)
621 621 -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
622 622 --pio_pad_7 : iopad
623 623 -- GENERIC MAP (tech => CFG_PADTECH)
624 624 -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
625 625
626 626 PROCESS (clk_25, rstn_25)
627 627 BEGIN -- PROCESS
628 628 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
629 629 -- --IO0 <= '0';
630 630 -- IO1 <= '0';
631 631 -- IO2 <= '0';
632 632 -- IO3 <= '0';
633 633 -- IO4 <= '0';
634 634 -- IO5 <= '0';
635 635 -- IO6 <= '0';
636 636 -- IO7 <= '0';
637 637 IO8 <= '0';
638 638 IO9 <= '0';
639 639 IO10 <= '0';
640 640 IO11 <= '0';
641 641 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
642 642 CASE gpioo.dout(2 DOWNTO 0) IS
643 643 WHEN "011" =>
644 644 -- --IO0 <= observation_reg(0 );
645 645 -- IO1 <= observation_reg(1 );
646 646 -- IO2 <= observation_reg(2 );
647 647 -- IO3 <= observation_reg(3 );
648 648 -- IO4 <= observation_reg(4 );
649 649 -- IO5 <= observation_reg(5 );
650 650 -- IO6 <= observation_reg(6 );
651 651 -- IO7 <= observation_reg(7 );
652 652 IO8 <= observation_reg(8);
653 653 IO9 <= observation_reg(9);
654 654 IO10 <= observation_reg(10);
655 655 IO11 <= observation_reg(11);
656 656 WHEN "001" =>
657 657 -- --IO0 <= observation_reg(0 + 12);
658 658 -- IO1 <= observation_reg(1 + 12);
659 659 -- IO2 <= observation_reg(2 + 12);
660 660 -- IO3 <= observation_reg(3 + 12);
661 661 -- IO4 <= observation_reg(4 + 12);
662 662 -- IO5 <= observation_reg(5 + 12);
663 663 -- IO6 <= observation_reg(6 + 12);
664 664 -- IO7 <= observation_reg(7 + 12);
665 665 IO8 <= observation_reg(8 + 12);
666 666 IO9 <= observation_reg(9 + 12);
667 667 IO10 <= observation_reg(10 + 12);
668 668 IO11 <= observation_reg(11 + 12);
669 669 WHEN "010" =>
670 670 -- --IO0 <= observation_reg(0 + 12 + 12);
671 671 -- IO1 <= observation_reg(1 + 12 + 12);
672 672 -- IO2 <= observation_reg(2 + 12 + 12);
673 673 -- IO3 <= observation_reg(3 + 12 + 12);
674 674 -- IO4 <= observation_reg(4 + 12 + 12);
675 675 -- IO5 <= observation_reg(5 + 12 + 12);
676 676 -- IO6 <= observation_reg(6 + 12 + 12);
677 677 -- IO7 <= observation_reg(7 + 12 + 12);
678 678 IO8 <= '0';
679 679 IO9 <= '0';
680 680 IO10 <= '0';
681 681 IO11 <= '0';
682 682 WHEN "000" =>
683 683 -- --IO0 <= observation_vector_0(0 );
684 684 -- IO1 <= observation_vector_0(1 );
685 685 -- IO2 <= observation_vector_0(2 );
686 686 -- IO3 <= observation_vector_0(3 );
687 687 -- IO4 <= observation_vector_0(4 );
688 688 -- IO5 <= observation_vector_0(5 );
689 689 -- IO6 <= observation_vector_0(6 );
690 690 -- IO7 <= observation_vector_0(7 );
691 691 IO8 <= observation_vector_0(8);
692 692 IO9 <= observation_vector_0(9);
693 693 IO10 <= observation_vector_0(10);
694 694 IO11 <= observation_vector_0(11);
695 695 WHEN "100" =>
696 696 -- --IO0 <= observation_vector_1(0 );
697 697 -- IO1 <= observation_vector_1(1 );
698 698 -- IO2 <= observation_vector_1(2 );
699 699 -- IO3 <= observation_vector_1(3 );
700 700 -- IO4 <= observation_vector_1(4 );
701 701 -- IO5 <= observation_vector_1(5 );
702 702 -- IO6 <= observation_vector_1(6 );
703 703 -- IO7 <= observation_vector_1(7 );
704 704 IO8 <= observation_vector_1(8);
705 705 IO9 <= observation_vector_1(9);
706 706 IO10 <= observation_vector_1(10);
707 707 IO11 <= observation_vector_1(11);
708 708 WHEN OTHERS => NULL;
709 709 END CASE;
710 710
711 711 END IF;
712 712 END PROCESS;
713 713 -----------------------------------------------------------------------------
714 714 --
715 715 -----------------------------------------------------------------------------
716 716 all_apbo_ext : FOR I IN NB_APB_SLAVE-1+5 DOWNTO 5 GENERATE
717 717 apbo_ext_not_used : IF I /= 5 AND I /= 6 AND I /= 11 AND I /= 15 GENERATE
718 718 apbo_ext(I) <= apb_none;
719 719 END GENERATE apbo_ext_not_used;
720 720 END GENERATE all_apbo_ext;
721 721
722 722
723 723 all_ahbo_ext : FOR I IN NB_AHB_SLAVE-1+3 DOWNTO 3 GENERATE
724 724 ahbo_s_ext(I) <= ahbs_none;
725 725 END GENERATE all_ahbo_ext;
726 726
727 727 all_ahbo_m_ext : FOR I IN NB_AHB_MASTER-1+1 DOWNTO 1 GENERATE
728 728 ahbo_m_ext_not_used : IF I /= 1 AND I /= 2 GENERATE
729 729 ahbo_m_ext(I) <= ahbm_none;
730 730 END GENERATE ahbo_m_ext_not_used;
731 731 END GENERATE all_ahbo_m_ext;
732 732
733 733 END beh;
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@@ -1,31 +1,33
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -- jean-christophe.pellion@easii-ic.com
22 22 -------------------------------------------------------------------------------
23 23
24 24 LIBRARY ieee;
25 25 USE ieee.std_logic_1164.ALL;
26 26
27 27 PACKAGE data_type_pkg IS
28 28
29 TYPE array_integer IS ARRAY (NATURAL RANGE <>) OF INTEGER;
30
29 31 TYPE sample_vector IS ARRAY(NATURAL RANGE <>, NATURAL RANGE <>) OF STD_LOGIC;
30 32
31 33 END data_type_pkg;
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@@ -1,380 +1,387
1 1 ----------------------------------------------------------------------------------
2 2 -- Company:
3 3 -- Engineer:
4 4 --
5 5 -- Create Date: 11:17:05 07/02/2012
6 6 -- Design Name:
7 7 -- Module Name: apb_lfr_time_management - Behavioral
8 8 -- Project Name:
9 9 -- Target Devices:
10 10 -- Tool versions:
11 11 -- Description:
12 12 --
13 13 -- Dependencies:
14 14 --
15 15 -- Revision:
16 16 -- Revision 0.01 - File Created
17 17 -- Additional Comments:
18 18 --
19 19 ----------------------------------------------------------------------------------
20 20 LIBRARY IEEE;
21 21 USE IEEE.STD_LOGIC_1164.ALL;
22 22 USE IEEE.NUMERIC_STD.ALL;
23 23 LIBRARY grlib;
24 24 USE grlib.amba.ALL;
25 25 USE grlib.stdlib.ALL;
26 26 USE grlib.devices.ALL;
27 27 LIBRARY lpp;
28 28 USE lpp.apb_devices_list.ALL;
29 29 USE lpp.general_purpose.ALL;
30 30 USE lpp.lpp_lfr_management.ALL;
31 31 USE lpp.lpp_lfr_management_apbreg_pkg.ALL;
32 32
33 33
34 34 ENTITY apb_lfr_management IS
35 35
36 36 GENERIC(
37 pindex : INTEGER := 0; --! APB slave index
38 paddr : INTEGER := 0; --! ADDR field of the APB BAR
39 pmask : INTEGER := 16#fff#; --! MASK field of the APB BAR
37 pindex : INTEGER := 0; --! APB slave index
38 paddr : INTEGER := 0; --! ADDR field of the APB BAR
39 pmask : INTEGER := 16#fff#; --! MASK field of the APB BAR
40 40 FIRST_DIVISION : INTEGER := 374;
41 41 NB_SECOND_DESYNC : INTEGER := 60
42 42 );
43 43
44 44 PORT (
45 45 clk25MHz : IN STD_LOGIC; --! Clock
46 46 clk24_576MHz : IN STD_LOGIC; --! secondary clock
47 47 resetn : IN STD_LOGIC; --! Reset
48 48
49 49 grspw_tick : IN STD_LOGIC; --! grspw signal asserted when a valid time-code is received
50 50
51 apbi : IN apb_slv_in_type; --! APB slave input signals
52 apbo : OUT apb_slv_out_type; --! APB slave output signals
51 apbi : IN apb_slv_in_type; --! APB slave input signals
52 apbo : OUT apb_slv_out_type; --! APB slave output signals
53 53 ---------------------------------------------------------------------------
54 HK_sample : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
55 HK_val : IN STD_LOGIC;
56 HK_sel : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
54 HK_sample : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
55 HK_val : IN STD_LOGIC;
56 HK_sel : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
57 57 ---------------------------------------------------------------------------
58 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time
59 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); --! fine TIME
58 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time
59 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); --! fine TIME
60 60 ---------------------------------------------------------------------------
61 61 LFR_soft_rstn : OUT STD_LOGIC
62 62 );
63 63
64 64 END apb_lfr_management;
65 65
66 66 ARCHITECTURE Behavioral OF apb_lfr_management IS
67 67
68 68 CONSTANT REVISION : INTEGER := 1;
69 69 CONSTANT pconfig : apb_config_type := (
70 70 0 => ahb_device_reg (VENDOR_LPP, 14, 0, REVISION, 0),
71 71 1 => apb_iobar(paddr, pmask)
72 72 );
73 73
74 74 TYPE apb_lfr_time_management_Reg IS RECORD
75 75 ctrl : STD_LOGIC;
76 76 soft_reset : STD_LOGIC;
77 77 coarse_time_load : STD_LOGIC_VECTOR(30 DOWNTO 0);
78 78 coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
79 79 fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
80 80 LFR_soft_reset : STD_LOGIC;
81 HK_temp_0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
82 HK_temp_1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
83 HK_temp_2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
81 HK_temp_0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
82 HK_temp_1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
83 HK_temp_2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
84 84 END RECORD;
85 SIGNAL r : apb_lfr_time_management_Reg;
86
85 SIGNAL r : apb_lfr_time_management_Reg;
86
87 87 SIGNAL Rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
88 88 SIGNAL force_tick : STD_LOGIC;
89 89 SIGNAL previous_force_tick : STD_LOGIC;
90 90 SIGNAL soft_tick : STD_LOGIC;
91 91
92 92 SIGNAL coarsetime_reg_updated : STD_LOGIC;
93 93 SIGNAL coarsetime_reg : STD_LOGIC_VECTOR(30 DOWNTO 0);
94 94
95 95 --SIGNAL coarse_time_new : STD_LOGIC;
96 96 SIGNAL coarse_time_new_49 : STD_LOGIC;
97 97 SIGNAL coarse_time_49 : STD_LOGIC_VECTOR(31 DOWNTO 0);
98 98 SIGNAL coarse_time_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
99 99
100 100 --SIGNAL fine_time_new : STD_LOGIC;
101 101 --SIGNAL fine_time_new_temp : STD_LOGIC;
102 SIGNAL fine_time_new_49 : STD_LOGIC;
103 SIGNAL fine_time_49 : STD_LOGIC_VECTOR(15 DOWNTO 0);
104 SIGNAL fine_time_s : STD_LOGIC_VECTOR(15 DOWNTO 0);
105 SIGNAL tick : STD_LOGIC;
106 SIGNAL new_timecode : STD_LOGIC;
107 SIGNAL new_coarsetime : STD_LOGIC;
108
102 SIGNAL fine_time_new_49 : STD_LOGIC;
103 SIGNAL fine_time_49 : STD_LOGIC_VECTOR(15 DOWNTO 0);
104 SIGNAL fine_time_s : STD_LOGIC_VECTOR(15 DOWNTO 0);
105 SIGNAL tick : STD_LOGIC;
106 SIGNAL new_timecode : STD_LOGIC;
107 SIGNAL new_coarsetime : STD_LOGIC;
108
109 109 SIGNAL time_new_49 : STD_LOGIC;
110 110 SIGNAL time_new : STD_LOGIC;
111 111
112 112 -----------------------------------------------------------------------------
113 113 SIGNAL force_reset : STD_LOGIC;
114 114 SIGNAL previous_force_reset : STD_LOGIC;
115 SIGNAL soft_reset : STD_LOGIC;
116 SIGNAL soft_reset_sync : STD_LOGIC;
115 SIGNAL soft_reset : STD_LOGIC;
116 SIGNAL soft_reset_sync : STD_LOGIC;
117 117 -----------------------------------------------------------------------------
118 SIGNAL HK_temp_0_s : STD_LOGIC_VECTOR(15 DOWNTO 0);
119 SIGNAL HK_temp_1_s : STD_LOGIC_VECTOR(15 DOWNTO 0);
120 SIGNAL HK_temp_2_s : STD_LOGIC_VECTOR(15 DOWNTO 0);
121 SIGNAL HK_sel_s : STD_LOGIC_VECTOR( 1 DOWNTO 0);
118 SIGNAL HK_temp_0_s : STD_LOGIC_VECTOR(15 DOWNTO 0);
119 SIGNAL HK_temp_1_s : STD_LOGIC_VECTOR(15 DOWNTO 0);
120 SIGNAL HK_temp_2_s : STD_LOGIC_VECTOR(15 DOWNTO 0);
121 SIGNAL HK_sel_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
122 122
123 123 SIGNAL rstn_LFR_TM : STD_LOGIC;
124 124
125 125 BEGIN
126 126
127 127 LFR_soft_rstn <= NOT r.LFR_soft_reset;
128
128
129 129 PROCESS(resetn, clk25MHz)
130 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
130 131 BEGIN
131 132
132 133 IF resetn = '0' THEN
133 Rdata <= (OTHERS => '0');
134 r.coarse_time_load <= (OTHERS => '0');
135 r.soft_reset <= '0';
136 r.ctrl <= '0';
137 r.LFR_soft_reset <= '1';
138
134 Rdata <= (OTHERS => '0');
135 r.coarse_time_load <= (OTHERS => '0');
136 r.soft_reset <= '0';
137 r.ctrl <= '0';
138 r.LFR_soft_reset <= '1';
139
139 140 force_tick <= '0';
140 141 previous_force_tick <= '0';
141 142 soft_tick <= '0';
142 143
143 144 coarsetime_reg_updated <= '0';
144 145
145 146 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN
146 147 coarsetime_reg_updated <= '0';
147 148
148 149 force_tick <= r.ctrl;
149 150 previous_force_tick <= force_tick;
150 151 IF (previous_force_tick = '0') AND (force_tick = '1') THEN
151 152 soft_tick <= '1';
152 153 ELSE
153 154 soft_tick <= '0';
154 155 END IF;
155
156
156 157 force_reset <= r.soft_reset;
157 158 previous_force_reset <= force_reset;
158 159 IF (previous_force_reset = '0') AND (force_reset = '1') THEN
159 160 soft_reset <= '1';
160 161 ELSE
161 162 soft_reset <= '0';
162 163 END IF;
163 164
164 --APB Write OP
165 IF (apbi.psel(pindex) AND apbi.penable AND apbi.pwrite) = '1' THEN
166 CASE apbi.paddr(7 DOWNTO 2) IS
165 paddr := "000000";
166 paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
167 Rdata <= (OTHERS => '0');
168
169
170 IF apbi.psel(pindex) = '1' THEN
171 --APB READ OP
172 CASE paddr(7 DOWNTO 2) IS
167 173 WHEN ADDR_LFR_MANAGMENT_CONTROL =>
168 r.ctrl <= apbi.pwdata(0);
169 r.soft_reset <= apbi.pwdata(1);
170 r.LFR_soft_reset <= apbi.pwdata(2);
174 Rdata(0) <= r.ctrl;
175 Rdata(1) <= r.soft_reset;
176 Rdata(2) <= r.LFR_soft_reset;
177 Rdata(31 DOWNTO 3) <= (OTHERS => '0');
171 178 WHEN ADDR_LFR_MANAGMENT_TIME_LOAD =>
172 r.coarse_time_load <= apbi.pwdata(30 DOWNTO 0);
173 coarsetime_reg_updated <= '1';
174 WHEN OTHERS =>
175 NULL;
176 END CASE;
177 ELSE
178 IF r.ctrl = '1' THEN
179 r.ctrl <= '0';
180 END if;
181 IF r.soft_reset = '1' THEN
182 r.soft_reset <= '0';
183 END if;
184 END IF;
185
186 --APB READ OP
187 IF (apbi.psel(pindex) AND (NOT apbi.pwrite)) = '1' THEN
188 CASE apbi.paddr(7 DOWNTO 2) IS
189 WHEN ADDR_LFR_MANAGMENT_CONTROL =>
190 Rdata(0) <= r.ctrl;
191 Rdata(1) <= r.soft_reset;
192 Rdata(2) <= r.LFR_soft_reset;
193 Rdata(31 DOWNTO 3) <= (others => '0');
194 WHEN ADDR_LFR_MANAGMENT_TIME_LOAD =>
195 Rdata(30 DOWNTO 0) <= r.coarse_time_load(30 DOWNTO 0);
179 Rdata(30 DOWNTO 0) <= r.coarse_time_load(30 DOWNTO 0);
196 180 WHEN ADDR_LFR_MANAGMENT_TIME_COARSE =>
197 Rdata(31 DOWNTO 0) <= r.coarse_time(31 DOWNTO 0);
181 Rdata(31 DOWNTO 0) <= r.coarse_time(31 DOWNTO 0);
198 182 WHEN ADDR_LFR_MANAGMENT_TIME_FINE =>
199 183 Rdata(31 DOWNTO 16) <= (OTHERS => '0');
200 184 Rdata(15 DOWNTO 0) <= r.fine_time(15 DOWNTO 0);
201 WHEN ADDR_LFR_MANAGMENT_HK_TEMP_0 =>
185 WHEN ADDR_LFR_MANAGMENT_HK_TEMP_0 =>
202 186 Rdata(31 DOWNTO 16) <= (OTHERS => '0');
203 187 Rdata(15 DOWNTO 0) <= r.HK_temp_0;
204 WHEN ADDR_LFR_MANAGMENT_HK_TEMP_1 =>
188 WHEN ADDR_LFR_MANAGMENT_HK_TEMP_1 =>
205 189 Rdata(31 DOWNTO 16) <= (OTHERS => '0');
206 190 Rdata(15 DOWNTO 0) <= r.HK_temp_1;
207 WHEN ADDR_LFR_MANAGMENT_HK_TEMP_2 =>
191 WHEN ADDR_LFR_MANAGMENT_HK_TEMP_2 =>
208 192 Rdata(31 DOWNTO 16) <= (OTHERS => '0');
209 193 Rdata(15 DOWNTO 0) <= r.HK_temp_2;
210 194 WHEN OTHERS =>
211 Rdata(31 DOWNTO 0) <= (others => '0');
195 Rdata(31 DOWNTO 0) <= (OTHERS => '0');
212 196 END CASE;
197
198 --APB Write OP
199 IF (apbi.pwrite AND apbi.penable) = '1' THEN
200 CASE paddr(7 DOWNTO 2) IS
201 WHEN ADDR_LFR_MANAGMENT_CONTROL =>
202 r.ctrl <= apbi.pwdata(0);
203 r.soft_reset <= apbi.pwdata(1);
204 r.LFR_soft_reset <= apbi.pwdata(2);
205 WHEN ADDR_LFR_MANAGMENT_TIME_LOAD =>
206 r.coarse_time_load <= apbi.pwdata(30 DOWNTO 0);
207 coarsetime_reg_updated <= '1';
208 WHEN OTHERS =>
209 NULL;
210 END CASE;
211 ELSE
212 IF r.ctrl = '1' THEN
213 r.ctrl <= '0';
214 END IF;
215 IF r.soft_reset = '1' THEN
216 r.soft_reset <= '0';
217 END IF;
218 END IF;
219
213 220 END IF;
214 221
215 222 END IF;
216 223 END PROCESS;
217 224
218 225 apbo.pirq <= (OTHERS => '0');
219 226 apbo.prdata <= Rdata;
220 227 apbo.pconfig <= pconfig;
221 228 apbo.pindex <= pindex;
222 229
223 230 -----------------------------------------------------------------------------
224 231 -- IN
225 232 coarse_time <= r.coarse_time;
226 233 fine_time <= r.fine_time;
227 234 coarsetime_reg <= r.coarse_time_load;
228 235 -----------------------------------------------------------------------------
229 236
230 237 -----------------------------------------------------------------------------
231 238 -- OUT
232 r.coarse_time <= coarse_time_s;
233 r.fine_time <= fine_time_s;
239 r.coarse_time <= coarse_time_s;
240 r.fine_time <= fine_time_s;
234 241 -----------------------------------------------------------------------------
235 242
236 243 -----------------------------------------------------------------------------
237 244 tick <= grspw_tick OR soft_tick;
238 245
239 246 SYNC_VALID_BIT_1 : SYNC_VALID_BIT
240 247 GENERIC MAP (
241 248 NB_FF_OF_SYNC => 2)
242 249 PORT MAP (
243 250 clk_in => clk25MHz,
244 251 clk_out => clk24_576MHz,
245 252 rstn => resetn,
246 253 sin => tick,
247 254 sout => new_timecode);
248 255
249 256 SYNC_VALID_BIT_2 : SYNC_VALID_BIT
250 257 GENERIC MAP (
251 258 NB_FF_OF_SYNC => 2)
252 259 PORT MAP (
253 260 clk_in => clk25MHz,
254 261 clk_out => clk24_576MHz,
255 262 rstn => resetn,
256 263 sin => coarsetime_reg_updated,
257 264 sout => new_coarsetime);
258
265
259 266 SYNC_VALID_BIT_3 : SYNC_VALID_BIT
260 267 GENERIC MAP (
261 268 NB_FF_OF_SYNC => 2)
262 269 PORT MAP (
263 270 clk_in => clk25MHz,
264 271 clk_out => clk24_576MHz,
265 272 rstn => resetn,
266 273 sin => soft_reset,
267 274 sout => soft_reset_sync);
268 275
269 276 -----------------------------------------------------------------------------
270 277 --SYNC_FF_1 : SYNC_FF
271 278 -- GENERIC MAP (
272 279 -- NB_FF_OF_SYNC => 2)
273 280 -- PORT MAP (
274 281 -- clk => clk25MHz,
275 282 -- rstn => resetn,
276 283 -- A => fine_time_new_49,
277 284 -- A_sync => fine_time_new_temp);
278 285
279 286 --lpp_front_detection_1 : lpp_front_detection
280 287 -- PORT MAP (
281 288 -- clk => clk25MHz,
282 289 -- rstn => resetn,
283 290 -- sin => fine_time_new_temp,
284 291 -- sout => fine_time_new);
285 292
286 293 --SYNC_VALID_BIT_4 : SYNC_VALID_BIT
287 294 -- GENERIC MAP (
288 295 -- NB_FF_OF_SYNC => 2)
289 296 -- PORT MAP (
290 297 -- clk_in => clk24_576MHz,
291 298 -- clk_out => clk25MHz,
292 299 -- rstn => resetn,
293 300 -- sin => coarse_time_new_49,
294 301 -- sout => coarse_time_new);
295 302
296 303 time_new_49 <= coarse_time_new_49 OR fine_time_new_49;
297 304
298 305 SYNC_VALID_BIT_4 : SYNC_VALID_BIT
299 GENERIC MAP (
300 NB_FF_OF_SYNC => 2)
301 PORT MAP (
302 clk_in => clk24_576MHz,
303 clk_out => clk25MHz,
304 rstn => resetn,
305 sin => time_new_49,
306 sout => time_new);
307
306 GENERIC MAP (
307 NB_FF_OF_SYNC => 2)
308 PORT MAP (
309 clk_in => clk24_576MHz,
310 clk_out => clk25MHz,
311 rstn => resetn,
312 sin => time_new_49,
313 sout => time_new);
308 314
309
315
316
310 317 PROCESS (clk25MHz, resetn)
311 318 BEGIN -- PROCESS
312 319 IF resetn = '0' THEN -- asynchronous reset (active low)
313 320 fine_time_s <= (OTHERS => '0');
314 321 coarse_time_s <= (OTHERS => '0');
315 322 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN -- rising clock edge
316 323 IF time_new = '1' THEN
317 324 fine_time_s <= fine_time_49;
318 325 coarse_time_s <= coarse_time_49;
319 326 END IF;
320 327 END IF;
321 328 END PROCESS;
322 329
323 330
324 331 rstn_LFR_TM <= '0' WHEN resetn = '0' ELSE
325 332 '0' WHEN soft_reset_sync = '1' ELSE
326 333 '1';
327
328
334
335
329 336 -----------------------------------------------------------------------------
330 337 -- LFR_TIME_MANAGMENT
331 338 -----------------------------------------------------------------------------
332 339 lfr_time_management_1 : lfr_time_management
333 340 GENERIC MAP (
334 341 FIRST_DIVISION => FIRST_DIVISION,
335 342 NB_SECOND_DESYNC => NB_SECOND_DESYNC)
336 343 PORT MAP (
337 344 clk => clk24_576MHz,
338 345 rstn => rstn_LFR_TM,
339 346
340 347 tick => new_timecode,
341 348 new_coarsetime => new_coarsetime,
342 349 coarsetime_reg => coarsetime_reg(30 DOWNTO 0),
343 350
344 351 fine_time => fine_time_49,
345 352 fine_time_new => fine_time_new_49,
346 353 coarse_time => coarse_time_49,
347 354 coarse_time_new => coarse_time_new_49);
348 355
349 356 -----------------------------------------------------------------------------
350 357 -- HK
351 358 -----------------------------------------------------------------------------
352 359
353 360 PROCESS (clk25MHz, resetn)
354 361 BEGIN -- PROCESS
355 IF resetn = '0' THEN -- asynchronous reset (active low)
362 IF resetn = '0' THEN -- asynchronous reset (active low)
356 363
357 364 r.HK_temp_0 <= (OTHERS => '0');
358 365 r.HK_temp_1 <= (OTHERS => '0');
359 366 r.HK_temp_2 <= (OTHERS => '0');
360
367
361 368 HK_sel_s <= "00";
362 369
363 ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge
370 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN -- rising clock edge
364 371
365 372 IF HK_val = '1' THEN
366 373 CASE HK_sel_s IS
367 WHEN "00" => r.HK_temp_0 <= HK_sample; HK_sel_s <= "01";
368 WHEN "01" => r.HK_temp_1 <= HK_sample; HK_sel_s <= "10";
369 WHEN "10" => r.HK_temp_2 <= HK_sample; HK_sel_s <= "00";
374 WHEN "00" => r.HK_temp_0 <= HK_sample; HK_sel_s <= "01";
375 WHEN "01" => r.HK_temp_1 <= HK_sample; HK_sel_s <= "10";
376 WHEN "10" => r.HK_temp_2 <= HK_sample; HK_sel_s <= "00";
370 377 WHEN OTHERS => NULL;
371 378 END CASE;
372 379
373 380 END IF;
374 381
375 382 END IF;
376 END PROCESS;
383 END PROCESS;
377 384
378 385 HK_sel <= HK_sel_s;
379 386
380 END Behavioral; No newline at end of file
387 END Behavioral;
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