# HG changeset patch # User pellion # Date 2015-01-28 09:25:11 # Node ID 7d6d07e76b74e34914057567a755c1545e3023ca # Parent fe7254c1482e5e51def98220213c41ed15b1dd04 (MINI-LFR) WFP_MS-0.1-53 diff --git a/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd b/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd --- a/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd +++ b/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd @@ -518,7 +518,7 @@ BEGIN -- beh pirq_ms => 6, pirq_wfp => 14, hindex => 2, - top_lfr_version => X"000134") -- aa.bb.cc version + top_lfr_version => X"000135") -- aa.bb.cc version PORT MAP ( clk => clk_25, rstn => LFR_rstn, @@ -583,7 +583,7 @@ BEGIN -- beh sample_hk <= "0001000100010001" WHEN HK_SEL = "00" ELSE "0010001000100010" WHEN HK_SEL = "10" ELSE - "0100010001000100" WHEN HK_SEL = "10" ELSE + "0100010001000100" WHEN HK_SEL = "11" ELSE (OTHERS => '0'); diff --git a/lib/lpp/general_purpose/data_type_pkg.vhd b/lib/lpp/general_purpose/data_type_pkg.vhd --- a/lib/lpp/general_purpose/data_type_pkg.vhd +++ b/lib/lpp/general_purpose/data_type_pkg.vhd @@ -26,6 +26,8 @@ USE ieee.std_logic_1164.ALL; PACKAGE data_type_pkg IS + TYPE array_integer IS ARRAY (NATURAL RANGE <>) OF INTEGER; + TYPE sample_vector IS ARRAY(NATURAL RANGE <>, NATURAL RANGE <>) OF STD_LOGIC; END data_type_pkg; diff --git a/lib/lpp/lfr_management/apb_lfr_management.vhd b/lib/lpp/lfr_management/apb_lfr_management.vhd --- a/lib/lpp/lfr_management/apb_lfr_management.vhd +++ b/lib/lpp/lfr_management/apb_lfr_management.vhd @@ -34,9 +34,9 @@ USE lpp.lpp_lfr_management_apbreg_pkg.AL ENTITY apb_lfr_management IS GENERIC( - pindex : INTEGER := 0; --! APB slave index - paddr : INTEGER := 0; --! ADDR field of the APB BAR - pmask : INTEGER := 16#fff#; --! MASK field of the APB BAR + pindex : INTEGER := 0; --! APB slave index + paddr : INTEGER := 0; --! ADDR field of the APB BAR + pmask : INTEGER := 16#fff#; --! MASK field of the APB BAR FIRST_DIVISION : INTEGER := 374; NB_SECOND_DESYNC : INTEGER := 60 ); @@ -48,15 +48,15 @@ ENTITY apb_lfr_management IS grspw_tick : IN STD_LOGIC; --! grspw signal asserted when a valid time-code is received - apbi : IN apb_slv_in_type; --! APB slave input signals - apbo : OUT apb_slv_out_type; --! APB slave output signals + apbi : IN apb_slv_in_type; --! APB slave input signals + apbo : OUT apb_slv_out_type; --! APB slave output signals --------------------------------------------------------------------------- - HK_sample : IN STD_LOGIC_VECTOR(15 DOWNTO 0); - HK_val : IN STD_LOGIC; - HK_sel : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + HK_sample : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + HK_val : IN STD_LOGIC; + HK_sel : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); --------------------------------------------------------------------------- - coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time - fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); --! fine TIME + coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time + fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); --! fine TIME --------------------------------------------------------------------------- LFR_soft_rstn : OUT STD_LOGIC ); @@ -78,12 +78,12 @@ ARCHITECTURE Behavioral OF apb_lfr_manag coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); LFR_soft_reset : STD_LOGIC; - HK_temp_0 : STD_LOGIC_VECTOR(15 DOWNTO 0); - HK_temp_1 : STD_LOGIC_VECTOR(15 DOWNTO 0); - HK_temp_2 : STD_LOGIC_VECTOR(15 DOWNTO 0); + HK_temp_0 : STD_LOGIC_VECTOR(15 DOWNTO 0); + HK_temp_1 : STD_LOGIC_VECTOR(15 DOWNTO 0); + HK_temp_2 : STD_LOGIC_VECTOR(15 DOWNTO 0); END RECORD; - SIGNAL r : apb_lfr_time_management_Reg; - + SIGNAL r : apb_lfr_time_management_Reg; + SIGNAL Rdata : STD_LOGIC_VECTOR(31 DOWNTO 0); SIGNAL force_tick : STD_LOGIC; SIGNAL previous_force_tick : STD_LOGIC; @@ -99,43 +99,44 @@ ARCHITECTURE Behavioral OF apb_lfr_manag --SIGNAL fine_time_new : STD_LOGIC; --SIGNAL fine_time_new_temp : STD_LOGIC; - SIGNAL fine_time_new_49 : STD_LOGIC; - SIGNAL fine_time_49 : STD_LOGIC_VECTOR(15 DOWNTO 0); - SIGNAL fine_time_s : STD_LOGIC_VECTOR(15 DOWNTO 0); - SIGNAL tick : STD_LOGIC; - SIGNAL new_timecode : STD_LOGIC; - SIGNAL new_coarsetime : STD_LOGIC; - + SIGNAL fine_time_new_49 : STD_LOGIC; + SIGNAL fine_time_49 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL fine_time_s : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL tick : STD_LOGIC; + SIGNAL new_timecode : STD_LOGIC; + SIGNAL new_coarsetime : STD_LOGIC; + SIGNAL time_new_49 : STD_LOGIC; SIGNAL time_new : STD_LOGIC; ----------------------------------------------------------------------------- SIGNAL force_reset : STD_LOGIC; SIGNAL previous_force_reset : STD_LOGIC; - SIGNAL soft_reset : STD_LOGIC; - SIGNAL soft_reset_sync : STD_LOGIC; + SIGNAL soft_reset : STD_LOGIC; + SIGNAL soft_reset_sync : STD_LOGIC; ----------------------------------------------------------------------------- - SIGNAL HK_temp_0_s : STD_LOGIC_VECTOR(15 DOWNTO 0); - SIGNAL HK_temp_1_s : STD_LOGIC_VECTOR(15 DOWNTO 0); - SIGNAL HK_temp_2_s : STD_LOGIC_VECTOR(15 DOWNTO 0); - SIGNAL HK_sel_s : STD_LOGIC_VECTOR( 1 DOWNTO 0); + SIGNAL HK_temp_0_s : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL HK_temp_1_s : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL HK_temp_2_s : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL HK_sel_s : STD_LOGIC_VECTOR(1 DOWNTO 0); SIGNAL rstn_LFR_TM : STD_LOGIC; BEGIN LFR_soft_rstn <= NOT r.LFR_soft_reset; - + PROCESS(resetn, clk25MHz) + VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2); BEGIN IF resetn = '0' THEN - Rdata <= (OTHERS => '0'); - r.coarse_time_load <= (OTHERS => '0'); - r.soft_reset <= '0'; - r.ctrl <= '0'; - r.LFR_soft_reset <= '1'; - + Rdata <= (OTHERS => '0'); + r.coarse_time_load <= (OTHERS => '0'); + r.soft_reset <= '0'; + r.ctrl <= '0'; + r.LFR_soft_reset <= '1'; + force_tick <= '0'; previous_force_tick <= '0'; soft_tick <= '0'; @@ -152,7 +153,7 @@ BEGIN ELSE soft_tick <= '0'; END IF; - + force_reset <= r.soft_reset; previous_force_reset <= force_reset; IF (previous_force_reset = '0') AND (force_reset = '1') THEN @@ -161,55 +162,61 @@ BEGIN soft_reset <= '0'; END IF; ---APB Write OP - IF (apbi.psel(pindex) AND apbi.penable AND apbi.pwrite) = '1' THEN - CASE apbi.paddr(7 DOWNTO 2) IS + paddr := "000000"; + paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2); + Rdata <= (OTHERS => '0'); + + + IF apbi.psel(pindex) = '1' THEN + --APB READ OP + CASE paddr(7 DOWNTO 2) IS WHEN ADDR_LFR_MANAGMENT_CONTROL => - r.ctrl <= apbi.pwdata(0); - r.soft_reset <= apbi.pwdata(1); - r.LFR_soft_reset <= apbi.pwdata(2); + Rdata(0) <= r.ctrl; + Rdata(1) <= r.soft_reset; + Rdata(2) <= r.LFR_soft_reset; + Rdata(31 DOWNTO 3) <= (OTHERS => '0'); WHEN ADDR_LFR_MANAGMENT_TIME_LOAD => - r.coarse_time_load <= apbi.pwdata(30 DOWNTO 0); - coarsetime_reg_updated <= '1'; - WHEN OTHERS => - NULL; - END CASE; - ELSE - IF r.ctrl = '1' THEN - r.ctrl <= '0'; - END if; - IF r.soft_reset = '1' THEN - r.soft_reset <= '0'; - END if; - END IF; - ---APB READ OP - IF (apbi.psel(pindex) AND (NOT apbi.pwrite)) = '1' THEN - CASE apbi.paddr(7 DOWNTO 2) IS - WHEN ADDR_LFR_MANAGMENT_CONTROL => - Rdata(0) <= r.ctrl; - Rdata(1) <= r.soft_reset; - Rdata(2) <= r.LFR_soft_reset; - Rdata(31 DOWNTO 3) <= (others => '0'); - WHEN ADDR_LFR_MANAGMENT_TIME_LOAD => - Rdata(30 DOWNTO 0) <= r.coarse_time_load(30 DOWNTO 0); + Rdata(30 DOWNTO 0) <= r.coarse_time_load(30 DOWNTO 0); WHEN ADDR_LFR_MANAGMENT_TIME_COARSE => - Rdata(31 DOWNTO 0) <= r.coarse_time(31 DOWNTO 0); + Rdata(31 DOWNTO 0) <= r.coarse_time(31 DOWNTO 0); WHEN ADDR_LFR_MANAGMENT_TIME_FINE => Rdata(31 DOWNTO 16) <= (OTHERS => '0'); Rdata(15 DOWNTO 0) <= r.fine_time(15 DOWNTO 0); - WHEN ADDR_LFR_MANAGMENT_HK_TEMP_0 => + WHEN ADDR_LFR_MANAGMENT_HK_TEMP_0 => Rdata(31 DOWNTO 16) <= (OTHERS => '0'); Rdata(15 DOWNTO 0) <= r.HK_temp_0; - WHEN ADDR_LFR_MANAGMENT_HK_TEMP_1 => + WHEN ADDR_LFR_MANAGMENT_HK_TEMP_1 => Rdata(31 DOWNTO 16) <= (OTHERS => '0'); Rdata(15 DOWNTO 0) <= r.HK_temp_1; - WHEN ADDR_LFR_MANAGMENT_HK_TEMP_2 => + WHEN ADDR_LFR_MANAGMENT_HK_TEMP_2 => Rdata(31 DOWNTO 16) <= (OTHERS => '0'); Rdata(15 DOWNTO 0) <= r.HK_temp_2; WHEN OTHERS => - Rdata(31 DOWNTO 0) <= (others => '0'); + Rdata(31 DOWNTO 0) <= (OTHERS => '0'); END CASE; + + --APB Write OP + IF (apbi.pwrite AND apbi.penable) = '1' THEN + CASE paddr(7 DOWNTO 2) IS + WHEN ADDR_LFR_MANAGMENT_CONTROL => + r.ctrl <= apbi.pwdata(0); + r.soft_reset <= apbi.pwdata(1); + r.LFR_soft_reset <= apbi.pwdata(2); + WHEN ADDR_LFR_MANAGMENT_TIME_LOAD => + r.coarse_time_load <= apbi.pwdata(30 DOWNTO 0); + coarsetime_reg_updated <= '1'; + WHEN OTHERS => + NULL; + END CASE; + ELSE + IF r.ctrl = '1' THEN + r.ctrl <= '0'; + END IF; + IF r.soft_reset = '1' THEN + r.soft_reset <= '0'; + END IF; + END IF; + END IF; END IF; @@ -229,8 +236,8 @@ BEGIN ----------------------------------------------------------------------------- -- OUT - r.coarse_time <= coarse_time_s; - r.fine_time <= fine_time_s; + r.coarse_time <= coarse_time_s; + r.fine_time <= fine_time_s; ----------------------------------------------------------------------------- ----------------------------------------------------------------------------- @@ -255,7 +262,7 @@ BEGIN rstn => resetn, sin => coarsetime_reg_updated, sout => new_coarsetime); - + SYNC_VALID_BIT_3 : SYNC_VALID_BIT GENERIC MAP ( NB_FF_OF_SYNC => 2) @@ -296,17 +303,17 @@ BEGIN time_new_49 <= coarse_time_new_49 OR fine_time_new_49; SYNC_VALID_BIT_4 : SYNC_VALID_BIT - GENERIC MAP ( - NB_FF_OF_SYNC => 2) - PORT MAP ( - clk_in => clk24_576MHz, - clk_out => clk25MHz, - rstn => resetn, - sin => time_new_49, - sout => time_new); - + GENERIC MAP ( + NB_FF_OF_SYNC => 2) + PORT MAP ( + clk_in => clk24_576MHz, + clk_out => clk25MHz, + rstn => resetn, + sin => time_new_49, + sout => time_new); - + + PROCESS (clk25MHz, resetn) BEGIN -- PROCESS IF resetn = '0' THEN -- asynchronous reset (active low) @@ -324,8 +331,8 @@ BEGIN rstn_LFR_TM <= '0' WHEN resetn = '0' ELSE '0' WHEN soft_reset_sync = '1' ELSE '1'; - - + + ----------------------------------------------------------------------------- -- LFR_TIME_MANAGMENT ----------------------------------------------------------------------------- @@ -352,29 +359,29 @@ BEGIN PROCESS (clk25MHz, resetn) BEGIN -- PROCESS - IF resetn = '0' THEN -- asynchronous reset (active low) + IF resetn = '0' THEN -- asynchronous reset (active low) r.HK_temp_0 <= (OTHERS => '0'); r.HK_temp_1 <= (OTHERS => '0'); r.HK_temp_2 <= (OTHERS => '0'); - + HK_sel_s <= "00"; - ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge + ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN -- rising clock edge IF HK_val = '1' THEN CASE HK_sel_s IS - WHEN "00" => r.HK_temp_0 <= HK_sample; HK_sel_s <= "01"; - WHEN "01" => r.HK_temp_1 <= HK_sample; HK_sel_s <= "10"; - WHEN "10" => r.HK_temp_2 <= HK_sample; HK_sel_s <= "00"; + WHEN "00" => r.HK_temp_0 <= HK_sample; HK_sel_s <= "01"; + WHEN "01" => r.HK_temp_1 <= HK_sample; HK_sel_s <= "10"; + WHEN "10" => r.HK_temp_2 <= HK_sample; HK_sel_s <= "00"; WHEN OTHERS => NULL; END CASE; END IF; END IF; - END PROCESS; + END PROCESS; HK_sel <= HK_sel_s; -END Behavioral; \ No newline at end of file +END Behavioral;