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(MINI-LFR) WFP_MS-0.1-53
pellion -
r519:7d6d07e76b74 JC
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@@ -518,7 +518,7 BEGIN -- beh
518 518 pirq_ms => 6,
519 519 pirq_wfp => 14,
520 520 hindex => 2,
521 top_lfr_version => X"000134") -- aa.bb.cc version
521 top_lfr_version => X"000135") -- aa.bb.cc version
522 522 PORT MAP (
523 523 clk => clk_25,
524 524 rstn => LFR_rstn,
@@ -583,7 +583,7 BEGIN -- beh
583 583
584 584 sample_hk <= "0001000100010001" WHEN HK_SEL = "00" ELSE
585 585 "0010001000100010" WHEN HK_SEL = "10" ELSE
586 "0100010001000100" WHEN HK_SEL = "10" ELSE
586 "0100010001000100" WHEN HK_SEL = "11" ELSE
587 587 (OTHERS => '0');
588 588
589 589
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@@ -26,6 +26,8 USE ieee.std_logic_1164.ALL;
26 26
27 27 PACKAGE data_type_pkg IS
28 28
29 TYPE array_integer IS ARRAY (NATURAL RANGE <>) OF INTEGER;
30
29 31 TYPE sample_vector IS ARRAY(NATURAL RANGE <>, NATURAL RANGE <>) OF STD_LOGIC;
30 32
31 33 END data_type_pkg;
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@@ -34,9 +34,9 USE lpp.lpp_lfr_management_apbreg_pkg.AL
34 34 ENTITY apb_lfr_management IS
35 35
36 36 GENERIC(
37 pindex : INTEGER := 0; --! APB slave index
38 paddr : INTEGER := 0; --! ADDR field of the APB BAR
39 pmask : INTEGER := 16#fff#; --! MASK field of the APB BAR
37 pindex : INTEGER := 0; --! APB slave index
38 paddr : INTEGER := 0; --! ADDR field of the APB BAR
39 pmask : INTEGER := 16#fff#; --! MASK field of the APB BAR
40 40 FIRST_DIVISION : INTEGER := 374;
41 41 NB_SECOND_DESYNC : INTEGER := 60
42 42 );
@@ -48,15 +48,15 ENTITY apb_lfr_management IS
48 48
49 49 grspw_tick : IN STD_LOGIC; --! grspw signal asserted when a valid time-code is received
50 50
51 apbi : IN apb_slv_in_type; --! APB slave input signals
52 apbo : OUT apb_slv_out_type; --! APB slave output signals
51 apbi : IN apb_slv_in_type; --! APB slave input signals
52 apbo : OUT apb_slv_out_type; --! APB slave output signals
53 53 ---------------------------------------------------------------------------
54 HK_sample : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
55 HK_val : IN STD_LOGIC;
56 HK_sel : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
54 HK_sample : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
55 HK_val : IN STD_LOGIC;
56 HK_sel : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
57 57 ---------------------------------------------------------------------------
58 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time
59 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); --! fine TIME
58 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time
59 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); --! fine TIME
60 60 ---------------------------------------------------------------------------
61 61 LFR_soft_rstn : OUT STD_LOGIC
62 62 );
@@ -78,12 +78,12 ARCHITECTURE Behavioral OF apb_lfr_manag
78 78 coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
79 79 fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
80 80 LFR_soft_reset : STD_LOGIC;
81 HK_temp_0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
82 HK_temp_1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
83 HK_temp_2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
81 HK_temp_0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
82 HK_temp_1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
83 HK_temp_2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
84 84 END RECORD;
85 SIGNAL r : apb_lfr_time_management_Reg;
86
85 SIGNAL r : apb_lfr_time_management_Reg;
86
87 87 SIGNAL Rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
88 88 SIGNAL force_tick : STD_LOGIC;
89 89 SIGNAL previous_force_tick : STD_LOGIC;
@@ -99,43 +99,44 ARCHITECTURE Behavioral OF apb_lfr_manag
99 99
100 100 --SIGNAL fine_time_new : STD_LOGIC;
101 101 --SIGNAL fine_time_new_temp : STD_LOGIC;
102 SIGNAL fine_time_new_49 : STD_LOGIC;
103 SIGNAL fine_time_49 : STD_LOGIC_VECTOR(15 DOWNTO 0);
104 SIGNAL fine_time_s : STD_LOGIC_VECTOR(15 DOWNTO 0);
105 SIGNAL tick : STD_LOGIC;
106 SIGNAL new_timecode : STD_LOGIC;
107 SIGNAL new_coarsetime : STD_LOGIC;
108
102 SIGNAL fine_time_new_49 : STD_LOGIC;
103 SIGNAL fine_time_49 : STD_LOGIC_VECTOR(15 DOWNTO 0);
104 SIGNAL fine_time_s : STD_LOGIC_VECTOR(15 DOWNTO 0);
105 SIGNAL tick : STD_LOGIC;
106 SIGNAL new_timecode : STD_LOGIC;
107 SIGNAL new_coarsetime : STD_LOGIC;
108
109 109 SIGNAL time_new_49 : STD_LOGIC;
110 110 SIGNAL time_new : STD_LOGIC;
111 111
112 112 -----------------------------------------------------------------------------
113 113 SIGNAL force_reset : STD_LOGIC;
114 114 SIGNAL previous_force_reset : STD_LOGIC;
115 SIGNAL soft_reset : STD_LOGIC;
116 SIGNAL soft_reset_sync : STD_LOGIC;
115 SIGNAL soft_reset : STD_LOGIC;
116 SIGNAL soft_reset_sync : STD_LOGIC;
117 117 -----------------------------------------------------------------------------
118 SIGNAL HK_temp_0_s : STD_LOGIC_VECTOR(15 DOWNTO 0);
119 SIGNAL HK_temp_1_s : STD_LOGIC_VECTOR(15 DOWNTO 0);
120 SIGNAL HK_temp_2_s : STD_LOGIC_VECTOR(15 DOWNTO 0);
121 SIGNAL HK_sel_s : STD_LOGIC_VECTOR( 1 DOWNTO 0);
118 SIGNAL HK_temp_0_s : STD_LOGIC_VECTOR(15 DOWNTO 0);
119 SIGNAL HK_temp_1_s : STD_LOGIC_VECTOR(15 DOWNTO 0);
120 SIGNAL HK_temp_2_s : STD_LOGIC_VECTOR(15 DOWNTO 0);
121 SIGNAL HK_sel_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
122 122
123 123 SIGNAL rstn_LFR_TM : STD_LOGIC;
124 124
125 125 BEGIN
126 126
127 127 LFR_soft_rstn <= NOT r.LFR_soft_reset;
128
128
129 129 PROCESS(resetn, clk25MHz)
130 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
130 131 BEGIN
131 132
132 133 IF resetn = '0' THEN
133 Rdata <= (OTHERS => '0');
134 r.coarse_time_load <= (OTHERS => '0');
135 r.soft_reset <= '0';
136 r.ctrl <= '0';
137 r.LFR_soft_reset <= '1';
138
134 Rdata <= (OTHERS => '0');
135 r.coarse_time_load <= (OTHERS => '0');
136 r.soft_reset <= '0';
137 r.ctrl <= '0';
138 r.LFR_soft_reset <= '1';
139
139 140 force_tick <= '0';
140 141 previous_force_tick <= '0';
141 142 soft_tick <= '0';
@@ -152,7 +153,7 BEGIN
152 153 ELSE
153 154 soft_tick <= '0';
154 155 END IF;
155
156
156 157 force_reset <= r.soft_reset;
157 158 previous_force_reset <= force_reset;
158 159 IF (previous_force_reset = '0') AND (force_reset = '1') THEN
@@ -161,55 +162,61 BEGIN
161 162 soft_reset <= '0';
162 163 END IF;
163 164
164 --APB Write OP
165 IF (apbi.psel(pindex) AND apbi.penable AND apbi.pwrite) = '1' THEN
166 CASE apbi.paddr(7 DOWNTO 2) IS
165 paddr := "000000";
166 paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
167 Rdata <= (OTHERS => '0');
168
169
170 IF apbi.psel(pindex) = '1' THEN
171 --APB READ OP
172 CASE paddr(7 DOWNTO 2) IS
167 173 WHEN ADDR_LFR_MANAGMENT_CONTROL =>
168 r.ctrl <= apbi.pwdata(0);
169 r.soft_reset <= apbi.pwdata(1);
170 r.LFR_soft_reset <= apbi.pwdata(2);
174 Rdata(0) <= r.ctrl;
175 Rdata(1) <= r.soft_reset;
176 Rdata(2) <= r.LFR_soft_reset;
177 Rdata(31 DOWNTO 3) <= (OTHERS => '0');
171 178 WHEN ADDR_LFR_MANAGMENT_TIME_LOAD =>
172 r.coarse_time_load <= apbi.pwdata(30 DOWNTO 0);
173 coarsetime_reg_updated <= '1';
174 WHEN OTHERS =>
175 NULL;
176 END CASE;
177 ELSE
178 IF r.ctrl = '1' THEN
179 r.ctrl <= '0';
180 END if;
181 IF r.soft_reset = '1' THEN
182 r.soft_reset <= '0';
183 END if;
184 END IF;
185
186 --APB READ OP
187 IF (apbi.psel(pindex) AND (NOT apbi.pwrite)) = '1' THEN
188 CASE apbi.paddr(7 DOWNTO 2) IS
189 WHEN ADDR_LFR_MANAGMENT_CONTROL =>
190 Rdata(0) <= r.ctrl;
191 Rdata(1) <= r.soft_reset;
192 Rdata(2) <= r.LFR_soft_reset;
193 Rdata(31 DOWNTO 3) <= (others => '0');
194 WHEN ADDR_LFR_MANAGMENT_TIME_LOAD =>
195 Rdata(30 DOWNTO 0) <= r.coarse_time_load(30 DOWNTO 0);
179 Rdata(30 DOWNTO 0) <= r.coarse_time_load(30 DOWNTO 0);
196 180 WHEN ADDR_LFR_MANAGMENT_TIME_COARSE =>
197 Rdata(31 DOWNTO 0) <= r.coarse_time(31 DOWNTO 0);
181 Rdata(31 DOWNTO 0) <= r.coarse_time(31 DOWNTO 0);
198 182 WHEN ADDR_LFR_MANAGMENT_TIME_FINE =>
199 183 Rdata(31 DOWNTO 16) <= (OTHERS => '0');
200 184 Rdata(15 DOWNTO 0) <= r.fine_time(15 DOWNTO 0);
201 WHEN ADDR_LFR_MANAGMENT_HK_TEMP_0 =>
185 WHEN ADDR_LFR_MANAGMENT_HK_TEMP_0 =>
202 186 Rdata(31 DOWNTO 16) <= (OTHERS => '0');
203 187 Rdata(15 DOWNTO 0) <= r.HK_temp_0;
204 WHEN ADDR_LFR_MANAGMENT_HK_TEMP_1 =>
188 WHEN ADDR_LFR_MANAGMENT_HK_TEMP_1 =>
205 189 Rdata(31 DOWNTO 16) <= (OTHERS => '0');
206 190 Rdata(15 DOWNTO 0) <= r.HK_temp_1;
207 WHEN ADDR_LFR_MANAGMENT_HK_TEMP_2 =>
191 WHEN ADDR_LFR_MANAGMENT_HK_TEMP_2 =>
208 192 Rdata(31 DOWNTO 16) <= (OTHERS => '0');
209 193 Rdata(15 DOWNTO 0) <= r.HK_temp_2;
210 194 WHEN OTHERS =>
211 Rdata(31 DOWNTO 0) <= (others => '0');
195 Rdata(31 DOWNTO 0) <= (OTHERS => '0');
212 196 END CASE;
197
198 --APB Write OP
199 IF (apbi.pwrite AND apbi.penable) = '1' THEN
200 CASE paddr(7 DOWNTO 2) IS
201 WHEN ADDR_LFR_MANAGMENT_CONTROL =>
202 r.ctrl <= apbi.pwdata(0);
203 r.soft_reset <= apbi.pwdata(1);
204 r.LFR_soft_reset <= apbi.pwdata(2);
205 WHEN ADDR_LFR_MANAGMENT_TIME_LOAD =>
206 r.coarse_time_load <= apbi.pwdata(30 DOWNTO 0);
207 coarsetime_reg_updated <= '1';
208 WHEN OTHERS =>
209 NULL;
210 END CASE;
211 ELSE
212 IF r.ctrl = '1' THEN
213 r.ctrl <= '0';
214 END IF;
215 IF r.soft_reset = '1' THEN
216 r.soft_reset <= '0';
217 END IF;
218 END IF;
219
213 220 END IF;
214 221
215 222 END IF;
@@ -229,8 +236,8 BEGIN
229 236
230 237 -----------------------------------------------------------------------------
231 238 -- OUT
232 r.coarse_time <= coarse_time_s;
233 r.fine_time <= fine_time_s;
239 r.coarse_time <= coarse_time_s;
240 r.fine_time <= fine_time_s;
234 241 -----------------------------------------------------------------------------
235 242
236 243 -----------------------------------------------------------------------------
@@ -255,7 +262,7 BEGIN
255 262 rstn => resetn,
256 263 sin => coarsetime_reg_updated,
257 264 sout => new_coarsetime);
258
265
259 266 SYNC_VALID_BIT_3 : SYNC_VALID_BIT
260 267 GENERIC MAP (
261 268 NB_FF_OF_SYNC => 2)
@@ -296,17 +303,17 BEGIN
296 303 time_new_49 <= coarse_time_new_49 OR fine_time_new_49;
297 304
298 305 SYNC_VALID_BIT_4 : SYNC_VALID_BIT
299 GENERIC MAP (
300 NB_FF_OF_SYNC => 2)
301 PORT MAP (
302 clk_in => clk24_576MHz,
303 clk_out => clk25MHz,
304 rstn => resetn,
305 sin => time_new_49,
306 sout => time_new);
307
306 GENERIC MAP (
307 NB_FF_OF_SYNC => 2)
308 PORT MAP (
309 clk_in => clk24_576MHz,
310 clk_out => clk25MHz,
311 rstn => resetn,
312 sin => time_new_49,
313 sout => time_new);
308 314
309
315
316
310 317 PROCESS (clk25MHz, resetn)
311 318 BEGIN -- PROCESS
312 319 IF resetn = '0' THEN -- asynchronous reset (active low)
@@ -324,8 +331,8 BEGIN
324 331 rstn_LFR_TM <= '0' WHEN resetn = '0' ELSE
325 332 '0' WHEN soft_reset_sync = '1' ELSE
326 333 '1';
327
328
334
335
329 336 -----------------------------------------------------------------------------
330 337 -- LFR_TIME_MANAGMENT
331 338 -----------------------------------------------------------------------------
@@ -352,29 +359,29 BEGIN
352 359
353 360 PROCESS (clk25MHz, resetn)
354 361 BEGIN -- PROCESS
355 IF resetn = '0' THEN -- asynchronous reset (active low)
362 IF resetn = '0' THEN -- asynchronous reset (active low)
356 363
357 364 r.HK_temp_0 <= (OTHERS => '0');
358 365 r.HK_temp_1 <= (OTHERS => '0');
359 366 r.HK_temp_2 <= (OTHERS => '0');
360
367
361 368 HK_sel_s <= "00";
362 369
363 ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge
370 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN -- rising clock edge
364 371
365 372 IF HK_val = '1' THEN
366 373 CASE HK_sel_s IS
367 WHEN "00" => r.HK_temp_0 <= HK_sample; HK_sel_s <= "01";
368 WHEN "01" => r.HK_temp_1 <= HK_sample; HK_sel_s <= "10";
369 WHEN "10" => r.HK_temp_2 <= HK_sample; HK_sel_s <= "00";
374 WHEN "00" => r.HK_temp_0 <= HK_sample; HK_sel_s <= "01";
375 WHEN "01" => r.HK_temp_1 <= HK_sample; HK_sel_s <= "10";
376 WHEN "10" => r.HK_temp_2 <= HK_sample; HK_sel_s <= "00";
370 377 WHEN OTHERS => NULL;
371 378 END CASE;
372 379
373 380 END IF;
374 381
375 382 END IF;
376 END PROCESS;
383 END PROCESS;
377 384
378 385 HK_sel <= HK_sel_s;
379 386
380 END Behavioral; No newline at end of file
387 END Behavioral;
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