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1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
29 USE techmap.gencomp.ALL;
30 LIBRARY gaisler;
30 LIBRARY gaisler;
31 USE gaisler.memctrl.ALL;
31 USE gaisler.memctrl.ALL;
32 USE gaisler.leon3.ALL;
32 USE gaisler.leon3.ALL;
33 USE gaisler.uart.ALL;
33 USE gaisler.uart.ALL;
34 USE gaisler.misc.ALL;
34 USE gaisler.misc.ALL;
35 USE gaisler.spacewire.ALL;
35 USE gaisler.spacewire.ALL;
36 LIBRARY esa;
36 LIBRARY esa;
37 USE esa.memoryctrl.ALL;
37 USE esa.memoryctrl.ALL;
38 LIBRARY lpp;
38 LIBRARY lpp;
39 USE lpp.lpp_memory.ALL;
39 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_ad_conv.ALL;
40 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 USE lpp.iir_filter.ALL;
43 USE lpp.iir_filter.ALL;
44 USE lpp.general_purpose.ALL;
44 USE lpp.general_purpose.ALL;
45 USE lpp.lpp_lfr_time_management.ALL;
45 USE lpp.lpp_lfr_time_management.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
47
47
48 ENTITY LFR_em IS
48 ENTITY LFR_em IS
49
49
50 PORT (
50 PORT (
51 clk100MHz : IN STD_ULOGIC;
51 clk100MHz : IN STD_ULOGIC;
52 clk49_152MHz : IN STD_ULOGIC;
52 clk49_152MHz : IN STD_ULOGIC;
53 reset : IN STD_ULOGIC;
53 reset : IN STD_ULOGIC;
54
54
55 -- TAG --------------------------------------------------------------------
55 -- TAG --------------------------------------------------------------------
56 TAG1 : IN STD_ULOGIC; -- DSU rx data
56 TAG1 : IN STD_ULOGIC; -- DSU rx data
57 TAG3 : OUT STD_ULOGIC; -- DSU tx data
57 TAG3 : OUT STD_ULOGIC; -- DSU tx data
58 -- UART APB ---------------------------------------------------------------
58 -- UART APB ---------------------------------------------------------------
59 TAG2 : IN STD_ULOGIC; -- UART1 rx data
59 TAG2 : IN STD_ULOGIC; -- UART1 rx data
60 TAG4 : OUT STD_ULOGIC; -- UART1 tx data
60 TAG4 : OUT STD_ULOGIC; -- UART1 tx data
61 -- RAM --------------------------------------------------------------------
61 -- RAM --------------------------------------------------------------------
62 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
62 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
63 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
63 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
64 nSRAM_BE0 : OUT STD_LOGIC;
64 nSRAM_BE0 : OUT STD_LOGIC;
65 nSRAM_BE1 : OUT STD_LOGIC;
65 nSRAM_BE1 : OUT STD_LOGIC;
66 nSRAM_BE2 : OUT STD_LOGIC;
66 nSRAM_BE2 : OUT STD_LOGIC;
67 nSRAM_BE3 : OUT STD_LOGIC;
67 nSRAM_BE3 : OUT STD_LOGIC;
68 nSRAM_WE : OUT STD_LOGIC;
68 nSRAM_WE : OUT STD_LOGIC;
69 nSRAM_CE : OUT STD_LOGIC;
69 nSRAM_CE : OUT STD_LOGIC;
70 nSRAM_OE : OUT STD_LOGIC;
70 nSRAM_OE : OUT STD_LOGIC;
71 -- SPW --------------------------------------------------------------------
71 -- SPW --------------------------------------------------------------------
72 spw1_din : IN STD_LOGIC;
72 spw1_din : IN STD_LOGIC;
73 spw1_sin : IN STD_LOGIC;
73 spw1_sin : IN STD_LOGIC;
74 spw1_dout : OUT STD_LOGIC;
74 spw1_dout : OUT STD_LOGIC;
75 spw1_sout : OUT STD_LOGIC;
75 spw1_sout : OUT STD_LOGIC;
76 spw2_din : IN STD_LOGIC;
76 spw2_din : IN STD_LOGIC;
77 spw2_sin : IN STD_LOGIC;
77 spw2_sin : IN STD_LOGIC;
78 spw2_dout : OUT STD_LOGIC;
78 spw2_dout : OUT STD_LOGIC;
79 spw2_sout : OUT STD_LOGIC;
79 spw2_sout : OUT STD_LOGIC;
80 -- ADC --------------------------------------------------------------------
80 -- ADC --------------------------------------------------------------------
81 bias_fail_sw : OUT STD_LOGIC;
81 bias_fail_sw : OUT STD_LOGIC;
82 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
82 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
83 ADC_smpclk : OUT STD_LOGIC;
83 ADC_smpclk : OUT STD_LOGIC;
84 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
84 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
85 ---------------------------------------------------------------------------
85 ---------------------------------------------------------------------------
86 TAG8 : OUT STD_LOGIC;
86 TAG8 : OUT STD_LOGIC;
87 led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
87 led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
88 );
88 );
89
89
90 END LFR_em;
90 END LFR_em;
91
91
92
92
93 ARCHITECTURE beh OF LFR_em IS
93 ARCHITECTURE beh OF LFR_em IS
94 SIGNAL clk_50_s : STD_LOGIC := '0';
94 SIGNAL clk_50_s : STD_LOGIC := '0';
95 SIGNAL clk_25 : STD_LOGIC := '0';
95 SIGNAL clk_25 : STD_LOGIC := '0';
96 SIGNAL clk_24 : STD_LOGIC := '0';
96 SIGNAL clk_24 : STD_LOGIC := '0';
97 -----------------------------------------------------------------------------
97 -----------------------------------------------------------------------------
98 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
98 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
99 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
99 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
100
100
101 -- CONSTANTS
101 -- CONSTANTS
102 CONSTANT CFG_PADTECH : INTEGER := inferred;
102 CONSTANT CFG_PADTECH : INTEGER := inferred;
103 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
103 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
104 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
104 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
105 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
105 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
106
106
107 SIGNAL apbi_ext : apb_slv_in_type;
107 SIGNAL apbi_ext : apb_slv_in_type;
108 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
108 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
109 SIGNAL ahbi_s_ext : ahb_slv_in_type;
109 SIGNAL ahbi_s_ext : ahb_slv_in_type;
110 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
110 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
111 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
111 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
112 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
112 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
113
113
114 -- Spacewire signals
114 -- Spacewire signals
115 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
115 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
116 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
116 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
117 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
117 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
118 SIGNAL spw_rxtxclk : STD_ULOGIC;
118 SIGNAL spw_rxtxclk : STD_ULOGIC;
119 SIGNAL spw_rxclkn : STD_ULOGIC;
119 SIGNAL spw_rxclkn : STD_ULOGIC;
120 SIGNAL spw_clk : STD_LOGIC;
120 SIGNAL spw_clk : STD_LOGIC;
121 SIGNAL swni : grspw_in_type;
121 SIGNAL swni : grspw_in_type;
122 SIGNAL swno : grspw_out_type;
122 SIGNAL swno : grspw_out_type;
123
123
124 --GPIO
124 --GPIO
125 SIGNAL gpioi : gpio_in_type;
125 SIGNAL gpioi : gpio_in_type;
126 SIGNAL gpioo : gpio_out_type;
126 SIGNAL gpioo : gpio_out_type;
127
127
128 -- AD Converter ADS7886
128 -- AD Converter ADS7886
129 SIGNAL sample : Samples14v(7 DOWNTO 0);
129 SIGNAL sample : Samples14v(7 DOWNTO 0);
130 SIGNAL sample_s : Samples(7 DOWNTO 0);
130 SIGNAL sample_s : Samples(7 DOWNTO 0);
131 SIGNAL sample_val : STD_LOGIC;
131 SIGNAL sample_val : STD_LOGIC;
132 SIGNAL ADC_nCS_sig : STD_LOGIC;
132 SIGNAL ADC_nCS_sig : STD_LOGIC;
133 SIGNAL ADC_CLK_sig : STD_LOGIC;
133 SIGNAL ADC_CLK_sig : STD_LOGIC;
134 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
134 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
135
135
136 -----------------------------------------------------------------------------
136 -----------------------------------------------------------------------------
137 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
137 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
138
138
139 -----------------------------------------------------------------------------
139 -----------------------------------------------------------------------------
140 SIGNAL rstn : STD_LOGIC;
140 SIGNAL rstn : STD_LOGIC;
141
141
142 SIGNAL ADC_smpclk_s : STD_LOGIC;
142 SIGNAL ADC_smpclk_s : STD_LOGIC;
143
143
144 BEGIN -- beh
144 BEGIN -- beh
145
145
146 -----------------------------------------------------------------------------
146 -----------------------------------------------------------------------------
147 -- CLK
147 -- CLK
148 -----------------------------------------------------------------------------
148 -----------------------------------------------------------------------------
149 rst0 : rstgen PORT MAP (reset, clk_25, '1', rstn, OPEN);
149 rst0 : rstgen PORT MAP (reset, clk_25, '1', rstn, OPEN);
150
150
151 PROCESS(clk100MHz)
151 PROCESS(clk100MHz)
152 BEGIN
152 BEGIN
153 IF clk100MHz'EVENT AND clk100MHz = '1' THEN
153 IF clk100MHz'EVENT AND clk100MHz = '1' THEN
154 clk_50_s <= NOT clk_50_s;
154 clk_50_s <= NOT clk_50_s;
155 END IF;
155 END IF;
156 END PROCESS;
156 END PROCESS;
157
157
158 PROCESS(clk_50_s)
158 PROCESS(clk_50_s)
159 BEGIN
159 BEGIN
160 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
160 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
161 clk_25 <= NOT clk_25;
161 clk_25 <= NOT clk_25;
162 END IF;
162 END IF;
163 END PROCESS;
163 END PROCESS;
164
164
165 PROCESS(clk49_152MHz)
165 PROCESS(clk49_152MHz)
166 BEGIN
166 BEGIN
167 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
167 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
168 clk_24 <= NOT clk_24;
168 clk_24 <= NOT clk_24;
169 END IF;
169 END IF;
170 END PROCESS;
170 END PROCESS;
171
171
172 -----------------------------------------------------------------------------
172 -----------------------------------------------------------------------------
173
173
174 PROCESS (clk_25, rstn)
174 PROCESS (clk_25, rstn)
175 BEGIN -- PROCESS
175 BEGIN -- PROCESS
176 IF rstn = '0' THEN -- asynchronous reset (active low)
176 IF rstn = '0' THEN -- asynchronous reset (active low)
177 led(0) <= '0';
177 led(0) <= '0';
178 led(1) <= '0';
178 led(1) <= '0';
179 led(2) <= '0';
179 led(2) <= '0';
180 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
180 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
181 led(0) <= '0';
181 led(0) <= '0';
182 led(1) <= '1';
182 led(1) <= '1';
183 led(2) <= '1';
183 led(2) <= '1';
184 END IF;
184 END IF;
185 END PROCESS;
185 END PROCESS;
186
186
187 --
187 --
188 leon3_soc_1 : leon3_soc
188 leon3_soc_1 : leon3_soc
189 GENERIC MAP (
189 GENERIC MAP (
190 fabtech => apa3e,
190 fabtech => apa3e,
191 memtech => apa3e,
191 memtech => apa3e,
192 padtech => inferred,
192 padtech => inferred,
193 clktech => inferred,
193 clktech => inferred,
194 disas => 0,
194 disas => 0,
195 dbguart => 0,
195 dbguart => 0,
196 pclow => 2,
196 pclow => 2,
197 clk_freq => 25000,
197 clk_freq => 25000,
198 NB_CPU => 1,
198 NB_CPU => 1,
199 ENABLE_FPU => 1,
199 ENABLE_FPU => 1,
200 FPU_NETLIST => 0,
200 FPU_NETLIST => 0,
201 ENABLE_DSU => 1,
201 ENABLE_DSU => 1,
202 ENABLE_AHB_UART => 1,
202 ENABLE_AHB_UART => 1,
203 ENABLE_APB_UART => 1,
203 ENABLE_APB_UART => 1,
204 ENABLE_IRQMP => 1,
204 ENABLE_IRQMP => 1,
205 ENABLE_GPT => 1,
205 ENABLE_GPT => 1,
206 NB_AHB_MASTER => NB_AHB_MASTER,
206 NB_AHB_MASTER => NB_AHB_MASTER,
207 NB_AHB_SLAVE => NB_AHB_SLAVE,
207 NB_AHB_SLAVE => NB_AHB_SLAVE,
208 NB_APB_SLAVE => NB_APB_SLAVE)
208 NB_APB_SLAVE => NB_APB_SLAVE)
209 PORT MAP (
209 PORT MAP (
210 clk => clk_25,
210 clk => clk_25,
211 reset => rstn,
211 reset => rstn,
212 errorn => OPEN,
212 errorn => OPEN,
213
213
214 ahbrxd => TAG1,
214 ahbrxd => TAG1,
215 ahbtxd => TAG3,
215 ahbtxd => TAG3,
216 urxd1 => TAG2,
216 urxd1 => TAG2,
217 utxd1 => TAG4,
217 utxd1 => TAG4,
218
218
219 address => address,
219 address => address,
220 data => data,
220 data => data,
221 nSRAM_BE0 => nSRAM_BE0,
221 nSRAM_BE0 => nSRAM_BE0,
222 nSRAM_BE1 => nSRAM_BE1,
222 nSRAM_BE1 => nSRAM_BE1,
223 nSRAM_BE2 => nSRAM_BE2,
223 nSRAM_BE2 => nSRAM_BE2,
224 nSRAM_BE3 => nSRAM_BE3,
224 nSRAM_BE3 => nSRAM_BE3,
225 nSRAM_WE => nSRAM_WE,
225 nSRAM_WE => nSRAM_WE,
226 nSRAM_CE => nSRAM_CE,
226 nSRAM_CE => nSRAM_CE,
227 nSRAM_OE => nSRAM_OE,
227 nSRAM_OE => nSRAM_OE,
228
228
229 apbi_ext => apbi_ext,
229 apbi_ext => apbi_ext,
230 apbo_ext => apbo_ext,
230 apbo_ext => apbo_ext,
231 ahbi_s_ext => ahbi_s_ext,
231 ahbi_s_ext => ahbi_s_ext,
232 ahbo_s_ext => ahbo_s_ext,
232 ahbo_s_ext => ahbo_s_ext,
233 ahbi_m_ext => ahbi_m_ext,
233 ahbi_m_ext => ahbi_m_ext,
234 ahbo_m_ext => ahbo_m_ext);
234 ahbo_m_ext => ahbo_m_ext);
235
235
236
236
237 -------------------------------------------------------------------------------
237 -------------------------------------------------------------------------------
238 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
238 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
239 -------------------------------------------------------------------------------
239 -------------------------------------------------------------------------------
240 apb_lfr_time_management_1 : apb_lfr_time_management
240 apb_lfr_time_management_1 : apb_lfr_time_management
241 GENERIC MAP (
241 GENERIC MAP (
242 pindex => 6,
242 pindex => 6,
243 paddr => 6,
243 paddr => 6,
244 pmask => 16#fff#,
244 pmask => 16#fff#,
245 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
245 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
246 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
246 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
247 PORT MAP (
247 PORT MAP (
248 clk25MHz => clk_25,
248 clk25MHz => clk_25,
249 clk24_576MHz => clk_24, -- 49.152MHz/2
249 clk24_576MHz => clk_24, -- 49.152MHz/2
250 resetn => rstn,
250 resetn => rstn,
251 grspw_tick => swno.tickout,
251 grspw_tick => swno.tickout,
252 apbi => apbi_ext,
252 apbi => apbi_ext,
253 apbo => apbo_ext(6),
253 apbo => apbo_ext(6),
254 coarse_time => coarse_time,
254 coarse_time => coarse_time,
255 fine_time => fine_time);
255 fine_time => fine_time);
256
256
257 -----------------------------------------------------------------------
257 -----------------------------------------------------------------------
258 --- SpaceWire --------------------------------------------------------
258 --- SpaceWire --------------------------------------------------------
259 -----------------------------------------------------------------------
259 -----------------------------------------------------------------------
260
260
261 -- SPW_EN <= '1';
261 -- SPW_EN <= '1';
262
262
263 spw_clk <= clk_50_s;
263 spw_clk <= clk_50_s;
264 spw_rxtxclk <= spw_clk;
264 spw_rxtxclk <= spw_clk;
265 spw_rxclkn <= NOT spw_rxtxclk;
265 spw_rxclkn <= NOT spw_rxtxclk;
266
266
267 -- PADS for SPW1
267 -- PADS for SPW1
268 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
268 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
269 PORT MAP (spw1_din, dtmp(0));
269 PORT MAP (spw1_din, dtmp(0));
270 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
270 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
271 PORT MAP (spw1_sin, stmp(0));
271 PORT MAP (spw1_sin, stmp(0));
272 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
272 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
273 PORT MAP (spw1_dout, swno.d(0));
273 PORT MAP (spw1_dout, swno.d(0));
274 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
274 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
275 PORT MAP (spw1_sout, swno.s(0));
275 PORT MAP (spw1_sout, swno.s(0));
276 -- PADS FOR SPW2
276 -- PADS FOR SPW2
277 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
277 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
278 PORT MAP (spw2_sin, dtmp(1));
278 PORT MAP (spw2_sin, dtmp(1));
279 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
279 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
280 PORT MAP (spw2_din, stmp(1));
280 PORT MAP (spw2_din, stmp(1));
281 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
281 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
282 PORT MAP (spw2_dout, swno.d(1));
282 PORT MAP (spw2_dout, swno.d(1));
283 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
283 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
284 PORT MAP (spw2_sout, swno.s(1));
284 PORT MAP (spw2_sout, swno.s(1));
285
285
286 -- GRSPW PHY
286 -- GRSPW PHY
287 --spw1_input: if CFG_SPW_GRSPW = 1 generate
287 --spw1_input: if CFG_SPW_GRSPW = 1 generate
288 spw_inputloop : FOR j IN 0 TO 1 GENERATE
288 spw_inputloop : FOR j IN 0 TO 1 GENERATE
289 spw_phy0 : grspw_phy
289 spw_phy0 : grspw_phy
290 GENERIC MAP(
290 GENERIC MAP(
291 tech => apa3e,
291 tech => apa3e,
292 rxclkbuftype => 1,
292 rxclkbuftype => 1,
293 scantest => 0)
293 scantest => 0)
294 PORT MAP(
294 PORT MAP(
295 rxrst => swno.rxrst,
295 rxrst => swno.rxrst,
296 di => dtmp(j),
296 di => dtmp(j),
297 si => stmp(j),
297 si => stmp(j),
298 rxclko => spw_rxclk(j),
298 rxclko => spw_rxclk(j),
299 do => swni.d(j),
299 do => swni.d(j),
300 ndo => swni.nd(j*5+4 DOWNTO j*5),
300 ndo => swni.nd(j*5+4 DOWNTO j*5),
301 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
301 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
302 END GENERATE spw_inputloop;
302 END GENERATE spw_inputloop;
303
303
304 -- SPW core
304 -- SPW core
305 sw0 : grspwm GENERIC MAP(
305 sw0 : grspwm GENERIC MAP(
306 tech => apa3e,
306 tech => apa3e,
307 hindex => 1,
307 hindex => 1,
308 pindex => 5,
308 pindex => 5,
309 paddr => 5,
309 paddr => 5,
310 pirq => 11,
310 pirq => 11,
311 sysfreq => 25000, -- CPU_FREQ
311 sysfreq => 25000, -- CPU_FREQ
312 rmap => 1,
312 rmap => 1,
313 rmapcrc => 1,
313 rmapcrc => 1,
314 fifosize1 => 16,
314 fifosize1 => 16,
315 fifosize2 => 16,
315 fifosize2 => 16,
316 rxclkbuftype => 1,
316 rxclkbuftype => 1,
317 rxunaligned => 0,
317 rxunaligned => 0,
318 rmapbufs => 4,
318 rmapbufs => 4,
319 ft => 0,
319 ft => 0,
320 netlist => 0,
320 netlist => 0,
321 ports => 2,
321 ports => 2,
322 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
322 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
323 memtech => apa3e,
323 memtech => apa3e,
324 destkey => 2,
324 destkey => 2,
325 spwcore => 1
325 spwcore => 1
326 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
326 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
327 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
327 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
328 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
328 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
329 )
329 )
330 PORT MAP(rstn, clk_25, spw_rxclk(0),
330 PORT MAP(rstn, clk_25, spw_rxclk(0),
331 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
331 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
332 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
332 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
333 swni, swno);
333 swni, swno);
334
334
335 swni.tickin <= '0';
335 swni.tickin <= '0';
336 swni.rmapen <= '1';
336 swni.rmapen <= '1';
337 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
337 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
338 swni.tickinraw <= '0';
338 swni.tickinraw <= '0';
339 swni.timein <= (OTHERS => '0');
339 swni.timein <= (OTHERS => '0');
340 swni.dcrstval <= (OTHERS => '0');
340 swni.dcrstval <= (OTHERS => '0');
341 swni.timerrstval <= (OTHERS => '0');
341 swni.timerrstval <= (OTHERS => '0');
342
342
343 -------------------------------------------------------------------------------
343 -------------------------------------------------------------------------------
344 -- LFR ------------------------------------------------------------------------
344 -- LFR ------------------------------------------------------------------------
345 -------------------------------------------------------------------------------
345 -------------------------------------------------------------------------------
346 lpp_lfr_1 : lpp_lfr
346 lpp_lfr_1 : lpp_lfr
347 GENERIC MAP (
347 GENERIC MAP (
348 Mem_use => use_RAM,
348 Mem_use => use_RAM,
349 nb_data_by_buffer_size => 32,
349 nb_data_by_buffer_size => 32,
350 nb_word_by_buffer_size => 30,
350 nb_word_by_buffer_size => 30,
351 nb_snapshot_param_size => 32,
351 nb_snapshot_param_size => 32,
352 delta_vector_size => 32,
352 delta_vector_size => 32,
353 delta_vector_size_f0_2 => 7, -- log2(96)
353 delta_vector_size_f0_2 => 7, -- log2(96)
354 pindex => 15,
354 pindex => 15,
355 paddr => 15,
355 paddr => 15,
356 pmask => 16#fff#,
356 pmask => 16#fff#,
357 pirq_ms => 6,
357 pirq_ms => 6,
358 pirq_wfp => 14,
358 pirq_wfp => 14,
359 hindex => 2,
359 hindex => 2,
360 top_lfr_version => X"010118") -- aa.bb.cc version
360 top_lfr_version => X"01011A") -- aa.bb.cc version
361 -- AA : BOARD NUMBER
361 -- AA : BOARD NUMBER
362 -- 0 => MINI_LFR
362 -- 0 => MINI_LFR
363 -- 1 => EM
363 -- 1 => EM
364 PORT MAP (
364 PORT MAP (
365 clk => clk_25,
365 clk => clk_25,
366 rstn => rstn,
366 rstn => rstn,
367 sample_B => sample_s(2 DOWNTO 0),
367 sample_B => sample_s(2 DOWNTO 0),
368 sample_E => sample_s(7 DOWNTO 3),
368 sample_E => sample_s(7 DOWNTO 3),
369 sample_val => sample_val,
369 sample_val => sample_val,
370 apbi => apbi_ext,
370 apbi => apbi_ext,
371 apbo => apbo_ext(15),
371 apbo => apbo_ext(15),
372 ahbi => ahbi_m_ext,
372 ahbi => ahbi_m_ext,
373 ahbo => ahbo_m_ext(2),
373 ahbo => ahbo_m_ext(2),
374 coarse_time => coarse_time,
374 coarse_time => coarse_time,
375 fine_time => fine_time,
375 fine_time => fine_time,
376 data_shaping_BW => bias_fail_sw,
376 data_shaping_BW => bias_fail_sw,
377 observation_vector_0 => OPEN,
377 observation_vector_0 => OPEN,
378 observation_vector_1 => OPEN,
378 observation_vector_1 => OPEN,
379 observation_reg => observation_reg);
379 observation_reg => observation_reg);
380
380
381
381
382 all_sample: FOR I IN 7 DOWNTO 0 GENERATE
382 all_sample: FOR I IN 7 DOWNTO 0 GENERATE
383 sample_s(I) <= sample(I) & '0' & '0';
383 sample_s(I) <= sample(I) & '0' & '0';
384 END GENERATE all_sample;
384 END GENERATE all_sample;
385
385
386 -----------------------------------------------------------------------------
386 -----------------------------------------------------------------------------
387 --
387 --
388 -----------------------------------------------------------------------------
388 -----------------------------------------------------------------------------
389 top_ad_conv_RHF1401_withFilter_1: top_ad_conv_RHF1401_withFilter
389 top_ad_conv_RHF1401_withFilter_1: top_ad_conv_RHF1401_withFilter
390 GENERIC MAP (
390 GENERIC MAP (
391 ChanelCount => 8,
391 ChanelCount => 8,
392 ncycle_cnv_high => 13,
392 ncycle_cnv_high => 13,
393 ncycle_cnv => 25)
393 ncycle_cnv => 25)
394 PORT MAP (
394 PORT MAP (
395 cnv_clk => clk_24,
395 cnv_clk => clk_24,
396 cnv_rstn => rstn,
396 cnv_rstn => rstn,
397 cnv => ADC_smpclk_s,
397 cnv => ADC_smpclk_s,
398 clk => clk_25,
398 clk => clk_25,
399 rstn => rstn,
399 rstn => rstn,
400 ADC_data => ADC_data,
400 ADC_data => ADC_data,
401 ADC_nOE => ADC_OEB_bar_CH,
401 ADC_nOE => ADC_OEB_bar_CH,
402 sample => sample,
402 sample => sample,
403 sample_val => sample_val);
403 sample_val => sample_val);
404
404
405
405
406
406
407
407
408 --top_ad_conv_RHF1401_1 : top_ad_conv_RHF1401
408 --top_ad_conv_RHF1401_1 : top_ad_conv_RHF1401
409 -- GENERIC MAP (
409 -- GENERIC MAP (
410 -- ChanelCount => 8,
410 -- ChanelCount => 8,
411 -- ncycle_cnv_high => 40, -- TODO : 79
411 -- ncycle_cnv_high => 40, -- TODO : 79
412 -- ncycle_cnv => 250) -- TODO : 500
412 -- ncycle_cnv => 250) -- TODO : 500
413 -- PORT MAP (
413 -- PORT MAP (
414 -- cnv_clk => clk_24, -- TODO : 49.152
414 -- cnv_clk => clk_24, -- TODO : 49.152
415 -- cnv_rstn => rstn, -- ok
415 -- cnv_rstn => rstn, -- ok
416 -- cnv => ADC_smpclk_s, -- ok
416 -- cnv => ADC_smpclk_s, -- ok
417 -- clk => clk_25, -- ok
417 -- clk => clk_25, -- ok
418 -- rstn => rstn, -- ok
418 -- rstn => rstn, -- ok
419 -- ADC_data => ADC_data, -- ok
419 -- ADC_data => ADC_data, -- ok
420 -- ADC_nOE => ADC_OEB_bar_CH, -- ok
420 -- ADC_nOE => ADC_OEB_bar_CH, -- ok
421 -- sample => sample, -- ok
421 -- sample => sample, -- ok
422 -- sample_val => sample_val); -- ok
422 -- sample_val => sample_val); -- ok
423
423
424 ADC_smpclk <= ADC_smpclk_s;
424 ADC_smpclk <= ADC_smpclk_s;
425
425
426 TAG8 <= ADC_smpclk_s;
426 TAG8 <= ADC_smpclk_s;
427
427
428 END beh;
428 END beh;
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