##// END OF EJS Templates
HG_REPOSITORIES » LPP » INSTRUMENTATION » USERS » PELLION » VHD_Lib
RSS

Clone from http://pc-instru.lpp.polytechnique.fr:5000/VHD_Lib

Modification UART (VHDL)...
martin -
r59:7a2c75e9a56c default
parent child
Show More
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 100644, binary diff hidden
Show file before | Show file after | Hide comments
@@ -0,0 +1,19
1 #include <stdio.h>
2 #include "lpp_apb_functions.h"
3 #include "apb_uart_Driver.h"
4
5
6 int main()
7 {
8 printf("Debut Main\n\n");
9 UART_Device* dev = openUART(0);
10 printf("addr: %x\n",(unsigned int)dev);
11 printf("cfg: %x\n",dev->ConfigReg);
12 char* a = "hello world\n";
13 uartputs(dev,a);
14 printf("Try #1 done\n");
15 uartputs(dev,"salut monde\n");
16 printf("Try #2 done\n");
17 return 0;
18 }
19
Show file before | Show file after | Hide comments
@@ -0,0 +1,60
1 /*------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 -----------------------------------------------------------------------------*/
22 #ifndef APB_CNA_DRIVER_H
23 #define APB_CNA_DRIVER_H
24
25 #define DAC_ready 3
26 #define DAC_enable 1
27 #define DAC_disable 0
28
29
30 /*===================================================
31 T Y P E S D E F
32 ====================================================*/
33
34 /** Structure reprοΏ½sentant le registre du CNA */
35 struct DAC_Driver
36 {
37 int configReg; /**< Registre de configuration: Flag Ready [1] ; Flag Enable [0] */
38 int dataReg; /**< Registre de donnοΏ½e sur 16 bits */
39 };
40
41 typedef struct DAC_Driver DAC_Device;
42
43 /*===================================================
44 F U N C T I O N S
45 ====================================================*/
46
47 /** Ouvre l'accοΏ½ au CNA */
48 DAC_Device* DacOpen(int count);
49
50 //DAC_Device* DacClose(int count);
51
52 /** Les donnοΏ½es sont lus a partir d'un tableau pour obtenir le signal de CAL (10Khz + 625hz) */
53 int DacTable();
54
55 /** Les donnοΏ½es sont entrοΏ½e par l'utilisateur, la conversion se fait a chaque nouvelle donnοΏ½e */
56 int DacConst();
57
58
59
60 #endif
Show file before | Show file after | Hide comments
@@ -0,0 +1,60
1 /*------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 -----------------------------------------------------------------------------*/
22 #include "apb_uart_Driver.h"
23 #include "lpp_apb_functions.h"
24 #include <stdio.h>
25
26
27 UART_Device* openUART(int count)
28 {
29 UART_Device* uart0;
30 uart0 = (UART_Device*) apbgetdevice(LPP_UART_CTRLR,VENDOR_LPP,count);
31 uart0->ConfigReg = BaudGenOnDuty;
32 return uart0;
33 }
34
35
36 void uartputc(UART_Device* dev,char c)
37 {
38 //while (!(dev->ConfigReg & (1<<5)));
39 while (!((dev->ConfigReg & DataSended) == DataSended));
40 dev->DataWReg = c;
41 printf(" ");
42 }
43
44 void uartputs(UART_Device* dev,char* s)
45 {
46 while (*s) uartputc(dev,*(s++));
47 }
48
49 char uartgetc(UART_Device* dev)
50 {
51 //while (!((dev->ConfigReg & (1<<2))));
52 while (!((dev->ConfigReg & NewData) == NewData));
53 return dev->DataRReg;
54 }
55
56 void uartgets(UART_Device* dev,char* s)
57 {
58 while (*s && (*s!=0xd)) *s++ = uartgetc(dev);
59 }
60
Show file before | Show file after | Hide comments
@@ -0,0 +1,56
1 /*------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 -----------------------------------------------------------------------------*/
22 #ifndef APB_UART_DRIVER_H
23 #define APB_UART_DRIVER_H
24
25
26 #define BaudGenOnDuty 0
27 #define DataSended 0x10
28 #define NewData 0x100
29
30 /*===================================================
31 T Y P E S D E F
32 ====================================================*/
33
34 struct UART_Driver
35 {
36 int ConfigReg;
37 int DataWReg;
38 int DataRReg;
39 };
40
41 typedef struct UART_Driver UART_Device;
42
43
44 /*===================================================
45 F U N C T I O N S
46 ====================================================*/
47
48
49 UART_Device* openUART(int count);
50 void uartputc(UART_Device* dev,char c);
51 void uartputs(UART_Device* dev,char* s);
52 char uartgetc(UART_Device* dev);
53 void uartgets(UART_Device* dev,char* s);
54
55
56 #endif
Show file before | Show file after | Hide comments
@@ -1,26 +1,27
1 1 #------------------------------------------------------------------------------
2 2 #-- This file is a part of the LPP VHDL IP LIBRARY
3 3 #-- Copyright (C) 2010, Laboratory of Plasmas Physic - CNRS
4 4 #--
5 5 #-- This program is free software; you can redistribute it and/or modify
6 6 #-- it under the terms of the GNU General Public License as published by
7 7 #-- the Free Software Foundation; either version 3 of the License, or
8 8 #-- (at your option) any later version.
9 9 #--
10 10 #-- This program is distributed in the hope that it will be useful,
11 11 #-- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 #-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 #-- GNU General Public License for more details.
14 14 #--
15 15 #-- You should have received a copy of the GNU General Public License
16 16 #-- along with this program; if not, write to the Free Software
17 17 #-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 #------------------------------------------------------------------------------
19 19
20 20
21 21
22 22 all:
23 23 make all -C ScanAPB
24 24 make all -C APB_lcd_ctrlr
25 25 make all -C BenchFIFO
26 make all -C BenchUART
26 27
Show file before | Show file after | Hide comments
@@ -1,36 +1,38
1 1 #------------------------------------------------------------------------------
2 2 #-- This file is a part of the LPP VHDL IP LIBRARY
3 3 #-- Copyright (C) 2010, Laboratory of Plasmas Physic - CNRS
4 4 #--
5 5 #-- This program is free software; you can redistribute it and/or modify
6 6 #-- it under the terms of the GNU General Public License as published by
7 7 #-- the Free Software Foundation; either version 3 of the License, or
8 8 #-- (at your option) any later version.
9 9 #--
10 10 #-- This program is distributed in the hope that it will be useful,
11 11 #-- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 #-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 #-- GNU General Public License for more details.
14 14 #--
15 15 #-- You should have received a copy of the GNU General Public License
16 16 #-- along with this program; if not, write to the Free Software
17 17 #-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 #------------------------------------------------------------------------------
19 19
20 20 include ../rules.mk
21 21
22 22
23 23
24 24 all:
25 25 make all -C AMBA
26 26 make all -C LCD
27 27 make all -C DAC
28 28 make all -C FIFO
29 make all -C UART
29 30
30 31
31 32 cleanall:
32 33 make clean -C AMBA
33 34 make clean -C LCD
34 35 make clean -C DAC
35 36 make clean -C FIFO
37 make clean -C UART
36 38
Show file before | Show file after | Hide comments
@@ -1,115 +1,115
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Alexis Jeandet
20 20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 21 ----------------------------------------------------------------------------
22 22 library IEEE;
23 23 use IEEE.numeric_std.all;
24 24 use IEEE.std_logic_1164.all;
25 25
26 26 --! Gestion Reception/Transmission
27 27
28 28 entity Shift_REG is
29 29 generic(Data_sz : integer := 10);
30 30 port(
31 31 clk : in std_logic;
32 32 Sclk : in std_logic;
33 33 reset : in std_logic;
34 34 SIN : in std_logic;
35 35 SOUT : out std_logic;
36 36 Serialize : in std_logic;
37 37 Serialized : out std_logic;
38 38 D : in std_logic_vector(Data_sz-1 downto 0);
39 39 Q : out std_logic_vector(Data_sz-1 downto 0)
40 40 );
41 41 end entity;
42 42
43 43
44 44 architecture ar_Shift_REG of Shift_REG is
45 45
46 46 signal REG : std_logic_vector(Data_sz-1 downto 0);
47 47 signal Serialized_int : std_logic;
48 48 signal Serialize_reg : std_logic;
49 49 signal Serial_reg : std_logic;
50 50 signal CptBits : std_logic_vector(Data_sz-1 downto 0);
51 51 constant CptBits_trig : std_logic_vector(Data_sz-1 downto 0) := (others => '1');
52 52 signal CptBits_flag : std_logic;
53 53 signal CptBits_flag_reg : std_logic;
54 54
55 55 begin
56 56
57 57 Serialized <= Serialized_int;
58 58 CptBits_flag <= '1' when CptBits = CptBits_trig else '0';
59 59
60 60 process(reset,clk)
61 61 begin
62 62 if reset = '0' then
63 63 Serialized_int <= '1';
64 64 CptBits_flag_reg <= '0';
65 65 Serial_reg <= '0';
66 66 Q <= (others => '0');
67 67 elsif clk'event and clk = '1' then
68 68 CptBits_flag_reg <= CptBits_flag;
69 69 Serial_reg <= Serialize;
70 70
71 71 if CptBits_flag = '1' and CptBits_flag_reg = '0' then
72 72 Serialized_int <= '1';
73 73 Q <= REG;
74 74 elsif(Serial_reg='0' and Serialize='1')then
75 75 Serialized_int <= '0';
76 76 end if;
77 77 end if;
78 78 end process;
79 79
80 80
81 81 process(reset,Sclk)
82 82 begin
83 83 if reset = '0' then
84 84 CptBits <= (others => '0');
85 85 REG <= (others => '0');
86 86 SOUT <= '1';
87 87 Serialize_reg <= '0';
88 88 elsif Sclk'event and Sclk = '1' then
89 89 Serialize_reg <= Serialized_int;
90 90 if (Serialized_int = '0' and Serialize_reg ='1') then
91 91 REG <= SIN & D(Data_sz-1 downto 1);
92 92 SOUT <= D(0);
93 elsif CptBits_flag ='1' then
94 REG <= SIN & D(Data_sz-1 downto 1);
95 SOUT <= D(0);
93 -- elsif CptBits_flag ='1' then
94 -- REG <= SIN & D(Data_sz-1 downto 1);
95 -- SOUT <= D(0);
96 96 elsif Serialized_int = '0' then
97 97 REG <= SIN & REG(Data_sz-1 downto 1);
98 98 SOUT <= REG(0);
99 99 else
100 100 SOUT <= '1';
101 101 end if;
102 102 if Serialized_int = '0' then
103 103 if CptBits_flag = '1' then
104 104 CptBits <= (others => '0');
105 105 else
106 106 CptBits <= '1' & CptBits(Data_sz-1 downto 1);
107 107 end if;
108 108 else
109 109 CptBits <= (others => '0');
110 110 end if;
111 111
112 112 end if;
113 113 end process;
114 114
115 115 end ar_Shift_REG;
Show file before | Show file after | Hide comments
@@ -1,106 +1,106
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Alexis Jeandet
20 20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 21 ----------------------------------------------------------------------------
22 22 library IEEE;
23 23 use IEEE.numeric_std.all;
24 24 use IEEE.std_logic_1164.all;
25 25 library lpp;
26 26 use lpp.lpp_uart.all;
27 27
28 28 --! Programme qui va gerer toute la communication entre le PC et le FPGA
29 29
30 30 entity UART is
31 31 generic(Data_sz : integer := 8); --! Constante de taille pour un mot de donnee
32 32 port(
33 33 clk : in std_logic; --! Horloge a 25Mhz du systeme
34 34 reset : in std_logic; --! Reset du systeme
35 35 TXD : out std_logic; --! Transmission, cote PC
36 36 RXD : in std_logic; --! Reception, cote PC
37 37 Capture : in std_logic; --! "Reset" cible pour le generateur de bauds, ici indissocie du reset global
38 38 NwDat : out std_logic; --! Flag, Nouvelle donnee presente
39 39 ACK : in std_logic; --! Flag, Reponse au flag precedent
40 40 Send : in std_logic; --! Flag, Demande d'envoi sur le bus
41 41 Sended : out std_logic; --! Flag, Envoi termine
42 42 BTrigger : out std_logic_vector(11 downto 0); --! Registre contenant la valeur du diviseur de frequence pour la transmission
43 43 RDATA : out std_logic_vector(Data_sz-1 downto 0); --! Mot de donnee en provenance de l'utilisateur
44 44 WDATA : in std_logic_vector(Data_sz-1 downto 0) --! Mot de donnee a transmettre a l'utilisateur
45 45 );
46 46 end entity;
47 47
48 48 --! @details Gestion de la Reception/Transmission donc de la Vectorisation/Serialisation
49 49 --! ainsi que la detection et le reglage de le frequence de transmission optimale sur le bus (Generateur de Bauds)
50 50
51 51 architecture ar_UART of UART is
52 52 signal Bclk : std_logic;
53 53
54 54 signal RDATA_int : std_logic_vector(Data_sz+1 downto 0);
55 55 signal WDATA_int : std_logic_vector(Data_sz+1 downto 0);
56 56
57 57 signal TXD_Dummy : std_logic;
58 58 signal NwDat_int : std_logic;
59 59 signal NwDat_int_reg : std_logic;
60 60 signal receive : std_logic;
61 61 constant zeroVect : std_logic_vector(Data_sz+1 downto 0) := (others => '0');
62 62
63 63 begin
64 64
65 65
66 66
67 67 WDATA_int <= '1' & WDATA & '0';
68 68
69 BaudGenerator : BaudGen
69 BaudGenerator : entity work.BaudGen
70 70 port map(clk,reset,Capture,Bclk,RXD,BTrigger);
71 71
72 72
73 RX_REG : Shift_REG
73 RX_REG : entity work.Shift_REG
74 74 generic map(Data_sz+2)
75 75 port map(clk,Bclk,reset,RXD,TXD_Dummy,receive,NwDat_int,zeroVect,RDATA_int);
76 76
77 TX_REG : Shift_REG
77 TX_REG : entity work.Shift_REG
78 78 generic map(Data_sz+2)
79 79 port map(clk,Bclk,reset,'1',TXD,Send,Sended,WDATA_int);
80 80
81 81
82 82
83 83 process(clk,reset)
84 84 begin
85 85 if reset = '0' then
86 86 NwDat <= '0';
87 87 elsif clk'event and clk = '1' then
88 88 NwDat_int_reg <= NwDat_int;
89 89 if RXD = '1' and NwDat_int = '1' then
90 90 receive <= '0';
91 91 elsif RXD = '0' then
92 92 receive <= '1';
93 93 end if;
94 94 if NwDat_int_reg = '0' and NwDat_int = '1' then
95 95 NwDat <= '1';
96 96 RDATA <= RDATA_int(8 downto 1);
97 97 elsif ack = '1' then
98 98 NwDat <= '0';
99 99 end if;
100 100 end if;
101 101 end process;
102 102
103 103 end ar_UART;
104 104
105 105
106 106
General Comments 0
You need to be logged in to leave comments. Login now