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(LFR-EM) WFP_MS-1-1-26...
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r426:793daca937bf JC
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1 # Top Level Design Parameters
1 # Top Level Design Parameters
2
2
3 # Clocks
3 # Clocks
4
4
5 create_clock -period 10.000000 -waveform {0.000000 5.000000} clk100MHz
5 create_clock -period 10.000000 -waveform {0.000000 5.000000} clk100MHz
6 create_clock -period 20.344999 -waveform {0.000000 10.172500} clk49_152MHz
6 create_clock -period 20.344999 -waveform {0.000000 10.172500} clk49_152MHz
7 create_clock -period 20.000000 -waveform {0.000000 10.000000} clk_50_s:Q
7 create_clock -period 20.000000 -waveform {0.000000 10.000000} clk_50_s:Q
8 create_clock -period 40.000000 -waveform {0.000000 20.000000} clk_25:Q
8 create_clock -period 40.000000 -waveform {0.000000 20.000000} clk_25:Q
9 create_clock -period 40.690000 -waveform {0.000000 20.345100} clk_24:Q
9 create_clock -period 40.690000 -waveform {0.000000 20.345100} clk_24:Q
10 create_clock -name SPW_CLOCK -period 100.000000 -waveform {0.000000 50.000000} {SPW1_DIN SPW1_SIN SPW2_DIN SPW2_SIN}
10 create_clock -name SPW_CLOCK -period 100.000000 -waveform {0.000000 50.000000} {spw1_din spw1_sin spw2_din spw2_sin}
11
11
12
12
13 # False Paths Between Clocks
13 # False Paths Between Clocks
14
14
15
15
16 # False Path Constraints
16 # False Path Constraints
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18
18
19 # Maximum Delay Constraints
19 # Maximum Delay Constraints
20
20
21
21
22 # Multicycle Constraints
22 # Multicycle Constraints
23
23
24
24
25 # Virtual Clocks
25 # Virtual Clocks
26 # Output Load Constraints
26 # Output Load Constraints
27 # Driving Cell Constraints
27 # Driving Cell Constraints
28 # Wire Loads
28 # Wire Loads
29 # set_wire_load_mode top
29 # set_wire_load_mode top
30
30
31 # Other Constraints
31 # Other Constraints
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