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1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
21 -- jean-christophe.pellion@easii-ic.com
22 -------------------------------------------------------------------------------
22 -------------------------------------------------------------------------------
23 LIBRARY IEEE;
23 LIBRARY IEEE;
24 USE IEEE.STD_LOGIC_1164.ALL;
24 USE IEEE.STD_LOGIC_1164.ALL;
25 USE ieee.numeric_std.ALL;
25 USE ieee.numeric_std.ALL;
26
26
27 LIBRARY grlib;
27 LIBRARY grlib;
28 USE grlib.amba.ALL;
28 USE grlib.amba.ALL;
29 USE grlib.stdlib.ALL;
29 USE grlib.stdlib.ALL;
30 USE grlib.devices.ALL;
30 USE grlib.devices.ALL;
31 USE GRLIB.DMA2AHB_Package.ALL;
31 USE GRLIB.DMA2AHB_Package.ALL;
32
32
33 LIBRARY lpp;
33 LIBRARY lpp;
34 USE lpp.lpp_waveform_pkg.ALL;
34 USE lpp.lpp_waveform_pkg.ALL;
35 USE lpp.iir_filter.ALL;
35 USE lpp.iir_filter.ALL;
36 USE lpp.lpp_memory.ALL;
36 USE lpp.lpp_memory.ALL;
37
37
38 LIBRARY techmap;
38 LIBRARY techmap;
39 USE techmap.gencomp.ALL;
39 USE techmap.gencomp.ALL;
40
40
41 ENTITY lpp_waveform IS
41 ENTITY lpp_waveform IS
42
42
43 GENERIC (
43 GENERIC (
44 tech : INTEGER := inferred;
44 tech : INTEGER := inferred;
45 data_size : INTEGER := 96; --16*6
45 data_size : INTEGER := 96; --16*6
46 nb_data_by_buffer_size : INTEGER := 11;
46 nb_data_by_buffer_size : INTEGER := 11;
47 -- nb_word_by_buffer_size : INTEGER := 11;
47 -- nb_word_by_buffer_size : INTEGER := 11;
48 nb_snapshot_param_size : INTEGER := 11;
48 nb_snapshot_param_size : INTEGER := 11;
49 delta_vector_size : INTEGER := 20;
49 delta_vector_size : INTEGER := 20;
50 delta_vector_size_f0_2 : INTEGER := 3);
50 delta_vector_size_f0_2 : INTEGER := 3);
51
51
52 PORT (
52 PORT (
53 clk : IN STD_LOGIC;
53 clk : IN STD_LOGIC;
54 rstn : IN STD_LOGIC;
54 rstn : IN STD_LOGIC;
55
55
56 ---- AMBA AHB Master Interface
56 ---- AMBA AHB Master Interface
57 --AHB_Master_In : IN AHB_Mst_In_Type; -- TODO
57 --AHB_Master_In : IN AHB_Mst_In_Type; -- TODO
58 --AHB_Master_Out : OUT AHB_Mst_Out_Type; -- TODO
58 --AHB_Master_Out : OUT AHB_Mst_Out_Type; -- TODO
59
59
60 --config
60 --config
61 reg_run : IN STD_LOGIC;
61 reg_run : IN STD_LOGIC;
62 reg_start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
62 reg_start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
63 reg_delta_snapshot : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
63 reg_delta_snapshot : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
64 reg_delta_f0 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
64 reg_delta_f0 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
65 reg_delta_f0_2 : IN STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
65 reg_delta_f0_2 : IN STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
66 reg_delta_f1 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
66 reg_delta_f1 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
67 reg_delta_f2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
67 reg_delta_f2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
68
68
69 enable_f0 : IN STD_LOGIC;
69 enable_f0 : IN STD_LOGIC;
70 enable_f1 : IN STD_LOGIC;
70 enable_f1 : IN STD_LOGIC;
71 enable_f2 : IN STD_LOGIC;
71 enable_f2 : IN STD_LOGIC;
72 enable_f3 : IN STD_LOGIC;
72 enable_f3 : IN STD_LOGIC;
73
73
74 burst_f0 : IN STD_LOGIC;
74 burst_f0 : IN STD_LOGIC;
75 burst_f1 : IN STD_LOGIC;
75 burst_f1 : IN STD_LOGIC;
76 burst_f2 : IN STD_LOGIC;
76 burst_f2 : IN STD_LOGIC;
77
77
78 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
78 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
79 -- nb_word_by_buffer : IN STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
79 -- nb_word_by_buffer : IN STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
80 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
80 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
81
81
82 status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma
82 status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma
83
83
84
84
85 -- REG DMA
85 -- REG DMA
86 status_buffer_ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
86 status_buffer_ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
87 addr_buffer : IN STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
87 addr_buffer : IN STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
88 length_buffer : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
88 length_buffer : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
89
89
90 ready_buffer : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
90 ready_buffer : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
91 buffer_time : OUT STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
91 buffer_time : OUT STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
92 error_buffer_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
92 error_buffer_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
93
93
94 ---------------------------------------------------------------------------
94 ---------------------------------------------------------------------------
95 -- INPUT
95 -- INPUT
96 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
96 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
97 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
97 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
98
98
99 --f0
99 --f0
100 data_f0_in_valid : IN STD_LOGIC;
100 data_f0_in_valid : IN STD_LOGIC;
101 data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
101 data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
102 --f1
102 --f1
103 data_f1_in_valid : IN STD_LOGIC;
103 data_f1_in_valid : IN STD_LOGIC;
104 data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
104 data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
105 --f2
105 --f2
106 data_f2_in_valid : IN STD_LOGIC;
106 data_f2_in_valid : IN STD_LOGIC;
107 data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
107 data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
108 --f3
108 --f3
109 data_f3_in_valid : IN STD_LOGIC;
109 data_f3_in_valid : IN STD_LOGIC;
110 data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
110 data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
111
111
112 ---------------------------------------------------------------------------
112 ---------------------------------------------------------------------------
113 -- DMA --------------------------------------------------------------------
113 -- DMA --------------------------------------------------------------------
114
114
115 dma_fifo_valid_burst : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
115 dma_fifo_valid_burst : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
116 dma_fifo_data : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
116 dma_fifo_data : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
117 dma_fifo_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
117 dma_fifo_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
118 dma_buffer_new : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
118 dma_buffer_new : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
119 dma_buffer_addr : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
119 dma_buffer_addr : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
120 dma_buffer_length : OUT STD_LOGIC_VECTOR(26*4-1 DOWNTO 0);
120 dma_buffer_length : OUT STD_LOGIC_VECTOR(26*4-1 DOWNTO 0);
121 dma_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
121 dma_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
122 dma_buffer_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0)
122 dma_buffer_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0)
123
123
124 );
124 );
125
125
126 END lpp_waveform;
126 END lpp_waveform;
127
127
128 ARCHITECTURE beh OF lpp_waveform IS
128 ARCHITECTURE beh OF lpp_waveform IS
129 SIGNAL start_snapshot_f0 : STD_LOGIC;
129 SIGNAL start_snapshot_f0 : STD_LOGIC;
130 SIGNAL start_snapshot_f1 : STD_LOGIC;
130 SIGNAL start_snapshot_f1 : STD_LOGIC;
131 SIGNAL start_snapshot_f2 : STD_LOGIC;
131 SIGNAL start_snapshot_f2 : STD_LOGIC;
132
132
133 SIGNAL data_f0_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
133 SIGNAL data_f0_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
134 SIGNAL data_f1_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
134 SIGNAL data_f1_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
135 SIGNAL data_f2_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
135 SIGNAL data_f2_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
136 SIGNAL data_f3_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
136 SIGNAL data_f3_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
137
137
138 SIGNAL data_f0_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
138 SIGNAL data_f0_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
139 SIGNAL data_f1_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
139 SIGNAL data_f1_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
140 SIGNAL data_f2_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
140 SIGNAL data_f2_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
141 SIGNAL data_f3_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
141 SIGNAL data_f3_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
142
142
143 SIGNAL data_f0_out_valid : STD_LOGIC;
143 SIGNAL data_f0_out_valid : STD_LOGIC;
144 SIGNAL data_f1_out_valid : STD_LOGIC;
144 SIGNAL data_f1_out_valid : STD_LOGIC;
145 SIGNAL data_f2_out_valid : STD_LOGIC;
145 SIGNAL data_f2_out_valid : STD_LOGIC;
146 SIGNAL data_f3_out_valid : STD_LOGIC;
146 SIGNAL data_f3_out_valid : STD_LOGIC;
147 SIGNAL nb_snapshot_param_more_one : STD_LOGIC_VECTOR(nb_snapshot_param_size DOWNTO 0);
147 SIGNAL nb_snapshot_param_more_one : STD_LOGIC_VECTOR(nb_snapshot_param_size DOWNTO 0);
148 --
148 --
149 SIGNAL valid_in : STD_LOGIC_VECTOR(3 DOWNTO 0);
149 SIGNAL valid_in : STD_LOGIC_VECTOR(3 DOWNTO 0);
150 SIGNAL valid_out : STD_LOGIC_VECTOR(3 DOWNTO 0);
150 SIGNAL valid_out : STD_LOGIC_VECTOR(3 DOWNTO 0);
151 SIGNAL valid_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
151 SIGNAL valid_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
152 SIGNAL time_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
152 SIGNAL time_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
153 SIGNAL data_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
153 SIGNAL data_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
154 SIGNAL ready_arb : STD_LOGIC_VECTOR(3 DOWNTO 0);
154 SIGNAL ready_arb : STD_LOGIC_VECTOR(3 DOWNTO 0);
155 SIGNAL data_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
155 SIGNAL data_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
156 SIGNAL time_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
156 SIGNAL time_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
157 SIGNAL wdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
157 SIGNAL wdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
158 SIGNAL full_almost : STD_LOGIC_VECTOR(3 DOWNTO 0);
158 SIGNAL full_almost : STD_LOGIC_VECTOR(3 DOWNTO 0);
159 SIGNAL full : STD_LOGIC_VECTOR(3 DOWNTO 0);
159 SIGNAL full : STD_LOGIC_VECTOR(3 DOWNTO 0);
160 SIGNAL empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0);
160 SIGNAL empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0);
161 SIGNAL empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
161 SIGNAL empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
162 --
162 --
163 SIGNAL data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
163 SIGNAL data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
164 SIGNAL time_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
164 SIGNAL time_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
165 SIGNAL rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
165 SIGNAL rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
166 SIGNAL enable : STD_LOGIC_VECTOR(3 DOWNTO 0);
166 SIGNAL enable : STD_LOGIC_VECTOR(3 DOWNTO 0);
167 --
167 --
168 SIGNAL run : STD_LOGIC;
168 SIGNAL run : STD_LOGIC;
169 --
169 --
170 TYPE TIME_VECTOR IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(47 DOWNTO 0);
170 TYPE TIME_VECTOR IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(47 DOWNTO 0);
171 SIGNAL data_out : Data_Vector(3 DOWNTO 0, 95 DOWNTO 0);
171 SIGNAL data_out : Data_Vector(3 DOWNTO 0, 95 DOWNTO 0);
172 SIGNAL time_out_2 : Data_Vector(3 DOWNTO 0, 47 DOWNTO 0);
172 SIGNAL time_out_2 : Data_Vector(3 DOWNTO 0, 47 DOWNTO 0);
173 SIGNAL time_out : TIME_VECTOR(3 DOWNTO 0);
173 SIGNAL time_out : TIME_VECTOR(3 DOWNTO 0);
174 SIGNAL time_out_debug : TIME_VECTOR(3 DOWNTO 0); -- TODO : debug
174 SIGNAL time_out_debug : TIME_VECTOR(3 DOWNTO 0); -- TODO : debug
175 SIGNAL time_reg1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
175 SIGNAL time_reg1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
176 SIGNAL time_reg2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
176 SIGNAL time_reg2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
177 --
177 --
178
178
179 SIGNAL s_empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0); --occupancy is lesser than 16 * 32b
179 SIGNAL s_empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0); --occupancy is lesser than 16 * 32b
180 SIGNAL s_empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
180 SIGNAL s_empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
181 SIGNAL s_data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
181 SIGNAL s_data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
182 -- SIGNAL s_rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
182 -- SIGNAL s_rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
183 SIGNAL s_rdata_v : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
183 SIGNAL s_rdata_v : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
184
184
185 --
185 --
186 SIGNAL arbiter_time_out : STD_LOGIC_VECTOR(47 DOWNTO 0);
186 SIGNAL arbiter_time_out : STD_LOGIC_VECTOR(47 DOWNTO 0);
187 SIGNAL arbiter_time_out_new : STD_LOGIC_VECTOR(3 DOWNTO 0);
187 SIGNAL arbiter_time_out_new : STD_LOGIC_VECTOR(3 DOWNTO 0);
188
188
189 SIGNAL fifo_buffer_time : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
189 SIGNAL fifo_buffer_time : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
190
190
191 SIGNAL fifo_buffer_time_s : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
191 SIGNAL fifo_buffer_time_s : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
192
192
193 BEGIN -- beh
193 BEGIN -- beh
194
194
195 -----------------------------------------------------------------------------
195 -----------------------------------------------------------------------------
196
196
197 lpp_waveform_snapshot_controler_1 : lpp_waveform_snapshot_controler
197 lpp_waveform_snapshot_controler_1 : lpp_waveform_snapshot_controler
198 GENERIC MAP (
198 GENERIC MAP (
199 delta_vector_size => delta_vector_size,
199 delta_vector_size => delta_vector_size,
200 delta_vector_size_f0_2 => delta_vector_size_f0_2
200 delta_vector_size_f0_2 => delta_vector_size_f0_2
201 )
201 )
202 PORT MAP (
202 PORT MAP (
203 clk => clk,
203 clk => clk,
204 rstn => rstn,
204 rstn => rstn,
205 reg_run => reg_run,
205 reg_run => reg_run,
206 reg_start_date => reg_start_date,
206 reg_start_date => reg_start_date,
207 reg_delta_snapshot => reg_delta_snapshot,
207 reg_delta_snapshot => reg_delta_snapshot,
208 reg_delta_f0 => reg_delta_f0,
208 reg_delta_f0 => reg_delta_f0,
209 reg_delta_f0_2 => reg_delta_f0_2,
209 reg_delta_f0_2 => reg_delta_f0_2,
210 reg_delta_f1 => reg_delta_f1,
210 reg_delta_f1 => reg_delta_f1,
211 reg_delta_f2 => reg_delta_f2,
211 reg_delta_f2 => reg_delta_f2,
212 coarse_time => coarse_time(30 DOWNTO 0),
212 coarse_time => coarse_time(30 DOWNTO 0),
213 data_f0_valid => data_f0_in_valid,
213 data_f0_valid => data_f0_in_valid,
214 data_f2_valid => data_f2_in_valid,
214 data_f2_valid => data_f2_in_valid,
215 start_snapshot_f0 => start_snapshot_f0,
215 start_snapshot_f0 => start_snapshot_f0,
216 start_snapshot_f1 => start_snapshot_f1,
216 start_snapshot_f1 => start_snapshot_f1,
217 start_snapshot_f2 => start_snapshot_f2,
217 start_snapshot_f2 => start_snapshot_f2,
218 wfp_on => run);
218 wfp_on => run);
219
219
220 lpp_waveform_snapshot_f0 : lpp_waveform_snapshot
220 lpp_waveform_snapshot_f0 : lpp_waveform_snapshot
221 GENERIC MAP (
221 GENERIC MAP (
222 data_size => data_size,
222 data_size => data_size,
223 nb_snapshot_param_size => nb_snapshot_param_size)
223 nb_snapshot_param_size => nb_snapshot_param_size)
224 PORT MAP (
224 PORT MAP (
225 clk => clk,
225 clk => clk,
226 rstn => rstn,
226 rstn => rstn,
227 run => run,
227 run => run,
228 enable => enable_f0,
228 enable => enable_f0,
229 burst_enable => burst_f0,
229 burst_enable => burst_f0,
230 nb_snapshot_param => nb_snapshot_param,
230 nb_snapshot_param => nb_snapshot_param,
231 start_snapshot => start_snapshot_f0,
231 start_snapshot => start_snapshot_f0,
232 data_in => data_f0_in,
232 data_in => data_f0_in,
233 data_in_valid => data_f0_in_valid,
233 data_in_valid => data_f0_in_valid,
234 data_out => data_f0_out,
234 data_out => data_f0_out,
235 data_out_valid => data_f0_out_valid);
235 data_out_valid => data_f0_out_valid);
236
236
237 nb_snapshot_param_more_one <= ('0' & nb_snapshot_param) ;--+ 1;
237 nb_snapshot_param_more_one <= ('0' & nb_snapshot_param) ;--+ 1;
238
238
239 lpp_waveform_snapshot_f1 : lpp_waveform_snapshot
239 lpp_waveform_snapshot_f1 : lpp_waveform_snapshot
240 GENERIC MAP (
240 GENERIC MAP (
241 data_size => data_size,
241 data_size => data_size,
242 nb_snapshot_param_size => nb_snapshot_param_size+1)
242 nb_snapshot_param_size => nb_snapshot_param_size+1)
243 PORT MAP (
243 PORT MAP (
244 clk => clk,
244 clk => clk,
245 rstn => rstn,
245 rstn => rstn,
246 run => run,
246 run => run,
247 enable => enable_f1,
247 enable => enable_f1,
248 burst_enable => burst_f1,
248 burst_enable => burst_f1,
249 nb_snapshot_param => nb_snapshot_param_more_one,
249 nb_snapshot_param => nb_snapshot_param_more_one,
250 start_snapshot => start_snapshot_f1,
250 start_snapshot => start_snapshot_f1,
251 data_in => data_f1_in,
251 data_in => data_f1_in,
252 data_in_valid => data_f1_in_valid,
252 data_in_valid => data_f1_in_valid,
253 data_out => data_f1_out,
253 data_out => data_f1_out,
254 data_out_valid => data_f1_out_valid);
254 data_out_valid => data_f1_out_valid);
255
255
256 lpp_waveform_snapshot_f2 : lpp_waveform_snapshot
256 lpp_waveform_snapshot_f2 : lpp_waveform_snapshot
257 GENERIC MAP (
257 GENERIC MAP (
258 data_size => data_size,
258 data_size => data_size,
259 nb_snapshot_param_size => nb_snapshot_param_size+1)
259 nb_snapshot_param_size => nb_snapshot_param_size+1)
260 PORT MAP (
260 PORT MAP (
261 clk => clk,
261 clk => clk,
262 rstn => rstn,
262 rstn => rstn,
263 run => run,
263 run => run,
264 enable => enable_f2,
264 enable => enable_f2,
265 burst_enable => burst_f2,
265 burst_enable => burst_f2,
266 nb_snapshot_param => nb_snapshot_param_more_one,
266 nb_snapshot_param => nb_snapshot_param_more_one,
267 start_snapshot => start_snapshot_f2,
267 start_snapshot => start_snapshot_f2,
268 data_in => data_f2_in,
268 data_in => data_f2_in,
269 data_in_valid => data_f2_in_valid,
269 data_in_valid => data_f2_in_valid,
270 data_out => data_f2_out,
270 data_out => data_f2_out,
271 data_out_valid => data_f2_out_valid);
271 data_out_valid => data_f2_out_valid);
272
272
273 lpp_waveform_burst_f3 : lpp_waveform_burst
273 lpp_waveform_burst_f3 : lpp_waveform_burst
274 GENERIC MAP (
274 GENERIC MAP (
275 data_size => data_size)
275 data_size => data_size)
276 PORT MAP (
276 PORT MAP (
277 clk => clk,
277 clk => clk,
278 rstn => rstn,
278 rstn => rstn,
279 run => run,
279 run => run,
280 enable => enable_f3,
280 enable => enable_f3,
281 data_in => data_f3_in,
281 data_in => data_f3_in,
282 data_in_valid => data_f3_in_valid,
282 data_in_valid => data_f3_in_valid,
283 data_out => data_f3_out,
283 data_out => data_f3_out,
284 data_out_valid => data_f3_out_valid);
284 data_out_valid => data_f3_out_valid);
285
285
286 -----------------------------------------------------------------------------
286 -----------------------------------------------------------------------------
287 -- DEBUG -- SNAPSHOT OUT
287 -- DEBUG -- SNAPSHOT OUT
288 --debug_f0_data_valid <= data_f0_out_valid;
288 --debug_f0_data_valid <= data_f0_out_valid;
289 --debug_f0_data <= data_f0_out;
289 --debug_f0_data <= data_f0_out;
290 --debug_f1_data_valid <= data_f1_out_valid;
290 --debug_f1_data_valid <= data_f1_out_valid;
291 --debug_f1_data <= data_f1_out;
291 --debug_f1_data <= data_f1_out;
292 --debug_f2_data_valid <= data_f2_out_valid;
292 --debug_f2_data_valid <= data_f2_out_valid;
293 --debug_f2_data <= data_f2_out;
293 --debug_f2_data <= data_f2_out;
294 --debug_f3_data_valid <= data_f3_out_valid;
294 --debug_f3_data_valid <= data_f3_out_valid;
295 --debug_f3_data <= data_f3_out;
295 --debug_f3_data <= data_f3_out;
296 -----------------------------------------------------------------------------
296 -----------------------------------------------------------------------------
297
297
298 PROCESS (clk, rstn)
298 PROCESS (clk, rstn)
299 BEGIN -- PROCESS
299 BEGIN -- PROCESS
300 IF rstn = '0' THEN -- asynchronous reset (active low)
300 IF rstn = '0' THEN -- asynchronous reset (active low)
301 time_reg1 <= (OTHERS => '0');
301 time_reg1 <= (OTHERS => '0');
302 time_reg2 <= (OTHERS => '0');
302 time_reg2 <= (OTHERS => '0');
303 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
303 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
304 time_reg1 <= fine_time & coarse_time;
304 time_reg1 <= fine_time & coarse_time;
305 time_reg2 <= time_reg1;
305 time_reg2 <= time_reg1;
306 END IF;
306 END IF;
307 END PROCESS;
307 END PROCESS;
308
308
309 valid_in <= data_f3_out_valid & data_f2_out_valid & data_f1_out_valid & data_f0_out_valid;
309 valid_in <= data_f3_out_valid & data_f2_out_valid & data_f1_out_valid & data_f0_out_valid;
310 all_input_valid : FOR i IN 3 DOWNTO 0 GENERATE
310 all_input_valid : FOR i IN 3 DOWNTO 0 GENERATE
311 lpp_waveform_dma_genvalid_I : lpp_waveform_dma_genvalid
311 lpp_waveform_dma_genvalid_I : lpp_waveform_dma_genvalid
312 PORT MAP (
312 PORT MAP (
313 HCLK => clk,
313 HCLK => clk,
314 HRESETn => rstn,
314 HRESETn => rstn,
315 run => run,
315 run => run,
316 valid_in => valid_in(I),
316 valid_in => valid_in(I),
317 ack_in => valid_ack(I),
317 ack_in => valid_ack(I),
318 time_in => time_reg2, -- Todo
318 time_in => time_reg2, -- Todo
319 valid_out => valid_out(I),
319 valid_out => valid_out(I),
320 time_out => time_out(I), -- Todo
320 time_out => time_out(I), -- Todo
321 error => status_new_err(I));
321 error => status_new_err(I));
322 END GENERATE all_input_valid;
322 END GENERATE all_input_valid;
323
323
324 data_f0_out_swap <= data_f0_out((16*5)-1 DOWNTO 16*4) &
324 data_f0_out_swap <= data_f0_out((16*5)-1 DOWNTO 16*4) &
325 data_f0_out((16*6)-1 DOWNTO 16*5) &
325 data_f0_out((16*6)-1 DOWNTO 16*5) &
326 data_f0_out((16*3)-1 DOWNTO 16*2) &
326 data_f0_out((16*3)-1 DOWNTO 16*2) &
327 data_f0_out((16*4)-1 DOWNTO 16*3) &
327 data_f0_out((16*4)-1 DOWNTO 16*3) &
328 data_f0_out((16*1)-1 DOWNTO 16*0) &
328 data_f0_out((16*1)-1 DOWNTO 16*0) &
329 data_f0_out((16*2)-1 DOWNTO 16*1) ;
329 data_f0_out((16*2)-1 DOWNTO 16*1) ;
330
330
331 data_f1_out_swap <= data_f1_out((16*5)-1 DOWNTO 16*4) &
331 data_f1_out_swap <= data_f1_out((16*5)-1 DOWNTO 16*4) &
332 data_f1_out((16*6)-1 DOWNTO 16*5) &
332 data_f1_out((16*6)-1 DOWNTO 16*5) &
333 data_f1_out((16*3)-1 DOWNTO 16*2) &
333 data_f1_out((16*3)-1 DOWNTO 16*2) &
334 data_f1_out((16*4)-1 DOWNTO 16*3) &
334 data_f1_out((16*4)-1 DOWNTO 16*3) &
335 data_f1_out((16*1)-1 DOWNTO 16*0) &
335 data_f1_out((16*1)-1 DOWNTO 16*0) &
336 data_f1_out((16*2)-1 DOWNTO 16*1) ;
336 data_f1_out((16*2)-1 DOWNTO 16*1) ;
337
337
338 data_f2_out_swap <= data_f2_out((16*5)-1 DOWNTO 16*4) &
338 data_f2_out_swap <= data_f2_out((16*5)-1 DOWNTO 16*4) &
339 data_f2_out((16*6)-1 DOWNTO 16*5) &
339 data_f2_out((16*6)-1 DOWNTO 16*5) &
340 data_f2_out((16*3)-1 DOWNTO 16*2) &
340 data_f2_out((16*3)-1 DOWNTO 16*2) &
341 data_f2_out((16*4)-1 DOWNTO 16*3) &
341 data_f2_out((16*4)-1 DOWNTO 16*3) &
342 data_f2_out((16*1)-1 DOWNTO 16*0) &
342 data_f2_out((16*1)-1 DOWNTO 16*0) &
343 data_f2_out((16*2)-1 DOWNTO 16*1) ;
343 data_f2_out((16*2)-1 DOWNTO 16*1) ;
344
344
345 data_f3_out_swap <= data_f3_out((16*5)-1 DOWNTO 16*4) &
345 data_f3_out_swap <= data_f3_out((16*5)-1 DOWNTO 16*4) &
346 data_f3_out((16*6)-1 DOWNTO 16*5) &
346 data_f3_out((16*6)-1 DOWNTO 16*5) &
347 data_f3_out((16*3)-1 DOWNTO 16*2) &
347 data_f3_out((16*3)-1 DOWNTO 16*2) &
348 data_f3_out((16*4)-1 DOWNTO 16*3) &
348 data_f3_out((16*4)-1 DOWNTO 16*3) &
349 data_f3_out((16*1)-1 DOWNTO 16*0) &
349 data_f3_out((16*1)-1 DOWNTO 16*0) &
350 data_f3_out((16*2)-1 DOWNTO 16*1) ;
350 data_f3_out((16*2)-1 DOWNTO 16*1) ;
351
351
352 all_bit_of_data_out : FOR I IN 95 DOWNTO 0 GENERATE
352 all_bit_of_data_out : FOR I IN 95 DOWNTO 0 GENERATE
353 data_out(0, I) <= data_f0_out_swap(I);
353 data_out(0, I) <= data_f0_out_swap(I);
354 data_out(1, I) <= data_f1_out_swap(I);
354 data_out(1, I) <= data_f1_out_swap(I);
355 data_out(2, I) <= data_f2_out_swap(I);
355 data_out(2, I) <= data_f2_out_swap(I);
356 data_out(3, I) <= data_f3_out_swap(I);
356 data_out(3, I) <= data_f3_out_swap(I);
357 END GENERATE all_bit_of_data_out;
357 END GENERATE all_bit_of_data_out;
358
358
359 -----------------------------------------------------------------------------
359 -----------------------------------------------------------------------------
360 -- TODO : debug
360 -- TODO : debug
361 -----------------------------------------------------------------------------
361 -----------------------------------------------------------------------------
362 all_bit_of_time_out : FOR I IN 47 DOWNTO 0 GENERATE
362 all_bit_of_time_out : FOR I IN 47 DOWNTO 0 GENERATE
363 all_sample_of_time_out : FOR J IN 3 DOWNTO 0 GENERATE
363 all_sample_of_time_out : FOR J IN 3 DOWNTO 0 GENERATE
364 time_out_2(J, I) <= time_out(J)(I);
364 time_out_2(J, I) <= time_out(J)(I);
365 END GENERATE all_sample_of_time_out;
365 END GENERATE all_sample_of_time_out;
366 END GENERATE all_bit_of_time_out;
366 END GENERATE all_bit_of_time_out;
367
367
368 lpp_waveform_fifo_arbiter_1 : lpp_waveform_fifo_arbiter
368 lpp_waveform_fifo_arbiter_1 : lpp_waveform_fifo_arbiter
369 GENERIC MAP (tech => tech,
369 GENERIC MAP (tech => tech,
370 nb_data_by_buffer_size => nb_data_by_buffer_size)
370 nb_data_by_buffer_size => nb_data_by_buffer_size)
371 PORT MAP (
371 PORT MAP (
372 clk => clk,
372 clk => clk,
373 rstn => rstn,
373 rstn => rstn,
374 run => run,
374 run => run,
375 nb_data_by_buffer => nb_data_by_buffer,
375 nb_data_by_buffer => nb_data_by_buffer,
376 data_in_valid => valid_out,
376 data_in_valid => valid_out,
377 data_in_ack => valid_ack,
377 data_in_ack => valid_ack,
378 data_in => data_out,
378 data_in => data_out,
379 time_in => time_out_2,
379 time_in => time_out_2,
380
380
381 data_out => wdata,
381 data_out => wdata,
382 data_out_wen => data_wen,
382 data_out_wen => data_wen,
383 full_almost => full_almost,
383 full_almost => full_almost,
384 full => full,
384 full => full,
385
385
386 time_out => arbiter_time_out,
386 time_out => arbiter_time_out,
387 time_out_new => arbiter_time_out_new
387 time_out_new => arbiter_time_out_new
388
388
389 );
389 );
390
390
391 -----------------------------------------------------------------------------
391 -----------------------------------------------------------------------------
392 -----------------------------------------------------------------------------
392 -----------------------------------------------------------------------------
393
393
394 generate_all_fifo: FOR I IN 0 TO 3 GENERATE
394 generate_all_fifo: FOR I IN 0 TO 3 GENERATE
395 lpp_fifo_1: lpp_fifo
395 lpp_fifo_1: lpp_fifo
396 GENERIC MAP (
396 GENERIC MAP (
397 tech => tech,
397 tech => tech,
398 Mem_use => use_RAM,
398 Mem_use => use_RAM,
399 EMPTY_THRESHOLD_LIMIT => 15,
399 EMPTY_THRESHOLD_LIMIT => 15,
400 FULL_THRESHOLD_LIMIT => 3,
400 FULL_THRESHOLD_LIMIT => 3,
401 DataSz => 32,
401 DataSz => 32,
402 AddrSz => 7)
402 AddrSz => 7)
403 PORT MAP (
403 PORT MAP (
404 clk => clk,
404 clk => clk,
405 rstn => rstn,
405 rstn => rstn,
406 reUse => '0',
406 reUse => '0',
407 run => run,
407 run => run,
408 ren => data_ren(I),
408 ren => data_ren(I),
409 rdata => s_rdata_v((I+1)*32-1 downto I*32),
409 rdata => s_rdata_v((I+1)*32-1 downto I*32),
410 wen => data_wen(I),
410 wen => data_wen(I),
411 wdata => wdata,
411 wdata => wdata,
412 empty => empty(I),
412 empty => empty(I),
413 full => full(I),
413 full => full(I),
414 full_almost => OPEN,
414 full_almost => OPEN,
415 empty_threshold => empty_almost(I),
415 empty_threshold => empty_almost(I),
416 full_threshold => full_almost(I) );
416 full_threshold => full_almost(I) );
417
417
418 END GENERATE generate_all_fifo;
418 END GENERATE generate_all_fifo;
419
419
420 -----------------------------------------------------------------------------
420 -----------------------------------------------------------------------------
421 --
421 --
422 -----------------------------------------------------------------------------
422 -----------------------------------------------------------------------------
423
423
424 all_channel: FOR I IN 3 DOWNTO 0 GENERATE
424 all_channel: FOR I IN 3 DOWNTO 0 GENERATE
425
425
426 PROCESS (clk, rstn)
426 PROCESS (clk, rstn)
427 BEGIN
427 BEGIN
428 IF rstn = '0' THEN
428 IF rstn = '0' THEN
429 fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I) <= (OTHERS => '0');
429 fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I) <= (OTHERS => '0');
430 ELSIF clk'event AND clk = '1' THEN
430 ELSIF clk'event AND clk = '1' THEN
431 IF run = '0' THEN
431 IF run = '0' THEN
432 fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I) <= (OTHERS => '0');
432 fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I) <= (OTHERS => '0');
433 ELSE
433 ELSE
434 IF arbiter_time_out_new(I) = '1' THEN -- modif JC 15-01-2015
434 IF arbiter_time_out_new(I) = '1' THEN -- modif JC 15-01-2015
435 fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I) <= arbiter_time_out;
435 fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I) <= arbiter_time_out;
436 END IF;
436 END IF;
437 END IF;
437 END IF;
438 END IF;
438 END IF;
439 END PROCESS;
439 END PROCESS;
440
440
441 fifo_buffer_time_s(48*(I+1)-1 DOWNTO 48*I) <= arbiter_time_out WHEN arbiter_time_out_new(I) = '1' ELSE
441 fifo_buffer_time_s(48*(I+1)-1 DOWNTO 48*I) <= arbiter_time_out WHEN arbiter_time_out_new(I) = '1' ELSE
442 fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I);
442 fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I);
443
443
444 lpp_waveform_fsmdma_I: lpp_waveform_fsmdma
444 lpp_waveform_fsmdma_I: lpp_waveform_fsmdma
445 PORT MAP (
445 PORT MAP (
446 clk => clk,
446 clk => clk,
447 rstn => rstn,
447 rstn => rstn,
448 run => run,
448 run => run,
449
449
450 fifo_buffer_time => fifo_buffer_time_s(48*(I+1)-1 DOWNTO 48*I),
450 fifo_buffer_time => fifo_buffer_time_s(48*(I+1)-1 DOWNTO 48*I),
451
451
452 fifo_data => s_rdata_v(32*(I+1)-1 DOWNTO 32*I),
452 fifo_data => s_rdata_v(32*(I+1)-1 DOWNTO 32*I),
453 fifo_empty => empty(I),
453 fifo_empty => empty(I),
454 fifo_empty_threshold => empty_almost(I),
454 fifo_empty_threshold => empty_almost(I),
455 fifo_ren => data_ren(I),
455 fifo_ren => data_ren(I),
456
456
457 dma_fifo_valid_burst => dma_fifo_valid_burst(I),
457 dma_fifo_valid_burst => dma_fifo_valid_burst(I),
458 dma_fifo_data => dma_fifo_data(32*(I+1)-1 DOWNTO 32*I),
458 dma_fifo_data => dma_fifo_data(32*(I+1)-1 DOWNTO 32*I),
459 dma_fifo_ren => dma_fifo_ren(I),
459 dma_fifo_ren => dma_fifo_ren(I),
460 dma_buffer_new => dma_buffer_new(I),
460 dma_buffer_new => dma_buffer_new(I),
461 dma_buffer_addr => dma_buffer_addr(32*(I+1)-1 DOWNTO 32*I),
461 dma_buffer_addr => dma_buffer_addr(32*(I+1)-1 DOWNTO 32*I),
462 dma_buffer_length => dma_buffer_length(26*(I+1)-1 DOWNTO 26*I),
462 dma_buffer_length => dma_buffer_length(26*(I+1)-1 DOWNTO 26*I),
463 dma_buffer_full => dma_buffer_full(I),
463 dma_buffer_full => dma_buffer_full(I),
464 dma_buffer_full_err => dma_buffer_full_err(I),
464 dma_buffer_full_err => dma_buffer_full_err(I),
465
465
466 status_buffer_ready => status_buffer_ready(I), -- TODO
466 status_buffer_ready => status_buffer_ready(I), -- TODO
467 addr_buffer => addr_buffer(32*(I+1)-1 DOWNTO 32*I), -- TODO
467 addr_buffer => addr_buffer(32*(I+1)-1 DOWNTO 32*I), -- TODO
468 length_buffer => length_buffer,--(26*(I+1)-1 DOWNTO 26*I), -- TODO
468 length_buffer => length_buffer,--(26*(I+1)-1 DOWNTO 26*I), -- TODO
469 ready_buffer => ready_buffer(I), -- TODO
469 ready_buffer => ready_buffer(I), -- TODO
470 buffer_time => buffer_time(48*(I+1)-1 DOWNTO 48*I), -- TODO
470 buffer_time => OPEN,--buffer_time(48*(I+1)-1 DOWNTO 48*I), -- TODO
471 error_buffer_full => error_buffer_full(I)); -- TODO
471 error_buffer_full => error_buffer_full(I)); -- TODO
472
473 buffer_time(48*(I+1)-1 DOWNTO 48*I) <= fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I);
472
474
473 END GENERATE all_channel;
475 END GENERATE all_channel;
474
476
475
477
476 END beh;
478 END beh;
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