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1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
21 ----------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY lpp;
25 LIBRARY lpp;
26 USE lpp.iir_filter.ALL;
26 USE lpp.iir_filter.ALL;
27 USE lpp.FILTERcfg.ALL;
27 USE lpp.FILTERcfg.ALL;
28 USE lpp.general_purpose.ALL;
28 USE lpp.general_purpose.ALL;
29 LIBRARY techmap;
29 LIBRARY techmap;
30 USE techmap.gencomp.ALL;
30 USE techmap.gencomp.ALL;
31
31
32 ENTITY RAM_CTRLR_v2 IS
32 ENTITY RAM_CTRLR_v2 IS
33 GENERIC(
33 GENERIC(
34 tech : INTEGER := 0;
34 tech : INTEGER := 0;
35 Input_SZ_1 : INTEGER := 16;
35 Input_SZ_1 : INTEGER := 16;
36 Mem_use : INTEGER := use_RAM
36 Mem_use : INTEGER := use_RAM
37 );
37 );
38 PORT(
38 PORT(
39 rstn : IN STD_LOGIC;
39 rstn : IN STD_LOGIC;
40 clk : IN STD_LOGIC;
40 clk : IN STD_LOGIC;
41 -- R/W Ctrl
41 -- R/W Ctrl
42 ram_write : IN STD_LOGIC;
42 ram_write : IN STD_LOGIC;
43 ram_read : IN STD_LOGIC;
43 ram_read : IN STD_LOGIC;
44 -- ADDR Ctrl
44 -- ADDR Ctrl
45 raddr_rst : IN STD_LOGIC;
45 raddr_rst : IN STD_LOGIC;
46 raddr_add1 : IN STD_LOGIC;
46 raddr_add1 : IN STD_LOGIC;
47 waddr_previous : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
47 waddr_previous : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
48 -- Data
48 -- Data
49 sample_in : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
49 sample_in : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
50 sample_out : OUT STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0)
50 sample_out : OUT STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0)
51 );
51 );
52 END RAM_CTRLR_v2;
52 END RAM_CTRLR_v2;
53
53
54
54
55 ARCHITECTURE ar_RAM_CTRLR_v2 OF RAM_CTRLR_v2 IS
55 ARCHITECTURE ar_RAM_CTRLR_v2 OF RAM_CTRLR_v2 IS
56
56
57 SIGNAL WD : STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
57 SIGNAL WD : STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
58 SIGNAL RD : STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
58 SIGNAL RD : STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
59 SIGNAL WEN, REN : STD_LOGIC;
59 SIGNAL WEN, REN : STD_LOGIC;
60 SIGNAL RADDR : STD_LOGIC_VECTOR(7 DOWNTO 0);
60 SIGNAL RADDR : STD_LOGIC_VECTOR(7 DOWNTO 0);
61 SIGNAL WADDR : STD_LOGIC_VECTOR(7 DOWNTO 0);
61 SIGNAL WADDR : STD_LOGIC_VECTOR(7 DOWNTO 0);
62 SIGNAL counter : STD_LOGIC_VECTOR(7 DOWNTO 0);
62 SIGNAL counter : STD_LOGIC_VECTOR(7 DOWNTO 0);
63
63
64 BEGIN
64 BEGIN
65
65
66 sample_out <= RD(Input_SZ_1-1 DOWNTO 0);
66 sample_out <= RD(Input_SZ_1-1 DOWNTO 0);
67 WD(Input_SZ_1-1 DOWNTO 0) <= sample_in;
67 WD(Input_SZ_1-1 DOWNTO 0) <= sample_in;
68 -----------------------------------------------------------------------------
68 -----------------------------------------------------------------------------
69 -- RAM
69 -- RAM
70 -----------------------------------------------------------------------------
70 -----------------------------------------------------------------------------
71
71
72 memCEL : IF Mem_use = use_CEL GENERATE
72 memCEL : IF Mem_use = use_CEL GENERATE
73 WEN <= NOT ram_write;
73 WEN <= NOT ram_write;
74 REN <= NOT ram_read;
74 REN <= NOT ram_read;
75 -- RAMblk : RAM_CEL_N
75 -- RAMblk : RAM_CEL_N
76 RAMblk : RAM_CEL_N
76 RAMblk : RAM_CEL_N
77 GENERIC MAP(Input_SZ_1)
77 GENERIC MAP(Input_SZ_1)
78 PORT MAP(
78 PORT MAP(
79 WD => WD,
79 WD => WD,
80 RD => RD,
80 RD => RD,
81 WEN => WEN,
81 WEN => WEN,
82 REN => REN,
82 REN => REN,
83 WADDR => WADDR,
83 WADDR => WADDR,
84 RADDR => RADDR,
84 RADDR => RADDR,
85 RWCLK => clk,
85 RWCLK => clk,
86 RESET => rstn
86 RESET => rstn
87 ) ;
87 ) ;
88 END GENERATE;
88 END GENERATE;
89
89
90 memRAM : IF Mem_use = use_RAM GENERATE
90 memRAM : IF Mem_use = use_RAM GENERATE
91 SRAM : syncram_2p
91 SRAM : syncram_2p
92 GENERIC MAP(tech, 8, Input_SZ_1)
92 GENERIC MAP(tech, 8, Input_SZ_1)
93 PORT MAP(clk, ram_read, RADDR, RD, clk, ram_write, WADDR, WD);
93 PORT MAP(clk, ram_read, RADDR, RD, clk, ram_write, WADDR, WD);
94 END GENERATE;
94 END GENERATE;
95
95
96 -----------------------------------------------------------------------------
96 -----------------------------------------------------------------------------
97 -- RADDR
97 -- RADDR
98 -----------------------------------------------------------------------------
98 -----------------------------------------------------------------------------
99 PROCESS (clk, rstn)
99 PROCESS (clk, rstn)
100 BEGIN -- PROCESS
100 BEGIN -- PROCESS
101 IF rstn = '0' THEN -- asynchronous reset (active low)
101 IF rstn = '0' THEN -- asynchronous reset (active low)
102 counter <= (OTHERS => '0');
102 counter <= (OTHERS => '0');
103 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
103 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
104 IF raddr_rst = '1' THEN
104 IF raddr_rst = '1' THEN
105 counter <= (OTHERS => '0');
105 counter <= (OTHERS => '0');
106 ELSIF raddr_add1 = '1' THEN
106 ELSIF raddr_add1 = '1' THEN
107 counter <= STD_LOGIC_VECTOR(UNSIGNED(counter)+1);
107 counter <= STD_LOGIC_VECTOR(UNSIGNED(counter)+1);
108 END IF;
108 END IF;
109 END IF;
109 END IF;
110 END PROCESS;
110 END PROCESS;
111 RADDR <= counter;
111 RADDR <= counter;
112
112
113 -----------------------------------------------------------------------------
113 -----------------------------------------------------------------------------
114 -- WADDR
114 -- WADDR
115 -----------------------------------------------------------------------------
115 -----------------------------------------------------------------------------
116 WADDR <= STD_LOGIC_VECTOR(UNSIGNED(counter)-2) WHEN waddr_previous = "10" ELSE
116 WADDR <= STD_LOGIC_VECTOR(UNSIGNED(counter)-2) WHEN waddr_previous = "10" ELSE
117 STD_LOGIC_VECTOR(UNSIGNED(counter)-1) WHEN waddr_previous = "01" ELSE
117 STD_LOGIC_VECTOR(UNSIGNED(counter)-1) WHEN waddr_previous = "01" ELSE
118 STD_LOGIC_VECTOR(UNSIGNED(counter));
118 STD_LOGIC_VECTOR(UNSIGNED(counter));
119
119
120
120
121 END ar_RAM_CTRLR_v2;
121 END ar_RAM_CTRLR_v2; No newline at end of file
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1 ----------------------------------------------------------------------------------
1 ----------------------------------------------------------------------------------
2 -- Company:
2 -- Company:
3 -- Engineer:
3 -- Engineer:
4 --
4 --
5 -- Create Date: 11:17:05 07/02/2012
5 -- Create Date: 11:17:05 07/02/2012
6 -- Design Name:
6 -- Design Name:
7 -- Module Name: apb_lfr_time_management - Behavioral
7 -- Module Name: apb_lfr_time_management - Behavioral
8 -- Project Name:
8 -- Project Name:
9 -- Target Devices:
9 -- Target Devices:
10 -- Tool versions:
10 -- Tool versions:
11 -- Description:
11 -- Description:
12 --
12 --
13 -- Dependencies:
13 -- Dependencies:
14 --
14 --
15 -- Revision:
15 -- Revision:
16 -- Revision 0.01 - File Created
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
17 -- Additional Comments:
18 --
18 --
19 ----------------------------------------------------------------------------------
19 ----------------------------------------------------------------------------------
20 LIBRARY IEEE;
20 LIBRARY IEEE;
21 USE IEEE.STD_LOGIC_1164.ALL;
21 USE IEEE.STD_LOGIC_1164.ALL;
22 USE IEEE.NUMERIC_STD.ALL;
22 USE IEEE.NUMERIC_STD.ALL;
23 LIBRARY grlib;
23 LIBRARY grlib;
24 USE grlib.amba.ALL;
24 USE grlib.amba.ALL;
25 USE grlib.stdlib.ALL;
25 USE grlib.stdlib.ALL;
26 USE grlib.devices.ALL;
26 USE grlib.devices.ALL;
27 LIBRARY lpp;
27 LIBRARY lpp;
28 USE lpp.apb_devices_list.ALL;
28 USE lpp.apb_devices_list.ALL;
29 USE lpp.lpp_lfr_time_management.ALL;
29 USE lpp.lpp_lfr_time_management.ALL;
30
30
31 ENTITY apb_lfr_time_management IS
31 ENTITY apb_lfr_time_management IS
32
32
33 GENERIC(
33 GENERIC(
34 pindex : INTEGER := 0; --! APB slave index
34 pindex : INTEGER := 0; --! APB slave index
35 paddr : INTEGER := 0; --! ADDR field of the APB BAR
35 paddr : INTEGER := 0; --! ADDR field of the APB BAR
36 pmask : INTEGER := 16#fff#; --! MASK field of the APB BAR
36 pmask : INTEGER := 16#fff#; --! MASK field of the APB BAR
37 pirq : INTEGER := 0; --! 2 consecutive IRQ lines are used
37 pirq : INTEGER := 0; --! 2 consecutive IRQ lines are used
38 masterclk : INTEGER := 25000000; --! master clock in Hz
38 masterclk : INTEGER := 25000000; --! master clock in Hz
39 timeclk : INTEGER := 49152000; --! other clock in Hz
39 timeclk : INTEGER := 49152000; --! other clock in Hz
40 finetimeclk : INTEGER := 65536 --! divided clock used for the fine time counter
40 finetimeclk : INTEGER := 65536 --! divided clock used for the fine time counter
41 );
41 );
42
42
43 PORT (
43 PORT (
44 clk25MHz : IN STD_LOGIC; --! Clock
44 clk25MHz : IN STD_LOGIC; --! Clock
45 clk49_152MHz : IN STD_LOGIC; --! secondary clock
45 clk49_152MHz : IN STD_LOGIC; --! secondary clock
46 resetn : IN STD_LOGIC; --! Reset
46 resetn : IN STD_LOGIC; --! Reset
47 grspw_tick : IN STD_LOGIC; --! grspw signal asserted when a valid time-code is received
47 grspw_tick : IN STD_LOGIC; --! grspw signal asserted when a valid time-code is received
48 apbi : IN apb_slv_in_type; --! APB slave input signals
48 apbi : IN apb_slv_in_type; --! APB slave input signals
49 apbo : OUT apb_slv_out_type; --! APB slave output signals
49 apbo : OUT apb_slv_out_type; --! APB slave output signals
50 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time
50 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time
51 fine_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) --! fine time
51 fine_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) --! fine time
52 );
52 );
53
53
54 END apb_lfr_time_management;
54 END apb_lfr_time_management;
55
55
56 ARCHITECTURE Behavioral OF apb_lfr_time_management IS
56 ARCHITECTURE Behavioral OF apb_lfr_time_management IS
57
57
58 CONSTANT REVISION : INTEGER := 1;
58 CONSTANT REVISION : INTEGER := 1;
59
59
60 --! the following types are defined in the grlib amba package
60 --! the following types are defined in the grlib amba package
61 --! subtype amba_config_word is std_logic_vector(31 downto 0);
61 --! subtype amba_config_word is std_logic_vector(31 downto 0);
62 --! type apb_config_type is array (0 to NAPBCFG-1) of amba_config_word;
62 --! type apb_config_type is array (0 to NAPBCFG-1) of amba_config_word;
63 CONSTANT pconfig : apb_config_type := (
63 CONSTANT pconfig : apb_config_type := (
64 --! 0 => ahb_device_reg (VENDOR_LPP, LPP_ROTARY, 0, REVISION, 0),
64 --! 0 => ahb_device_reg (VENDOR_LPP, LPP_ROTARY, 0, REVISION, 0),
65 0 => ahb_device_reg (VENDOR_LPP, 14, 0, REVISION, pirq),
65 0 => ahb_device_reg (VENDOR_LPP, 14, 0, REVISION, pirq),
66 1 => apb_iobar(paddr, pmask));
66 1 => apb_iobar(paddr, pmask));
67
67
68 TYPE apb_lfr_time_management_Reg IS RECORD
68 TYPE apb_lfr_time_management_Reg IS RECORD
69 ctrl : STD_LOGIC_VECTOR(31 DOWNTO 0);
69 ctrl : STD_LOGIC_VECTOR(31 DOWNTO 0);
70 coarse_time_load : STD_LOGIC_VECTOR(31 DOWNTO 0);
70 coarse_time_load : STD_LOGIC_VECTOR(31 DOWNTO 0);
71 coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
71 coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
72 fine_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
72 fine_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
73 next_commutation : STD_LOGIC_VECTOR(31 DOWNTO 0);
73 next_commutation : STD_LOGIC_VECTOR(31 DOWNTO 0);
74 END RECORD;
74 END RECORD;
75
75
76 SIGNAL r : apb_lfr_time_management_Reg;
76 SIGNAL r : apb_lfr_time_management_Reg;
77 SIGNAL Rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
77 SIGNAL Rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
78 SIGNAL force_tick : STD_LOGIC;
78 SIGNAL force_tick : STD_LOGIC;
79 SIGNAL previous_force_tick : STD_LOGIC;
79 SIGNAL previous_force_tick : STD_LOGIC;
80 SIGNAL soft_tick : STD_LOGIC;
80 SIGNAL soft_tick : STD_LOGIC;
81 SIGNAL reset_next_commutation : STD_LOGIC;
81 SIGNAL reset_next_commutation : STD_LOGIC;
82
82
83 SIGNAL irq1 : STD_LOGIC;
83 SIGNAL irq1 : STD_LOGIC;
84 SIGNAL irq2 : STD_LOGIC;
84 SIGNAL irq2 : STD_LOGIC;
85
85
86 BEGIN
86 BEGIN
87
87
88 lfrtimemanagement0 : lfr_time_management
88 lfrtimemanagement0 : lfr_time_management
89 GENERIC MAP(
89 GENERIC MAP(
90 masterclk => masterclk,
90 masterclk => masterclk,
91 timeclk => timeclk,
91 timeclk => timeclk,
92 finetimeclk => finetimeclk,
92 finetimeclk => finetimeclk,
93 nb_clk_div_ticks => 1)
93 nb_clk_div_ticks => 1)
94 PORT MAP(
94 PORT MAP(
95 master_clock => clk25MHz,
95 master_clock => clk25MHz,
96 time_clock => clk49_152MHz,
96 time_clock => clk49_152MHz,
97 resetn => resetn,
97 resetn => resetn,
98 grspw_tick => grspw_tick,
98 grspw_tick => grspw_tick,
99 soft_tick => soft_tick,
99 soft_tick => soft_tick,
100 coarse_time_load => r.coarse_time_load,
100 coarse_time_load => r.coarse_time_load,
101 coarse_time => r.coarse_time,
101 coarse_time => r.coarse_time,
102 fine_time => r.fine_time,
102 fine_time => r.fine_time,
103 next_commutation => r.next_commutation,
103 next_commutation => r.next_commutation,
104 reset_next_commutation => reset_next_commutation,
104 reset_next_commutation => reset_next_commutation,
105 irq1 => irq1,--apbo.pirq(pirq),
105 irq1 => irq1,--apbo.pirq(pirq),
106 irq2 => irq2);--apbo.pirq(pirq+1));
106 irq2 => irq2);--apbo.pirq(pirq+1));
107
107
108 --apbo.pirq <= (OTHERS => '0');
108 --apbo.pirq <= (OTHERS => '0');
109
109
110 all_irq_gen: FOR I IN 15 DOWNTO 0 GENERATE
110 all_irq_gen: FOR I IN 15 DOWNTO 0 GENERATE
111 irq1_gen: IF I = pirq GENERATE
111 irq1_gen: IF I = pirq GENERATE
112 apbo.pirq(I) <= irq1;
112 apbo.pirq(I) <= irq1;
113 END GENERATE irq1_gen;
113 END GENERATE irq1_gen;
114 irq2_gen: IF I = pirq+1 GENERATE
114 irq2_gen: IF I = pirq+1 GENERATE
115 apbo.pirq(I) <= irq2;
115 apbo.pirq(I) <= irq2;
116 END GENERATE irq2_gen;
116 END GENERATE irq2_gen;
117 others_irq: IF (I < pirq) OR (I > (pirq + 1)) GENERATE
117 others_irq: IF (I < pirq) OR (I > (pirq + 1)) GENERATE
118 apbo.pirq(I) <= '0';
118 apbo.pirq(I) <= '0';
119 END GENERATE others_irq;
119 END GENERATE others_irq;
120 END GENERATE all_irq_gen;
120 END GENERATE all_irq_gen;
121
121
122 --all_irq_sig: FOR I IN 31 DOWNTO 0 GENERATE
122 --all_irq_sig: FOR I IN 31 DOWNTO 0 GENERATE
123 --END GENERATE all_irq_sig;
123 --END GENERATE all_irq_sig;
124
124
125 PROCESS(resetn, clk25MHz, reset_next_commutation)
125 PROCESS(resetn, clk25MHz, reset_next_commutation)
126 BEGIN
126 BEGIN
127
127
128 IF resetn = '0' THEN
128 IF resetn = '0' THEN
129 Rdata <= (OTHERS => '0');
129 Rdata <= (OTHERS => '0');
130 r.coarse_time_load <= x"80000000";
130 r.coarse_time_load <= x"80000000";
131 r.ctrl <= x"00000000";
131 r.ctrl <= x"00000000";
132 r.next_commutation <= x"ffffffff";
132 r.next_commutation <= x"ffffffff";
133 force_tick <= '0';
133 force_tick <= '0';
134 previous_force_tick <= '0';
134 previous_force_tick <= '0';
135 soft_tick <= '0';
135 soft_tick <= '0';
136
136
137 ELSIF reset_next_commutation = '1' THEN
137 ELSIF reset_next_commutation = '1' THEN
138 r.next_commutation <= x"ffffffff";
138 r.next_commutation <= x"ffffffff";
139
139
140 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN
140 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN
141
141
142 previous_force_tick <= force_tick;
142 previous_force_tick <= force_tick;
143 force_tick <= r.ctrl(0);
143 force_tick <= r.ctrl(0);
144 IF (previous_force_tick = '0') AND (force_tick = '1') THEN
144 IF (previous_force_tick = '0') AND (force_tick = '1') THEN
145 soft_tick <= '1';
145 soft_tick <= '1';
146 ELSE
146 ELSE
147 soft_tick <= '0';
147 soft_tick <= '0';
148 END IF;
148 END IF;
149
149
150 --APB Write OP
150 --APB Write OP
151 IF (apbi.psel(pindex) AND apbi.penable AND apbi.pwrite) = '1' THEN
151 IF (apbi.psel(pindex) AND apbi.penable AND apbi.pwrite) = '1' THEN
152 CASE apbi.paddr(7 DOWNTO 2) IS
152 CASE apbi.paddr(7 DOWNTO 2) IS
153 WHEN "000000" =>
153 WHEN "000000" =>
154 r.ctrl <= apbi.pwdata(31 DOWNTO 0);
154 r.ctrl <= apbi.pwdata(31 DOWNTO 0);
155 WHEN "000001" =>
155 WHEN "000001" =>
156 r.coarse_time_load <= apbi.pwdata(31 DOWNTO 0);
156 r.coarse_time_load <= apbi.pwdata(31 DOWNTO 0);
157 WHEN "000100" =>
157 WHEN "000100" =>
158 r.next_commutation <= apbi.pwdata(31 DOWNTO 0);
158 r.next_commutation <= apbi.pwdata(31 DOWNTO 0);
159 WHEN OTHERS =>
159 WHEN OTHERS =>
160 r.coarse_time_load <= x"00000000";
160 r.coarse_time_load <= x"00000000";
161 END CASE;
161 END CASE;
162 ELSIF r.ctrl(0) = '1' THEN
162 ELSIF r.ctrl(0) = '1' THEN
163 r.ctrl(0) <= '0';
163 r.ctrl(0) <= '0';
164 END IF;
164 END IF;
165
165
166 --APB READ OP
166 --APB READ OP
167 IF (apbi.psel(pindex) AND (NOT apbi.pwrite)) = '1' THEN
167 IF (apbi.psel(pindex) AND (NOT apbi.pwrite)) = '1' THEN
168 CASE apbi.paddr(7 DOWNTO 2) IS
168 CASE apbi.paddr(7 DOWNTO 2) IS
169 WHEN "000000" =>
169 WHEN "000000" =>
170 Rdata(31 DOWNTO 24) <= r.ctrl(31 DOWNTO 24);
170 Rdata(31 DOWNTO 24) <= r.ctrl(31 DOWNTO 24);
171 Rdata(23 DOWNTO 16) <= r.ctrl(23 DOWNTO 16);
171 Rdata(23 DOWNTO 16) <= r.ctrl(23 DOWNTO 16);
172 Rdata(15 DOWNTO 8) <= r.ctrl(15 DOWNTO 8);
172 Rdata(15 DOWNTO 8) <= r.ctrl(15 DOWNTO 8);
173 Rdata(7 DOWNTO 0) <= r.ctrl(7 DOWNTO 0);
173 Rdata(7 DOWNTO 0) <= r.ctrl(7 DOWNTO 0);
174 WHEN "000001" =>
174 WHEN "000001" =>
175 Rdata(31 DOWNTO 24) <= r.coarse_time_load(31 DOWNTO 24);
175 Rdata(31 DOWNTO 24) <= r.coarse_time_load(31 DOWNTO 24);
176 Rdata(23 DOWNTO 16) <= r.coarse_time_load(23 DOWNTO 16);
176 Rdata(23 DOWNTO 16) <= r.coarse_time_load(23 DOWNTO 16);
177 Rdata(15 DOWNTO 8) <= r.coarse_time_load(15 DOWNTO 8);
177 Rdata(15 DOWNTO 8) <= r.coarse_time_load(15 DOWNTO 8);
178 Rdata(7 DOWNTO 0) <= r.coarse_time_load(7 DOWNTO 0);
178 Rdata(7 DOWNTO 0) <= r.coarse_time_load(7 DOWNTO 0);
179 WHEN "000010" =>
179 WHEN "000010" =>
180 Rdata(31 DOWNTO 24) <= r.coarse_time(31 DOWNTO 24);
180 Rdata(31 DOWNTO 24) <= r.coarse_time(31 DOWNTO 24);
181 Rdata(23 DOWNTO 16) <= r.coarse_time(23 DOWNTO 16);
181 Rdata(23 DOWNTO 16) <= r.coarse_time(23 DOWNTO 16);
182 Rdata(15 DOWNTO 8) <= r.coarse_time(15 DOWNTO 8);
182 Rdata(15 DOWNTO 8) <= r.coarse_time(15 DOWNTO 8);
183 Rdata(7 DOWNTO 0) <= r.coarse_time(7 DOWNTO 0);
183 Rdata(7 DOWNTO 0) <= r.coarse_time(7 DOWNTO 0);
184 WHEN "000011" =>
184 WHEN "000011" =>
185 Rdata(31 DOWNTO 24) <= r.fine_time(31 DOWNTO 24);
185 Rdata(31 DOWNTO 24) <= r.fine_time(31 DOWNTO 24);
186 Rdata(23 DOWNTO 16) <= r.fine_time(23 DOWNTO 16);
186 Rdata(23 DOWNTO 16) <= r.fine_time(23 DOWNTO 16);
187 Rdata(15 DOWNTO 8) <= r.fine_time(15 DOWNTO 8);
187 Rdata(15 DOWNTO 8) <= r.fine_time(15 DOWNTO 8);
188 Rdata(7 DOWNTO 0) <= r.fine_time(7 DOWNTO 0);
188 Rdata(7 DOWNTO 0) <= r.fine_time(7 DOWNTO 0);
189 WHEN "000100" =>
189 WHEN "000100" =>
190 Rdata(31 DOWNTO 24) <= r.next_commutation(31 DOWNTO 24);
190 Rdata(31 DOWNTO 24) <= r.next_commutation(31 DOWNTO 24);
191 Rdata(23 DOWNTO 16) <= r.next_commutation(23 DOWNTO 16);
191 Rdata(23 DOWNTO 16) <= r.next_commutation(23 DOWNTO 16);
192 Rdata(15 DOWNTO 8) <= r.next_commutation(15 DOWNTO 8);
192 Rdata(15 DOWNTO 8) <= r.next_commutation(15 DOWNTO 8);
193 Rdata(7 DOWNTO 0) <= r.next_commutation(7 DOWNTO 0);
193 Rdata(7 DOWNTO 0) <= r.next_commutation(7 DOWNTO 0);
194 WHEN OTHERS =>
194 WHEN OTHERS =>
195 Rdata(31 DOWNTO 0) <= x"00000000";
195 Rdata(31 DOWNTO 0) <= x"00000000";
196 END CASE;
196 END CASE;
197 END IF;
197 END IF;
198
198
199 END IF;
199 END IF;
200 END PROCESS;
200 END PROCESS;
201
201
202 apbo.prdata <= Rdata ;--WHEN apbi.penable = '1';
202 apbo.prdata <= Rdata ;--WHEN apbi.penable = '1';
203 coarse_time <= r.coarse_time;
203 coarse_time <= r.coarse_time;
204 fine_time <= r.fine_time;
204 fine_time <= r.fine_time;
205 apbo.pconfig <= pconfig;
205 apbo.pconfig <= pconfig;
206 apbo.pindex <= pindex;
206 apbo.pindex <= pindex;
207
207
208 END Behavioral;
208 END Behavioral; No newline at end of file
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@@ -1,197 +1,196
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 -- MODIFIED by Jean-christophe PELLION
22 -- MODIFIED by Jean-christophe PELLION
23 -- jean-christophe.pellion@lpp.polytechnique.fr
23 -- jean-christophe.pellion@lpp.polytechnique.fr
24 -------------------------------------------------------------------------------
24 -------------------------------------------------------------------------------
25 LIBRARY IEEE;
25 LIBRARY IEEE;
26 USE IEEE.STD_LOGIC_1164.ALL;
26 USE IEEE.STD_LOGIC_1164.ALL;
27 LIBRARY lpp;
27 LIBRARY lpp;
28 USE lpp.lpp_ad_conv.ALL;
28 USE lpp.lpp_ad_conv.ALL;
29 USE lpp.general_purpose.SYNC_FF;
29 USE lpp.general_purpose.SYNC_FF;
30
30
31 ENTITY AD7688_drvr IS
31 ENTITY AD7688_drvr IS
32 GENERIC(
32 GENERIC(
33 ChanelCount : INTEGER;
33 ChanelCount : INTEGER;
34 ncycle_cnv_high : INTEGER := 79;
34 ncycle_cnv_high : INTEGER := 79;
35 ncycle_cnv : INTEGER := 500);
35 ncycle_cnv : INTEGER := 500);
36 PORT (
36 PORT (
37 -- CONV --
37 -- CONV --
38 cnv_clk : IN STD_LOGIC;
38 cnv_clk : IN STD_LOGIC;
39 cnv_rstn : IN STD_LOGIC;
39 cnv_rstn : IN STD_LOGIC;
40 cnv_run : IN STD_LOGIC;
40 cnv_run : IN STD_LOGIC;
41 cnv : OUT STD_LOGIC;
41 cnv : OUT STD_LOGIC;
42
42
43 -- DATA --
43 -- DATA --
44 clk : IN STD_LOGIC;
44 clk : IN STD_LOGIC;
45 rstn : IN STD_LOGIC;
45 rstn : IN STD_LOGIC;
46 sck : OUT STD_LOGIC;
46 sck : OUT STD_LOGIC;
47 sdo : IN STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
47 sdo : IN STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
48
48
49 sample : OUT Samples(ChanelCount-1 DOWNTO 0);
49 sample : OUT Samples(ChanelCount-1 DOWNTO 0);
50 sample_val : OUT STD_LOGIC
50 sample_val : OUT STD_LOGIC
51 );
51 );
52 END AD7688_drvr;
52 END AD7688_drvr;
53
53
54 ARCHITECTURE ar_AD7688_drvr OF AD7688_drvr IS
54 ARCHITECTURE ar_AD7688_drvr OF AD7688_drvr IS
55
55
56 COMPONENT SYNC_FF
56 COMPONENT SYNC_FF
57 GENERIC (
57 GENERIC (
58 NB_FF_OF_SYNC : INTEGER);
58 NB_FF_OF_SYNC : INTEGER);
59 PORT (
59 PORT (
60 clk : IN STD_LOGIC;
60 clk : IN STD_LOGIC;
61 rstn : IN STD_LOGIC;
61 rstn : IN STD_LOGIC;
62 A : IN STD_LOGIC;
62 A : IN STD_LOGIC;
63 A_sync : OUT STD_LOGIC);
63 A_sync : OUT STD_LOGIC);
64 END COMPONENT;
64 END COMPONENT;
65
65
66
66
67 SIGNAL cnv_cycle_counter : INTEGER;
67 SIGNAL cnv_cycle_counter : INTEGER;
68 SIGNAL cnv_s : STD_LOGIC;
68 SIGNAL cnv_s : STD_LOGIC;
69 SIGNAL cnv_sync : STD_LOGIC;
69 SIGNAL cnv_sync : STD_LOGIC;
70 SIGNAL cnv_sync_r : STD_LOGIC;
70 SIGNAL cnv_sync_r : STD_LOGIC;
71 SIGNAL cnv_done : STD_LOGIC;
71 SIGNAL cnv_done : STD_LOGIC;
72 SIGNAL sample_bit_counter : INTEGER;
72 SIGNAL sample_bit_counter : INTEGER;
73 SIGNAL shift_reg : Samples(ChanelCount-1 DOWNTO 0);
73 SIGNAL shift_reg : Samples(ChanelCount-1 DOWNTO 0);
74
74
75 SIGNAL cnv_run_sync : STD_LOGIC;
75 SIGNAL cnv_run_sync : STD_LOGIC;
76
76
77 BEGIN
77 BEGIN
78 -----------------------------------------------------------------------------
78 -----------------------------------------------------------------------------
79 -- CONV
79 -- CONV
80 -----------------------------------------------------------------------------
80 -----------------------------------------------------------------------------
81 PROCESS (cnv_clk, cnv_rstn)
81 PROCESS (cnv_clk, cnv_rstn)
82 BEGIN -- PROCESS
82 BEGIN -- PROCESS
83 IF cnv_rstn = '0' THEN -- asynchronous reset (active low)
83 IF cnv_rstn = '0' THEN -- asynchronous reset (active low)
84 cnv_cycle_counter <= 0;
84 cnv_cycle_counter <= 0;
85 cnv_s <= '0';
85 cnv_s <= '0';
86 ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge
86 ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge
87 IF cnv_run = '1' THEN
87 IF cnv_run = '1' THEN
88 IF cnv_cycle_counter < ncycle_cnv THEN
88 IF cnv_cycle_counter < ncycle_cnv THEN
89 cnv_cycle_counter <= cnv_cycle_counter +1;
89 cnv_cycle_counter <= cnv_cycle_counter +1;
90 IF cnv_cycle_counter < ncycle_cnv_high THEN
90 IF cnv_cycle_counter < ncycle_cnv_high THEN
91 cnv_s <= '1';
91 cnv_s <= '1';
92 ELSE
92 ELSE
93 cnv_s <= '0';
93 cnv_s <= '0';
94 END IF;
94 END IF;
95 ELSE
95 ELSE
96 cnv_s <= '1';
96 cnv_s <= '1';
97 cnv_cycle_counter <= 0;
97 cnv_cycle_counter <= 0;
98 END IF;
98 END IF;
99 ELSE
99 ELSE
100 cnv_s <= '0';
100 cnv_s <= '0';
101 cnv_cycle_counter <= 0;
101 cnv_cycle_counter <= 0;
102 END IF;
102 END IF;
103 END IF;
103 END IF;
104 END PROCESS;
104 END PROCESS;
105
105
106 cnv <= cnv_s;
106 cnv <= cnv_s;
107
107
108 -----------------------------------------------------------------------------
108 -----------------------------------------------------------------------------
109
109
110
110
111 -----------------------------------------------------------------------------
111 -----------------------------------------------------------------------------
112 -- SYNC CNV
112 -- SYNC CNV
113 -----------------------------------------------------------------------------
113 -----------------------------------------------------------------------------
114
114
115 SYNC_FF_cnv : SYNC_FF
115 SYNC_FF_cnv : SYNC_FF
116 GENERIC MAP (
116 GENERIC MAP (
117 NB_FF_OF_SYNC => 2)
117 NB_FF_OF_SYNC => 2)
118 PORT MAP (
118 PORT MAP (
119 clk => clk,
119 clk => clk,
120 rstn => rstn,
120 rstn => rstn,
121 A => cnv_s,
121 A => cnv_s,
122 A_sync => cnv_sync);
122 A_sync => cnv_sync);
123
123
124 PROCESS (clk, rstn)
124 PROCESS (clk, rstn)
125 BEGIN
125 BEGIN
126 IF rstn = '0' THEN
126 IF rstn = '0' THEN
127 cnv_sync_r <= '0';
127 cnv_sync_r <= '0';
128 cnv_done <= '0';
128 cnv_done <= '0';
129 ELSIF clk'EVENT AND clk = '1' THEN
129 ELSIF clk'EVENT AND clk = '1' THEN
130 cnv_sync_r <= cnv_sync;
130 cnv_sync_r <= cnv_sync;
131 cnv_done <= (NOT cnv_sync) AND cnv_sync_r;
131 cnv_done <= (NOT cnv_sync) AND cnv_sync_r;
132 END IF;
132 END IF;
133 END PROCESS;
133 END PROCESS;
134
134
135 -----------------------------------------------------------------------------
135 -----------------------------------------------------------------------------
136
136
137 SYNC_FF_run : SYNC_FF
137 SYNC_FF_run : SYNC_FF
138 GENERIC MAP (
138 GENERIC MAP (
139 NB_FF_OF_SYNC => 2)
139 NB_FF_OF_SYNC => 2)
140 PORT MAP (
140 PORT MAP (
141 clk => clk,
141 clk => clk,
142 rstn => rstn,
142 rstn => rstn,
143 A => cnv_run,
143 A => cnv_run,
144 A_sync => cnv_run_sync);
144 A_sync => cnv_run_sync);
145
145
146
146
147
147
148 -----------------------------------------------------------------------------
148 -----------------------------------------------------------------------------
149 -- DATA
149 -- DATA
150 -----------------------------------------------------------------------------
150 -----------------------------------------------------------------------------
151 PROCESS (clk, rstn)
151 PROCESS (clk, rstn)
152 BEGIN -- PROCESS
152 BEGIN -- PROCESS
153 IF rstn = '0' THEN
153 IF rstn = '0' THEN
154 FOR l IN 0 TO ChanelCount-1 LOOP
154 FOR l IN 0 TO ChanelCount-1 LOOP
155 shift_reg(l) <= (OTHERS => '0');
155 shift_reg(l) <= (OTHERS => '0');
156 END LOOP;
156 END LOOP;
157 sample_bit_counter <= 0;
157 sample_bit_counter <= 0;
158 sample_val <= '0';
158 sample_val <= '0';
159 SCK <= '1';
159 SCK <= '1';
160 ELSIF clk'EVENT AND clk = '1' THEN
160 ELSIF clk'EVENT AND clk = '1' THEN
161
161
162 IF cnv_run_sync = '0' THEN
162 IF cnv_run_sync = '0' THEN
163 sample_bit_counter <= 0;
163 sample_bit_counter <= 0;
164 ELSIF cnv_done = '1' THEN
164 ELSIF cnv_done = '1' THEN
165 sample_bit_counter <= 1;
165 sample_bit_counter <= 1;
166 ELSIF sample_bit_counter > 0 AND sample_bit_counter < 32 THEN
166 ELSIF sample_bit_counter > 0 AND sample_bit_counter < 32 THEN
167 sample_bit_counter <= sample_bit_counter + 1;
167 sample_bit_counter <= sample_bit_counter + 1;
168 END IF;
168 END IF;
169
169
170 IF (sample_bit_counter MOD 2) = 1 THEN
170 IF (sample_bit_counter MOD 2) = 1 THEN
171 FOR l IN 0 TO ChanelCount-1 LOOP
171 FOR l IN 0 TO ChanelCount-1 LOOP
172 --shift_reg(l)(15) <= sdo(l);
172 --shift_reg(l)(15) <= sdo(l);
173 --shift_reg(l)(14 DOWNTO 0) <= shift_reg(l)(15 DOWNTO 1);
173 --shift_reg(l)(14 DOWNTO 0) <= shift_reg(l)(15 DOWNTO 1);
174 shift_reg(l)(0) <= sdo(l);
174 shift_reg(l)(0) <= sdo(l);
175 shift_reg(l)(15 DOWNTO 1) <= shift_reg(l)(14 DOWNTO 0);
175 shift_reg(l)(14 DOWNTO 1) <= shift_reg(l)(13 DOWNTO 0);
176 END LOOP;
176 END LOOP;
177 SCK <= '0';
177 SCK <= '0';
178 ELSE
178 ELSE
179 SCK <= '1';
179 SCK <= '1';
180 END IF;
180 END IF;
181
181
182 IF sample_bit_counter = 31 THEN
182 IF sample_bit_counter = 31 THEN
183 sample_val <= '1';
183 sample_val <= '1';
184 FOR l IN 0 TO ChanelCount-1 LOOP
184 FOR l IN 0 TO ChanelCount-1 LOOP
185 --sample(l)(15) <= sdo(l);
185 --sample(l)(15) <= sdo(l);
186 --sample(l)(14 DOWNTO 0) <= shift_reg(l)(15 DOWNTO 1);
186 --sample(l)(14 DOWNTO 0) <= shift_reg(l)(15 DOWNTO 1);
187 sample(l)(0) <= sdo(l);
187 sample(l)(0) <= sdo(l);
188 sample(l)(15 DOWNTO 1) <= shift_reg(l)(14 DOWNTO 0);
188 sample(l)(15 DOWNTO 1) <= shift_reg(l)(14 DOWNTO 0);
189 END LOOP;
189 END LOOP;
190 ELSE
190 ELSE
191 sample_val <= '0';
191 sample_val <= '0';
192 END IF;
192 END IF;
193 END IF;
193 END IF;
194 END PROCESS;
194 END PROCESS;
195
195
196 END ar_AD7688_drvr;
196 END ar_AD7688_drvr;
197
Show file before | Show file after | Hide comments
@@ -1,408 +1,408
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
22 ----------------------------------------------------------------------------
23 LIBRARY ieee;
23 LIBRARY ieee;
24 USE ieee.std_logic_1164.ALL;
24 USE ieee.std_logic_1164.ALL;
25 USE ieee.numeric_std.ALL;
25 USE ieee.numeric_std.ALL;
26 LIBRARY grlib;
26 LIBRARY grlib;
27 USE grlib.amba.ALL;
27 USE grlib.amba.ALL;
28 USE grlib.stdlib.ALL;
28 USE grlib.stdlib.ALL;
29 USE grlib.devices.ALL;
29 USE grlib.devices.ALL;
30 LIBRARY lpp;
30 LIBRARY lpp;
31 USE lpp.lpp_amba.ALL;
31 USE lpp.lpp_amba.ALL;
32 USE lpp.apb_devices_list.ALL;
32 USE lpp.apb_devices_list.ALL;
33 USE lpp.lpp_memory.ALL;
33 USE lpp.lpp_memory.ALL;
34 LIBRARY techmap;
34 LIBRARY techmap;
35 USE techmap.gencomp.ALL;
35 USE techmap.gencomp.ALL;
36
36
37 ENTITY lpp_top_apbreg IS
37 ENTITY lpp_top_apbreg IS
38 GENERIC (
38 GENERIC (
39 nb_burst_available_size : INTEGER := 11;
39 nb_burst_available_size : INTEGER := 11;
40 nb_snapshot_param_size : INTEGER := 11;
40 nb_snapshot_param_size : INTEGER := 11;
41 delta_snapshot_size : INTEGER := 16;
41 delta_snapshot_size : INTEGER := 16;
42 delta_f2_f0_size : INTEGER := 10;
42 delta_f2_f0_size : INTEGER := 10;
43 delta_f2_f1_size : INTEGER := 10;
43 delta_f2_f1_size : INTEGER := 10;
44
44
45 pindex : INTEGER := 4;
45 pindex : INTEGER := 4;
46 paddr : INTEGER := 4;
46 paddr : INTEGER := 4;
47 pmask : INTEGER := 16#fff#;
47 pmask : INTEGER := 16#fff#;
48 pirq : INTEGER := 0);
48 pirq : INTEGER := 0);
49 PORT (
49 PORT (
50 -- AMBA AHB system signals
50 -- AMBA AHB system signals
51 HCLK : IN STD_ULOGIC;
51 HCLK : IN STD_ULOGIC;
52 HRESETn : IN STD_ULOGIC;
52 HRESETn : IN STD_ULOGIC;
53
53
54 -- AMBA APB Slave Interface
54 -- AMBA APB Slave Interface
55 apbi : IN apb_slv_in_type;
55 apbi : IN apb_slv_in_type;
56 apbo : OUT apb_slv_out_type;
56 apbo : OUT apb_slv_out_type;
57
57
58 ---------------------------------------------------------------------------
58 ---------------------------------------------------------------------------
59 -- Spectral Matrix Reg
59 -- Spectral Matrix Reg
60 -- IN
60 -- IN
61 ready_matrix_f0_0 : IN STD_LOGIC;
61 ready_matrix_f0_0 : IN STD_LOGIC;
62 ready_matrix_f0_1 : IN STD_LOGIC;
62 ready_matrix_f0_1 : IN STD_LOGIC;
63 ready_matrix_f1 : IN STD_LOGIC;
63 ready_matrix_f1 : IN STD_LOGIC;
64 ready_matrix_f2 : IN STD_LOGIC;
64 ready_matrix_f2 : IN STD_LOGIC;
65 error_anticipating_empty_fifo : IN STD_LOGIC;
65 error_anticipating_empty_fifo : IN STD_LOGIC;
66 error_bad_component_error : IN STD_LOGIC;
66 error_bad_component_error : IN STD_LOGIC;
67 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
67 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
68
68
69 -- OUT
69 -- OUT
70 status_ready_matrix_f0_0 : OUT STD_LOGIC;
70 status_ready_matrix_f0_0 : OUT STD_LOGIC;
71 status_ready_matrix_f0_1 : OUT STD_LOGIC;
71 status_ready_matrix_f0_1 : OUT STD_LOGIC;
72 status_ready_matrix_f1 : OUT STD_LOGIC;
72 status_ready_matrix_f1 : OUT STD_LOGIC;
73 status_ready_matrix_f2 : OUT STD_LOGIC;
73 status_ready_matrix_f2 : OUT STD_LOGIC;
74 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
74 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
75 status_error_bad_component_error : OUT STD_LOGIC;
75 status_error_bad_component_error : OUT STD_LOGIC;
76
76
77 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
77 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
78 config_active_interruption_onError : OUT STD_LOGIC;
78 config_active_interruption_onError : OUT STD_LOGIC;
79 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
79 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
80 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
80 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
81 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
81 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
82 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
82 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
83 ---------------------------------------------------------------------------
83 ---------------------------------------------------------------------------
84 ---------------------------------------------------------------------------
84 ---------------------------------------------------------------------------
85 -- WaveForm picker Reg
85 -- WaveForm picker Reg
86 status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
86 status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
87 status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
87 status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
88 status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
88 status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
89 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
89 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
90
90
91 -- OUT
91 -- OUT
92 data_shaping_BW : OUT STD_LOGIC;
92 data_shaping_BW : OUT STD_LOGIC;
93 data_shaping_SP0 : OUT STD_LOGIC;
93 data_shaping_SP0 : OUT STD_LOGIC;
94 data_shaping_SP1 : OUT STD_LOGIC;
94 data_shaping_SP1 : OUT STD_LOGIC;
95 data_shaping_R0 : OUT STD_LOGIC;
95 data_shaping_R0 : OUT STD_LOGIC;
96 data_shaping_R1 : OUT STD_LOGIC;
96 data_shaping_R1 : OUT STD_LOGIC;
97
97
98 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
98 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
99 delta_f2_f1 : OUT STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
99 delta_f2_f1 : OUT STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
100 delta_f2_f0 : OUT STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
100 delta_f2_f0 : OUT STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
101 nb_burst_available : OUT STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
101 nb_burst_available : OUT STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
102 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
102 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
103
103
104 enable_f0 : OUT STD_LOGIC;
104 enable_f0 : OUT STD_LOGIC;
105 enable_f1 : OUT STD_LOGIC;
105 enable_f1 : OUT STD_LOGIC;
106 enable_f2 : OUT STD_LOGIC;
106 enable_f2 : OUT STD_LOGIC;
107 enable_f3 : OUT STD_LOGIC;
107 enable_f3 : OUT STD_LOGIC;
108
108
109 burst_f0 : OUT STD_LOGIC;
109 burst_f0 : OUT STD_LOGIC;
110 burst_f1 : OUT STD_LOGIC;
110 burst_f1 : OUT STD_LOGIC;
111 burst_f2 : OUT STD_LOGIC;
111 burst_f2 : OUT STD_LOGIC;
112
112
113 addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
113 addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
114 addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
114 addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
115 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
115 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
116 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
116 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
117
117
118 ---------------------------------------------------------------------------
118 ---------------------------------------------------------------------------
119 );
119 );
120
120
121 END lpp_top_apbreg;
121 END lpp_top_apbreg;
122
122
123 ARCHITECTURE beh OF lpp_top_apbreg IS
123 ARCHITECTURE beh OF lpp_top_apbreg IS
124
124
125 CONSTANT REVISION : INTEGER := 1;
125 CONSTANT REVISION : INTEGER := 1;
126
126
127 CONSTANT pconfig : apb_config_type := (
127 CONSTANT pconfig : apb_config_type := (
128 0 => ahb_device_reg (VENDOR_LPP, LPP_DMA_TYPE, 10, REVISION, pirq),
128 0 => ahb_device_reg (VENDOR_LPP, LPP_DMA_TYPE, 10, REVISION, pirq),
129 1 => apb_iobar(paddr, pmask));
129 1 => apb_iobar(paddr, pmask));
130
130
131 TYPE lpp_SpectralMatrix_regs IS RECORD
131 TYPE lpp_SpectralMatrix_regs IS RECORD
132 config_active_interruption_onNewMatrix : STD_LOGIC;
132 config_active_interruption_onNewMatrix : STD_LOGIC;
133 config_active_interruption_onError : STD_LOGIC;
133 config_active_interruption_onError : STD_LOGIC;
134 status_ready_matrix_f0_0 : STD_LOGIC;
134 status_ready_matrix_f0_0 : STD_LOGIC;
135 status_ready_matrix_f0_1 : STD_LOGIC;
135 status_ready_matrix_f0_1 : STD_LOGIC;
136 status_ready_matrix_f1 : STD_LOGIC;
136 status_ready_matrix_f1 : STD_LOGIC;
137 status_ready_matrix_f2 : STD_LOGIC;
137 status_ready_matrix_f2 : STD_LOGIC;
138 status_error_anticipating_empty_fifo : STD_LOGIC;
138 status_error_anticipating_empty_fifo : STD_LOGIC;
139 status_error_bad_component_error : STD_LOGIC;
139 status_error_bad_component_error : STD_LOGIC;
140 addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
140 addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
141 addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
141 addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
142 addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
142 addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
143 addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
143 addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
144 END RECORD;
144 END RECORD;
145 SIGNAL reg_sp : lpp_SpectralMatrix_regs;
145 SIGNAL reg_sp : lpp_SpectralMatrix_regs;
146
146
147 TYPE lpp_WaveformPicker_regs IS RECORD
147 TYPE lpp_WaveformPicker_regs IS RECORD
148 status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
148 status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
149 status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
149 status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
150 status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
150 status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
151 data_shaping_BW : STD_LOGIC;
151 data_shaping_BW : STD_LOGIC;
152 data_shaping_SP0 : STD_LOGIC;
152 data_shaping_SP0 : STD_LOGIC;
153 data_shaping_SP1 : STD_LOGIC;
153 data_shaping_SP1 : STD_LOGIC;
154 data_shaping_R0 : STD_LOGIC;
154 data_shaping_R0 : STD_LOGIC;
155 data_shaping_R1 : STD_LOGIC;
155 data_shaping_R1 : STD_LOGIC;
156 delta_snapshot : STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
156 delta_snapshot : STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
157 delta_f2_f1 : STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
157 delta_f2_f1 : STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
158 delta_f2_f0 : STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
158 delta_f2_f0 : STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
159 nb_burst_available : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
159 nb_burst_available : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
160 nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
160 nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
161 enable_f0 : STD_LOGIC;
161 enable_f0 : STD_LOGIC;
162 enable_f1 : STD_LOGIC;
162 enable_f1 : STD_LOGIC;
163 enable_f2 : STD_LOGIC;
163 enable_f2 : STD_LOGIC;
164 enable_f3 : STD_LOGIC;
164 enable_f3 : STD_LOGIC;
165 burst_f0 : STD_LOGIC;
165 burst_f0 : STD_LOGIC;
166 burst_f1 : STD_LOGIC;
166 burst_f1 : STD_LOGIC;
167 burst_f2 : STD_LOGIC;
167 burst_f2 : STD_LOGIC;
168 addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
168 addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
169 addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
169 addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
170 addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
170 addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
171 addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
171 addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
172 END RECORD;
172 END RECORD;
173 SIGNAL reg_wp : lpp_WaveformPicker_regs;
173 SIGNAL reg_wp : lpp_WaveformPicker_regs;
174
174
175 SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
175 SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
176
176
177 BEGIN -- beh
177 BEGIN -- beh
178
178
179 status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0;
179 status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0;
180 status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1;
180 status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1;
181 status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1;
181 status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1;
182 status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2;
182 status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2;
183 status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo;
183 status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo;
184 status_error_bad_component_error <= reg_sp.status_error_bad_component_error;
184 status_error_bad_component_error <= reg_sp.status_error_bad_component_error;
185
185
186 config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix;
186 config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix;
187 config_active_interruption_onError <= reg_sp.config_active_interruption_onError;
187 config_active_interruption_onError <= reg_sp.config_active_interruption_onError;
188 addr_matrix_f0_0 <= reg_sp.addr_matrix_f0_0;
188 addr_matrix_f0_0 <= reg_sp.addr_matrix_f0_0;
189 addr_matrix_f0_1 <= reg_sp.addr_matrix_f0_1;
189 addr_matrix_f0_1 <= reg_sp.addr_matrix_f0_1;
190 addr_matrix_f1 <= reg_sp.addr_matrix_f1;
190 addr_matrix_f1 <= reg_sp.addr_matrix_f1;
191 addr_matrix_f2 <= reg_sp.addr_matrix_f2;
191 addr_matrix_f2 <= reg_sp.addr_matrix_f2;
192
192
193
193
194
194
195
195
196 data_shaping_BW <= reg_wp.data_shaping_BW;
196 data_shaping_BW <= reg_wp.data_shaping_BW;
197 data_shaping_SP0 <= reg_wp.data_shaping_SP0;
197 data_shaping_SP0 <= reg_wp.data_shaping_SP0;
198 data_shaping_SP1 <= reg_wp.data_shaping_SP1;
198 data_shaping_SP1 <= reg_wp.data_shaping_SP1;
199 data_shaping_R0 <= reg_wp.data_shaping_R0;
199 data_shaping_R0 <= reg_wp.data_shaping_R0;
200 data_shaping_R1 <= reg_wp.data_shaping_R1;
200 data_shaping_R1 <= reg_wp.data_shaping_R1;
201
201
202 delta_snapshot <= reg_wp.delta_snapshot;
202 delta_snapshot <= reg_wp.delta_snapshot;
203 delta_f2_f1 <= reg_wp.delta_f2_f1;
203 delta_f2_f1 <= reg_wp.delta_f2_f1;
204 delta_f2_f0 <= reg_wp.delta_f2_f0;
204 delta_f2_f0 <= reg_wp.delta_f2_f0;
205 nb_burst_available <= reg_wp.nb_burst_available;
205 nb_burst_available <= reg_wp.nb_burst_available;
206 nb_snapshot_param <= reg_wp.nb_snapshot_param;
206 nb_snapshot_param <= reg_wp.nb_snapshot_param;
207
207
208 enable_f0 <= reg_wp.enable_f0;
208 enable_f0 <= reg_wp.enable_f0;
209 enable_f1 <= reg_wp.enable_f1;
209 enable_f1 <= reg_wp.enable_f1;
210 enable_f2 <= reg_wp.enable_f2;
210 enable_f2 <= reg_wp.enable_f2;
211 enable_f3 <= reg_wp.enable_f3;
211 enable_f3 <= reg_wp.enable_f3;
212
212
213 burst_f0 <= reg_wp.burst_f0;
213 burst_f0 <= reg_wp.burst_f0;
214 burst_f1 <= reg_wp.burst_f1;
214 burst_f1 <= reg_wp.burst_f1;
215 burst_f2 <= reg_wp.burst_f2;
215 burst_f2 <= reg_wp.burst_f2;
216
216
217 addr_data_f0 <= reg_wp.addr_data_f0;
217 addr_data_f0 <= reg_wp.addr_data_f0;
218 addr_data_f1 <= reg_wp.addr_data_f1;
218 addr_data_f1 <= reg_wp.addr_data_f1;
219 addr_data_f2 <= reg_wp.addr_data_f2;
219 addr_data_f2 <= reg_wp.addr_data_f2;
220 addr_data_f3 <= reg_wp.addr_data_f3;
220 addr_data_f3 <= reg_wp.addr_data_f3;
221
221
222 lpp_top_apbreg : PROCESS (HCLK, HRESETn)
222 lpp_top_apbreg : PROCESS (HCLK, HRESETn)
223 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
223 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
224 BEGIN -- PROCESS lpp_dma_top
224 BEGIN -- PROCESS lpp_dma_top
225 IF HRESETn = '0' THEN -- asynchronous reset (active low)
225 IF HRESETn = '0' THEN -- asynchronous reset (active low)
226 reg_sp.config_active_interruption_onNewMatrix <= '0';
226 reg_sp.config_active_interruption_onNewMatrix <= '0';
227 reg_sp.config_active_interruption_onError <= '0';
227 reg_sp.config_active_interruption_onError <= '0';
228 reg_sp.status_ready_matrix_f0_0 <= '0';
228 reg_sp.status_ready_matrix_f0_0 <= '0';
229 reg_sp.status_ready_matrix_f0_1 <= '0';
229 reg_sp.status_ready_matrix_f0_1 <= '0';
230 reg_sp.status_ready_matrix_f1 <= '0';
230 reg_sp.status_ready_matrix_f1 <= '0';
231 reg_sp.status_ready_matrix_f2 <= '0';
231 reg_sp.status_ready_matrix_f2 <= '0';
232 reg_sp.status_error_anticipating_empty_fifo <= '0';
232 reg_sp.status_error_anticipating_empty_fifo <= '0';
233 reg_sp.status_error_bad_component_error <= '0';
233 reg_sp.status_error_bad_component_error <= '0';
234 reg_sp.addr_matrix_f0_0 <= (OTHERS => '0');
234 reg_sp.addr_matrix_f0_0 <= (OTHERS => '0');
235 reg_sp.addr_matrix_f0_1 <= (OTHERS => '0');
235 reg_sp.addr_matrix_f0_1 <= (OTHERS => '0');
236 reg_sp.addr_matrix_f1 <= (OTHERS => '0');
236 reg_sp.addr_matrix_f1 <= (OTHERS => '0');
237 reg_sp.addr_matrix_f2 <= (OTHERS => '0');
237 reg_sp.addr_matrix_f2 <= (OTHERS => '0');
238 prdata <= (OTHERS => '0');
238 prdata <= (OTHERS => '0');
239
239
240 apbo.pirq <= (OTHERS => '0');
240 apbo.pirq <= (OTHERS => '0');
241
241
242 status_full_ack <= (OTHERS => '0');
242 status_full_ack <= (OTHERS => '0');
243
243
244 reg_wp.data_shaping_BW <= '0';
244 reg_wp.data_shaping_BW <= '0';
245 reg_wp.data_shaping_SP0 <= '0';
245 reg_wp.data_shaping_SP0 <= '0';
246 reg_wp.data_shaping_SP1 <= '0';
246 reg_wp.data_shaping_SP1 <= '0';
247 reg_wp.data_shaping_R0 <= '0';
247 reg_wp.data_shaping_R0 <= '0';
248 reg_wp.data_shaping_R1 <= '0';
248 reg_wp.data_shaping_R1 <= '0';
249 reg_wp.enable_f0 <= '0';
249 reg_wp.enable_f0 <= '0';
250 reg_wp.enable_f1 <= '0';
250 reg_wp.enable_f1 <= '0';
251 reg_wp.enable_f2 <= '0';
251 reg_wp.enable_f2 <= '0';
252 reg_wp.enable_f3 <= '0';
252 reg_wp.enable_f3 <= '0';
253 reg_wp.burst_f0 <= '0';
253 reg_wp.burst_f0 <= '0';
254 reg_wp.burst_f1 <= '0';
254 reg_wp.burst_f1 <= '0';
255 reg_wp.burst_f2 <= '0';
255 reg_wp.burst_f2 <= '0';
256 reg_wp.addr_data_f0 <= (OTHERS => '0');
256 reg_wp.addr_data_f0 <= (OTHERS => '0');
257 reg_wp.addr_data_f1 <= (OTHERS => '0');
257 reg_wp.addr_data_f1 <= (OTHERS => '0');
258 reg_wp.addr_data_f2 <= (OTHERS => '0');
258 reg_wp.addr_data_f2 <= (OTHERS => '0');
259 reg_wp.addr_data_f3 <= (OTHERS => '0');
259 reg_wp.addr_data_f3 <= (OTHERS => '0');
260 reg_wp.status_full <= (OTHERS => '0');
260 reg_wp.status_full <= (OTHERS => '0');
261 reg_wp.status_full_err <= (OTHERS => '0');
261 reg_wp.status_full_err <= (OTHERS => '0');
262 reg_wp.status_new_err <= (OTHERS => '0');
262 reg_wp.status_new_err <= (OTHERS => '0');
263 reg_wp.delta_snapshot <= (OTHERS => '0');
263 reg_wp.delta_snapshot <= (OTHERS => '0');
264 reg_wp.delta_f2_f1 <= (OTHERS => '0');
264 reg_wp.delta_f2_f1 <= (OTHERS => '0');
265 reg_wp.delta_f2_f0 <= (OTHERS => '0');
265 reg_wp.delta_f2_f0 <= (OTHERS => '0');
266 reg_wp.nb_burst_available <= (OTHERS => '0');
266 reg_wp.nb_burst_available <= (OTHERS => '0');
267 reg_wp.nb_snapshot_param <= (OTHERS => '0');
267 reg_wp.nb_snapshot_param <= (OTHERS => '0');
268
268
269 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
269 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
270 status_full_ack <= (OTHERS => '0');
270 status_full_ack <= (OTHERS => '0');
271
271
272 reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR ready_matrix_f0_0;
272 reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR ready_matrix_f0_0;
273 reg_sp.status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1 OR ready_matrix_f0_1;
273 reg_sp.status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1 OR ready_matrix_f0_1;
274 reg_sp.status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1 OR ready_matrix_f1;
274 reg_sp.status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1 OR ready_matrix_f1;
275 reg_sp.status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2 OR ready_matrix_f2;
275 reg_sp.status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2 OR ready_matrix_f2;
276
276
277 reg_sp.status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo OR error_anticipating_empty_fifo;
277 reg_sp.status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo OR error_anticipating_empty_fifo;
278 reg_sp.status_error_bad_component_error <= reg_sp.status_error_bad_component_error OR error_bad_component_error;
278 reg_sp.status_error_bad_component_error <= reg_sp.status_error_bad_component_error OR error_bad_component_error;
279
279
280 reg_wp.status_full <= reg_wp.status_full OR status_full;
280 reg_wp.status_full <= reg_wp.status_full OR status_full;
281 reg_wp.status_full_err <= reg_wp.status_full_err OR status_full_err;
281 reg_wp.status_full_err <= reg_wp.status_full_err OR status_full_err;
282 reg_wp.status_new_err <= reg_wp.status_new_err OR status_new_err;
282 reg_wp.status_new_err <= reg_wp.status_new_err OR status_new_err;
283
283
284 paddr := "000000";
284 paddr := "000000";
285 paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
285 paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
286 prdata <= (OTHERS => '0');
286 prdata <= (OTHERS => '0');
287 IF apbi.psel(pindex) = '1' THEN
287 IF apbi.psel(pindex) = '1' THEN
288 -- APB DMA READ --
288 -- APB DMA READ --
289 CASE paddr(7 DOWNTO 2) IS
289 CASE paddr(7 DOWNTO 2) IS
290 --
290 --
291 WHEN "000000" => prdata(0) <= reg_sp.config_active_interruption_onNewMatrix;
291 WHEN "000000" => prdata(0) <= reg_sp.config_active_interruption_onNewMatrix;
292 prdata(1) <= reg_sp.config_active_interruption_onError;
292 prdata(1) <= reg_sp.config_active_interruption_onError;
293 WHEN "000001" => prdata(0) <= reg_sp.status_ready_matrix_f0_0;
293 WHEN "000001" => prdata(0) <= reg_sp.status_ready_matrix_f0_0;
294 prdata(1) <= reg_sp.status_ready_matrix_f0_1;
294 prdata(1) <= reg_sp.status_ready_matrix_f0_1;
295 prdata(2) <= reg_sp.status_ready_matrix_f1;
295 prdata(2) <= reg_sp.status_ready_matrix_f1;
296 prdata(3) <= reg_sp.status_ready_matrix_f2;
296 prdata(3) <= reg_sp.status_ready_matrix_f2;
297 prdata(4) <= reg_sp.status_error_anticipating_empty_fifo;
297 prdata(4) <= reg_sp.status_error_anticipating_empty_fifo;
298 prdata(5) <= reg_sp.status_error_bad_component_error;
298 prdata(5) <= reg_sp.status_error_bad_component_error;
299 WHEN "000010" => prdata <= reg_sp.addr_matrix_f0_0;
299 WHEN "000010" => prdata <= reg_sp.addr_matrix_f0_0;
300 WHEN "000011" => prdata <= reg_sp.addr_matrix_f0_1;
300 WHEN "000011" => prdata <= reg_sp.addr_matrix_f0_1;
301 WHEN "000100" => prdata <= reg_sp.addr_matrix_f1;
301 WHEN "000100" => prdata <= reg_sp.addr_matrix_f1;
302 WHEN "000101" => prdata <= reg_sp.addr_matrix_f2;
302 WHEN "000101" => prdata <= reg_sp.addr_matrix_f2;
303 WHEN "000110" => prdata <= debug_reg;
303 WHEN "000110" => prdata <= debug_reg;
304 --
304 --
305 WHEN "001000" => prdata(0) <= reg_wp.data_shaping_BW;
305 WHEN "001000" => prdata(0) <= reg_wp.data_shaping_BW;
306 prdata(1) <= reg_wp.data_shaping_SP0;
306 prdata(1) <= reg_wp.data_shaping_SP0;
307 prdata(2) <= reg_wp.data_shaping_SP1;
307 prdata(2) <= reg_wp.data_shaping_SP1;
308 prdata(3) <= reg_wp.data_shaping_R0;
308 prdata(3) <= reg_wp.data_shaping_R0;
309 prdata(4) <= reg_wp.data_shaping_R1;
309 prdata(4) <= reg_wp.data_shaping_R1;
310 WHEN "001001" => prdata(0) <= reg_wp.enable_f0;
310 WHEN "001001" => prdata(0) <= reg_wp.enable_f0;
311 prdata(1) <= reg_wp.enable_f1;
311 prdata(1) <= reg_wp.enable_f1;
312 prdata(2) <= reg_wp.enable_f2;
312 prdata(2) <= reg_wp.enable_f2;
313 prdata(3) <= reg_wp.enable_f3;
313 prdata(3) <= reg_wp.enable_f3;
314 prdata(4) <= reg_wp.burst_f0;
314 prdata(4) <= reg_wp.burst_f0;
315 prdata(5) <= reg_wp.burst_f1;
315 prdata(5) <= reg_wp.burst_f1;
316 prdata(6) <= reg_wp.burst_f2;
316 prdata(6) <= reg_wp.burst_f2;
317 WHEN "001010" => prdata <= reg_wp.addr_data_f0;
317 WHEN "001010" => prdata <= reg_wp.addr_data_f0;
318 WHEN "001011" => prdata <= reg_wp.addr_data_f1;
318 WHEN "001011" => prdata <= reg_wp.addr_data_f1;
319 WHEN "001100" => prdata <= reg_wp.addr_data_f2;
319 WHEN "001100" => prdata <= reg_wp.addr_data_f2;
320 WHEN "001101" => prdata <= reg_wp.addr_data_f3;
320 WHEN "001101" => prdata <= reg_wp.addr_data_f3;
321 WHEN "001110" => prdata(3 DOWNTO 0) <= reg_wp.status_full;
321 WHEN "001110" => prdata(3 DOWNTO 0) <= reg_wp.status_full;
322 prdata(7 DOWNTO 4) <= reg_wp.status_full_err;
322 prdata(7 DOWNTO 4) <= reg_wp.status_full_err;
323 prdata(11 DOWNTO 8) <= reg_wp.status_new_err;
323 prdata(11 DOWNTO 8) <= reg_wp.status_new_err;
324 WHEN "001111" => prdata(delta_snapshot_size-1 DOWNTO 0) <= reg_wp.delta_snapshot;
324 WHEN "001111" => prdata(delta_snapshot_size-1 DOWNTO 0) <= reg_wp.delta_snapshot;
325 WHEN "010000" => prdata(delta_f2_f1_size-1 DOWNTO 0) <= reg_wp.delta_f2_f1;
325 WHEN "010000" => prdata(delta_f2_f1_size-1 DOWNTO 0) <= reg_wp.delta_f2_f1;
326 WHEN "010001" => prdata(delta_f2_f0_size-1 DOWNTO 0) <= reg_wp.delta_f2_f0;
326 WHEN "010001" => prdata(delta_f2_f0_size-1 DOWNTO 0) <= reg_wp.delta_f2_f0;
327 WHEN "010010" => prdata(nb_burst_available_size-1 DOWNTO 0) <= reg_wp.nb_burst_available;
327 WHEN "010010" => prdata(nb_burst_available_size-1 DOWNTO 0) <= reg_wp.nb_burst_available;
328 WHEN "010011" => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param;
328 WHEN "010011" => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param;
329 --
329 --
330 WHEN OTHERS => NULL;
330 WHEN OTHERS => NULL;
331 END CASE;
331 END CASE;
332 IF (apbi.pwrite AND apbi.penable) = '1' THEN
332 IF (apbi.pwrite AND apbi.penable) = '1' THEN
333 -- APB DMA WRITE --
333 -- APB DMA WRITE --
334 CASE paddr(7 DOWNTO 2) IS
334 CASE paddr(7 DOWNTO 2) IS
335 --
335 --
336 WHEN "000000" => reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0);
336 WHEN "000000" => reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0);
337 reg_sp.config_active_interruption_onError <= apbi.pwdata(1);
337 reg_sp.config_active_interruption_onError <= apbi.pwdata(1);
338 WHEN "000001" => reg_sp.status_ready_matrix_f0_0 <= apbi.pwdata(0);
338 WHEN "000001" => reg_sp.status_ready_matrix_f0_0 <= apbi.pwdata(0);
339 reg_sp.status_ready_matrix_f0_1 <= apbi.pwdata(1);
339 reg_sp.status_ready_matrix_f0_1 <= apbi.pwdata(1);
340 reg_sp.status_ready_matrix_f1 <= apbi.pwdata(2);
340 reg_sp.status_ready_matrix_f1 <= apbi.pwdata(2);
341 reg_sp.status_ready_matrix_f2 <= apbi.pwdata(3);
341 reg_sp.status_ready_matrix_f2 <= apbi.pwdata(3);
342 reg_sp.status_error_anticipating_empty_fifo <= apbi.pwdata(4);
342 reg_sp.status_error_anticipating_empty_fifo <= apbi.pwdata(4);
343 reg_sp.status_error_bad_component_error <= apbi.pwdata(5);
343 reg_sp.status_error_bad_component_error <= apbi.pwdata(5);
344 WHEN "000010" => reg_sp.addr_matrix_f0_0 <= apbi.pwdata;
344 WHEN "000010" => reg_sp.addr_matrix_f0_0 <= apbi.pwdata;
345 WHEN "000011" => reg_sp.addr_matrix_f0_1 <= apbi.pwdata;
345 WHEN "000011" => reg_sp.addr_matrix_f0_1 <= apbi.pwdata;
346 WHEN "000100" => reg_sp.addr_matrix_f1 <= apbi.pwdata;
346 WHEN "000100" => reg_sp.addr_matrix_f1 <= apbi.pwdata;
347 WHEN "000101" => reg_sp.addr_matrix_f2 <= apbi.pwdata;
347 WHEN "000101" => reg_sp.addr_matrix_f2 <= apbi.pwdata;
348 --
348 --
349 WHEN "001000" => reg_wp.data_shaping_BW <= apbi.pwdata(0);
349 WHEN "001000" => reg_wp.data_shaping_BW <= apbi.pwdata(0);
350 reg_wp.data_shaping_SP0 <= apbi.pwdata(1);
350 reg_wp.data_shaping_SP0 <= apbi.pwdata(1);
351 reg_wp.data_shaping_SP1 <= apbi.pwdata(2);
351 reg_wp.data_shaping_SP1 <= apbi.pwdata(2);
352 reg_wp.data_shaping_R0 <= apbi.pwdata(3);
352 reg_wp.data_shaping_R0 <= apbi.pwdata(3);
353 reg_wp.data_shaping_R1 <= apbi.pwdata(4);
353 reg_wp.data_shaping_R1 <= apbi.pwdata(4);
354 WHEN "001001" => reg_wp.enable_f0 <= apbi.pwdata(0);
354 WHEN "001001" => reg_wp.enable_f0 <= apbi.pwdata(0);
355 reg_wp.enable_f1 <= apbi.pwdata(1);
355 reg_wp.enable_f1 <= apbi.pwdata(1);
356 reg_wp.enable_f2 <= apbi.pwdata(2);
356 reg_wp.enable_f2 <= apbi.pwdata(2);
357 reg_wp.enable_f3 <= apbi.pwdata(3);
357 reg_wp.enable_f3 <= apbi.pwdata(3);
358 reg_wp.burst_f0 <= apbi.pwdata(4);
358 reg_wp.burst_f0 <= apbi.pwdata(4);
359 reg_wp.burst_f1 <= apbi.pwdata(5);
359 reg_wp.burst_f1 <= apbi.pwdata(5);
360 reg_wp.burst_f2 <= apbi.pwdata(6);
360 reg_wp.burst_f2 <= apbi.pwdata(6);
361 WHEN "001010" => reg_wp.addr_data_f0 <= apbi.pwdata;
361 WHEN "001010" => reg_wp.addr_data_f0 <= apbi.pwdata;
362 WHEN "001011" => reg_wp.addr_data_f1 <= apbi.pwdata;
362 WHEN "001011" => reg_wp.addr_data_f1 <= apbi.pwdata;
363 WHEN "001100" => reg_wp.addr_data_f2 <= apbi.pwdata;
363 WHEN "001100" => reg_wp.addr_data_f2 <= apbi.pwdata;
364 WHEN "001101" => reg_wp.addr_data_f3 <= apbi.pwdata;
364 WHEN "001101" => reg_wp.addr_data_f3 <= apbi.pwdata;
365 WHEN "001110" => reg_wp.status_full <= apbi.pwdata(3 DOWNTO 0);
365 WHEN "001110" => reg_wp.status_full <= apbi.pwdata(3 DOWNTO 0);
366 reg_wp.status_full_err <= apbi.pwdata(7 DOWNTO 4);
366 reg_wp.status_full_err <= apbi.pwdata(7 DOWNTO 4);
367 reg_wp.status_new_err <= apbi.pwdata(11 DOWNTO 8);
367 reg_wp.status_new_err <= apbi.pwdata(11 DOWNTO 8);
368 status_full_ack(0) <= reg_wp.status_full(0) AND NOT apbi.pwdata(0);
368 status_full_ack(0) <= reg_wp.status_full(0) AND NOT apbi.pwdata(0);
369 status_full_ack(1) <= reg_wp.status_full(1) AND NOT apbi.pwdata(1);
369 status_full_ack(1) <= reg_wp.status_full(1) AND NOT apbi.pwdata(1);
370 status_full_ack(2) <= reg_wp.status_full(2) AND NOT apbi.pwdata(2);
370 status_full_ack(2) <= reg_wp.status_full(2) AND NOT apbi.pwdata(2);
371 status_full_ack(3) <= reg_wp.status_full(3) AND NOT apbi.pwdata(3);
371 status_full_ack(3) <= reg_wp.status_full(3) AND NOT apbi.pwdata(3);
372 WHEN "001111" => reg_wp.delta_snapshot <= apbi.pwdata(delta_snapshot_size-1 DOWNTO 0);
372 WHEN "001111" => reg_wp.delta_snapshot <= apbi.pwdata(delta_snapshot_size-1 DOWNTO 0);
373 WHEN "010000" => reg_wp.delta_f2_f1 <= apbi.pwdata(delta_f2_f1_size-1 DOWNTO 0);
373 WHEN "010000" => reg_wp.delta_f2_f1 <= apbi.pwdata(delta_f2_f1_size-1 DOWNTO 0);
374 WHEN "010001" => reg_wp.delta_f2_f0 <= apbi.pwdata(delta_f2_f0_size-1 DOWNTO 0);
374 WHEN "010001" => reg_wp.delta_f2_f0 <= apbi.pwdata(delta_f2_f0_size-1 DOWNTO 0);
375 WHEN "010010" => reg_wp.nb_burst_available <= apbi.pwdata(nb_burst_available_size-1 DOWNTO 0);
375 WHEN "010010" => reg_wp.nb_burst_available <= apbi.pwdata(nb_burst_available_size-1 DOWNTO 0);
376 WHEN "010011" => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0);
376 WHEN "010011" => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0);
377 --
377 --
378 WHEN OTHERS => NULL;
378 WHEN OTHERS => NULL;
379 END CASE;
379 END CASE;
380 END IF;
380 END IF;
381 END IF;
381 END IF;
382
382
383 apbo.pirq(pirq) <= (reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0_0 OR
383 apbo.pirq(pirq) <= (reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0_0 OR
384 ready_matrix_f0_1 OR
384 ready_matrix_f0_1 OR
385 ready_matrix_f1 OR
385 ready_matrix_f1 OR
386 ready_matrix_f2)
386 ready_matrix_f2)
387 )
387 )
388 OR
388 OR
389 (reg_sp.config_active_interruption_onError AND (error_anticipating_empty_fifo OR
389 (reg_sp.config_active_interruption_onError AND (error_anticipating_empty_fifo OR
390 error_bad_component_error)
390 error_bad_component_error)
391 )
391 )
392 OR
392 OR
393 (status_full(0) OR status_full_err(0) OR status_new_err(0) OR
393 (status_full(0) OR status_full_err(0) OR status_new_err(0) OR
394 status_full(1) OR status_full_err(1) OR status_new_err(1) OR
394 status_full(1) OR status_full_err(1) OR status_new_err(1) OR
395 status_full(2) OR status_full_err(2) OR status_new_err(2) OR
395 status_full(2) OR status_full_err(2) OR status_new_err(2) OR
396 status_full(3) OR status_full_err(3) OR status_new_err(3)
396 status_full(3) OR status_full_err(3) OR status_new_err(3)
397 );
397 );
398
398
399
399
400 END IF;
400 END IF;
401 END PROCESS lpp_top_apbreg;
401 END PROCESS lpp_top_apbreg;
402
402
403 apbo.pindex <= pindex;
403 apbo.pindex <= pindex;
404 apbo.pconfig <= pconfig;
404 apbo.pconfig <= pconfig;
405 apbo.prdata <= prdata;
405 apbo.prdata <= prdata;
406
406
407
407
408 END beh;
408 END beh; No newline at end of file
Show file before | Show file after | Hide comments
@@ -1,245 +1,253
1 LIBRARY ieee;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
2 USE ieee.std_logic_1164.ALL;
3 USE ieee.numeric_std.ALL;
3 USE ieee.numeric_std.ALL;
4
4
5 LIBRARY lpp;
5 LIBRARY lpp;
6 USE lpp.lpp_ad_conv.ALL;
6 USE lpp.lpp_ad_conv.ALL;
7 USE lpp.iir_filter.ALL;
7 USE lpp.iir_filter.ALL;
8 USE lpp.FILTERcfg.ALL;
8 USE lpp.FILTERcfg.ALL;
9 USE lpp.lpp_memory.ALL;
9 USE lpp.lpp_memory.ALL;
10 USE lpp.lpp_waveform_pkg.ALL;
10 USE lpp.lpp_waveform_pkg.ALL;
11 USE lpp.lpp_top_lfr_pkg.ALL;
11 USE lpp.lpp_top_lfr_pkg.ALL;
12
12
13 LIBRARY techmap;
13 LIBRARY techmap;
14 USE techmap.gencomp.ALL;
14 USE techmap.gencomp.ALL;
15
15
16 LIBRARY grlib;
16 LIBRARY grlib;
17 USE grlib.amba.ALL;
17 USE grlib.amba.ALL;
18 USE grlib.stdlib.ALL;
18 USE grlib.stdlib.ALL;
19 USE grlib.devices.ALL;
19 USE grlib.devices.ALL;
20 USE GRLIB.DMA2AHB_Package.ALL;
20 USE GRLIB.DMA2AHB_Package.ALL;
21
21
22 ENTITY lpp_top_lfr_wf_picker IS
22 ENTITY lpp_top_lfr_wf_picker IS
23 GENERIC (
23 GENERIC (
24 hindex : INTEGER := 2;
24 hindex : INTEGER := 2;
25 pindex : INTEGER := 4;
25 pindex : INTEGER := 15;
26 paddr : INTEGER := 4;
26 paddr : INTEGER := 15;
27 pmask : INTEGER := 16#fff#;
27 pmask : INTEGER := 16#fff#;
28 pirq : INTEGER := 0;
28 pirq : INTEGER := 15;
29 tech : INTEGER := 0;
29 tech : INTEGER := 0;
30 nb_burst_available_size : INTEGER := 11;
30 nb_burst_available_size : INTEGER := 11;
31 nb_snapshot_param_size : INTEGER := 11;
31 nb_snapshot_param_size : INTEGER := 11;
32 delta_snapshot_size : INTEGER := 16;
32 delta_snapshot_size : INTEGER := 16;
33 delta_f2_f0_size : INTEGER := 10;
33 delta_f2_f0_size : INTEGER := 10;
34 delta_f2_f1_size : INTEGER := 10
34 delta_f2_f1_size : INTEGER := 10
35 );
35 );
36 PORT (
36 PORT (
37 -- ADS7886
37 -- ADS7886
38 cnv_run : IN STD_LOGIC;
38 cnv_run : IN STD_LOGIC;
39 cnv : OUT STD_LOGIC;
39 cnv : OUT STD_LOGIC;
40 sck : OUT STD_LOGIC;
40 sck : OUT STD_LOGIC;
41 sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
41 sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
42 --
42 --
43 cnv_clk : IN STD_LOGIC;
43 cnv_clk : IN STD_LOGIC;
44 cnv_rstn : IN STD_LOGIC;
44 cnv_rstn : IN STD_LOGIC;
45
45
46 -- AMBA AHB system signals
46 -- AMBA AHB system signals
47 HCLK : IN STD_ULOGIC;
47 HCLK : IN STD_ULOGIC;
48 HRESETn : IN STD_ULOGIC;
48 HRESETn : IN STD_ULOGIC;
49
49
50 -- AMBA APB Slave Interface
50 -- AMBA APB Slave Interface
51 apbi : IN apb_slv_in_type;
51 apbi : IN apb_slv_in_type;
52 apbo : OUT apb_slv_out_type;
52 apbo : OUT apb_slv_out_type;
53
53
54 -- AMBA AHB Master Interface
54 -- AMBA AHB Master Interface
55 AHB_Master_In : IN AHB_Mst_In_Type;
55 AHB_Master_In : IN AHB_Mst_In_Type;
56 AHB_Master_Out : OUT AHB_Mst_Out_Type;
56 AHB_Master_Out : OUT AHB_Mst_Out_Type;
57
57
58 --
58 --
59 coarse_time_0 : IN STD_LOGIC;
59 coarse_time_0 : IN STD_LOGIC;
60
60
61 --
61 --
62 data_shaping_BW : OUT STD_LOGIC
62 data_shaping_BW : OUT STD_LOGIC
63 );
63 );
64 END lpp_top_lfr_wf_picker;
64 END lpp_top_lfr_wf_picker;
65
65
66 ARCHITECTURE tb OF lpp_top_lfr_wf_picker IS
66 ARCHITECTURE tb OF lpp_top_lfr_wf_picker IS
67
67
68 SIGNAL ready_matrix_f0_0 : STD_LOGIC;
68 SIGNAL ready_matrix_f0_0 : STD_LOGIC;
69 SIGNAL ready_matrix_f0_1 : STD_LOGIC;
69 SIGNAL ready_matrix_f0_1 : STD_LOGIC;
70 SIGNAL ready_matrix_f1 : STD_LOGIC;
70 SIGNAL ready_matrix_f1 : STD_LOGIC;
71 SIGNAL ready_matrix_f2 : STD_LOGIC;
71 SIGNAL ready_matrix_f2 : STD_LOGIC;
72 SIGNAL error_anticipating_empty_fifo : STD_LOGIC;
72 SIGNAL error_anticipating_empty_fifo : STD_LOGIC;
73 SIGNAL error_bad_component_error : STD_LOGIC;
73 SIGNAL error_bad_component_error : STD_LOGIC;
74 SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
74 SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
75 SIGNAL status_ready_matrix_f0_0 : STD_LOGIC;
75 SIGNAL status_ready_matrix_f0_0 : STD_LOGIC;
76 SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
76 SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
77 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
77 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
78 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
78 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
79 SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC;
79 SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC;
80 SIGNAL status_error_bad_component_error : STD_LOGIC;
80 SIGNAL status_error_bad_component_error : STD_LOGIC;
81 SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
81 SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
82 SIGNAL config_active_interruption_onError : STD_LOGIC;
82 SIGNAL config_active_interruption_onError : STD_LOGIC;
83 SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
83 SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
84 SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
84 SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
85 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
85 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
86 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
86 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
87
87
88 SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
88 SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
89 SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
89 SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
90 SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
90 SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
91 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
91 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
92 SIGNAL data_shaping_SP0 : STD_LOGIC;
92 SIGNAL data_shaping_SP0 : STD_LOGIC;
93 SIGNAL data_shaping_SP1 : STD_LOGIC;
93 SIGNAL data_shaping_SP1 : STD_LOGIC;
94 SIGNAL data_shaping_R0 : STD_LOGIC;
94 SIGNAL data_shaping_R0 : STD_LOGIC;
95 SIGNAL data_shaping_R1 : STD_LOGIC;
95 SIGNAL data_shaping_R1 : STD_LOGIC;
96 SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
96 SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
97 SIGNAL delta_f2_f1 : STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
97 SIGNAL delta_f2_f1 : STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
98 SIGNAL delta_f2_f0 : STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
98 SIGNAL delta_f2_f0 : STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
99 SIGNAL nb_burst_available : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
99 SIGNAL nb_burst_available : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
100 SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
100 SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
101 SIGNAL enable_f0 : STD_LOGIC;
101 SIGNAL enable_f0 : STD_LOGIC;
102 SIGNAL enable_f1 : STD_LOGIC;
102 SIGNAL enable_f1 : STD_LOGIC;
103 SIGNAL enable_f2 : STD_LOGIC;
103 SIGNAL enable_f2 : STD_LOGIC;
104 SIGNAL enable_f3 : STD_LOGIC;
104 SIGNAL enable_f3 : STD_LOGIC;
105 SIGNAL burst_f0 : STD_LOGIC;
105 SIGNAL burst_f0 : STD_LOGIC;
106 SIGNAL burst_f1 : STD_LOGIC;
106 SIGNAL burst_f1 : STD_LOGIC;
107 SIGNAL burst_f2 : STD_LOGIC;
107 SIGNAL burst_f2 : STD_LOGIC;
108 SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
108 SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
109 SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
109 SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
110 SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
110 SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
111 SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
111 SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
112
112
113 SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(5 DOWNTO 0);
113 SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(5 DOWNTO 0);
114 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
114 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
115 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(5 DOWNTO 0);
115 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(5 DOWNTO 0);
116 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
116 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
117 SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(5 DOWNTO 0);
117 SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(5 DOWNTO 0);
118 SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
118 SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
119 SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(5 DOWNTO 0);
119 SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(5 DOWNTO 0);
120 SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
120 SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
121
121
122
122
123 BEGIN
123 BEGIN
124
124
125 lpp_top_apbreg_1: lpp_top_apbreg
125 ready_matrix_f0_0 <= '0';
126 GENERIC MAP (
126 ready_matrix_f0_1 <= '0';
127 nb_burst_available_size => nb_burst_available_size,
127 ready_matrix_f1 <= '0';
128 nb_snapshot_param_size => nb_snapshot_param_size,
128 ready_matrix_f2 <= '0';
129 delta_snapshot_size => delta_snapshot_size,
129 error_anticipating_empty_fifo <= '0';
130 delta_f2_f0_size => delta_f2_f0_size,
130 error_bad_component_error <= '0';
131 delta_f2_f1_size => delta_f2_f1_size,
131 debug_reg <= (others => '0');
132 pindex => pindex,
132
133 paddr => paddr,
133 lpp_top_apbreg_1: lpp_top_apbreg
134 pmask => pmask,
134 GENERIC MAP (
135 pirq => pirq)
135 nb_burst_available_size => nb_burst_available_size,
136 PORT MAP (
136 nb_snapshot_param_size => nb_snapshot_param_size,
137 HCLK => HCLK,
137 delta_snapshot_size => delta_snapshot_size,
138 HRESETn => HRESETn,
138 delta_f2_f0_size => delta_f2_f0_size,
139 apbi => apbi,
139 delta_f2_f1_size => delta_f2_f1_size,
140 apbo => apbo,
140 pindex => pindex,
141
141 paddr => paddr,
142 ready_matrix_f0_0 => ready_matrix_f0_0,
142 pmask => pmask,
143 ready_matrix_f0_1 => ready_matrix_f0_1,
143 pirq => pirq)
144 ready_matrix_f1 => ready_matrix_f1,
144 PORT MAP (
145 ready_matrix_f2 => ready_matrix_f2,
145 HCLK => HCLK,
146 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
146 HRESETn => HRESETn,
147 error_bad_component_error => error_bad_component_error,
147 apbi => apbi,
148 debug_reg => debug_reg,
148 apbo => apbo,
149 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
149
150 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
150 ready_matrix_f0_0 => ready_matrix_f0_0,
151 status_ready_matrix_f1 => status_ready_matrix_f1,
151 ready_matrix_f0_1 => ready_matrix_f0_1,
152 status_ready_matrix_f2 => status_ready_matrix_f2,
152 ready_matrix_f1 => ready_matrix_f1,
153 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
153 ready_matrix_f2 => ready_matrix_f2,
154 status_error_bad_component_error => status_error_bad_component_error,
154 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
155 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
155 error_bad_component_error => error_bad_component_error,
156 config_active_interruption_onError => config_active_interruption_onError,
156 debug_reg => debug_reg,
157 addr_matrix_f0_0 => addr_matrix_f0_0,
157 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
158 addr_matrix_f0_1 => addr_matrix_f0_1,
158 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
159 addr_matrix_f1 => addr_matrix_f1,
159 status_ready_matrix_f1 => status_ready_matrix_f1,
160 addr_matrix_f2 => addr_matrix_f2,
160 status_ready_matrix_f2 => status_ready_matrix_f2,
161
161 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
162 status_full => status_full,
162 status_error_bad_component_error => status_error_bad_component_error,
163 status_full_ack => status_full_ack,
163 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
164 status_full_err => status_full_err,
164 config_active_interruption_onError => config_active_interruption_onError,
165 status_new_err => status_new_err,
165 addr_matrix_f0_0 => addr_matrix_f0_0,
166 data_shaping_BW => data_shaping_BW,
166 addr_matrix_f0_1 => addr_matrix_f0_1,
167 data_shaping_SP0 => data_shaping_SP0,
167 addr_matrix_f1 => addr_matrix_f1,
168 data_shaping_SP1 => data_shaping_SP1,
168 addr_matrix_f2 => addr_matrix_f2,
169 data_shaping_R0 => data_shaping_R0,
169
170 data_shaping_R1 => data_shaping_R1,
170 status_full => status_full,
171 delta_snapshot => delta_snapshot,
171 status_full_ack => status_full_ack,
172 delta_f2_f1 => delta_f2_f1,
172 status_full_err => status_full_err,
173 delta_f2_f0 => delta_f2_f0,
173 status_new_err => status_new_err,
174 nb_burst_available => nb_burst_available,
174 data_shaping_BW => data_shaping_BW,
175 nb_snapshot_param => nb_snapshot_param,
175 data_shaping_SP0 => data_shaping_SP0,
176 enable_f0 => enable_f0,
176 data_shaping_SP1 => data_shaping_SP1,
177 enable_f1 => enable_f1,
177 data_shaping_R0 => data_shaping_R0,
178 enable_f2 => enable_f2,
178 data_shaping_R1 => data_shaping_R1,
179 enable_f3 => enable_f3,
179 delta_snapshot => delta_snapshot,
180 burst_f0 => burst_f0,
180 delta_f2_f1 => delta_f2_f1,
181 burst_f1 => burst_f1,
181 delta_f2_f0 => delta_f2_f0,
182 burst_f2 => burst_f2,
182 nb_burst_available => nb_burst_available,
183 addr_data_f0 => addr_data_f0,
183 nb_snapshot_param => nb_snapshot_param,
184 addr_data_f1 => addr_data_f1,
184 enable_f0 => enable_f0,
185 addr_data_f2 => addr_data_f2,
185 enable_f1 => enable_f1,
186 addr_data_f3 => addr_data_f3);
186 enable_f2 => enable_f2,
187
187 enable_f3 => enable_f3,
188 lpp_top_lfr_wf_picker_ip_1: lpp_top_lfr_wf_picker_ip
188 burst_f0 => burst_f0,
189 GENERIC MAP (
189 burst_f1 => burst_f1,
190 hindex => hindex,
190 burst_f2 => burst_f2,
191 nb_burst_available_size => nb_burst_available_size,
191 addr_data_f0 => addr_data_f0,
192 nb_snapshot_param_size => nb_snapshot_param_size,
192 addr_data_f1 => addr_data_f1,
193 delta_snapshot_size => delta_snapshot_size,
193 addr_data_f2 => addr_data_f2,
194 delta_f2_f0_size => delta_f2_f0_size,
194 addr_data_f3 => addr_data_f3);
195 delta_f2_f1_size => delta_f2_f1_size,
195
196 tech => tech,
196 lpp_top_lfr_wf_picker_ip_1: lpp_top_lfr_wf_picker_ip
197 Mem_use => use_RAM
197 GENERIC MAP (
198 )
198 hindex => hindex,
199 PORT MAP (
199 nb_burst_available_size => nb_burst_available_size,
200 cnv_run => cnv_run,
200 nb_snapshot_param_size => nb_snapshot_param_size,
201 cnv => cnv,
201 delta_snapshot_size => delta_snapshot_size,
202 sck => sck,
202 delta_f2_f0_size => delta_f2_f0_size,
203 sdo => sdo,
203 delta_f2_f1_size => delta_f2_f1_size,
204 cnv_clk => cnv_clk,
204 tech => tech,
205 cnv_rstn => cnv_rstn,
205 Mem_use => use_RAM
206
206 )
207 clk => HCLK,
207 PORT MAP (
208 rstn => HRESETn,
208 cnv_run => cnv_run,
209
209 cnv => cnv,
210 sample_f0_wen => sample_f0_wen,
210 sck => sck,
211 sample_f0_wdata => sample_f0_wdata,
211 sdo => sdo,
212 sample_f1_wen => sample_f1_wen,
212 cnv_clk => cnv_clk,
213 sample_f1_wdata => sample_f1_wdata,
213 cnv_rstn => cnv_rstn,
214 sample_f2_wen => sample_f2_wen,
214
215 sample_f2_wdata => sample_f2_wdata,
215 clk => HCLK,
216 sample_f3_wen => sample_f3_wen,
216 rstn => HRESETn,
217 sample_f3_wdata => sample_f3_wdata,
217
218 AHB_Master_In => AHB_Master_In,
218 sample_f0_wen => sample_f0_wen,
219 AHB_Master_Out => AHB_Master_Out,
219 sample_f0_wdata => sample_f0_wdata,
220 coarse_time_0 => coarse_time_0,
220 sample_f1_wen => sample_f1_wen,
221 data_shaping_SP0 => data_shaping_SP0,
221 sample_f1_wdata => sample_f1_wdata,
222 data_shaping_SP1 => data_shaping_SP1,
222 sample_f2_wen => sample_f2_wen,
223 data_shaping_R0 => data_shaping_R0,
223 sample_f2_wdata => sample_f2_wdata,
224 data_shaping_R1 => data_shaping_R1,
224 sample_f3_wen => sample_f3_wen,
225 delta_snapshot => delta_snapshot,
225 sample_f3_wdata => sample_f3_wdata,
226 delta_f2_f1 => delta_f2_f1,
226 AHB_Master_In => AHB_Master_In,
227 delta_f2_f0 => delta_f2_f0,
227 AHB_Master_Out => AHB_Master_Out,
228 enable_f0 => enable_f0,
228 coarse_time_0 => coarse_time_0,
229 enable_f1 => enable_f1,
229 data_shaping_SP0 => data_shaping_SP0,
230 enable_f2 => enable_f2,
230 data_shaping_SP1 => data_shaping_SP1,
231 enable_f3 => enable_f3,
231 data_shaping_R0 => data_shaping_R0,
232 burst_f0 => burst_f0,
232 data_shaping_R1 => data_shaping_R1,
233 burst_f1 => burst_f1,
233 delta_snapshot => delta_snapshot,
234 burst_f2 => burst_f2,
234 delta_f2_f1 => delta_f2_f1,
235 nb_burst_available => nb_burst_available,
235 delta_f2_f0 => delta_f2_f0,
236 nb_snapshot_param => nb_snapshot_param,
236 enable_f0 => enable_f0,
237 status_full => status_full,
237 enable_f1 => enable_f1,
238 status_full_ack => status_full_ack,
238 enable_f2 => enable_f2,
239 status_full_err => status_full_err,
239 enable_f3 => enable_f3,
240 status_new_err => status_new_err,
240 burst_f0 => burst_f0,
241 addr_data_f0 => addr_data_f0,
241 burst_f1 => burst_f1,
242 addr_data_f1 => addr_data_f1,
242 burst_f2 => burst_f2,
243 addr_data_f2 => addr_data_f2,
243 nb_burst_available => nb_burst_available,
244 addr_data_f3 => addr_data_f3);
244 nb_snapshot_param => nb_snapshot_param,
245 END tb;
245 status_full => status_full,
246 status_full_ack => status_full_ack,
247 status_full_err => status_full_err,
248 status_new_err => status_new_err,
249 addr_data_f0 => addr_data_f0,
250 addr_data_f1 => addr_data_f1,
251 addr_data_f2 => addr_data_f2,
252 addr_data_f3 => addr_data_f3);
253 END tb; No newline at end of file
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@@ -1,116 +1,114
1 LIBRARY IEEE;
1 LIBRARY IEEE;
2 USE IEEE.STD_LOGIC_1164.ALL;
2 USE IEEE.STD_LOGIC_1164.ALL;
3 USE ieee.numeric_std.ALL;
3 USE ieee.numeric_std.ALL;
4
4
5 ENTITY lpp_waveform_snapshot_controler IS
5 ENTITY lpp_waveform_snapshot_controler IS
6
6
7 GENERIC (
7 GENERIC (
8 delta_snapshot_size : INTEGER := 16;
8 delta_snapshot_size : INTEGER := 16;
9 delta_f2_f0_size : INTEGER := 10;
9 delta_f2_f0_size : INTEGER := 10;
10 delta_f2_f1_size : INTEGER := 10);
10 delta_f2_f1_size : INTEGER := 10);
11
11
12 PORT (
12 PORT (
13 clk : IN STD_LOGIC;
13 clk : IN STD_LOGIC;
14 rstn : IN STD_LOGIC;
14 rstn : IN STD_LOGIC;
15 --config
15 --config
16 delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
16 delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
17 delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
17 delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
18 delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
18 delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
19
19
20 --input
20 --input
21 coarse_time_0 : IN STD_LOGIC;
21 coarse_time_0 : IN STD_LOGIC;
22 data_f0_in_valid : IN STD_LOGIC;
22 data_f0_in_valid : IN STD_LOGIC;
23 data_f2_in_valid : IN STD_LOGIC;
23 data_f2_in_valid : IN STD_LOGIC;
24 --output
24 --output
25 start_snapshot_f0 : OUT STD_LOGIC;
25 start_snapshot_f0 : OUT STD_LOGIC;
26 start_snapshot_f1 : OUT STD_LOGIC;
26 start_snapshot_f1 : OUT STD_LOGIC;
27 start_snapshot_f2 : OUT STD_LOGIC
27 start_snapshot_f2 : OUT STD_LOGIC
28 );
28 );
29
29
30 END lpp_waveform_snapshot_controler;
30 END lpp_waveform_snapshot_controler;
31
31
32 ARCHITECTURE beh OF lpp_waveform_snapshot_controler IS
32 ARCHITECTURE beh OF lpp_waveform_snapshot_controler IS
33 SIGNAL counter_delta_snapshot : INTEGER;
33 SIGNAL counter_delta_snapshot : INTEGER;
34 SIGNAL counter_delta_f0 : INTEGER;
34 SIGNAL counter_delta_f0 : INTEGER;
35
35
36 SIGNAL coarse_time_0_r : STD_LOGIC;
36 SIGNAL coarse_time_0_r : STD_LOGIC;
37 SIGNAL start_snapshot_f2_temp : STD_LOGIC;
37 SIGNAL start_snapshot_f2_temp : STD_LOGIC;
38 SIGNAL start_snapshot_fothers_temp : STD_LOGIC;
38 SIGNAL start_snapshot_fothers_temp : STD_LOGIC;
39 SIGNAL start_snapshot_fothers_temp2 : STD_LOGIC;
39 BEGIN -- beh
40 BEGIN -- beh
40
41
41 PROCESS (clk, rstn)
42 PROCESS (clk, rstn)
42 BEGIN
43 BEGIN
43 IF rstn = '0' THEN
44 IF rstn = '0' THEN
44 start_snapshot_f0 <= '0';
45 start_snapshot_f0 <= '0';
45 start_snapshot_f1 <= '0';
46 start_snapshot_f1 <= '0';
46 start_snapshot_f2 <= '0';
47 start_snapshot_f2 <= '0';
47 counter_delta_snapshot <= 0;
48 counter_delta_snapshot <= 0;
48 counter_delta_f0 <= 0;
49 counter_delta_f0 <= 0;
49 coarse_time_0_r <= '0';
50 coarse_time_0_r <= '0';
50 start_snapshot_f2_temp <= '0';
51 start_snapshot_f2_temp <= '0';
51 start_snapshot_fothers_temp <= '0';
52 start_snapshot_fothers_temp <= '0';
52 ELSIF clk'EVENT AND clk = '1' THEN
53 start_snapshot_fothers_temp2 <= '0';
53 IF counter_delta_snapshot = UNSIGNED(delta_snapshot) THEN
54 ELSIF clk'EVENT AND clk = '1' THEN
54 start_snapshot_f2_temp <= '1';
55 IF counter_delta_snapshot = UNSIGNED(delta_snapshot) THEN
55 ELSE
56 start_snapshot_f2_temp <= '1';
56 start_snapshot_f2_temp <= '0';
57 ELSE
57 END IF;
58 start_snapshot_f2_temp <= '0';
58 -------------------------------------------------------------------------
59 END IF;
59 IF counter_delta_snapshot = UNSIGNED(delta_snapshot) AND start_snapshot_f2_temp = '0' THEN
60 -------------------------------------------------------------------------
60 start_snapshot_f2 <= '1';
61 IF counter_delta_snapshot = UNSIGNED(delta_snapshot) AND start_snapshot_f2_temp = '0' THEN
61 ELSE
62 start_snapshot_f2 <= '1';
62 start_snapshot_f2 <= '0';
63 ELSE
63 END IF;
64 start_snapshot_f2 <= '0';
64 -------------------------------------------------------------------------
65 END IF;
65 coarse_time_0_r <= coarse_time_0;
66 -------------------------------------------------------------------------
66 IF coarse_time_0 = NOT coarse_time_0_r THEN --AND coarse_time_0 = '1' THEN
67 coarse_time_0_r <= coarse_time_0;
67 IF counter_delta_snapshot = 0 THEN
68 IF coarse_time_0 = NOT coarse_time_0_r THEN --AND coarse_time_0 = '1' THEN
68 counter_delta_snapshot <= to_integer(UNSIGNED(delta_snapshot));
69 IF counter_delta_snapshot = 0 THEN
69 ELSE
70 counter_delta_snapshot <= to_integer(UNSIGNED(delta_snapshot));
70 counter_delta_snapshot <= counter_delta_snapshot - 1;
71 ELSE
71 END IF;
72 counter_delta_snapshot <= counter_delta_snapshot - 1;
72 END IF;
73 END IF;
73
74 END IF;
74
75
75 -------------------------------------------------------------------------
76
76
77 -------------------------------------------------------------------------
77
78
78
79
79 IF counter_delta_f0 = UNSIGNED(delta_f2_f1) THEN
80
80 start_snapshot_f1 <= '1';
81 IF counter_delta_f0 = UNSIGNED(delta_f2_f1) THEN
81 ELSE
82 start_snapshot_f1 <= '1';
82 start_snapshot_f1 <= '0';
83 ELSE
83 END IF;
84 start_snapshot_f1 <= '0';
84
85 END IF;
85 IF counter_delta_f0 = 1 THEN --UNSIGNED(delta_f2_f0) THEN
86
86 start_snapshot_f0 <= '1';
87 IF counter_delta_f0 = 1 THEN --UNSIGNED(delta_f2_f0) THEN
87 ELSE
88 start_snapshot_f0 <= '1';
88 start_snapshot_f0 <= '0';
89 ELSE
89 END IF;
90 start_snapshot_f0 <= '0';
90
91 END IF;
91 IF counter_delta_snapshot = UNSIGNED(delta_snapshot)
92
92 AND start_snapshot_f2_temp = '0'
93 IF counter_delta_snapshot = UNSIGNED(delta_snapshot)
93 THEN --
94 AND start_snapshot_f2_temp = '0'
94 start_snapshot_fothers_temp <= '1';
95 THEN --
95 ELSIF counter_delta_f0 > 0 THEN
96 start_snapshot_fothers_temp <= '1';
96 start_snapshot_fothers_temp <= '0';
97 ELSIF counter_delta_f0 > 0 THEN
97 END IF;
98 start_snapshot_fothers_temp <= '0';
98
99 END IF;
99
100
100 -------------------------------------------------------------------------
101
101 IF (start_snapshot_fothers_temp = '1' OR (counter_delta_snapshot = UNSIGNED(delta_snapshot) AND start_snapshot_f2_temp = '0')) AND data_f2_in_valid = '1' THEN
102 -------------------------------------------------------------------------
102 --counter_delta_snapshot = UNSIGNED(delta_snapshot) AND start_snapshot_f2_temp = '0' THEN --
103 IF (start_snapshot_fothers_temp = '1' OR (counter_delta_snapshot = UNSIGNED(delta_snapshot) AND start_snapshot_f2_temp = '0')) AND data_f2_in_valid = '1' THEN
103 --counter_delta_snapshot = UNSIGNED(delta_snapshot) THEN
104 --counter_delta_snapshot = UNSIGNED(delta_snapshot) AND start_snapshot_f2_temp = '0' THEN --
104 counter_delta_f0 <= to_integer(UNSIGNED(delta_f2_f0)); --0;
105 --counter_delta_snapshot = UNSIGNED(delta_snapshot) THEN
105 ELSE
106 counter_delta_f0 <= to_integer(UNSIGNED(delta_f2_f0)); --0;
106 IF (( counter_delta_f0 > 0 ) AND ( data_f0_in_valid = '1' )) THEN --<= UNSIGNED(delta_f2_f0) THEN
107 ELSE
107 counter_delta_f0 <= counter_delta_f0 - 1;--counter_delta_f0 + 1;
108 IF (( counter_delta_f0 > 0 ) AND ( data_f0_in_valid = '1' )) THEN --<= UNSIGNED(delta_f2_f0) THEN
108 END IF;
109 counter_delta_f0 <= counter_delta_f0 - 1;--counter_delta_f0 + 1;
109 END IF;
110 END IF;
110 -------------------------------------------------------------------------
111 END IF;
111 END IF;
112 -------------------------------------------------------------------------
112 END PROCESS;
113 END IF;
113
114 END PROCESS;
114 END beh; No newline at end of file
115
116 END beh;
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