@@ -1,121 +1,121 | |||
|
1 | ------------------------------------------------------------------------------ | |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
|
4 | -- | |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
|
6 | -- it under the terms of the GNU General Public License as published by | |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
|
8 | -- (at your option) any later version. | |
|
9 | -- | |
|
10 | -- This program is distributed in the hope that it will be useful, | |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
|
13 | -- GNU General Public License for more details. | |
|
14 | -- | |
|
15 | -- You should have received a copy of the GNU General Public License | |
|
16 | -- along with this program; if not, write to the Free Software | |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
|
18 | ------------------------------------------------------------------------------- | |
|
19 | -- Author : Alexis Jeandet | |
|
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr | |
|
21 | ---------------------------------------------------------------------------- | |
|
22 | LIBRARY IEEE; | |
|
23 | USE IEEE.numeric_std.ALL; | |
|
24 | USE IEEE.std_logic_1164.ALL; | |
|
25 | LIBRARY lpp; | |
|
26 | USE lpp.iir_filter.ALL; | |
|
27 | USE lpp.FILTERcfg.ALL; | |
|
28 | USE lpp.general_purpose.ALL; | |
|
29 | LIBRARY techmap; | |
|
30 | USE techmap.gencomp.ALL; | |
|
31 | ||
|
32 | ENTITY RAM_CTRLR_v2 IS | |
|
33 | GENERIC( | |
|
34 | tech : INTEGER := 0; | |
|
35 | Input_SZ_1 : INTEGER := 16; | |
|
36 | Mem_use : INTEGER := use_RAM | |
|
37 | ); | |
|
38 | PORT( | |
|
39 | rstn : IN STD_LOGIC; | |
|
40 | clk : IN STD_LOGIC; | |
|
41 | -- R/W Ctrl | |
|
42 | ram_write : IN STD_LOGIC; | |
|
43 | ram_read : IN STD_LOGIC; | |
|
44 | -- ADDR Ctrl | |
|
45 | raddr_rst : IN STD_LOGIC; | |
|
46 | raddr_add1 : IN STD_LOGIC; | |
|
47 | waddr_previous : IN STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
48 | -- Data | |
|
49 | sample_in : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); | |
|
50 | sample_out : OUT STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0) | |
|
51 | ); | |
|
52 | END RAM_CTRLR_v2; | |
|
53 | ||
|
54 | ||
|
55 | ARCHITECTURE ar_RAM_CTRLR_v2 OF RAM_CTRLR_v2 IS | |
|
56 | ||
|
57 | SIGNAL WD : STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); | |
|
58 | SIGNAL RD : STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); | |
|
59 |
|
|
|
60 | SIGNAL RADDR : STD_LOGIC_VECTOR(7 DOWNTO 0); | |
|
61 | SIGNAL WADDR : STD_LOGIC_VECTOR(7 DOWNTO 0); | |
|
62 | SIGNAL counter : STD_LOGIC_VECTOR(7 DOWNTO 0); | |
|
63 | ||
|
64 | BEGIN | |
|
65 | ||
|
66 | sample_out <= RD(Input_SZ_1-1 DOWNTO 0); | |
|
67 | WD(Input_SZ_1-1 DOWNTO 0) <= sample_in; | |
|
68 | ----------------------------------------------------------------------------- | |
|
69 | -- RAM | |
|
70 | ----------------------------------------------------------------------------- | |
|
71 | ||
|
72 | memCEL : IF Mem_use = use_CEL GENERATE | |
|
73 | WEN <= NOT ram_write; | |
|
74 | REN <= NOT ram_read; | |
|
75 | -- RAMblk : RAM_CEL_N | |
|
76 | RAMblk : RAM_CEL_N | |
|
77 | GENERIC MAP(Input_SZ_1) | |
|
78 | PORT MAP( | |
|
79 | WD => WD, | |
|
80 | RD => RD, | |
|
81 | WEN => WEN, | |
|
82 | REN => REN, | |
|
83 | WADDR => WADDR, | |
|
84 | RADDR => RADDR, | |
|
85 | RWCLK => clk, | |
|
86 | RESET => rstn | |
|
87 | ) ; | |
|
88 | END GENERATE; | |
|
89 | ||
|
90 | memRAM : IF Mem_use = use_RAM GENERATE | |
|
91 | SRAM : syncram_2p | |
|
92 | GENERIC MAP(tech, 8, Input_SZ_1) | |
|
93 | PORT MAP(clk, ram_read, RADDR, RD, clk, ram_write, WADDR, WD); | |
|
94 | END GENERATE; | |
|
95 | ||
|
96 | ----------------------------------------------------------------------------- | |
|
97 | -- RADDR | |
|
98 | ----------------------------------------------------------------------------- | |
|
99 | PROCESS (clk, rstn) | |
|
100 | BEGIN -- PROCESS | |
|
101 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
|
102 | counter <= (OTHERS => '0'); | |
|
103 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |
|
104 | IF raddr_rst = '1' THEN | |
|
105 | counter <= (OTHERS => '0'); | |
|
106 | ELSIF raddr_add1 = '1' THEN | |
|
107 | counter <= STD_LOGIC_VECTOR(UNSIGNED(counter)+1); | |
|
108 | END IF; | |
|
109 | END IF; | |
|
110 | END PROCESS; | |
|
111 | RADDR <= counter; | |
|
112 | ||
|
113 | ----------------------------------------------------------------------------- | |
|
114 | -- WADDR | |
|
115 | ----------------------------------------------------------------------------- | |
|
116 | WADDR <= STD_LOGIC_VECTOR(UNSIGNED(counter)-2) WHEN waddr_previous = "10" ELSE | |
|
117 | STD_LOGIC_VECTOR(UNSIGNED(counter)-1) WHEN waddr_previous = "01" ELSE | |
|
118 | STD_LOGIC_VECTOR(UNSIGNED(counter)); | |
|
119 | ||
|
120 | ||
|
121 |
END ar_RAM_CTRLR_v2; |
|
|
1 | ------------------------------------------------------------------------------ | |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
|
4 | -- | |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
|
6 | -- it under the terms of the GNU General Public License as published by | |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
|
8 | -- (at your option) any later version. | |
|
9 | -- | |
|
10 | -- This program is distributed in the hope that it will be useful, | |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
|
13 | -- GNU General Public License for more details. | |
|
14 | -- | |
|
15 | -- You should have received a copy of the GNU General Public License | |
|
16 | -- along with this program; if not, write to the Free Software | |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
|
18 | ------------------------------------------------------------------------------- | |
|
19 | -- Author : Alexis Jeandet | |
|
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr | |
|
21 | ---------------------------------------------------------------------------- | |
|
22 | LIBRARY IEEE; | |
|
23 | USE IEEE.numeric_std.ALL; | |
|
24 | USE IEEE.std_logic_1164.ALL; | |
|
25 | LIBRARY lpp; | |
|
26 | USE lpp.iir_filter.ALL; | |
|
27 | USE lpp.FILTERcfg.ALL; | |
|
28 | USE lpp.general_purpose.ALL; | |
|
29 | LIBRARY techmap; | |
|
30 | USE techmap.gencomp.ALL; | |
|
31 | ||
|
32 | ENTITY RAM_CTRLR_v2 IS | |
|
33 | GENERIC( | |
|
34 | tech : INTEGER := 0; | |
|
35 | Input_SZ_1 : INTEGER := 16; | |
|
36 | Mem_use : INTEGER := use_RAM | |
|
37 | ); | |
|
38 | PORT( | |
|
39 | rstn : IN STD_LOGIC; | |
|
40 | clk : IN STD_LOGIC; | |
|
41 | -- R/W Ctrl | |
|
42 | ram_write : IN STD_LOGIC; | |
|
43 | ram_read : IN STD_LOGIC; | |
|
44 | -- ADDR Ctrl | |
|
45 | raddr_rst : IN STD_LOGIC; | |
|
46 | raddr_add1 : IN STD_LOGIC; | |
|
47 | waddr_previous : IN STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
48 | -- Data | |
|
49 | sample_in : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); | |
|
50 | sample_out : OUT STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0) | |
|
51 | ); | |
|
52 | END RAM_CTRLR_v2; | |
|
53 | ||
|
54 | ||
|
55 | ARCHITECTURE ar_RAM_CTRLR_v2 OF RAM_CTRLR_v2 IS | |
|
56 | ||
|
57 | SIGNAL WD : STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); | |
|
58 | SIGNAL RD : STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); | |
|
59 | SIGNAL WEN, REN : STD_LOGIC; | |
|
60 | SIGNAL RADDR : STD_LOGIC_VECTOR(7 DOWNTO 0); | |
|
61 | SIGNAL WADDR : STD_LOGIC_VECTOR(7 DOWNTO 0); | |
|
62 | SIGNAL counter : STD_LOGIC_VECTOR(7 DOWNTO 0); | |
|
63 | ||
|
64 | BEGIN | |
|
65 | ||
|
66 | sample_out <= RD(Input_SZ_1-1 DOWNTO 0); | |
|
67 | WD(Input_SZ_1-1 DOWNTO 0) <= sample_in; | |
|
68 | ----------------------------------------------------------------------------- | |
|
69 | -- RAM | |
|
70 | ----------------------------------------------------------------------------- | |
|
71 | ||
|
72 | memCEL : IF Mem_use = use_CEL GENERATE | |
|
73 | WEN <= NOT ram_write; | |
|
74 | REN <= NOT ram_read; | |
|
75 | -- RAMblk : RAM_CEL_N | |
|
76 | RAMblk : RAM_CEL_N | |
|
77 | GENERIC MAP(Input_SZ_1) | |
|
78 | PORT MAP( | |
|
79 | WD => WD, | |
|
80 | RD => RD, | |
|
81 | WEN => WEN, | |
|
82 | REN => REN, | |
|
83 | WADDR => WADDR, | |
|
84 | RADDR => RADDR, | |
|
85 | RWCLK => clk, | |
|
86 | RESET => rstn | |
|
87 | ) ; | |
|
88 | END GENERATE; | |
|
89 | ||
|
90 | memRAM : IF Mem_use = use_RAM GENERATE | |
|
91 | SRAM : syncram_2p | |
|
92 | GENERIC MAP(tech, 8, Input_SZ_1) | |
|
93 | PORT MAP(clk, ram_read, RADDR, RD, clk, ram_write, WADDR, WD); | |
|
94 | END GENERATE; | |
|
95 | ||
|
96 | ----------------------------------------------------------------------------- | |
|
97 | -- RADDR | |
|
98 | ----------------------------------------------------------------------------- | |
|
99 | PROCESS (clk, rstn) | |
|
100 | BEGIN -- PROCESS | |
|
101 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
|
102 | counter <= (OTHERS => '0'); | |
|
103 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |
|
104 | IF raddr_rst = '1' THEN | |
|
105 | counter <= (OTHERS => '0'); | |
|
106 | ELSIF raddr_add1 = '1' THEN | |
|
107 | counter <= STD_LOGIC_VECTOR(UNSIGNED(counter)+1); | |
|
108 | END IF; | |
|
109 | END IF; | |
|
110 | END PROCESS; | |
|
111 | RADDR <= counter; | |
|
112 | ||
|
113 | ----------------------------------------------------------------------------- | |
|
114 | -- WADDR | |
|
115 | ----------------------------------------------------------------------------- | |
|
116 | WADDR <= STD_LOGIC_VECTOR(UNSIGNED(counter)-2) WHEN waddr_previous = "10" ELSE | |
|
117 | STD_LOGIC_VECTOR(UNSIGNED(counter)-1) WHEN waddr_previous = "01" ELSE | |
|
118 | STD_LOGIC_VECTOR(UNSIGNED(counter)); | |
|
119 | ||
|
120 | ||
|
121 | END ar_RAM_CTRLR_v2; No newline at end of file |
@@ -205,4 +205,4 BEGIN | |||
|
205 | 205 | apbo.pconfig <= pconfig; |
|
206 | 206 | apbo.pindex <= pindex; |
|
207 | 207 | |
|
208 |
END Behavioral; |
|
|
208 | END Behavioral; No newline at end of file |
@@ -1,197 +1,196 | |||
|
1 | ------------------------------------------------------------------------------ | |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
|
4 | -- | |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
|
6 | -- it under the terms of the GNU General Public License as published by | |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
|
8 | -- (at your option) any later version. | |
|
9 | -- | |
|
10 | -- This program is distributed in the hope that it will be useful, | |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
|
13 | -- GNU General Public License for more details. | |
|
14 | -- | |
|
15 | -- You should have received a copy of the GNU General Public License | |
|
16 | -- along with this program; if not, write to the Free Software | |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
|
18 | ------------------------------------------------------------------------------- | |
|
19 | -- Author : Alexis Jeandet | |
|
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr | |
|
21 | ------------------------------------------------------------------------------- | |
|
22 | -- MODIFIED by Jean-christophe PELLION | |
|
23 | -- jean-christophe.pellion@lpp.polytechnique.fr | |
|
24 | ------------------------------------------------------------------------------- | |
|
25 | LIBRARY IEEE; | |
|
26 | USE IEEE.STD_LOGIC_1164.ALL; | |
|
27 | LIBRARY lpp; | |
|
28 | USE lpp.lpp_ad_conv.ALL; | |
|
29 | USE lpp.general_purpose.SYNC_FF; | |
|
30 | ||
|
31 | ENTITY AD7688_drvr IS | |
|
32 | GENERIC( | |
|
33 | ChanelCount : INTEGER; | |
|
34 | ncycle_cnv_high : INTEGER := 79; | |
|
35 | ncycle_cnv : INTEGER := 500); | |
|
36 | PORT ( | |
|
37 | -- CONV -- | |
|
38 | cnv_clk : IN STD_LOGIC; | |
|
39 | cnv_rstn : IN STD_LOGIC; | |
|
40 | cnv_run : IN STD_LOGIC; | |
|
41 | cnv : OUT STD_LOGIC; | |
|
42 | ||
|
43 | -- DATA -- | |
|
44 | clk : IN STD_LOGIC; | |
|
45 | rstn : IN STD_LOGIC; | |
|
46 | sck : OUT STD_LOGIC; | |
|
47 | sdo : IN STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0); | |
|
48 | ||
|
49 | sample : OUT Samples(ChanelCount-1 DOWNTO 0); | |
|
50 | sample_val : OUT STD_LOGIC | |
|
51 | ); | |
|
52 | END AD7688_drvr; | |
|
53 | ||
|
54 | ARCHITECTURE ar_AD7688_drvr OF AD7688_drvr IS | |
|
55 | ||
|
56 | COMPONENT SYNC_FF | |
|
57 | GENERIC ( | |
|
58 | NB_FF_OF_SYNC : INTEGER); | |
|
59 | PORT ( | |
|
60 | clk : IN STD_LOGIC; | |
|
61 | rstn : IN STD_LOGIC; | |
|
62 | A : IN STD_LOGIC; | |
|
63 | A_sync : OUT STD_LOGIC); | |
|
64 | END COMPONENT; | |
|
65 | ||
|
66 | ||
|
67 | SIGNAL cnv_cycle_counter : INTEGER; | |
|
68 | SIGNAL cnv_s : STD_LOGIC; | |
|
69 | SIGNAL cnv_sync : STD_LOGIC; | |
|
70 | SIGNAL cnv_sync_r : STD_LOGIC; | |
|
71 | SIGNAL cnv_done : STD_LOGIC; | |
|
72 | SIGNAL sample_bit_counter : INTEGER; | |
|
73 | SIGNAL shift_reg : Samples(ChanelCount-1 DOWNTO 0); | |
|
74 | ||
|
75 | SIGNAL cnv_run_sync : STD_LOGIC; | |
|
76 | ||
|
77 | BEGIN | |
|
78 | ----------------------------------------------------------------------------- | |
|
79 | -- CONV | |
|
80 | ----------------------------------------------------------------------------- | |
|
81 | PROCESS (cnv_clk, cnv_rstn) | |
|
82 | BEGIN -- PROCESS | |
|
83 | IF cnv_rstn = '0' THEN -- asynchronous reset (active low) | |
|
84 | cnv_cycle_counter <= 0; | |
|
85 | cnv_s <= '0'; | |
|
86 | ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge | |
|
87 | IF cnv_run = '1' THEN | |
|
88 | IF cnv_cycle_counter < ncycle_cnv THEN | |
|
89 | cnv_cycle_counter <= cnv_cycle_counter +1; | |
|
90 | IF cnv_cycle_counter < ncycle_cnv_high THEN | |
|
91 | cnv_s <= '1'; | |
|
92 | ELSE | |
|
93 | cnv_s <= '0'; | |
|
94 | END IF; | |
|
95 | ELSE | |
|
96 | cnv_s <= '1'; | |
|
97 | cnv_cycle_counter <= 0; | |
|
98 | END IF; | |
|
99 | ELSE | |
|
100 | cnv_s <= '0'; | |
|
101 | cnv_cycle_counter <= 0; | |
|
102 | END IF; | |
|
103 | END IF; | |
|
104 | END PROCESS; | |
|
105 | ||
|
106 | cnv <= cnv_s; | |
|
107 | ||
|
108 | ----------------------------------------------------------------------------- | |
|
109 | ||
|
110 | ||
|
111 | ----------------------------------------------------------------------------- | |
|
112 | -- SYNC CNV | |
|
113 | ----------------------------------------------------------------------------- | |
|
114 | ||
|
115 | SYNC_FF_cnv : SYNC_FF | |
|
116 | GENERIC MAP ( | |
|
117 | NB_FF_OF_SYNC => 2) | |
|
118 | PORT MAP ( | |
|
119 | clk => clk, | |
|
120 | rstn => rstn, | |
|
121 | A => cnv_s, | |
|
122 | A_sync => cnv_sync); | |
|
123 | ||
|
124 | PROCESS (clk, rstn) | |
|
125 | BEGIN | |
|
126 | IF rstn = '0' THEN | |
|
127 | cnv_sync_r <= '0'; | |
|
128 | cnv_done <= '0'; | |
|
129 | ELSIF clk'EVENT AND clk = '1' THEN | |
|
130 | cnv_sync_r <= cnv_sync; | |
|
131 | cnv_done <= (NOT cnv_sync) AND cnv_sync_r; | |
|
132 | END IF; | |
|
133 | END PROCESS; | |
|
134 | ||
|
135 | ----------------------------------------------------------------------------- | |
|
136 | ||
|
137 | SYNC_FF_run : SYNC_FF | |
|
138 | GENERIC MAP ( | |
|
139 | NB_FF_OF_SYNC => 2) | |
|
140 | PORT MAP ( | |
|
141 | clk => clk, | |
|
142 | rstn => rstn, | |
|
143 | A => cnv_run, | |
|
144 | A_sync => cnv_run_sync); | |
|
145 | ||
|
146 | ||
|
147 | ||
|
148 | ----------------------------------------------------------------------------- | |
|
149 | -- DATA | |
|
150 | ----------------------------------------------------------------------------- | |
|
151 | PROCESS (clk, rstn) | |
|
152 | BEGIN -- PROCESS | |
|
153 | IF rstn = '0' THEN | |
|
154 | FOR l IN 0 TO ChanelCount-1 LOOP | |
|
155 | shift_reg(l) <= (OTHERS => '0'); | |
|
156 | END LOOP; | |
|
157 | sample_bit_counter <= 0; | |
|
158 | sample_val <= '0'; | |
|
159 | SCK <= '1'; | |
|
160 | ELSIF clk'EVENT AND clk = '1' THEN | |
|
161 | ||
|
162 | IF cnv_run_sync = '0' THEN | |
|
163 | sample_bit_counter <= 0; | |
|
164 | ELSIF cnv_done = '1' THEN | |
|
165 | sample_bit_counter <= 1; | |
|
166 | ELSIF sample_bit_counter > 0 AND sample_bit_counter < 32 THEN | |
|
167 | sample_bit_counter <= sample_bit_counter + 1; | |
|
168 | END IF; | |
|
169 | ||
|
170 | IF (sample_bit_counter MOD 2) = 1 THEN | |
|
171 | FOR l IN 0 TO ChanelCount-1 LOOP | |
|
172 | --shift_reg(l)(15) <= sdo(l); | |
|
173 | --shift_reg(l)(14 DOWNTO 0) <= shift_reg(l)(15 DOWNTO 1); | |
|
174 | shift_reg(l)(0) <= sdo(l); | |
|
175 |
shift_reg(l)(1 |
|
|
176 | END LOOP; | |
|
177 | SCK <= '0'; | |
|
178 | ELSE | |
|
179 | SCK <= '1'; | |
|
180 | END IF; | |
|
181 | ||
|
182 | IF sample_bit_counter = 31 THEN | |
|
183 | sample_val <= '1'; | |
|
184 | FOR l IN 0 TO ChanelCount-1 LOOP | |
|
185 | --sample(l)(15) <= sdo(l); | |
|
186 | --sample(l)(14 DOWNTO 0) <= shift_reg(l)(15 DOWNTO 1); | |
|
187 | sample(l)(0) <= sdo(l); | |
|
188 | sample(l)(15 DOWNTO 1) <= shift_reg(l)(14 DOWNTO 0); | |
|
189 | END LOOP; | |
|
190 | ELSE | |
|
191 | sample_val <= '0'; | |
|
192 | END IF; | |
|
193 | END IF; | |
|
194 | END PROCESS; | |
|
195 | ||
|
196 | END ar_AD7688_drvr; | |
|
197 | ||
|
1 | ------------------------------------------------------------------------------ | |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
|
4 | -- | |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
|
6 | -- it under the terms of the GNU General Public License as published by | |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
|
8 | -- (at your option) any later version. | |
|
9 | -- | |
|
10 | -- This program is distributed in the hope that it will be useful, | |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
|
13 | -- GNU General Public License for more details. | |
|
14 | -- | |
|
15 | -- You should have received a copy of the GNU General Public License | |
|
16 | -- along with this program; if not, write to the Free Software | |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
|
18 | ------------------------------------------------------------------------------- | |
|
19 | -- Author : Alexis Jeandet | |
|
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr | |
|
21 | ------------------------------------------------------------------------------- | |
|
22 | -- MODIFIED by Jean-christophe PELLION | |
|
23 | -- jean-christophe.pellion@lpp.polytechnique.fr | |
|
24 | ------------------------------------------------------------------------------- | |
|
25 | LIBRARY IEEE; | |
|
26 | USE IEEE.STD_LOGIC_1164.ALL; | |
|
27 | LIBRARY lpp; | |
|
28 | USE lpp.lpp_ad_conv.ALL; | |
|
29 | USE lpp.general_purpose.SYNC_FF; | |
|
30 | ||
|
31 | ENTITY AD7688_drvr IS | |
|
32 | GENERIC( | |
|
33 | ChanelCount : INTEGER; | |
|
34 | ncycle_cnv_high : INTEGER := 79; | |
|
35 | ncycle_cnv : INTEGER := 500); | |
|
36 | PORT ( | |
|
37 | -- CONV -- | |
|
38 | cnv_clk : IN STD_LOGIC; | |
|
39 | cnv_rstn : IN STD_LOGIC; | |
|
40 | cnv_run : IN STD_LOGIC; | |
|
41 | cnv : OUT STD_LOGIC; | |
|
42 | ||
|
43 | -- DATA -- | |
|
44 | clk : IN STD_LOGIC; | |
|
45 | rstn : IN STD_LOGIC; | |
|
46 | sck : OUT STD_LOGIC; | |
|
47 | sdo : IN STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0); | |
|
48 | ||
|
49 | sample : OUT Samples(ChanelCount-1 DOWNTO 0); | |
|
50 | sample_val : OUT STD_LOGIC | |
|
51 | ); | |
|
52 | END AD7688_drvr; | |
|
53 | ||
|
54 | ARCHITECTURE ar_AD7688_drvr OF AD7688_drvr IS | |
|
55 | ||
|
56 | COMPONENT SYNC_FF | |
|
57 | GENERIC ( | |
|
58 | NB_FF_OF_SYNC : INTEGER); | |
|
59 | PORT ( | |
|
60 | clk : IN STD_LOGIC; | |
|
61 | rstn : IN STD_LOGIC; | |
|
62 | A : IN STD_LOGIC; | |
|
63 | A_sync : OUT STD_LOGIC); | |
|
64 | END COMPONENT; | |
|
65 | ||
|
66 | ||
|
67 | SIGNAL cnv_cycle_counter : INTEGER; | |
|
68 | SIGNAL cnv_s : STD_LOGIC; | |
|
69 | SIGNAL cnv_sync : STD_LOGIC; | |
|
70 | SIGNAL cnv_sync_r : STD_LOGIC; | |
|
71 | SIGNAL cnv_done : STD_LOGIC; | |
|
72 | SIGNAL sample_bit_counter : INTEGER; | |
|
73 | SIGNAL shift_reg : Samples(ChanelCount-1 DOWNTO 0); | |
|
74 | ||
|
75 | SIGNAL cnv_run_sync : STD_LOGIC; | |
|
76 | ||
|
77 | BEGIN | |
|
78 | ----------------------------------------------------------------------------- | |
|
79 | -- CONV | |
|
80 | ----------------------------------------------------------------------------- | |
|
81 | PROCESS (cnv_clk, cnv_rstn) | |
|
82 | BEGIN -- PROCESS | |
|
83 | IF cnv_rstn = '0' THEN -- asynchronous reset (active low) | |
|
84 | cnv_cycle_counter <= 0; | |
|
85 | cnv_s <= '0'; | |
|
86 | ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge | |
|
87 | IF cnv_run = '1' THEN | |
|
88 | IF cnv_cycle_counter < ncycle_cnv THEN | |
|
89 | cnv_cycle_counter <= cnv_cycle_counter +1; | |
|
90 | IF cnv_cycle_counter < ncycle_cnv_high THEN | |
|
91 | cnv_s <= '1'; | |
|
92 | ELSE | |
|
93 | cnv_s <= '0'; | |
|
94 | END IF; | |
|
95 | ELSE | |
|
96 | cnv_s <= '1'; | |
|
97 | cnv_cycle_counter <= 0; | |
|
98 | END IF; | |
|
99 | ELSE | |
|
100 | cnv_s <= '0'; | |
|
101 | cnv_cycle_counter <= 0; | |
|
102 | END IF; | |
|
103 | END IF; | |
|
104 | END PROCESS; | |
|
105 | ||
|
106 | cnv <= cnv_s; | |
|
107 | ||
|
108 | ----------------------------------------------------------------------------- | |
|
109 | ||
|
110 | ||
|
111 | ----------------------------------------------------------------------------- | |
|
112 | -- SYNC CNV | |
|
113 | ----------------------------------------------------------------------------- | |
|
114 | ||
|
115 | SYNC_FF_cnv : SYNC_FF | |
|
116 | GENERIC MAP ( | |
|
117 | NB_FF_OF_SYNC => 2) | |
|
118 | PORT MAP ( | |
|
119 | clk => clk, | |
|
120 | rstn => rstn, | |
|
121 | A => cnv_s, | |
|
122 | A_sync => cnv_sync); | |
|
123 | ||
|
124 | PROCESS (clk, rstn) | |
|
125 | BEGIN | |
|
126 | IF rstn = '0' THEN | |
|
127 | cnv_sync_r <= '0'; | |
|
128 | cnv_done <= '0'; | |
|
129 | ELSIF clk'EVENT AND clk = '1' THEN | |
|
130 | cnv_sync_r <= cnv_sync; | |
|
131 | cnv_done <= (NOT cnv_sync) AND cnv_sync_r; | |
|
132 | END IF; | |
|
133 | END PROCESS; | |
|
134 | ||
|
135 | ----------------------------------------------------------------------------- | |
|
136 | ||
|
137 | SYNC_FF_run : SYNC_FF | |
|
138 | GENERIC MAP ( | |
|
139 | NB_FF_OF_SYNC => 2) | |
|
140 | PORT MAP ( | |
|
141 | clk => clk, | |
|
142 | rstn => rstn, | |
|
143 | A => cnv_run, | |
|
144 | A_sync => cnv_run_sync); | |
|
145 | ||
|
146 | ||
|
147 | ||
|
148 | ----------------------------------------------------------------------------- | |
|
149 | -- DATA | |
|
150 | ----------------------------------------------------------------------------- | |
|
151 | PROCESS (clk, rstn) | |
|
152 | BEGIN -- PROCESS | |
|
153 | IF rstn = '0' THEN | |
|
154 | FOR l IN 0 TO ChanelCount-1 LOOP | |
|
155 | shift_reg(l) <= (OTHERS => '0'); | |
|
156 | END LOOP; | |
|
157 | sample_bit_counter <= 0; | |
|
158 | sample_val <= '0'; | |
|
159 | SCK <= '1'; | |
|
160 | ELSIF clk'EVENT AND clk = '1' THEN | |
|
161 | ||
|
162 | IF cnv_run_sync = '0' THEN | |
|
163 | sample_bit_counter <= 0; | |
|
164 | ELSIF cnv_done = '1' THEN | |
|
165 | sample_bit_counter <= 1; | |
|
166 | ELSIF sample_bit_counter > 0 AND sample_bit_counter < 32 THEN | |
|
167 | sample_bit_counter <= sample_bit_counter + 1; | |
|
168 | END IF; | |
|
169 | ||
|
170 | IF (sample_bit_counter MOD 2) = 1 THEN | |
|
171 | FOR l IN 0 TO ChanelCount-1 LOOP | |
|
172 | --shift_reg(l)(15) <= sdo(l); | |
|
173 | --shift_reg(l)(14 DOWNTO 0) <= shift_reg(l)(15 DOWNTO 1); | |
|
174 | shift_reg(l)(0) <= sdo(l); | |
|
175 | shift_reg(l)(14 DOWNTO 1) <= shift_reg(l)(13 DOWNTO 0); | |
|
176 | END LOOP; | |
|
177 | SCK <= '0'; | |
|
178 | ELSE | |
|
179 | SCK <= '1'; | |
|
180 | END IF; | |
|
181 | ||
|
182 | IF sample_bit_counter = 31 THEN | |
|
183 | sample_val <= '1'; | |
|
184 | FOR l IN 0 TO ChanelCount-1 LOOP | |
|
185 | --sample(l)(15) <= sdo(l); | |
|
186 | --sample(l)(14 DOWNTO 0) <= shift_reg(l)(15 DOWNTO 1); | |
|
187 | sample(l)(0) <= sdo(l); | |
|
188 | sample(l)(15 DOWNTO 1) <= shift_reg(l)(14 DOWNTO 0); | |
|
189 | END LOOP; | |
|
190 | ELSE | |
|
191 | sample_val <= '0'; | |
|
192 | END IF; | |
|
193 | END IF; | |
|
194 | END PROCESS; | |
|
195 | ||
|
196 | END ar_AD7688_drvr; |
@@ -405,4 +405,4 BEGIN -- beh | |||
|
405 | 405 | apbo.prdata <= prdata; |
|
406 | 406 | |
|
407 | 407 | |
|
408 |
END beh; |
|
|
408 | END beh; No newline at end of file |
@@ -1,245 +1,253 | |||
|
1 | LIBRARY ieee; | |
|
2 | USE ieee.std_logic_1164.ALL; | |
|
3 | USE ieee.numeric_std.ALL; | |
|
4 | ||
|
5 | LIBRARY lpp; | |
|
6 | USE lpp.lpp_ad_conv.ALL; | |
|
7 | USE lpp.iir_filter.ALL; | |
|
8 | USE lpp.FILTERcfg.ALL; | |
|
9 | USE lpp.lpp_memory.ALL; | |
|
10 | USE lpp.lpp_waveform_pkg.ALL; | |
|
11 | USE lpp.lpp_top_lfr_pkg.ALL; | |
|
12 | ||
|
13 | LIBRARY techmap; | |
|
14 | USE techmap.gencomp.ALL; | |
|
15 | ||
|
16 | LIBRARY grlib; | |
|
17 | USE grlib.amba.ALL; | |
|
18 | USE grlib.stdlib.ALL; | |
|
19 | USE grlib.devices.ALL; | |
|
20 | USE GRLIB.DMA2AHB_Package.ALL; | |
|
21 | ||
|
22 | ENTITY lpp_top_lfr_wf_picker IS | |
|
23 | GENERIC ( | |
|
24 | hindex : INTEGER := 2; | |
|
25 |
pindex : INTEGER := |
|
|
26 |
paddr : INTEGER := |
|
|
27 | pmask : INTEGER := 16#fff#; | |
|
28 |
pirq : INTEGER := |
|
|
29 | tech : INTEGER := 0; | |
|
30 | nb_burst_available_size : INTEGER := 11; | |
|
31 | nb_snapshot_param_size : INTEGER := 11; | |
|
32 | delta_snapshot_size : INTEGER := 16; | |
|
33 | delta_f2_f0_size : INTEGER := 10; | |
|
34 | delta_f2_f1_size : INTEGER := 10 | |
|
35 | ); | |
|
36 | PORT ( | |
|
37 | -- ADS7886 | |
|
38 | cnv_run : IN STD_LOGIC; | |
|
39 | cnv : OUT STD_LOGIC; | |
|
40 | sck : OUT STD_LOGIC; | |
|
41 | sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0); | |
|
42 | -- | |
|
43 | cnv_clk : IN STD_LOGIC; | |
|
44 | cnv_rstn : IN STD_LOGIC; | |
|
45 | ||
|
46 | -- AMBA AHB system signals | |
|
47 | HCLK : IN STD_ULOGIC; | |
|
48 | HRESETn : IN STD_ULOGIC; | |
|
49 | ||
|
50 | -- AMBA APB Slave Interface | |
|
51 | apbi : IN apb_slv_in_type; | |
|
52 | apbo : OUT apb_slv_out_type; | |
|
53 | ||
|
54 | -- AMBA AHB Master Interface | |
|
55 | AHB_Master_In : IN AHB_Mst_In_Type; | |
|
56 | AHB_Master_Out : OUT AHB_Mst_Out_Type; | |
|
57 | ||
|
58 | -- | |
|
59 | coarse_time_0 : IN STD_LOGIC; | |
|
60 | ||
|
61 | -- | |
|
62 | data_shaping_BW : OUT STD_LOGIC | |
|
63 | ); | |
|
64 | END lpp_top_lfr_wf_picker; | |
|
65 | ||
|
66 | ARCHITECTURE tb OF lpp_top_lfr_wf_picker IS | |
|
67 | ||
|
68 | SIGNAL ready_matrix_f0_0 : STD_LOGIC; | |
|
69 | SIGNAL ready_matrix_f0_1 : STD_LOGIC; | |
|
70 | SIGNAL ready_matrix_f1 : STD_LOGIC; | |
|
71 | SIGNAL ready_matrix_f2 : STD_LOGIC; | |
|
72 | SIGNAL error_anticipating_empty_fifo : STD_LOGIC; | |
|
73 | SIGNAL error_bad_component_error : STD_LOGIC; | |
|
74 | SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
75 | SIGNAL status_ready_matrix_f0_0 : STD_LOGIC; | |
|
76 | SIGNAL status_ready_matrix_f0_1 : STD_LOGIC; | |
|
77 | SIGNAL status_ready_matrix_f1 : STD_LOGIC; | |
|
78 | SIGNAL status_ready_matrix_f2 : STD_LOGIC; | |
|
79 | SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC; | |
|
80 | SIGNAL status_error_bad_component_error : STD_LOGIC; | |
|
81 | SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC; | |
|
82 | SIGNAL config_active_interruption_onError : STD_LOGIC; | |
|
83 | SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
84 | SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
85 | SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
86 | SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
87 | ||
|
88 | SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
89 | SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
90 | SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
91 | SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
92 | SIGNAL data_shaping_SP0 : STD_LOGIC; | |
|
93 | SIGNAL data_shaping_SP1 : STD_LOGIC; | |
|
94 | SIGNAL data_shaping_R0 : STD_LOGIC; | |
|
95 | SIGNAL data_shaping_R1 : STD_LOGIC; | |
|
96 | SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); | |
|
97 | SIGNAL delta_f2_f1 : STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); | |
|
98 | SIGNAL delta_f2_f0 : STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); | |
|
99 | SIGNAL nb_burst_available : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); | |
|
100 | SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |
|
101 | SIGNAL enable_f0 : STD_LOGIC; | |
|
102 | SIGNAL enable_f1 : STD_LOGIC; | |
|
103 | SIGNAL enable_f2 : STD_LOGIC; | |
|
104 | SIGNAL enable_f3 : STD_LOGIC; | |
|
105 | SIGNAL burst_f0 : STD_LOGIC; | |
|
106 | SIGNAL burst_f1 : STD_LOGIC; | |
|
107 | SIGNAL burst_f2 : STD_LOGIC; | |
|
108 | SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
109 | SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
110 | SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
111 | SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
112 | ||
|
113 | SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(5 DOWNTO 0); | |
|
114 | SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
|
115 | SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(5 DOWNTO 0); | |
|
116 | SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
|
117 | SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(5 DOWNTO 0); | |
|
118 | SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
|
119 | SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(5 DOWNTO 0); | |
|
120 | SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
|
121 | ||
|
122 | ||
|
123 | BEGIN | |
|
124 | ||
|
125 | lpp_top_apbreg_1: lpp_top_apbreg | |
|
126 | GENERIC MAP ( | |
|
127 | nb_burst_available_size => nb_burst_available_size, | |
|
128 | nb_snapshot_param_size => nb_snapshot_param_size, | |
|
129 | delta_snapshot_size => delta_snapshot_size, | |
|
130 | delta_f2_f0_size => delta_f2_f0_size, | |
|
131 | delta_f2_f1_size => delta_f2_f1_size, | |
|
132 | pindex => pindex, | |
|
133 | paddr => paddr, | |
|
134 | pmask => pmask, | |
|
135 | pirq => pirq) | |
|
136 | PORT MAP ( | |
|
137 | HCLK => HCLK, | |
|
138 | HRESETn => HRESETn, | |
|
139 | apbi => apbi, | |
|
140 |
|
|
|
141 | ||
|
142 |
|
|
|
143 | ready_matrix_f0_1 => ready_matrix_f0_1, | |
|
144 | ready_matrix_f1 => ready_matrix_f1, | |
|
145 | ready_matrix_f2 => ready_matrix_f2, | |
|
146 | error_anticipating_empty_fifo => error_anticipating_empty_fifo, | |
|
147 | error_bad_component_error => error_bad_component_error, | |
|
148 |
|
|
|
149 | status_ready_matrix_f0_0 => status_ready_matrix_f0_0, | |
|
150 |
|
|
|
151 |
|
|
|
152 |
|
|
|
153 | status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo, | |
|
154 | status_error_bad_component_error => status_error_bad_component_error, | |
|
155 | config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, | |
|
156 | config_active_interruption_onError => config_active_interruption_onError, | |
|
157 |
|
|
|
158 |
|
|
|
159 |
|
|
|
160 |
|
|
|
161 | ||
|
162 | status_full => status_full, | |
|
163 | status_full_ack => status_full_ack, | |
|
164 | status_full_err => status_full_err, | |
|
165 |
|
|
|
166 |
|
|
|
167 |
|
|
|
168 |
|
|
|
169 | data_shaping_R0 => data_shaping_R0, | |
|
170 |
|
|
|
171 |
|
|
|
172 |
|
|
|
173 |
|
|
|
174 | nb_burst_available => nb_burst_available, | |
|
175 |
|
|
|
176 |
|
|
|
177 |
|
|
|
178 |
|
|
|
179 |
|
|
|
180 |
|
|
|
181 |
|
|
|
182 |
burst_ |
|
|
183 | addr_data_f0 => addr_data_f0, | |
|
184 |
|
|
|
185 |
|
|
|
186 |
|
|
|
187 | ||
|
188 | lpp_top_lfr_wf_picker_ip_1: lpp_top_lfr_wf_picker_ip | |
|
189 | GENERIC MAP ( | |
|
190 | hindex => hindex, | |
|
191 | nb_burst_available_size => nb_burst_available_size, | |
|
192 | nb_snapshot_param_size => nb_snapshot_param_size, | |
|
193 | delta_snapshot_size => delta_snapshot_size, | |
|
194 | delta_f2_f0_size => delta_f2_f0_size, | |
|
195 | delta_f2_f1_size => delta_f2_f1_size, | |
|
196 | tech => tech, | |
|
197 | Mem_use => use_RAM | |
|
198 | ) | |
|
199 | PORT MAP ( | |
|
200 | cnv_run => cnv_run, | |
|
201 | cnv => cnv, | |
|
202 | sck => sck, | |
|
203 | sdo => sdo, | |
|
204 |
|
|
|
205 | cnv_rstn => cnv_rstn, | |
|
206 | ||
|
207 | clk => HCLK, | |
|
208 |
|
|
|
209 | ||
|
210 | sample_f0_wen => sample_f0_wen, | |
|
211 | sample_f0_wdata => sample_f0_wdata, | |
|
212 | sample_f1_wen => sample_f1_wen, | |
|
213 | sample_f1_wdata => sample_f1_wdata, | |
|
214 | sample_f2_wen => sample_f2_wen, | |
|
215 | sample_f2_wdata => sample_f2_wdata, | |
|
216 | sample_f3_wen => sample_f3_wen, | |
|
217 | sample_f3_wdata => sample_f3_wdata, | |
|
218 | AHB_Master_In => AHB_Master_In, | |
|
219 | AHB_Master_Out => AHB_Master_Out, | |
|
220 | coarse_time_0 => coarse_time_0, | |
|
221 | data_shaping_SP0 => data_shaping_SP0, | |
|
222 | data_shaping_SP1 => data_shaping_SP1, | |
|
223 | data_shaping_R0 => data_shaping_R0, | |
|
224 | data_shaping_R1 => data_shaping_R1, | |
|
225 | delta_snapshot => delta_snapshot, | |
|
226 | delta_f2_f1 => delta_f2_f1, | |
|
227 | delta_f2_f0 => delta_f2_f0, | |
|
228 |
|
|
|
229 | enable_f1 => enable_f1, | |
|
230 | enable_f2 => enable_f2, | |
|
231 | enable_f3 => enable_f3, | |
|
232 | burst_f0 => burst_f0, | |
|
233 | burst_f1 => burst_f1, | |
|
234 |
|
|
|
235 | nb_burst_available => nb_burst_available, | |
|
236 | nb_snapshot_param => nb_snapshot_param, | |
|
237 |
|
|
|
238 | status_full_ack => status_full_ack, | |
|
239 | status_full_err => status_full_err, | |
|
240 | status_new_err => status_new_err, | |
|
241 |
|
|
|
242 |
|
|
|
243 | addr_data_f2 => addr_data_f2, | |
|
244 | addr_data_f3 => addr_data_f3); | |
|
245 | END tb; | |
|
1 | LIBRARY ieee; | |
|
2 | USE ieee.std_logic_1164.ALL; | |
|
3 | USE ieee.numeric_std.ALL; | |
|
4 | ||
|
5 | LIBRARY lpp; | |
|
6 | USE lpp.lpp_ad_conv.ALL; | |
|
7 | USE lpp.iir_filter.ALL; | |
|
8 | USE lpp.FILTERcfg.ALL; | |
|
9 | USE lpp.lpp_memory.ALL; | |
|
10 | USE lpp.lpp_waveform_pkg.ALL; | |
|
11 | USE lpp.lpp_top_lfr_pkg.ALL; | |
|
12 | ||
|
13 | LIBRARY techmap; | |
|
14 | USE techmap.gencomp.ALL; | |
|
15 | ||
|
16 | LIBRARY grlib; | |
|
17 | USE grlib.amba.ALL; | |
|
18 | USE grlib.stdlib.ALL; | |
|
19 | USE grlib.devices.ALL; | |
|
20 | USE GRLIB.DMA2AHB_Package.ALL; | |
|
21 | ||
|
22 | ENTITY lpp_top_lfr_wf_picker IS | |
|
23 | GENERIC ( | |
|
24 | hindex : INTEGER := 2; | |
|
25 | pindex : INTEGER := 15; | |
|
26 | paddr : INTEGER := 15; | |
|
27 | pmask : INTEGER := 16#fff#; | |
|
28 | pirq : INTEGER := 15; | |
|
29 | tech : INTEGER := 0; | |
|
30 | nb_burst_available_size : INTEGER := 11; | |
|
31 | nb_snapshot_param_size : INTEGER := 11; | |
|
32 | delta_snapshot_size : INTEGER := 16; | |
|
33 | delta_f2_f0_size : INTEGER := 10; | |
|
34 | delta_f2_f1_size : INTEGER := 10 | |
|
35 | ); | |
|
36 | PORT ( | |
|
37 | -- ADS7886 | |
|
38 | cnv_run : IN STD_LOGIC; | |
|
39 | cnv : OUT STD_LOGIC; | |
|
40 | sck : OUT STD_LOGIC; | |
|
41 | sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0); | |
|
42 | -- | |
|
43 | cnv_clk : IN STD_LOGIC; | |
|
44 | cnv_rstn : IN STD_LOGIC; | |
|
45 | ||
|
46 | -- AMBA AHB system signals | |
|
47 | HCLK : IN STD_ULOGIC; | |
|
48 | HRESETn : IN STD_ULOGIC; | |
|
49 | ||
|
50 | -- AMBA APB Slave Interface | |
|
51 | apbi : IN apb_slv_in_type; | |
|
52 | apbo : OUT apb_slv_out_type; | |
|
53 | ||
|
54 | -- AMBA AHB Master Interface | |
|
55 | AHB_Master_In : IN AHB_Mst_In_Type; | |
|
56 | AHB_Master_Out : OUT AHB_Mst_Out_Type; | |
|
57 | ||
|
58 | -- | |
|
59 | coarse_time_0 : IN STD_LOGIC; | |
|
60 | ||
|
61 | -- | |
|
62 | data_shaping_BW : OUT STD_LOGIC | |
|
63 | ); | |
|
64 | END lpp_top_lfr_wf_picker; | |
|
65 | ||
|
66 | ARCHITECTURE tb OF lpp_top_lfr_wf_picker IS | |
|
67 | ||
|
68 | SIGNAL ready_matrix_f0_0 : STD_LOGIC; | |
|
69 | SIGNAL ready_matrix_f0_1 : STD_LOGIC; | |
|
70 | SIGNAL ready_matrix_f1 : STD_LOGIC; | |
|
71 | SIGNAL ready_matrix_f2 : STD_LOGIC; | |
|
72 | SIGNAL error_anticipating_empty_fifo : STD_LOGIC; | |
|
73 | SIGNAL error_bad_component_error : STD_LOGIC; | |
|
74 | SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
75 | SIGNAL status_ready_matrix_f0_0 : STD_LOGIC; | |
|
76 | SIGNAL status_ready_matrix_f0_1 : STD_LOGIC; | |
|
77 | SIGNAL status_ready_matrix_f1 : STD_LOGIC; | |
|
78 | SIGNAL status_ready_matrix_f2 : STD_LOGIC; | |
|
79 | SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC; | |
|
80 | SIGNAL status_error_bad_component_error : STD_LOGIC; | |
|
81 | SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC; | |
|
82 | SIGNAL config_active_interruption_onError : STD_LOGIC; | |
|
83 | SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
84 | SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
85 | SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
86 | SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
87 | ||
|
88 | SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
89 | SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
90 | SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
91 | SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
92 | SIGNAL data_shaping_SP0 : STD_LOGIC; | |
|
93 | SIGNAL data_shaping_SP1 : STD_LOGIC; | |
|
94 | SIGNAL data_shaping_R0 : STD_LOGIC; | |
|
95 | SIGNAL data_shaping_R1 : STD_LOGIC; | |
|
96 | SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); | |
|
97 | SIGNAL delta_f2_f1 : STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); | |
|
98 | SIGNAL delta_f2_f0 : STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); | |
|
99 | SIGNAL nb_burst_available : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); | |
|
100 | SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |
|
101 | SIGNAL enable_f0 : STD_LOGIC; | |
|
102 | SIGNAL enable_f1 : STD_LOGIC; | |
|
103 | SIGNAL enable_f2 : STD_LOGIC; | |
|
104 | SIGNAL enable_f3 : STD_LOGIC; | |
|
105 | SIGNAL burst_f0 : STD_LOGIC; | |
|
106 | SIGNAL burst_f1 : STD_LOGIC; | |
|
107 | SIGNAL burst_f2 : STD_LOGIC; | |
|
108 | SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
109 | SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
110 | SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
111 | SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
112 | ||
|
113 | SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(5 DOWNTO 0); | |
|
114 | SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
|
115 | SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(5 DOWNTO 0); | |
|
116 | SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
|
117 | SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(5 DOWNTO 0); | |
|
118 | SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
|
119 | SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(5 DOWNTO 0); | |
|
120 | SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
|
121 | ||
|
122 | ||
|
123 | BEGIN | |
|
124 | ||
|
125 | ready_matrix_f0_0 <= '0'; | |
|
126 | ready_matrix_f0_1 <= '0'; | |
|
127 | ready_matrix_f1 <= '0'; | |
|
128 | ready_matrix_f2 <= '0'; | |
|
129 | error_anticipating_empty_fifo <= '0'; | |
|
130 | error_bad_component_error <= '0'; | |
|
131 | debug_reg <= (others => '0'); | |
|
132 | ||
|
133 | lpp_top_apbreg_1: lpp_top_apbreg | |
|
134 | GENERIC MAP ( | |
|
135 | nb_burst_available_size => nb_burst_available_size, | |
|
136 | nb_snapshot_param_size => nb_snapshot_param_size, | |
|
137 | delta_snapshot_size => delta_snapshot_size, | |
|
138 | delta_f2_f0_size => delta_f2_f0_size, | |
|
139 | delta_f2_f1_size => delta_f2_f1_size, | |
|
140 | pindex => pindex, | |
|
141 | paddr => paddr, | |
|
142 | pmask => pmask, | |
|
143 | pirq => pirq) | |
|
144 | PORT MAP ( | |
|
145 | HCLK => HCLK, | |
|
146 | HRESETn => HRESETn, | |
|
147 | apbi => apbi, | |
|
148 | apbo => apbo, | |
|
149 | ||
|
150 | ready_matrix_f0_0 => ready_matrix_f0_0, | |
|
151 | ready_matrix_f0_1 => ready_matrix_f0_1, | |
|
152 | ready_matrix_f1 => ready_matrix_f1, | |
|
153 | ready_matrix_f2 => ready_matrix_f2, | |
|
154 | error_anticipating_empty_fifo => error_anticipating_empty_fifo, | |
|
155 | error_bad_component_error => error_bad_component_error, | |
|
156 | debug_reg => debug_reg, | |
|
157 | status_ready_matrix_f0_0 => status_ready_matrix_f0_0, | |
|
158 | status_ready_matrix_f0_1 => status_ready_matrix_f0_1, | |
|
159 | status_ready_matrix_f1 => status_ready_matrix_f1, | |
|
160 | status_ready_matrix_f2 => status_ready_matrix_f2, | |
|
161 | status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo, | |
|
162 | status_error_bad_component_error => status_error_bad_component_error, | |
|
163 | config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, | |
|
164 | config_active_interruption_onError => config_active_interruption_onError, | |
|
165 | addr_matrix_f0_0 => addr_matrix_f0_0, | |
|
166 | addr_matrix_f0_1 => addr_matrix_f0_1, | |
|
167 | addr_matrix_f1 => addr_matrix_f1, | |
|
168 | addr_matrix_f2 => addr_matrix_f2, | |
|
169 | ||
|
170 | status_full => status_full, | |
|
171 | status_full_ack => status_full_ack, | |
|
172 | status_full_err => status_full_err, | |
|
173 | status_new_err => status_new_err, | |
|
174 | data_shaping_BW => data_shaping_BW, | |
|
175 | data_shaping_SP0 => data_shaping_SP0, | |
|
176 | data_shaping_SP1 => data_shaping_SP1, | |
|
177 | data_shaping_R0 => data_shaping_R0, | |
|
178 | data_shaping_R1 => data_shaping_R1, | |
|
179 | delta_snapshot => delta_snapshot, | |
|
180 | delta_f2_f1 => delta_f2_f1, | |
|
181 | delta_f2_f0 => delta_f2_f0, | |
|
182 | nb_burst_available => nb_burst_available, | |
|
183 | nb_snapshot_param => nb_snapshot_param, | |
|
184 | enable_f0 => enable_f0, | |
|
185 | enable_f1 => enable_f1, | |
|
186 | enable_f2 => enable_f2, | |
|
187 | enable_f3 => enable_f3, | |
|
188 | burst_f0 => burst_f0, | |
|
189 | burst_f1 => burst_f1, | |
|
190 | burst_f2 => burst_f2, | |
|
191 | addr_data_f0 => addr_data_f0, | |
|
192 | addr_data_f1 => addr_data_f1, | |
|
193 | addr_data_f2 => addr_data_f2, | |
|
194 | addr_data_f3 => addr_data_f3); | |
|
195 | ||
|
196 | lpp_top_lfr_wf_picker_ip_1: lpp_top_lfr_wf_picker_ip | |
|
197 | GENERIC MAP ( | |
|
198 | hindex => hindex, | |
|
199 | nb_burst_available_size => nb_burst_available_size, | |
|
200 | nb_snapshot_param_size => nb_snapshot_param_size, | |
|
201 | delta_snapshot_size => delta_snapshot_size, | |
|
202 | delta_f2_f0_size => delta_f2_f0_size, | |
|
203 | delta_f2_f1_size => delta_f2_f1_size, | |
|
204 | tech => tech, | |
|
205 | Mem_use => use_RAM | |
|
206 | ) | |
|
207 | PORT MAP ( | |
|
208 | cnv_run => cnv_run, | |
|
209 | cnv => cnv, | |
|
210 | sck => sck, | |
|
211 | sdo => sdo, | |
|
212 | cnv_clk => cnv_clk, | |
|
213 | cnv_rstn => cnv_rstn, | |
|
214 | ||
|
215 | clk => HCLK, | |
|
216 | rstn => HRESETn, | |
|
217 | ||
|
218 | sample_f0_wen => sample_f0_wen, | |
|
219 | sample_f0_wdata => sample_f0_wdata, | |
|
220 | sample_f1_wen => sample_f1_wen, | |
|
221 | sample_f1_wdata => sample_f1_wdata, | |
|
222 | sample_f2_wen => sample_f2_wen, | |
|
223 | sample_f2_wdata => sample_f2_wdata, | |
|
224 | sample_f3_wen => sample_f3_wen, | |
|
225 | sample_f3_wdata => sample_f3_wdata, | |
|
226 | AHB_Master_In => AHB_Master_In, | |
|
227 | AHB_Master_Out => AHB_Master_Out, | |
|
228 | coarse_time_0 => coarse_time_0, | |
|
229 | data_shaping_SP0 => data_shaping_SP0, | |
|
230 | data_shaping_SP1 => data_shaping_SP1, | |
|
231 | data_shaping_R0 => data_shaping_R0, | |
|
232 | data_shaping_R1 => data_shaping_R1, | |
|
233 | delta_snapshot => delta_snapshot, | |
|
234 | delta_f2_f1 => delta_f2_f1, | |
|
235 | delta_f2_f0 => delta_f2_f0, | |
|
236 | enable_f0 => enable_f0, | |
|
237 | enable_f1 => enable_f1, | |
|
238 | enable_f2 => enable_f2, | |
|
239 | enable_f3 => enable_f3, | |
|
240 | burst_f0 => burst_f0, | |
|
241 | burst_f1 => burst_f1, | |
|
242 | burst_f2 => burst_f2, | |
|
243 | nb_burst_available => nb_burst_available, | |
|
244 | nb_snapshot_param => nb_snapshot_param, | |
|
245 | status_full => status_full, | |
|
246 | status_full_ack => status_full_ack, | |
|
247 | status_full_err => status_full_err, | |
|
248 | status_new_err => status_new_err, | |
|
249 | addr_data_f0 => addr_data_f0, | |
|
250 | addr_data_f1 => addr_data_f1, | |
|
251 | addr_data_f2 => addr_data_f2, | |
|
252 | addr_data_f3 => addr_data_f3); | |
|
253 | END tb; No newline at end of file |
@@ -1,116 +1,114 | |||
|
1 | LIBRARY IEEE; | |
|
2 | USE IEEE.STD_LOGIC_1164.ALL; | |
|
3 | USE ieee.numeric_std.ALL; | |
|
4 | ||
|
5 | ENTITY lpp_waveform_snapshot_controler IS | |
|
6 | ||
|
7 | GENERIC ( | |
|
8 | delta_snapshot_size : INTEGER := 16; | |
|
9 | delta_f2_f0_size : INTEGER := 10; | |
|
10 | delta_f2_f1_size : INTEGER := 10); | |
|
11 | ||
|
12 | PORT ( | |
|
13 | clk : IN STD_LOGIC; | |
|
14 | rstn : IN STD_LOGIC; | |
|
15 | --config | |
|
16 | delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); | |
|
17 | delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); | |
|
18 | delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); | |
|
19 | ||
|
20 | --input | |
|
21 | coarse_time_0 : IN STD_LOGIC; | |
|
22 | data_f0_in_valid : IN STD_LOGIC; | |
|
23 | data_f2_in_valid : IN STD_LOGIC; | |
|
24 | --output | |
|
25 | start_snapshot_f0 : OUT STD_LOGIC; | |
|
26 | start_snapshot_f1 : OUT STD_LOGIC; | |
|
27 | start_snapshot_f2 : OUT STD_LOGIC | |
|
28 | ); | |
|
29 | ||
|
30 | END lpp_waveform_snapshot_controler; | |
|
31 | ||
|
32 | ARCHITECTURE beh OF lpp_waveform_snapshot_controler IS | |
|
33 | SIGNAL counter_delta_snapshot : INTEGER; | |
|
34 | SIGNAL counter_delta_f0 : INTEGER; | |
|
35 | ||
|
36 | SIGNAL coarse_time_0_r : STD_LOGIC; | |
|
37 | SIGNAL start_snapshot_f2_temp : STD_LOGIC; | |
|
38 | SIGNAL start_snapshot_fothers_temp : STD_LOGIC; | |
|
39 | SIGNAL start_snapshot_fothers_temp2 : STD_LOGIC; | |
|
40 | BEGIN -- beh | |
|
41 | ||
|
42 | PROCESS (clk, rstn) | |
|
43 | BEGIN | |
|
44 | IF rstn = '0' THEN | |
|
45 |
start_snapshot_f |
|
|
46 |
start_snapshot_f |
|
|
47 |
|
|
|
48 |
counter_delta_ |
|
|
49 | counter_delta_f0 <= 0; | |
|
50 |
|
|
|
51 |
start_snapshot_f |
|
|
52 | start_snapshot_fothers_temp <= '0'; | |
|
53 | start_snapshot_fothers_temp2 <= '0'; | |
|
54 | ELSIF clk'EVENT AND clk = '1' THEN | |
|
55 | IF counter_delta_snapshot = UNSIGNED(delta_snapshot) THEN | |
|
56 |
start_snapshot_f2_temp <= |
|
|
57 |
E |
|
|
58 | start_snapshot_f2_temp <= '0'; | |
|
59 | END IF; | |
|
60 | ------------------------------------------------------------------------- | |
|
61 | IF counter_delta_snapshot = UNSIGNED(delta_snapshot) AND start_snapshot_f2_temp = '0' THEN | |
|
62 |
start_snapshot_f2 <= ' |
|
|
63 |
E |
|
|
64 | start_snapshot_f2 <= '0'; | |
|
65 | END IF; | |
|
66 | ------------------------------------------------------------------------- | |
|
67 | coarse_time_0_r <= coarse_time_0; | |
|
68 | IF coarse_time_0 = NOT coarse_time_0_r THEN --AND coarse_time_0 = '1' THEN | |
|
69 | IF counter_delta_snapshot = 0 THEN | |
|
70 |
counter_delta_snapshot <= |
|
|
71 |
|
|
|
72 | counter_delta_snapshot <= counter_delta_snapshot - 1; | |
|
73 | END IF; | |
|
74 | END IF; | |
|
75 | ||
|
76 | ||
|
77 | ------------------------------------------------------------------------- | |
|
78 | ||
|
79 | ||
|
80 | ||
|
81 | IF counter_delta_f0 = UNSIGNED(delta_f2_f1) THEN | |
|
82 |
start_snapshot_f1 <= ' |
|
|
83 |
E |
|
|
84 | start_snapshot_f1 <= '0'; | |
|
85 | END IF; | |
|
86 | ||
|
87 | IF counter_delta_f0 = 1 THEN --UNSIGNED(delta_f2_f0) THEN | |
|
88 |
start_snapshot_f0 <= ' |
|
|
89 |
E |
|
|
90 | start_snapshot_f0 <= '0'; | |
|
91 | END IF; | |
|
92 | ||
|
93 | IF counter_delta_snapshot = UNSIGNED(delta_snapshot) | |
|
94 |
|
|
|
95 | THEN -- | |
|
96 |
start_snapshot_fothers_temp <= ' |
|
|
97 | ELSIF counter_delta_f0 > 0 THEN | |
|
98 | start_snapshot_fothers_temp <= '0'; | |
|
99 |
|
|
|
100 | ||
|
101 | ||
|
102 | ------------------------------------------------------------------------- | |
|
103 | IF (start_snapshot_fothers_temp = '1' OR (counter_delta_snapshot = UNSIGNED(delta_snapshot) AND start_snapshot_f2_temp = '0')) AND data_f2_in_valid = '1' THEN | |
|
104 | --counter_delta_snapshot = UNSIGNED(delta_snapshot) AND start_snapshot_f2_temp = '0' THEN -- | |
|
105 | --counter_delta_snapshot = UNSIGNED(delta_snapshot) THEN | |
|
106 | counter_delta_f0 <= to_integer(UNSIGNED(delta_f2_f0)); --0; | |
|
107 | ELSE | |
|
108 | IF (( counter_delta_f0 > 0 ) AND ( data_f0_in_valid = '1' )) THEN --<= UNSIGNED(delta_f2_f0) THEN | |
|
109 | counter_delta_f0 <= counter_delta_f0 - 1;--counter_delta_f0 + 1; | |
|
110 | END IF; | |
|
111 |
|
|
|
112 | ------------------------------------------------------------------------- | |
|
113 | END IF; | |
|
114 | END PROCESS; | |
|
115 | ||
|
116 | END beh; | |
|
1 | LIBRARY IEEE; | |
|
2 | USE IEEE.STD_LOGIC_1164.ALL; | |
|
3 | USE ieee.numeric_std.ALL; | |
|
4 | ||
|
5 | ENTITY lpp_waveform_snapshot_controler IS | |
|
6 | ||
|
7 | GENERIC ( | |
|
8 | delta_snapshot_size : INTEGER := 16; | |
|
9 | delta_f2_f0_size : INTEGER := 10; | |
|
10 | delta_f2_f1_size : INTEGER := 10); | |
|
11 | ||
|
12 | PORT ( | |
|
13 | clk : IN STD_LOGIC; | |
|
14 | rstn : IN STD_LOGIC; | |
|
15 | --config | |
|
16 | delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); | |
|
17 | delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); | |
|
18 | delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); | |
|
19 | ||
|
20 | --input | |
|
21 | coarse_time_0 : IN STD_LOGIC; | |
|
22 | data_f0_in_valid : IN STD_LOGIC; | |
|
23 | data_f2_in_valid : IN STD_LOGIC; | |
|
24 | --output | |
|
25 | start_snapshot_f0 : OUT STD_LOGIC; | |
|
26 | start_snapshot_f1 : OUT STD_LOGIC; | |
|
27 | start_snapshot_f2 : OUT STD_LOGIC | |
|
28 | ); | |
|
29 | ||
|
30 | END lpp_waveform_snapshot_controler; | |
|
31 | ||
|
32 | ARCHITECTURE beh OF lpp_waveform_snapshot_controler IS | |
|
33 | SIGNAL counter_delta_snapshot : INTEGER; | |
|
34 | SIGNAL counter_delta_f0 : INTEGER; | |
|
35 | ||
|
36 | SIGNAL coarse_time_0_r : STD_LOGIC; | |
|
37 | SIGNAL start_snapshot_f2_temp : STD_LOGIC; | |
|
38 | SIGNAL start_snapshot_fothers_temp : STD_LOGIC; | |
|
39 | BEGIN -- beh | |
|
40 | ||
|
41 | PROCESS (clk, rstn) | |
|
42 | BEGIN | |
|
43 | IF rstn = '0' THEN | |
|
44 | start_snapshot_f0 <= '0'; | |
|
45 | start_snapshot_f1 <= '0'; | |
|
46 | start_snapshot_f2 <= '0'; | |
|
47 | counter_delta_snapshot <= 0; | |
|
48 | counter_delta_f0 <= 0; | |
|
49 | coarse_time_0_r <= '0'; | |
|
50 | start_snapshot_f2_temp <= '0'; | |
|
51 | start_snapshot_fothers_temp <= '0'; | |
|
52 | ELSIF clk'EVENT AND clk = '1' THEN | |
|
53 | IF counter_delta_snapshot = UNSIGNED(delta_snapshot) THEN | |
|
54 | start_snapshot_f2_temp <= '1'; | |
|
55 | ELSE | |
|
56 | start_snapshot_f2_temp <= '0'; | |
|
57 | END IF; | |
|
58 | ------------------------------------------------------------------------- | |
|
59 | IF counter_delta_snapshot = UNSIGNED(delta_snapshot) AND start_snapshot_f2_temp = '0' THEN | |
|
60 | start_snapshot_f2 <= '1'; | |
|
61 | ELSE | |
|
62 | start_snapshot_f2 <= '0'; | |
|
63 | END IF; | |
|
64 | ------------------------------------------------------------------------- | |
|
65 | coarse_time_0_r <= coarse_time_0; | |
|
66 | IF coarse_time_0 = NOT coarse_time_0_r THEN --AND coarse_time_0 = '1' THEN | |
|
67 | IF counter_delta_snapshot = 0 THEN | |
|
68 | counter_delta_snapshot <= to_integer(UNSIGNED(delta_snapshot)); | |
|
69 | ELSE | |
|
70 | counter_delta_snapshot <= counter_delta_snapshot - 1; | |
|
71 | END IF; | |
|
72 | END IF; | |
|
73 | ||
|
74 | ||
|
75 | ------------------------------------------------------------------------- | |
|
76 | ||
|
77 | ||
|
78 | ||
|
79 | IF counter_delta_f0 = UNSIGNED(delta_f2_f1) THEN | |
|
80 | start_snapshot_f1 <= '1'; | |
|
81 | ELSE | |
|
82 | start_snapshot_f1 <= '0'; | |
|
83 | END IF; | |
|
84 | ||
|
85 | IF counter_delta_f0 = 1 THEN --UNSIGNED(delta_f2_f0) THEN | |
|
86 | start_snapshot_f0 <= '1'; | |
|
87 | ELSE | |
|
88 | start_snapshot_f0 <= '0'; | |
|
89 | END IF; | |
|
90 | ||
|
91 | IF counter_delta_snapshot = UNSIGNED(delta_snapshot) | |
|
92 | AND start_snapshot_f2_temp = '0' | |
|
93 | THEN -- | |
|
94 | start_snapshot_fothers_temp <= '1'; | |
|
95 | ELSIF counter_delta_f0 > 0 THEN | |
|
96 | start_snapshot_fothers_temp <= '0'; | |
|
97 | END IF; | |
|
98 | ||
|
99 | ||
|
100 | ------------------------------------------------------------------------- | |
|
101 | IF (start_snapshot_fothers_temp = '1' OR (counter_delta_snapshot = UNSIGNED(delta_snapshot) AND start_snapshot_f2_temp = '0')) AND data_f2_in_valid = '1' THEN | |
|
102 | --counter_delta_snapshot = UNSIGNED(delta_snapshot) AND start_snapshot_f2_temp = '0' THEN -- | |
|
103 | --counter_delta_snapshot = UNSIGNED(delta_snapshot) THEN | |
|
104 | counter_delta_f0 <= to_integer(UNSIGNED(delta_f2_f0)); --0; | |
|
105 | ELSE | |
|
106 | IF (( counter_delta_f0 > 0 ) AND ( data_f0_in_valid = '1' )) THEN --<= UNSIGNED(delta_f2_f0) THEN | |
|
107 | counter_delta_f0 <= counter_delta_f0 - 1;--counter_delta_f0 + 1; | |
|
108 | END IF; | |
|
109 | END IF; | |
|
110 | ------------------------------------------------------------------------- | |
|
111 | END IF; | |
|
112 | END PROCESS; | |
|
113 | ||
|
114 | END beh; No newline at end of file |
|
1 | NO CONTENT: file was removed |
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