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Add debug reg for LFR_MS
pellion -
r313:7171ec567127 JC
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@@ -169,7 +169,8 ARCHITECTURE beh OF MINI_LFR_top IS
169 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
169 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
170
170
171 SIGNAL bias_fail_sw_sig : STD_LOGIC;
171 SIGNAL bias_fail_sw_sig : STD_LOGIC;
172
172
173 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
173 -----------------------------------------------------------------------------
174 -----------------------------------------------------------------------------
174
175
175 BEGIN -- beh
176 BEGIN -- beh
@@ -221,7 +222,7 BEGIN -- beh
221 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
222 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
222 LED0 <= '0';
223 LED0 <= '0';
223 LED1 <= '1';
224 LED1 <= '1';
224 LED2 <= BP0;
225 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
225 --IO1 <= '1';
226 --IO1 <= '1';
226 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
227 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
227 --IO3 <= ADC_SDO(0);
228 --IO3 <= ADC_SDO(0);
@@ -232,7 +233,7 BEGIN -- beh
232 --IO8 <= ADC_SDO(5);
233 --IO8 <= ADC_SDO(5);
233 --IO9 <= ADC_SDO(6);
234 --IO9 <= ADC_SDO(6);
234 --IO10 <= ADC_SDO(7);
235 --IO10 <= ADC_SDO(7);
235 IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
236 --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
236 END IF;
237 END IF;
237 END PROCESS;
238 END PROCESS;
238
239
@@ -241,7 +242,7 BEGIN -- beh
241 IF reset = '0' THEN -- asynchronous reset (active low)
242 IF reset = '0' THEN -- asynchronous reset (active low)
242 I00_s <= '0';
243 I00_s <= '0';
243 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
244 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
244 I00_s <= NOT I00_s;
245 I00_s <= NOT I00_s ;
245 END IF;
246 END IF;
246 END PROCESS;
247 END PROCESS;
247 -- IO0 <= I00_s;
248 -- IO0 <= I00_s;
@@ -424,7 +425,7 BEGIN -- beh
424 pirq_ms => 6,
425 pirq_ms => 6,
425 pirq_wfp => 14,
426 pirq_wfp => 14,
426 hindex => 2,
427 hindex => 2,
427 top_lfr_version => X"000102") -- aa.bb.cc version
428 top_lfr_version => X"000103") -- aa.bb.cc version
428 PORT MAP (
429 PORT MAP (
429 clk => clk_25,
430 clk => clk_25,
430 rstn => reset,
431 rstn => reset,
@@ -437,7 +438,8 BEGIN -- beh
437 ahbo => ahbo_m_ext(2),
438 ahbo => ahbo_m_ext(2),
438 coarse_time => coarse_time,
439 coarse_time => coarse_time,
439 fine_time => fine_time,
440 fine_time => fine_time,
440 data_shaping_BW => bias_fail_sw_sig);
441 data_shaping_BW => bias_fail_sw_sig,
442 observation_reg => observation_reg);
441
443
442 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
444 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
443 GENERIC MAP(
445 GENERIC MAP(
@@ -459,9 +461,9 BEGIN -- beh
459 sample => sample,
461 sample => sample,
460 sample_val => sample_val);
462 sample_val => sample_val);
461
463
462 IO10 <= ADC_SDO_sig(5);
464 --IO10 <= ADC_SDO_sig(5);
463 IO9 <= ADC_SDO_sig(4);
465 --IO9 <= ADC_SDO_sig(4);
464 IO8 <= ADC_SDO_sig(3);
466 --IO8 <= ADC_SDO_sig(3);
465
467
466 ADC_nCS <= ADC_nCS_sig;
468 ADC_nCS <= ADC_nCS_sig;
467 ADC_CLK <= ADC_CLK_sig;
469 ADC_CLK <= ADC_CLK_sig;
@@ -475,29 +477,104 BEGIN -- beh
475 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
477 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
476 PORT MAP(reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
478 PORT MAP(reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
477
479
478 pio_pad_0 : iopad
480 --pio_pad_0 : iopad
479 GENERIC MAP (tech => CFG_PADTECH)
481 -- GENERIC MAP (tech => CFG_PADTECH)
480 PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
482 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
481 pio_pad_1 : iopad
483 --pio_pad_1 : iopad
482 GENERIC MAP (tech => CFG_PADTECH)
484 -- GENERIC MAP (tech => CFG_PADTECH)
483 PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
485 -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
484 pio_pad_2 : iopad
486 --pio_pad_2 : iopad
485 GENERIC MAP (tech => CFG_PADTECH)
487 -- GENERIC MAP (tech => CFG_PADTECH)
486 PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
488 -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
487 pio_pad_3 : iopad
489 --pio_pad_3 : iopad
488 GENERIC MAP (tech => CFG_PADTECH)
490 -- GENERIC MAP (tech => CFG_PADTECH)
489 PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
491 -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
490 pio_pad_4 : iopad
492 --pio_pad_4 : iopad
491 GENERIC MAP (tech => CFG_PADTECH)
493 -- GENERIC MAP (tech => CFG_PADTECH)
492 PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
494 -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
493 pio_pad_5 : iopad
495 --pio_pad_5 : iopad
494 GENERIC MAP (tech => CFG_PADTECH)
496 -- GENERIC MAP (tech => CFG_PADTECH)
495 PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
497 -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
496 pio_pad_6 : iopad
498 --pio_pad_6 : iopad
497 GENERIC MAP (tech => CFG_PADTECH)
499 -- GENERIC MAP (tech => CFG_PADTECH)
498 PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
500 -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
499 pio_pad_7 : iopad
501 --pio_pad_7 : iopad
500 GENERIC MAP (tech => CFG_PADTECH)
502 -- GENERIC MAP (tech => CFG_PADTECH)
501 PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
503 -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
502
504
503 END beh;
505 PROCESS (clk_25, reset)
506 BEGIN -- PROCESS
507 IF reset = '0' THEN -- asynchronous reset (active low)
508 IO0 <= '0';
509 IO1 <= '0';
510 IO2 <= '0';
511 IO3 <= '0';
512 IO4 <= '0';
513 IO5 <= '0';
514 IO6 <= '0';
515 IO7 <= '0';
516 IO8 <= '0';
517 IO9 <= '0';
518 IO10 <= '0';
519 IO11 <= '0';
520 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
521 CASE gpioo.dout(1 DOWNTO 0) IS
522 WHEN "00" =>
523 IO0 <= observation_reg(0 );
524 IO1 <= observation_reg(1 );
525 IO2 <= observation_reg(2 );
526 IO3 <= observation_reg(3 );
527 IO4 <= observation_reg(4 );
528 IO5 <= observation_reg(5 );
529 IO6 <= observation_reg(6 );
530 IO7 <= observation_reg(7 );
531 IO8 <= observation_reg(8 );
532 IO9 <= observation_reg(9 );
533 IO10 <= observation_reg(10);
534 IO11 <= observation_reg(11);
535 WHEN "01" =>
536 IO0 <= observation_reg(0 + 12);
537 IO1 <= observation_reg(1 + 12);
538 IO2 <= observation_reg(2 + 12);
539 IO3 <= observation_reg(3 + 12);
540 IO4 <= observation_reg(4 + 12);
541 IO5 <= observation_reg(5 + 12);
542 IO6 <= observation_reg(6 + 12);
543 IO7 <= observation_reg(7 + 12);
544 IO8 <= observation_reg(8 + 12);
545 IO9 <= observation_reg(9 + 12);
546 IO10 <= observation_reg(10 + 12);
547 IO11 <= observation_reg(11 + 12);
548 WHEN "10" =>
549 IO0 <= observation_reg(0 + 12 + 12);
550 IO1 <= observation_reg(1 + 12 + 12);
551 IO2 <= observation_reg(2 + 12 + 12);
552 IO3 <= observation_reg(3 + 12 + 12);
553 IO4 <= observation_reg(4 + 12 + 12);
554 IO5 <= observation_reg(5 + 12 + 12);
555 IO6 <= observation_reg(6 + 12 + 12);
556 IO7 <= observation_reg(7 + 12 + 12);
557 IO8 <= '0';
558 IO9 <= '0';
559 IO10 <= '0';
560 IO11 <= '0';
561 WHEN "11" =>
562 IO0 <= '0';
563 IO1 <= '0';
564 IO2 <= '0';
565 IO3 <= '0';
566 IO4 <= '0';
567 IO5 <= '0';
568 IO6 <= '0';
569 IO7 <= '0';
570 IO8 <= '0';
571 IO9 <= '0';
572 IO10 <= '0';
573 IO11 <= '0';
574 WHEN OTHERS => NULL;
575 END CASE;
576
577 END IF;
578 END PROCESS;
579
580 END beh; No newline at end of file
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@@ -118,4 +118,4 BEGIN
118 STD_LOGIC_VECTOR(UNSIGNED(counter));
118 STD_LOGIC_VECTOR(UNSIGNED(counter));
119
119
120
120
121 END ar_RAM_CTRLR_v2; No newline at end of file
121 END ar_RAM_CTRLR_v2;
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@@ -62,7 +62,7 ENTITY lpp_lfr IS
62 data_shaping_BW : OUT STD_LOGIC;
62 data_shaping_BW : OUT STD_LOGIC;
63 --
63 --
64 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
64 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
65
65
66 --debug
66 --debug
67 --debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
67 --debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
68 --debug_f0_data_valid : OUT STD_LOGIC;
68 --debug_f0_data_valid : OUT STD_LOGIC;
@@ -492,7 +492,7 BEGIN
492 data_f3_data_out_ren => data_f3_data_out_ren ,
492 data_f3_data_out_ren => data_f3_data_out_ren ,
493
493
494 -------------------------------------------------------------------------
494 -------------------------------------------------------------------------
495 observation_reg => observation_reg
495 observation_reg => OPEN --observation_reg
496 ---- debug SNAPSHOT_OUT
496 ---- debug SNAPSHOT_OUT
497 --debug_f0_data => debug_f0_data,
497 --debug_f0_data => debug_f0_data,
498 --debug_f0_data_valid => debug_f0_data_valid ,
498 --debug_f0_data_valid => debug_f0_data_valid ,
@@ -752,7 +752,7 BEGIN
752 ready_matrix_f2 => ready_matrix_f2,
752 ready_matrix_f2 => ready_matrix_f2,
753 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
753 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
754 error_bad_component_error => error_bad_component_error,
754 error_bad_component_error => error_bad_component_error,
755 debug_reg => debug_reg,
755 debug_reg => observation_reg,--debug_reg,
756 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
756 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
757 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
757 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
758 status_ready_matrix_f1 => status_ready_matrix_f1,
758 status_ready_matrix_f1 => status_ready_matrix_f1,
@@ -765,5 +765,5 BEGIN
765 addr_matrix_f0_1 => addr_matrix_f0_1,
765 addr_matrix_f0_1 => addr_matrix_f0_1,
766 addr_matrix_f1 => addr_matrix_f1,
766 addr_matrix_f1 => addr_matrix_f1,
767 addr_matrix_f2 => addr_matrix_f2);
767 addr_matrix_f2 => addr_matrix_f2);
768
768
769 END beh;
769 END beh;
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