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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
30 LIBRARY gaisler;
31 USE gaisler.memctrl.ALL;
32 USE gaisler.leon3.ALL;
33 USE gaisler.uart.ALL;
34 USE gaisler.misc.ALL;
35 USE gaisler.spacewire.ALL;
36 LIBRARY esa;
37 USE esa.memoryctrl.ALL;
38 LIBRARY lpp;
39 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 USE lpp.iir_filter.ALL;
44 USE lpp.general_purpose.ALL;
45 USE lpp.lpp_lfr_management.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
47
48 ENTITY LFR_em IS
49
50 PORT (
51 clk100MHz : IN STD_ULOGIC;
52 clk49_152MHz : IN STD_ULOGIC;
53 reset : IN STD_ULOGIC;
54
55 -- TAG --------------------------------------------------------------------
56 --TAG1 : IN STD_ULOGIC; -- DSU rx data
57 --TAG3 : OUT STD_ULOGIC; -- DSU tx data
58 -- UART APB ---------------------------------------------------------------
59 TAG2 : IN STD_ULOGIC; -- UART1 rx data
60 TAG4 : OUT STD_ULOGIC; -- UART1 tx data
61 -- RAM --------------------------------------------------------------------
62 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
63 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
64 nSRAM_BE0 : OUT STD_LOGIC;
65 nSRAM_BE1 : OUT STD_LOGIC;
66 nSRAM_BE2 : OUT STD_LOGIC;
67 nSRAM_BE3 : OUT STD_LOGIC;
68 nSRAM_WE : OUT STD_LOGIC;
69 nSRAM_CE : OUT STD_LOGIC;
70 nSRAM_OE : OUT STD_LOGIC;
71 -- SPW --------------------------------------------------------------------
72 spw1_din : IN STD_LOGIC;
73 spw1_sin : IN STD_LOGIC;
74 spw1_dout : OUT STD_LOGIC;
75 spw1_sout : OUT STD_LOGIC;
76 spw2_din : IN STD_LOGIC;
77 spw2_sin : IN STD_LOGIC;
78 spw2_dout : OUT STD_LOGIC;
79 spw2_sout : OUT STD_LOGIC;
80 -- ADC --------------------------------------------------------------------
81 bias_fail_sw : OUT STD_LOGIC;
82 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
83 ADC_smpclk : OUT STD_LOGIC;
84 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
85 -- DAC --------------------------------------------------------------------
86 DAC_SDO : OUT STD_LOGIC;
87 DAC_SCK : OUT STD_LOGIC;
88 DAC_SYNC : OUT STD_LOGIC;
89 DAC_CAL_EN : OUT STD_LOGIC;
90 -- HK ---------------------------------------------------------------------
91 HK_smpclk : OUT STD_LOGIC;
92 ADC_OEB_bar_HK : OUT STD_LOGIC;
93 HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
94 ---------------------------------------------------------------------------
95 TAG8 : OUT STD_LOGIC;
96 led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
97 );
98
99 END LFR_em;
100
101
102 ARCHITECTURE beh OF LFR_em IS
103
104 --==========================================================================
105 -- USE_IAP_MEMCTRL allow to use the srctrle-0ws on MINILFR board
106 -- when enabled, chip enable polarity should be reversed and bank size also
107 -- MINILFR -> 1 bank of 4MBytes -> SRBANKSZ=9
108 -- LFR EQM & FM -> 2 banks of 2MBytes -> SRBANKSZ=8
109 --==========================================================================
110 CONSTANT USE_IAP_MEMCTRL : integer := 1;
111 --==========================================================================
112
113 SIGNAL clk_50_s : STD_LOGIC := '0';
114 SIGNAL clk_25 : STD_LOGIC := '0';
115 SIGNAL clk_24 : STD_LOGIC := '0';
116 -----------------------------------------------------------------------------
117 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
118 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
119
120 -- CONSTANTS
121 CONSTANT CFG_PADTECH : INTEGER := inferred;
122 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
123 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
124 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
125
126 SIGNAL apbi_ext : apb_slv_in_type;
127 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
128 SIGNAL ahbi_s_ext : ahb_slv_in_type;
129 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
130 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
131 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
132
133 -- Spacewire signals
134 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
135 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
136 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
137 SIGNAL spw_rxtxclk : STD_ULOGIC;
138 SIGNAL spw_rxclkn : STD_ULOGIC;
139 SIGNAL spw_clk : STD_LOGIC;
140 SIGNAL swni : grspw_in_type;
141 SIGNAL swno : grspw_out_type;
142
143 --GPIO
144 SIGNAL gpioi : gpio_in_type;
145 SIGNAL gpioo : gpio_out_type;
146
147 -- AD Converter ADS7886
148 SIGNAL sample : Samples14v(8 DOWNTO 0);
149 SIGNAL sample_s : Samples(8 DOWNTO 0);
150 SIGNAL sample_val : STD_LOGIC;
151 SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0);
152
153 -----------------------------------------------------------------------------
154 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
155
156 -----------------------------------------------------------------------------
157 SIGNAL rstn_25 : STD_LOGIC;
158 SIGNAL rstn_24 : STD_LOGIC;
159
160 SIGNAL LFR_soft_rstn : STD_LOGIC;
161 SIGNAL LFR_rstn : STD_LOGIC;
162
163 SIGNAL ADC_smpclk_s : STD_LOGIC;
164 ----------------------------------------------------------------------------
165 SIGNAL nSRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
166 SIGNAL nSRAM_READY : STD_LOGIC;
167
168 BEGIN -- beh
169
170 -----------------------------------------------------------------------------
171 -- CLK
172 -----------------------------------------------------------------------------
173 rst_domain25 : rstgen PORT MAP (reset, clk_25, '1', rstn_25, OPEN);
174 rst_domain24 : rstgen PORT MAP (reset, clk_24, '1', rstn_24, OPEN);
175
176 PROCESS(clk100MHz)
177 BEGIN
178 IF clk100MHz'EVENT AND clk100MHz = '1' THEN
179 clk_50_s <= NOT clk_50_s;
180 END IF;
181 END PROCESS;
182
183 PROCESS(clk_50_s)
184 BEGIN
185 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
186 clk_25 <= NOT clk_25;
187 END IF;
188 END PROCESS;
189
190 PROCESS(clk49_152MHz)
191 BEGIN
192 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
193 clk_24 <= NOT clk_24;
194 END IF;
195 END PROCESS;
196
197 -----------------------------------------------------------------------------
198
199 PROCESS (clk_25, rstn_25)
200 BEGIN -- PROCESS
201 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
202 led(0) <= '0';
203 led(1) <= '0';
204 led(2) <= '0';
205 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
206 led(0) <= '0';
207 led(1) <= '1';
208 led(2) <= '1';
209 END IF;
210 END PROCESS;
211
212 --
213 leon3_soc_1 : leon3_soc
214 GENERIC MAP (
215 fabtech => apa3e,
216 memtech => apa3e,
217 padtech => inferred,
218 clktech => inferred,
219 disas => 0,
220 dbguart => 0,
221 pclow => 2,
222 clk_freq => 25000,
223 IS_RADHARD => 0,
224 NB_CPU => 1,
225 ENABLE_FPU => 1,
226 FPU_NETLIST => 0,
227 ENABLE_DSU => 1,
228 ENABLE_AHB_UART => 0,
229 ENABLE_APB_UART => 1,
230 ENABLE_IRQMP => 1,
231 ENABLE_GPT => 1,
232 NB_AHB_MASTER => NB_AHB_MASTER,
233 NB_AHB_SLAVE => NB_AHB_SLAVE,
234 NB_APB_SLAVE => NB_APB_SLAVE,
235 ADDRESS_SIZE => 20,
236 USES_IAP_MEMCTRLR => USE_IAP_MEMCTRL,
237 BYPASS_EDAC_MEMCTRLR => '0',
238 SRBANKSZ => 9,
239 SLOW_TIMING_EMULATION => 0
240 )
241 PORT MAP (
242 clk => clk_25,
243 reset => rstn_25,
244 errorn => OPEN,
245
246 ahbrxd => OPEN,
247 ahbtxd => OPEN,
248 urxd1 => TAG2,
249 utxd1 => TAG4,
250
251 address => address,
252 data => data,
253 nSRAM_BE0 => nSRAM_BE0,
254 nSRAM_BE1 => nSRAM_BE1,
255 nSRAM_BE2 => nSRAM_BE2,
256 nSRAM_BE3 => nSRAM_BE3,
257 nSRAM_WE => nSRAM_WE,
258 nSRAM_CE => nSRAM_CE_s,
259 nSRAM_OE => nSRAM_OE,
260 nSRAM_READY => nSRAM_READY,
261 SRAM_MBE => OPEN,
262
263 apbi_ext => apbi_ext,
264 apbo_ext => apbo_ext,
265 ahbi_s_ext => ahbi_s_ext,
266 ahbo_s_ext => ahbo_s_ext,
267 ahbi_m_ext => ahbi_m_ext,
268 ahbo_m_ext => ahbo_m_ext);
269
270 PROCESS (clk_25, rstn_25)
271 BEGIN -- PROCESS
272 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
273 nSRAM_READY <= '1';
274 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
275 nSRAM_READY <= '1';
276 END IF;
277 END PROCESS;
278
279 IAP:if USE_IAP_MEMCTRL = 1 GENERATE
280 nSRAM_CE <= not nSRAM_CE_s(0);
281 END GENERATE;
282
283 NOIAP:if USE_IAP_MEMCTRL = 0 GENERATE
284 nSRAM_CE <= nSRAM_CE_s(0);
285 END GENERATE;
286
287 -------------------------------------------------------------------------------
288 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
289 -------------------------------------------------------------------------------
290 apb_lfr_management_1 : apb_lfr_management
291 GENERIC MAP (
292 tech => apa3e,
293 pindex => 6,
294 paddr => 6,
295 pmask => 16#fff#,
296 -- FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
297 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
298 PORT MAP (
299 clk25MHz => clk_25,
300 resetn_25MHz => rstn_25, -- TODO
301 -- clk24_576MHz => clk_24, -- 49.152MHz/2
302 -- resetn_24_576MHz => rstn_24, -- TODO
303
304 grspw_tick => swno.tickout,
305 apbi => apbi_ext,
306 apbo => apbo_ext(6),
307
308 HK_sample => sample_s(8),
309 HK_val => sample_val,
310 HK_sel => HK_SEL,
311
312 DAC_SDO => DAC_SDO,
313 DAC_SCK => DAC_SCK,
314 DAC_SYNC => DAC_SYNC,
315 DAC_CAL_EN => DAC_CAL_EN,
316
317 coarse_time => coarse_time,
318 fine_time => fine_time,
319 LFR_soft_rstn => LFR_soft_rstn
320 );
321
322 -----------------------------------------------------------------------
323 --- SpaceWire --------------------------------------------------------
324 -----------------------------------------------------------------------
325
326 -- SPW_EN <= '1';
327
328 spw_clk <= clk_50_s;
329 spw_rxtxclk <= spw_clk;
330 spw_rxclkn <= NOT spw_rxtxclk;
331
332 -- PADS for SPW1
333 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
334 PORT MAP (spw1_din, dtmp(0));
335 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
336 PORT MAP (spw1_sin, stmp(0));
337 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
338 PORT MAP (spw1_dout, swno.d(0));
339 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
340 PORT MAP (spw1_sout, swno.s(0));
341 -- PADS FOR SPW2
342 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
343 PORT MAP (spw2_din, dtmp(1));
344 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
345 PORT MAP (spw2_sin, stmp(1));
346 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
347 PORT MAP (spw2_dout, swno.d(1));
348 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
349 PORT MAP (spw2_sout, swno.s(1));
350
351 -- GRSPW PHY
352 --spw1_input: if CFG_SPW_GRSPW = 1 generate
353 spw_inputloop : FOR j IN 0 TO 1 GENERATE
354 spw_phy0 : grspw_phy
355 GENERIC MAP(
356 tech => apa3e,
357 rxclkbuftype => 1,
358 scantest => 0)
359 PORT MAP(
360 rxrst => swno.rxrst,
361 di => dtmp(j),
362 si => stmp(j),
363 rxclko => spw_rxclk(j),
364 do => swni.d(j),
365 ndo => swni.nd(j*5+4 DOWNTO j*5),
366 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
367 END GENERATE spw_inputloop;
368
369 -- SPW core
370 sw0 : grspwm GENERIC MAP(
371 tech => apa3e,
372 hindex => 1,
373 pindex => 5,
374 paddr => 5,
375 pirq => 11,
376 sysfreq => 25000, -- CPU_FREQ
377 rmap => 1,
378 rmapcrc => 1,
379 fifosize1 => 16,
380 fifosize2 => 16,
381 rxclkbuftype => 1,
382 rxunaligned => 0,
383 rmapbufs => 4,
384 ft => 0,
385 netlist => 0,
386 ports => 2,
387 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
388 memtech => apa3e,
389 destkey => 2,
390 spwcore => 1
391 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
392 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
393 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
394 )
395 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
396 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
397 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
398 swni, swno);
399
400 swni.tickin <= '0';
401 swni.rmapen <= '1';
402 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
403 swni.tickinraw <= '0';
404 swni.timein <= (OTHERS => '0');
405 swni.dcrstval <= (OTHERS => '0');
406 swni.timerrstval <= (OTHERS => '0');
407
408 -------------------------------------------------------------------------------
409 -- LFR ------------------------------------------------------------------------
410 -------------------------------------------------------------------------------
411 LFR_rstn <= LFR_soft_rstn AND rstn_25;
412
413 lpp_lfr_1 : lpp_lfr
414 GENERIC MAP (
415 Mem_use => use_RAM,
416 tech => inferred,
417 nb_data_by_buffer_size => 32,
418 --nb_word_by_buffer_size => 30,
419 nb_snapshot_param_size => 32,
420 delta_vector_size => 32,
421 delta_vector_size_f0_2 => 7, -- log2(96)
422 pindex => 15,
423 paddr => 15,
424 pmask => 16#fff#,
425 pirq_ms => 6,
426 pirq_wfp => 14,
427 hindex => 2,
428 top_lfr_version => X"010158", -- aa.bb.cc version
429 -- AA : BOARD NUMBER
430 -- 0 => MINI_LFR
431 -- 1 => EM
432 DEBUG_FORCE_DATA_DMA => 0,
433 RTL_DESIGN_LIGHT => 1,
434 WINDOWS_HAANNING_PARAM_SIZE => 10)
435 PORT MAP (
436 clk => clk_25,
437 rstn => LFR_rstn,
438 sample_B => sample_s(2 DOWNTO 0),
439 sample_E => sample_s(7 DOWNTO 3),
440 sample_val => sample_val,
441 apbi => apbi_ext,
442 apbo => apbo_ext(15),
443 ahbi => ahbi_m_ext,
444 ahbo => ahbo_m_ext(2),
445 coarse_time => coarse_time,
446 fine_time => fine_time,
447 data_shaping_BW => bias_fail_sw,
448 debug_vector => OPEN,
449 debug_vector_ms => OPEN); --,
450 --observation_vector_0 => OPEN,
451 --observation_vector_1 => OPEN,
452 --observation_reg => observation_reg);
453
454
455 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
456 sample_s(I) <= sample(I) & '0' & '0';
457 END GENERATE all_sample;
458 sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8);
459
460 -----------------------------------------------------------------------------
461 --
462 -----------------------------------------------------------------------------
463 top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
464 GENERIC MAP (
465 ChanelCount => 9,
466 ncycle_cnv_high => 12,
467 ncycle_cnv => 25,
468 FILTER_ENABLED => 16#FF#)
469 PORT MAP (
470 cnv_clk => clk_24,
471 cnv_rstn => rstn_24,
472 cnv => ADC_smpclk_s,
473 clk => clk_25,
474 rstn => rstn_25,
475 ADC_data => ADC_data,
476 ADC_nOE => ADC_OEB_bar_CH_s,
477 sample => sample,
478 sample_val => sample_val);
479
480 ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0);
481
482 ADC_smpclk <= ADC_smpclk_s;
483 HK_smpclk <= ADC_smpclk_s;
484
485 TAG8 <= ADC_smpclk_s;
486
487 -----------------------------------------------------------------------------
488 -- HK
489 -----------------------------------------------------------------------------
490 ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8);
491
492 END beh;
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1 #GRLIB=../..
2 VHDLIB=../..
3 SCRIPTSDIR=$(VHDLIB)/scripts/
4 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
5 TOP=LFR_em
6 BOARD=em-LeonLPP-A3PE3kL-v3-core1
7 include $(VHDLIB)/boards/$(BOARD)/Makefile.inc
8 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
9 UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf
10 QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
11 EFFORT=high
12 XSTOPT=
13 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
14 #VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd
15 #VHDLSYNFILES=config.vhd leon3mp.vhd
16 VHDLSYNFILES=LFR-em.vhd
17 VHDLSIMFILES=testbench.vhd
18 #SIMTOP=testbench
19 #SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc
20 #SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc
21 PDC=$(VHDLIB)/boards/$(BOARD)/LFR-em_1.1.85.pdc
22
23 SDCFILE=$(VHDLIB)/boards/$(BOARD)/LFR-em_1.1.85.sdc
24 SDC=$(VHDLIB)/boards/$(BOARD)/LFR-em_1.1.85.sdc
25
26 BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut
27 CLEAN=soft-clean
28
29 TECHLIBS = proasic3e
30
31 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
32 tmtc openchip hynix ihp gleichmann micron usbhc
33
34 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
35 pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
36 ./amba_lcd_16x2_ctrlr \
37 ./general_purpose/lpp_AMR \
38 ./general_purpose/lpp_balise \
39 ./general_purpose/lpp_delay \
40 ./lpp_bootloader \
41 ./dsp/lpp_fft_rtax \
42 ./lpp_uart \
43 ./lpp_usb \
44 ./lpp_sim/CY7C1061DV33 \
45
46 FILESKIP = i2cmst.vhd \
47 APB_MULTI_DIODE.vhd \
48 APB_MULTI_DIODE.vhd \
49 Top_MatrixSpec.vhd \
50 APB_FFT.vhd\
51 CoreFFT_simu.vhd \
52 lpp_lfr_apbreg_simu.vhd
53
54 include $(GRLIB)/bin/Makefile
55 include $(GRLIB)/software/leon3/Makefile
56
57 ################## project specific targets ##########################
58
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@@ -1,223 +1,233
1
1
2 LIBRARY IEEE;
2 LIBRARY IEEE;
3 USE IEEE.STD_LOGIC_1164.ALL;
3 USE IEEE.STD_LOGIC_1164.ALL;
4 USE IEEE.numeric_std.ALL;
4 USE IEEE.numeric_std.ALL;
5 LIBRARY lpp;
5 LIBRARY lpp;
6 USE lpp.lpp_ad_conv.ALL;
6 USE lpp.lpp_ad_conv.ALL;
7 USE lpp.general_purpose.SYNC_FF;
7 USE lpp.general_purpose.SYNC_FF;
8
8
9 ENTITY top_ad_conv_RHF1401_withFilter IS
9 ENTITY top_ad_conv_RHF1401_withFilter IS
10 GENERIC(
10 GENERIC(
11 ChanelCount : INTEGER := 8;
11 ChanelCount : INTEGER := 8;
12 ncycle_cnv_high : INTEGER := 13;
12 ncycle_cnv_high : INTEGER := 13;
13 ncycle_cnv : INTEGER := 25;
13 ncycle_cnv : INTEGER := 25;
14 FILTER_ENABLED : INTEGER := 16#FF#
14 FILTER_ENABLED : INTEGER := 16#FF#
15 );
15 );
16 PORT (
16 PORT (
17 cnv_clk : IN STD_LOGIC; -- 24Mhz
17 cnv_clk : IN STD_LOGIC; -- 24Mhz
18 cnv_rstn : IN STD_LOGIC;
18 cnv_rstn : IN STD_LOGIC;
19
19
20 cnv : OUT STD_LOGIC;
20 cnv : OUT STD_LOGIC;
21
21
22 clk : IN STD_LOGIC; -- 25MHz
22 clk : IN STD_LOGIC; -- 25MHz
23 rstn : IN STD_LOGIC;
23 rstn : IN STD_LOGIC;
24 ADC_data : IN Samples14;
24 ADC_data : IN Samples14;
25 ADC_nOE : OUT STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
25 ADC_nOE : OUT STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
26 sample : OUT Samples14v(ChanelCount-1 DOWNTO 0);
26 sample : OUT Samples14v(ChanelCount-1 DOWNTO 0);
27 sample_val : OUT STD_LOGIC
27 sample_val : OUT STD_LOGIC
28 );
28 );
29 END top_ad_conv_RHF1401_withFilter;
29 END top_ad_conv_RHF1401_withFilter;
30
30
31 ARCHITECTURE ar_top_ad_conv_RHF1401 OF top_ad_conv_RHF1401_withFilter IS
31 ARCHITECTURE ar_top_ad_conv_RHF1401 OF top_ad_conv_RHF1401_withFilter IS
32
32
33 -----------------------------------------------------------------------------
33 -----------------------------------------------------------------------------
34 -- CNV GEN
34 -- CNV GEN
35 -----------------------------------------------------------------------------
35 -----------------------------------------------------------------------------
36 SIGNAL cnv_cycle_counter : INTEGER RANGE 0 TO ncycle_cnv-1;
36 SIGNAL cnv_cycle_counter : INTEGER RANGE 0 TO ncycle_cnv-1;
37 SIGNAL cnv_s : STD_LOGIC;
37 SIGNAL cnv_s : STD_LOGIC;
38 SIGNAL cnv_s_reg : STD_LOGIC;
38 SIGNAL cnv_s_reg : STD_LOGIC;
39
39
40 -----------------------------------------------------------------------------
40 -----------------------------------------------------------------------------
41 -- SYNC CNV
41 -- SYNC CNV
42 -----------------------------------------------------------------------------
42 -----------------------------------------------------------------------------
43 SIGNAL cnv_sync : STD_LOGIC;
43 SIGNAL cnv_sync : STD_LOGIC;
44 SIGNAL cnv_sync_pre : STD_LOGIC;
44 SIGNAL cnv_sync_pre : STD_LOGIC;
45 SIGNAL cnv_sync_falling_edge : STD_LOGIC;
45 SIGNAL cnv_sync_falling_edge : STD_LOGIC;
46
46
47 -----------------------------------------------------------------------------
47 -----------------------------------------------------------------------------
48 -- DATA Read and Data Output Enable
48 -- DATA Read and Data Output Enable
49 -----------------------------------------------------------------------------
49 -----------------------------------------------------------------------------
50 CONSTANT MAX_CHANNEL_COUNTER : INTEGER := (ChanelCount-1)*2 + 5;
50 CONSTANT MAX_CHANNEL_COUNTER : INTEGER := (ChanelCount-1)*2 + 5;
51 SIGNAL channel_counter : INTEGER RANGE 0 TO MAX_CHANNEL_COUNTER;
51 SIGNAL channel_counter : INTEGER RANGE 0 TO MAX_CHANNEL_COUNTER;
52 SIGNAL channel_counter_r : INTEGER RANGE 0 TO MAX_CHANNEL_COUNTER;
52 SIGNAL channel_counter_r : INTEGER RANGE 0 TO MAX_CHANNEL_COUNTER;
53 SIGNAL channel_counter_r2 : INTEGER RANGE 0 TO MAX_CHANNEL_COUNTER;
53 SIGNAL channel_counter_r2 : INTEGER RANGE 0 TO MAX_CHANNEL_COUNTER;
54 SIGNAL channel_counter_d1 : INTEGER RANGE 0 TO MAX_CHANNEL_COUNTER;
54 SIGNAL channel_counter_d1 : INTEGER RANGE 0 TO MAX_CHANNEL_COUNTER;
55
55
56 SIGNAL channel_sel_n : STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
56 SIGNAL channel_sel_n : STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
57
57
58 SIGNAL sample_reg : Samples14v(ChanelCount-1 DOWNTO 0);
58 SIGNAL sample_reg : Samples14v(ChanelCount-1 DOWNTO 0);
59 SIGNAL ADC_data_d1 : Samples14;
59 SIGNAL ADC_data_d1 : Samples14;
60 SIGNAL ADC_data_selected : Samples14;
60 SIGNAL ADC_data_selected : Samples14;
61 SIGNAL ADC_data_result : Samples15;
61 SIGNAL ADC_data_result : Samples15;
62
63 CONSTANT SAMPLE_FREQ_DIV_FACTOR : INTEGER := 10;
64 SIGNAL sample_val_counter : INTEGER RANGE 0 TO SAMPLE_FREQ_DIV_FACTOR;
62
65
63
66
64 CONSTANT FILTER_ENABLED_STDLOGIC : STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(FILTER_ENABLED, ChanelCount));
67 CONSTANT FILTER_ENABLED_STDLOGIC : STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(FILTER_ENABLED, ChanelCount));
65
68
66 BEGIN
69 BEGIN
67
70
68
71
69 -----------------------------------------------------------------------------
72 -----------------------------------------------------------------------------
70 -- CNV GEN
73 -- CNV GEN
71 -----------------------------------------------------------------------------
74 -----------------------------------------------------------------------------
72 PROCESS (cnv_clk, cnv_rstn)
75 PROCESS (cnv_clk, cnv_rstn)
73 BEGIN -- PROCESS
76 BEGIN -- PROCESS
74 IF cnv_rstn = '0' THEN -- asynchronous reset (active low)
77 IF cnv_rstn = '0' THEN -- asynchronous reset (active low)
75 cnv_cycle_counter <= 0;
78 cnv_cycle_counter <= 0;
76 cnv_s <= '0';
79 cnv_s <= '0';
77 ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge
80 ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge
78 IF cnv_cycle_counter < ncycle_cnv-1 THEN
81 IF cnv_cycle_counter < ncycle_cnv-1 THEN
79 cnv_cycle_counter <= cnv_cycle_counter + 1;
82 cnv_cycle_counter <= cnv_cycle_counter + 1;
80 IF cnv_cycle_counter < ncycle_cnv_high THEN
83 IF cnv_cycle_counter < ncycle_cnv_high THEN
81 cnv_s <= '1';
84 cnv_s <= '1';
82 ELSE
85 ELSE
83 cnv_s <= '0';
86 cnv_s <= '0';
84 END IF;
87 END IF;
85 ELSE
88 ELSE
86 cnv_s <= '1';
89 cnv_s <= '1';
87 cnv_cycle_counter <= 0;
90 cnv_cycle_counter <= 0;
88 END IF;
91 END IF;
89 END IF;
92 END IF;
90 END PROCESS;
93 END PROCESS;
91
94
92 cnv <= cnv_s;
95 cnv <= cnv_s;
93
96
94 PROCESS (cnv_clk, cnv_rstn)
97 PROCESS (cnv_clk, cnv_rstn)
95 BEGIN -- PROCESS
98 BEGIN -- PROCESS
96 IF cnv_rstn = '0' THEN -- asynchronous reset (active low)
99 IF cnv_rstn = '0' THEN -- asynchronous reset (active low)
97 cnv_s_reg <= '0';
100 cnv_s_reg <= '0';
98 ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge
101 ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge
99 cnv_s_reg <= cnv_s;
102 cnv_s_reg <= cnv_s;
100 END IF;
103 END IF;
101 END PROCESS;
104 END PROCESS;
102
105
103
106
104 -----------------------------------------------------------------------------
107 -----------------------------------------------------------------------------
105 -- SYNC CNV
108 -- SYNC CNV
106 -----------------------------------------------------------------------------
109 -----------------------------------------------------------------------------
107
110
108 SYNC_FF_cnv : SYNC_FF
111 SYNC_FF_cnv : SYNC_FF
109 GENERIC MAP (
112 GENERIC MAP (
110 NB_FF_OF_SYNC => 2)
113 NB_FF_OF_SYNC => 2)
111 PORT MAP (
114 PORT MAP (
112 clk => clk,
115 clk => clk,
113 rstn => rstn,
116 rstn => rstn,
114 A => cnv_s_reg,
117 A => cnv_s_reg,
115 A_sync => cnv_sync);
118 A_sync => cnv_sync);
116
119
117 PROCESS (clk, rstn)
120 PROCESS (clk, rstn)
118 BEGIN -- PROCESS
121 BEGIN -- PROCESS
119 IF rstn = '0' THEN -- asynchronous reset (active low)
122 IF rstn = '0' THEN -- asynchronous reset (active low)
120 cnv_sync_pre <= '0';
123 cnv_sync_pre <= '0';
121 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
124 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
122 cnv_sync_pre <= cnv_sync;
125 cnv_sync_pre <= cnv_sync;
123 END IF;
126 END IF;
124 END PROCESS;
127 END PROCESS;
125
128
126 cnv_sync_falling_edge <= '1' WHEN cnv_sync = '0' AND cnv_sync_pre = '1' ELSE '0';
129 cnv_sync_falling_edge <= '1' WHEN cnv_sync = '0' AND cnv_sync_pre = '1' ELSE '0';
127
130
128
131
129 -----------------------------------------------------------------------------
132 -----------------------------------------------------------------------------
130 -- DATA Read and Data Output Enable
133 -- DATA Read and Data Output Enable
131 -----------------------------------------------------------------------------
134 -----------------------------------------------------------------------------
132
135
133 PROCESS (clk, rstn)
136 PROCESS (clk, rstn)
134 BEGIN -- PROCESS
137 BEGIN -- PROCESS
135 IF rstn = '0' THEN -- asynchronous reset (active low)
138 IF rstn = '0' THEN -- asynchronous reset (active low)
136 channel_counter <= MAX_CHANNEL_COUNTER;
139 channel_counter <= MAX_CHANNEL_COUNTER;
137 sample_val <= '0';
140 sample_val <= '0';
141 sample_val_counter <= 0;
138 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
142 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
139 IF cnv_sync_falling_edge = '1' THEN
143 IF cnv_sync_falling_edge = '1' THEN
140 channel_counter <= 0;
144 channel_counter <= 0;
141 ELSE
145 ELSE
142 IF channel_counter < MAX_CHANNEL_COUNTER THEN
146 IF channel_counter < MAX_CHANNEL_COUNTER THEN
143 channel_counter <= channel_counter + 1;
147 channel_counter <= channel_counter + 1;
144 END IF;
148 END IF;
145 END IF;
149 END IF;
146
150
147 IF channel_counter = MAX_CHANNEL_COUNTER-1 THEN
151 IF channel_counter = MAX_CHANNEL_COUNTER-1 THEN
148 sample_val <= '1';
152 IF sample_val_counter = SAMPLE_FREQ_DIV_FACTOR-1 THEN
153 sample_val_counter <= 0;
154 sample_val <= '1';
155 ELSE
156 sample_val_counter <= sample_val_counter +1;
157 sample_val <= '0';
158 END IF;
149 ELSE
159 ELSE
150 sample_val <= '0';
160 sample_val <= '0';
151 END IF;
161 END IF;
152 END IF;
162 END IF;
153 END PROCESS;
163 END PROCESS;
154
164
155 all_channel: FOR I IN 0 TO ChanelCount-1 GENERATE
165 all_channel: FOR I IN 0 TO ChanelCount-1 GENERATE
156 channel_sel_n(I) <= '0' WHEN channel_counter = 2*I ELSE '1';
166 channel_sel_n(I) <= '0' WHEN channel_counter = 2*I ELSE '1';
157
167
158 PROCESS (clk, rstn)
168 PROCESS (clk, rstn)
159 BEGIN -- PROCESS
169 BEGIN -- PROCESS
160 IF rstn = '0' THEN -- asynchronous reset (active low)
170 IF rstn = '0' THEN -- asynchronous reset (active low)
161 sample_reg(I) <= (OTHERS => '0');
171 sample_reg(I) <= (OTHERS => '0');
162 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
172 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
163 IF channel_counter_d1 = 2*I THEN
173 IF channel_counter_d1 = 2*I THEN
164 IF FILTER_ENABLED_STDLOGIC(I) = '1' THEN
174 IF FILTER_ENABLED_STDLOGIC(I) = '1' THEN
165 sample_reg(I) <= ADC_data_result(14 DOWNTO 1);
175 sample_reg(I) <= ADC_data_result(14 DOWNTO 1);
166 ELSE
176 ELSE
167 sample_reg(I) <= ADC_data_d1;
177 sample_reg(I) <= ADC_data_d1;
168 END IF;
178 END IF;
169 END IF;
179 END IF;
170 END IF;
180 END IF;
171 END PROCESS;
181 END PROCESS;
172
182
173 END GENERATE all_channel;
183 END GENERATE all_channel;
174
184
175 PROCESS (clk, rstn)
185 PROCESS (clk, rstn)
176 BEGIN -- PROCESS
186 BEGIN -- PROCESS
177 IF rstn = '0' THEN -- asynchronous reset (active low)
187 IF rstn = '0' THEN -- asynchronous reset (active low)
178 ADC_nOE <= (OTHERS => '1');
188 ADC_nOE <= (OTHERS => '1');
179 channel_counter_r <= MAX_CHANNEL_COUNTER;
189 channel_counter_r <= MAX_CHANNEL_COUNTER;
180 channel_counter_r2 <= MAX_CHANNEL_COUNTER;
190 channel_counter_r2 <= MAX_CHANNEL_COUNTER;
181 channel_counter_d1 <= MAX_CHANNEL_COUNTER;
191 channel_counter_d1 <= MAX_CHANNEL_COUNTER;
182 ADC_data_d1 <= (OTHERS => '0');
192 ADC_data_d1 <= (OTHERS => '0');
183 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
193 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
184 ADC_nOE <= channel_sel_n;
194 ADC_nOE <= channel_sel_n;
185 channel_counter_r <= channel_counter;
195 channel_counter_r <= channel_counter;
186 channel_counter_r2 <= channel_counter_r;
196 channel_counter_r2 <= channel_counter_r;
187 channel_counter_d1 <= channel_counter_r2;
197 channel_counter_d1 <= channel_counter_r2;
188 ADC_data_d1 <= ADC_data;
198 ADC_data_d1 <= ADC_data;
189 END IF;
199 END IF;
190 END PROCESS;
200 END PROCESS;
191
201
192 WITH channel_counter_d1 SELECT
202 WITH channel_counter_d1 SELECT
193 ADC_data_selected <= sample_reg(0) WHEN 0*2,
203 ADC_data_selected <= sample_reg(0) WHEN 0*2,
194 sample_reg(1) WHEN 1*2,
204 sample_reg(1) WHEN 1*2,
195 sample_reg(2) WHEN 2*2,
205 sample_reg(2) WHEN 2*2,
196 sample_reg(3) WHEN 3*2,
206 sample_reg(3) WHEN 3*2,
197 sample_reg(4) WHEN 4*2,
207 sample_reg(4) WHEN 4*2,
198 sample_reg(5) WHEN 5*2,
208 sample_reg(5) WHEN 5*2,
199 sample_reg(6) WHEN 6*2,
209 sample_reg(6) WHEN 6*2,
200 sample_reg(7) WHEN 7*2,
210 sample_reg(7) WHEN 7*2,
201 sample_reg(8) WHEN OTHERS;
211 sample_reg(8) WHEN OTHERS;
202
212
203 ADC_data_result <= STD_LOGIC_VECTOR((SIGNED(ADC_data_selected(13) & ADC_data_selected) + SIGNED(ADC_data_d1(13) & ADC_data_d1)));
213 ADC_data_result <= STD_LOGIC_VECTOR((SIGNED(ADC_data_selected(13) & ADC_data_selected) + SIGNED(ADC_data_d1(13) & ADC_data_d1)));
204
214
205 sample <= sample_reg;
215 sample <= sample_reg;
206
216
207
217
208
218
209 END ar_top_ad_conv_RHF1401;
219 END ar_top_ad_conv_RHF1401;
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