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1 | ------------------------------------------------------------------------------ | |||
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2 | -- This file is a part of the LPP VHDL IP LIBRARY | |||
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3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |||
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4 | -- | |||
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5 | -- This program is free software; you can redistribute it and/or modify | |||
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6 | -- it under the terms of the GNU General Public License as published by | |||
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7 | -- the Free Software Foundation; either version 3 of the License, or | |||
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8 | -- (at your option) any later version. | |||
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9 | -- | |||
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10 | -- This program is distributed in the hope that it will be useful, | |||
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11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
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12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
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13 | -- GNU General Public License for more details. | |||
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14 | -- | |||
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15 | -- You should have received a copy of the GNU General Public License | |||
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16 | -- along with this program; if not, write to the Free Software | |||
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17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
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18 | ------------------------------------------------------------------------------- | |||
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19 | -- Author : Jean-christophe Pellion | |||
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20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |||
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21 | -- jean-christophe.pellion@easii-ic.com | |||
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22 | ---------------------------------------------------------------------------- | |||
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23 | ||||
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24 | LIBRARY ieee; | |||
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25 | USE ieee.std_logic_1164.ALL; | |||
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26 | ||||
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27 | ENTITY lpp_apbreg_ms_pointer IS | |||
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28 | ||||
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29 | PORT ( | |||
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30 | clk : IN STD_LOGIC; | |||
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31 | rstn : IN STD_LOGIC; | |||
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32 | ||||
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33 | -- REG 0 | |||
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34 | reg0_status_ready_matrix : IN STD_LOGIC; | |||
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35 | reg0_ready_matrix : OUT STD_LOGIC; | |||
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36 | reg0_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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37 | reg0_matrix_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |||
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38 | ||||
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39 | -- REG 1 | |||
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40 | reg1_status_ready_matrix : IN STD_LOGIC; | |||
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41 | reg1_ready_matrix : OUT STD_LOGIC; | |||
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42 | reg1_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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43 | reg1_matrix_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |||
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44 | ||||
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45 | -- SpectralMatrix | |||
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46 | ready_matrix : IN STD_LOGIC; | |||
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47 | status_ready_matrix : OUT STD_LOGIC; | |||
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48 | addr_matrix : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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49 | matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0) | |||
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50 | ); | |||
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51 | ||||
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52 | END lpp_apbreg_ms_pointer; | |||
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53 | ||||
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54 | ARCHITECTURE beh OF lpp_apbreg_ms_pointer IS | |||
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55 | ||||
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56 | SIGNAL current_reg : STD_LOGIC; | |||
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57 | ||||
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58 | BEGIN -- beh | |||
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59 | ||||
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60 | PROCESS (clk, rstn) | |||
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61 | BEGIN -- PROCESS | |||
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62 | IF rstn = '0' THEN -- asynchronous reset (active low) | |||
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63 | current_reg <= '0'; | |||
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64 | ||||
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65 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |||
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66 | IF ready_matrix = '1' THEN | |||
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67 | current_reg <= NOT current_reg; | |||
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68 | END IF; | |||
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69 | END IF; | |||
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70 | END PROCESS; | |||
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71 | ||||
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72 | addr_matrix <= reg0_addr_matrix WHEN current_reg = '0' ELSE | |||
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73 | reg1_addr_matrix; | |||
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74 | ||||
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75 | status_ready_matrix <= reg0_status_ready_matrix WHEN current_reg = '0' ELSE | |||
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76 | reg1_status_ready_matrix; | |||
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77 | ||||
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78 | reg0_ready_matrix <= ready_matrix WHEN current_reg = '0' ELSE '0'; | |||
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79 | reg1_ready_matrix <= ready_matrix WHEN current_reg = '1' ELSE '0'; | |||
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80 | ||||
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81 | END beh; No newline at end of file | |||
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