@@ -1,198 +1,212 | |||
|
1 | 1 | ------------------------------------------------------------------------------ |
|
2 | 2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
3 | 3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
4 | 4 | -- |
|
5 | 5 | -- This program is free software; you can redistribute it and/or modify |
|
6 | 6 | -- it under the terms of the GNU General Public License as published by |
|
7 | 7 | -- the Free Software Foundation; either version 3 of the License, or |
|
8 | 8 | -- (at your option) any later version. |
|
9 | 9 | -- |
|
10 | 10 | -- This program is distributed in the hope that it will be useful, |
|
11 | 11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
12 | 12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
13 | 13 | -- GNU General Public License for more details. |
|
14 | 14 | -- |
|
15 | 15 | -- You should have received a copy of the GNU General Public License |
|
16 | 16 | -- along with this program; if not, write to the Free Software |
|
17 | 17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
18 | 18 | ------------------------------------------------------------------------------- |
|
19 | 19 | -- Author : Jean-christophe Pellion |
|
20 | 20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
|
21 | 21 | -- jean-christophe.pellion@easii-ic.com |
|
22 | 22 | ---------------------------------------------------------------------------- |
|
23 | 23 | LIBRARY ieee; |
|
24 | 24 | USE ieee.std_logic_1164.ALL; |
|
25 | 25 | USE ieee.numeric_std.ALL; |
|
26 | 26 | LIBRARY grlib; |
|
27 | 27 | USE grlib.amba.ALL; |
|
28 | 28 | USE grlib.stdlib.ALL; |
|
29 | 29 | USE grlib.devices.ALL; |
|
30 | 30 | LIBRARY lpp; |
|
31 | 31 | USE lpp.lpp_amba.ALL; |
|
32 | 32 | USE lpp.apb_devices_list.ALL; |
|
33 | 33 | USE lpp.lpp_memory.ALL; |
|
34 | 34 | LIBRARY techmap; |
|
35 | 35 | USE techmap.gencomp.ALL; |
|
36 | 36 | |
|
37 | 37 | ENTITY lpp_top_apbreg IS |
|
38 | 38 | GENERIC ( |
|
39 | 39 | pindex : INTEGER := 4; |
|
40 | 40 | paddr : INTEGER := 4; |
|
41 | 41 | pmask : INTEGER := 16#fff#; |
|
42 | 42 | pirq : INTEGER := 0); |
|
43 | 43 | PORT ( |
|
44 | 44 | -- AMBA AHB system signals |
|
45 | 45 | HCLK : IN STD_ULOGIC; |
|
46 | 46 | HRESETn : IN STD_ULOGIC; |
|
47 | 47 | |
|
48 | 48 | -- AMBA APB Slave Interface |
|
49 | 49 | apbi : IN apb_slv_in_type; |
|
50 | 50 | apbo : OUT apb_slv_out_type; |
|
51 | 51 | |
|
52 | 52 | -- IN |
|
53 | 53 | ready_matrix_f0_0 : IN STD_LOGIC; |
|
54 | 54 | ready_matrix_f0_1 : IN STD_LOGIC; |
|
55 | 55 | ready_matrix_f1 : IN STD_LOGIC; |
|
56 | 56 | ready_matrix_f2 : IN STD_LOGIC; |
|
57 | 57 | error_anticipating_empty_fifo : IN STD_LOGIC; |
|
58 | 58 | error_bad_component_error : IN STD_LOGIC; |
|
59 | 59 | debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
60 | 60 | |
|
61 | 61 | -- OUT |
|
62 | 62 | status_ready_matrix_f0_0 : OUT STD_LOGIC; |
|
63 | 63 | status_ready_matrix_f0_1 : OUT STD_LOGIC; |
|
64 | 64 | status_ready_matrix_f1 : OUT STD_LOGIC; |
|
65 | 65 | status_ready_matrix_f2 : OUT STD_LOGIC; |
|
66 | 66 | status_error_anticipating_empty_fifo : OUT STD_LOGIC; |
|
67 | 67 | status_error_bad_component_error : OUT STD_LOGIC; |
|
68 | 68 | |
|
69 | 69 | config_active_interruption_onNewMatrix : OUT STD_LOGIC; |
|
70 | 70 | config_active_interruption_onError : OUT STD_LOGIC; |
|
71 | 71 | addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
72 | 72 | addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
73 | 73 | addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
74 | 74 | addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) |
|
75 | 75 | ); |
|
76 | 76 | |
|
77 | 77 | END lpp_top_apbreg; |
|
78 | 78 | |
|
79 | 79 | ARCHITECTURE beh OF lpp_top_apbreg IS |
|
80 | 80 | |
|
81 | 81 | CONSTANT REVISION : INTEGER := 1; |
|
82 | 82 | |
|
83 | 83 | CONSTANT pconfig : apb_config_type := ( |
|
84 | 84 | 0 => ahb_device_reg (VENDOR_LPP, LPP_DMA_TYPE, 0, REVISION, pirq), |
|
85 | 85 | 1 => apb_iobar(paddr, pmask)); |
|
86 | 86 | |
|
87 | 87 | TYPE lpp_dma_regs IS RECORD |
|
88 | 88 | config_active_interruption_onNewMatrix : STD_LOGIC; |
|
89 | 89 | config_active_interruption_onError : STD_LOGIC; |
|
90 | 90 | status_ready_matrix_f0_0 : STD_LOGIC; |
|
91 | 91 | status_ready_matrix_f0_1 : STD_LOGIC; |
|
92 | 92 | status_ready_matrix_f1 : STD_LOGIC; |
|
93 | 93 | status_ready_matrix_f2 : STD_LOGIC; |
|
94 | 94 | status_error_anticipating_empty_fifo : STD_LOGIC; |
|
95 | 95 | status_error_bad_component_error : STD_LOGIC; |
|
96 | 96 | addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
97 | 97 | addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
98 | 98 | addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
99 | 99 | addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
100 | 100 | END RECORD; |
|
101 | 101 | |
|
102 | 102 | SIGNAL reg : lpp_dma_regs; |
|
103 | 103 | |
|
104 | 104 | SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
105 | 105 | |
|
106 | 106 | BEGIN -- beh |
|
107 | 107 | |
|
108 | 108 | status_ready_matrix_f0_0 <= reg.status_ready_matrix_f0_0; |
|
109 | 109 | status_ready_matrix_f0_1 <= reg.status_ready_matrix_f0_1; |
|
110 | 110 | status_ready_matrix_f1 <= reg.status_ready_matrix_f1; |
|
111 | 111 | status_ready_matrix_f2 <= reg.status_ready_matrix_f2; |
|
112 | 112 | status_error_anticipating_empty_fifo <= reg.status_error_anticipating_empty_fifo; |
|
113 | 113 | status_error_bad_component_error <= reg.status_error_bad_component_error; |
|
114 | 114 | |
|
115 | 115 | config_active_interruption_onNewMatrix <= reg.config_active_interruption_onNewMatrix; |
|
116 | 116 | config_active_interruption_onError <= reg.config_active_interruption_onError; |
|
117 | 117 | addr_matrix_f0_0 <= reg.addr_matrix_f0_0; |
|
118 | 118 | addr_matrix_f0_1 <= reg.addr_matrix_f0_1; |
|
119 | 119 | addr_matrix_f1 <= reg.addr_matrix_f1; |
|
120 | 120 | addr_matrix_f2 <= reg.addr_matrix_f2; |
|
121 | 121 | |
|
122 | 122 | lpp_top_apbreg : PROCESS (HCLK, HRESETn) |
|
123 | 123 | VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2); |
|
124 | 124 | BEGIN -- PROCESS lpp_dma_top |
|
125 | 125 | IF HRESETn = '0' THEN -- asynchronous reset (active low) |
|
126 | 126 | reg.config_active_interruption_onNewMatrix <= '0'; |
|
127 | 127 | reg.config_active_interruption_onError <= '0'; |
|
128 | 128 | reg.status_ready_matrix_f0_0 <= '0'; |
|
129 | 129 | reg.status_ready_matrix_f0_1 <= '0'; |
|
130 | 130 | reg.status_ready_matrix_f1 <= '0'; |
|
131 | 131 | reg.status_ready_matrix_f2 <= '0'; |
|
132 | 132 | reg.status_error_anticipating_empty_fifo <= '0'; |
|
133 | 133 | reg.status_error_bad_component_error <= '0'; |
|
134 | 134 | reg.addr_matrix_f0_0 <= (OTHERS => '0'); |
|
135 | 135 | reg.addr_matrix_f0_1 <= (OTHERS => '0'); |
|
136 | 136 | reg.addr_matrix_f1 <= (OTHERS => '0'); |
|
137 | 137 | reg.addr_matrix_f2 <= (OTHERS => '0'); |
|
138 | 138 | prdata <= (OTHERS => '0'); |
|
139 | ||
|
140 | apbo.pirq <= (OTHERS => '0'); | |
|
141 | ||
|
139 | 142 |
|
|
140 | 143 | |
|
141 | 144 | reg.status_ready_matrix_f0_0 <= reg.status_ready_matrix_f0_0 OR ready_matrix_f0_0; |
|
142 | 145 | reg.status_ready_matrix_f0_1 <= reg.status_ready_matrix_f0_1 OR ready_matrix_f0_1; |
|
143 | 146 | reg.status_ready_matrix_f1 <= reg.status_ready_matrix_f1 OR ready_matrix_f1; |
|
144 | 147 | reg.status_ready_matrix_f2 <= reg.status_ready_matrix_f2 OR ready_matrix_f2; |
|
145 | 148 | |
|
146 | 149 | reg.status_error_anticipating_empty_fifo <= reg.status_error_anticipating_empty_fifo OR error_anticipating_empty_fifo; |
|
147 | 150 | reg.status_error_bad_component_error <= reg.status_error_bad_component_error OR error_bad_component_error; |
|
148 | 151 | |
|
149 | 152 | paddr := "000000"; |
|
150 | 153 | paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2); |
|
151 | 154 | prdata <= (OTHERS => '0'); |
|
152 | 155 | IF apbi.psel(pindex) = '1' THEN |
|
153 | 156 | -- APB DMA READ -- |
|
154 | 157 | CASE paddr(7 DOWNTO 2) IS |
|
155 | 158 | WHEN "000000" => prdata(0) <= reg.config_active_interruption_onNewMatrix; |
|
156 | 159 | prdata(1) <= reg.config_active_interruption_onError; |
|
157 | 160 | WHEN "000001" => prdata(0) <= reg.status_ready_matrix_f0_0; |
|
158 | 161 | prdata(1) <= reg.status_ready_matrix_f0_1; |
|
159 | 162 | prdata(2) <= reg.status_ready_matrix_f1; |
|
160 | 163 | prdata(3) <= reg.status_ready_matrix_f2; |
|
161 | 164 | prdata(4) <= reg.status_error_anticipating_empty_fifo; |
|
162 | 165 | prdata(5) <= reg.status_error_bad_component_error; |
|
163 | 166 | WHEN "000010" => prdata <= reg.addr_matrix_f0_0; |
|
164 | 167 | WHEN "000011" => prdata <= reg.addr_matrix_f0_1; |
|
165 | 168 | WHEN "000100" => prdata <= reg.addr_matrix_f1; |
|
166 | 169 | WHEN "000101" => prdata <= reg.addr_matrix_f2; |
|
167 | 170 | WHEN "000110" => prdata <= debug_reg; |
|
168 | 171 | WHEN OTHERS => NULL; |
|
169 | 172 | END CASE; |
|
170 | 173 | IF (apbi.pwrite AND apbi.penable) = '1' THEN |
|
171 | 174 | -- APB DMA WRITE -- |
|
172 | 175 | CASE paddr(7 DOWNTO 2) IS |
|
173 | 176 | WHEN "000000" => reg.config_active_interruption_onNewMatrix <= apbi.pwdata(0); |
|
174 | 177 | reg.config_active_interruption_onError <= apbi.pwdata(1); |
|
175 | 178 | WHEN "000001" => reg.status_ready_matrix_f0_0 <= apbi.pwdata(0); |
|
176 | 179 | reg.status_ready_matrix_f0_1 <= apbi.pwdata(1); |
|
177 | 180 | reg.status_ready_matrix_f1 <= apbi.pwdata(2); |
|
178 | 181 | reg.status_ready_matrix_f2 <= apbi.pwdata(3); |
|
179 | 182 | reg.status_error_anticipating_empty_fifo <= apbi.pwdata(4); |
|
180 | 183 | reg.status_error_bad_component_error <= apbi.pwdata(5); |
|
181 | 184 | WHEN "000010" => reg.addr_matrix_f0_0 <= apbi.pwdata; |
|
182 | 185 | WHEN "000011" => reg.addr_matrix_f0_1 <= apbi.pwdata; |
|
183 | 186 | WHEN "000100" => reg.addr_matrix_f1 <= apbi.pwdata; |
|
184 | 187 | WHEN "000101" => reg.addr_matrix_f2 <= apbi.pwdata; |
|
185 | 188 | WHEN OTHERS => NULL; |
|
186 | 189 | END CASE; |
|
187 | 190 | END IF; |
|
188 | 191 | END IF; |
|
192 | ||
|
193 | apbo.pirq(pirq) <= ( reg.config_active_interruption_onNewMatrix AND ( ready_matrix_f0_0 OR | |
|
194 | ready_matrix_f0_1 OR | |
|
195 | ready_matrix_f1 OR | |
|
196 | ready_matrix_f2) | |
|
197 | ) | |
|
198 | OR | |
|
199 | ( reg.config_active_interruption_onError AND ( error_anticipating_empty_fifo OR | |
|
200 | error_bad_component_error) | |
|
201 | ); | |
|
202 | ||
|
203 | ||
|
189 | 204 |
|
|
190 | 205 | END PROCESS lpp_top_apbreg; |
|
191 | ||
|
192 | apbo.pirq <= (OTHERS => '0'); | |
|
206 | ||
|
193 | 207 |
|
|
194 | 208 | apbo.pconfig <= pconfig; |
|
195 | 209 | apbo.prdata <= prdata; |
|
196 | 210 | |
|
197 | 211 | |
|
198 | 212 | END beh; |
@@ -1,411 +1,414 | |||
|
1 | 1 | LIBRARY ieee; |
|
2 | 2 | USE ieee.std_logic_1164.ALL; |
|
3 | 3 | LIBRARY grlib; |
|
4 | 4 | USE grlib.amba.ALL; |
|
5 | 5 | USE grlib.stdlib.ALL; |
|
6 | 6 | USE grlib.devices.ALL; |
|
7 | 7 | USE GRLIB.DMA2AHB_Package.ALL; |
|
8 | 8 | LIBRARY lpp; |
|
9 | 9 | USE lpp.lpp_ad_conv.ALL; |
|
10 | 10 | USE lpp.iir_filter.ALL; |
|
11 | 11 | USE lpp.FILTERcfg.ALL; |
|
12 | 12 | USE lpp.lpp_memory.ALL; |
|
13 | 13 | USE lpp.lpp_top_lfr_pkg.ALL; |
|
14 | 14 | USE lpp.lpp_dma_pkg.ALL; |
|
15 | 15 | USE lpp.lpp_demux.ALL; |
|
16 | 16 | USE lpp.lpp_fft.ALL; |
|
17 | 17 | use lpp.lpp_matrix.all; |
|
18 | 18 | LIBRARY techmap; |
|
19 | 19 | USE techmap.gencomp.ALL; |
|
20 | 20 | |
|
21 | 21 | ENTITY lpp_top_lfr IS |
|
22 | 22 | GENERIC( |
|
23 | 23 | tech : INTEGER := 0; |
|
24 | 24 | hindex_SpectralMatrix : INTEGER := 2; |
|
25 | 25 | pindex : INTEGER := 4; |
|
26 | 26 | paddr : INTEGER := 4; |
|
27 | 27 | pmask : INTEGER := 16#fff#; |
|
28 | 28 | pirq : INTEGER := 0 |
|
29 | 29 | ); |
|
30 | 30 | PORT ( |
|
31 | 31 | -- ADS7886 |
|
32 | 32 | cnv_run : IN STD_LOGIC; |
|
33 | 33 | cnv : OUT STD_LOGIC; |
|
34 | 34 | sck : OUT STD_LOGIC; |
|
35 | 35 | sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0); |
|
36 | 36 | -- |
|
37 | 37 | cnv_clk : IN STD_LOGIC; -- 49 MHz |
|
38 | 38 | cnv_rstn : IN STD_LOGIC; |
|
39 | 39 | -- |
|
40 | 40 | clk : IN STD_LOGIC; -- 25 MHz |
|
41 | 41 | rstn : IN STD_LOGIC; |
|
42 | 42 | -- |
|
43 | 43 | apbi : IN apb_slv_in_type; |
|
44 | 44 | apbo : OUT apb_slv_out_type; |
|
45 | 45 | |
|
46 | 46 | -- AMBA AHB Master Interface |
|
47 | 47 | AHB_DMA_SpectralMatrix_In : IN AHB_Mst_In_Type; |
|
48 | 48 | AHB_DMA_SpectralMatrix_Out : OUT AHB_Mst_Out_Type |
|
49 | 49 | ); |
|
50 | 50 | END lpp_top_lfr; |
|
51 | 51 | |
|
52 | 52 | ARCHITECTURE tb OF lpp_top_lfr IS |
|
53 | 53 | |
|
54 | 54 | ----------------------------------------------------------------------------- |
|
55 | 55 | -- f0 |
|
56 | 56 | SIGNAL sample_f0_0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
57 | 57 | SIGNAL sample_f0_1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
58 | 58 | SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
59 | 59 | -- |
|
60 | 60 | SIGNAL sample_f0_0_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
61 | 61 | SIGNAL sample_f0_0_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
62 | 62 | SIGNAL sample_f0_0_full : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
63 | 63 | SIGNAL sample_f0_0_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
64 | 64 | -- |
|
65 | 65 | SIGNAL sample_f0_1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
66 | 66 | SIGNAL sample_f0_1_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
67 | 67 | SIGNAL sample_f0_1_full : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
68 | 68 | SIGNAL sample_f0_1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
69 | 69 | ----------------------------------------------------------------------------- |
|
70 | 70 | -- f1 |
|
71 | 71 | SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
72 | 72 | SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
73 | 73 | -- |
|
74 | 74 | SIGNAL sample_f1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
75 | 75 | SIGNAL sample_f1_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
76 | 76 | SIGNAL sample_f1_full : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
77 | 77 | SIGNAL sample_f1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
78 | 78 | ----------------------------------------------------------------------------- |
|
79 | 79 | -- f2 |
|
80 | 80 | SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
81 | 81 | SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
82 | 82 | ----------------------------------------------------------------------------- |
|
83 | 83 | -- f3 |
|
84 | 84 | SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
85 | 85 | SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
86 | 86 | -- |
|
87 | 87 | SIGNAL sample_f3_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
88 | 88 | SIGNAL sample_f3_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
89 | 89 | SIGNAL sample_f3_full : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
90 | 90 | SIGNAL sample_f3_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
91 | 91 | ----------------------------------------------------------------------------- |
|
92 | 92 | |
|
93 | 93 | ----------------------------------------------------------------------------- |
|
94 | 94 | -- SPECTRAL MATRIX |
|
95 | 95 | ----------------------------------------------------------------------------- |
|
96 | 96 | SIGNAL sample_ren : STD_LOGIC_VECTOR(19 DOWNTO 0); |
|
97 | 97 | |
|
98 | 98 | SIGNAL demux_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
99 | 99 | SIGNAL demux_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
100 | 100 | SIGNAL demux_data : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
101 | 101 | |
|
102 | 102 | SIGNAL fft_fifo_full : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
103 | 103 | SIGNAL fft_fifo_data : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
104 | 104 | SIGNAL fft_fifo_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
105 | 105 | SIGNAL fft_fifo_reuse : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
106 | 106 | |
|
107 | 107 | SIGNAL SP_fifo_data : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
108 | 108 | SIGNAL SP_fifo_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
109 | 109 | |
|
110 | 110 | SIGNAL fifo_data : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
111 | 111 | SIGNAL fifo_empty : STD_LOGIC; |
|
112 | 112 | SIGNAL fifo_ren : STD_LOGIC; |
|
113 | 113 | SIGNAL header : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
114 | 114 | SIGNAL header_val : STD_LOGIC; |
|
115 | 115 | SIGNAL header_ack : STD_LOGIC; |
|
116 | 116 | |
|
117 | 117 | ----------------------------------------------------------------------------- |
|
118 | 118 | -- APB REG |
|
119 | 119 | ----------------------------------------------------------------------------- |
|
120 | 120 | SIGNAL ready_matrix_f0_0 : STD_LOGIC; |
|
121 | 121 | SIGNAL ready_matrix_f0_1 : STD_LOGIC; |
|
122 | 122 | SIGNAL ready_matrix_f1 : STD_LOGIC; |
|
123 | 123 | SIGNAL ready_matrix_f2 : STD_LOGIC; |
|
124 | 124 | SIGNAL error_anticipating_empty_fifo : STD_LOGIC; |
|
125 | 125 | SIGNAL error_bad_component_error : STD_LOGIC; |
|
126 | 126 | SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
127 | 127 | SIGNAL status_ready_matrix_f0_0 : STD_LOGIC; |
|
128 | 128 | SIGNAL status_ready_matrix_f0_1 : STD_LOGIC; |
|
129 | 129 | SIGNAL status_ready_matrix_f1 : STD_LOGIC; |
|
130 | 130 | SIGNAL status_ready_matrix_f2 : STD_LOGIC; |
|
131 | 131 | SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC; |
|
132 | 132 | SIGNAL status_error_bad_component_error : STD_LOGIC; |
|
133 | 133 | SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC; |
|
134 | 134 | SIGNAL config_active_interruption_onError : STD_LOGIC; |
|
135 | 135 | SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
136 | 136 | SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
137 | 137 | SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
138 | 138 | SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
139 | 139 | |
|
140 | 140 | BEGIN |
|
141 | 141 | |
|
142 | 142 | ----------------------------------------------------------------------------- |
|
143 | 143 | -- CNA + FILTER |
|
144 | 144 | ----------------------------------------------------------------------------- |
|
145 | 145 | lpp_top_acq_1 : lpp_top_acq |
|
146 | 146 | GENERIC MAP ( |
|
147 | 147 | tech => tech) |
|
148 | 148 | PORT MAP ( |
|
149 | 149 | cnv_run => cnv_run, |
|
150 | 150 | cnv => cnv, |
|
151 | 151 | sck => sck, |
|
152 | 152 | sdo => sdo, |
|
153 | 153 | cnv_clk => cnv_clk, |
|
154 | 154 | cnv_rstn => cnv_rstn, |
|
155 | 155 | clk => clk, |
|
156 | 156 | rstn => rstn, |
|
157 | 157 | |
|
158 | 158 | sample_f0_0_wen => sample_f0_0_wen, |
|
159 | 159 | sample_f0_1_wen => sample_f0_1_wen, |
|
160 | 160 | sample_f0_wdata => sample_f0_wdata, |
|
161 | 161 | sample_f1_wen => sample_f1_wen, |
|
162 | 162 | sample_f1_wdata => sample_f1_wdata, |
|
163 | 163 | sample_f2_wen => sample_f2_wen, |
|
164 | 164 | sample_f2_wdata => sample_f2_wdata, |
|
165 | 165 | sample_f3_wen => sample_f3_wen, |
|
166 | 166 | sample_f3_wdata => sample_f3_wdata); |
|
167 | 167 | |
|
168 | 168 | ----------------------------------------------------------------------------- |
|
169 | 169 | -- FIFO |
|
170 | 170 | ----------------------------------------------------------------------------- |
|
171 | 171 | |
|
172 | 172 | lppFIFO_f0_0 : lppFIFOxN |
|
173 | 173 | GENERIC MAP ( |
|
174 | 174 | tech => tech, |
|
175 | 175 | Data_sz => 16, |
|
176 | 176 | FifoCnt => 5, |
|
177 | 177 | Enable_ReUse => '0') |
|
178 | 178 | PORT MAP ( |
|
179 | 179 | rst => rstn, |
|
180 | 180 | wclk => clk, |
|
181 | 181 | rclk => clk, |
|
182 | 182 | ReUse => (OTHERS => '0'), |
|
183 | 183 | |
|
184 | 184 | wen => sample_f0_0_wen, |
|
185 | 185 | ren => sample_f0_0_ren, |
|
186 | 186 | wdata => sample_f0_wdata, |
|
187 | 187 | rdata => sample_f0_0_rdata, |
|
188 | 188 | full => sample_f0_0_full, |
|
189 | 189 | empty => sample_f0_0_empty); |
|
190 | 190 | |
|
191 | 191 | lppFIFO_f0_1 : lppFIFOxN |
|
192 | 192 | GENERIC MAP ( |
|
193 | 193 | tech => tech, |
|
194 | 194 | Data_sz => 16, |
|
195 | 195 | FifoCnt => 5, |
|
196 | 196 | Enable_ReUse => '0') |
|
197 | 197 | PORT MAP ( |
|
198 | 198 | rst => rstn, |
|
199 | 199 | wclk => clk, |
|
200 | 200 | rclk => clk, |
|
201 | 201 | ReUse => (OTHERS => '0'), |
|
202 | 202 | |
|
203 | 203 | wen => sample_f0_1_wen, |
|
204 | 204 | ren => sample_f0_1_ren, |
|
205 | 205 | wdata => sample_f0_wdata, |
|
206 | 206 | rdata => sample_f0_1_rdata, |
|
207 | 207 | full => sample_f0_1_full, |
|
208 | 208 | empty => sample_f0_1_empty); |
|
209 | 209 | |
|
210 | 210 | lppFIFO_f1 : lppFIFOxN |
|
211 | 211 | GENERIC MAP ( |
|
212 | 212 | tech => tech, |
|
213 | 213 | Data_sz => 16, |
|
214 | 214 | FifoCnt => 5, |
|
215 | 215 | Enable_ReUse => '0') |
|
216 | 216 | PORT MAP ( |
|
217 | 217 | rst => rstn, |
|
218 | 218 | wclk => clk, |
|
219 | 219 | rclk => clk, |
|
220 | 220 | ReUse => (OTHERS => '0'), |
|
221 | 221 | |
|
222 | 222 | wen => sample_f1_wen, |
|
223 | 223 | ren => sample_f1_ren, |
|
224 | 224 | wdata => sample_f1_wdata, |
|
225 | 225 | rdata => sample_f1_rdata, |
|
226 | 226 | full => sample_f1_full, |
|
227 | 227 | empty => sample_f1_empty); |
|
228 | 228 | |
|
229 | 229 | lppFIFO_f3 : lppFIFOxN |
|
230 | 230 | GENERIC MAP ( |
|
231 | 231 | tech => tech, |
|
232 | 232 | Data_sz => 16, |
|
233 | 233 | FifoCnt => 5, |
|
234 | 234 | Enable_ReUse => '0') |
|
235 | 235 | PORT MAP ( |
|
236 | 236 | rst => rstn, |
|
237 | 237 | wclk => clk, |
|
238 | 238 | rclk => clk, |
|
239 | 239 | ReUse => (OTHERS => '0'), |
|
240 | 240 | |
|
241 | 241 | wen => sample_f3_wen, |
|
242 | 242 | ren => sample_f3_ren, |
|
243 | 243 | wdata => sample_f3_wdata, |
|
244 | 244 | rdata => sample_f3_rdata, |
|
245 | 245 | full => sample_f3_full, |
|
246 | 246 | empty => sample_f3_empty); |
|
247 | 247 | |
|
248 | 248 | ----------------------------------------------------------------------------- |
|
249 | 249 | -- SPECTRAL MATRIX |
|
250 | 250 | ----------------------------------------------------------------------------- |
|
251 | 251 | sample_f0_0_ren <= sample_ren(4 DOWNTO 0); |
|
252 | 252 | sample_f0_1_ren <= sample_ren(9 DOWNTO 5); |
|
253 | 253 | sample_f1_ren <= sample_ren(14 DOWNTO 10); |
|
254 | 254 | sample_f3_ren <= sample_ren(19 DOWNTO 15); |
|
255 | 255 | |
|
256 | 256 | Demultiplex_1 : Demultiplex |
|
257 | 257 | GENERIC MAP ( |
|
258 | 258 | Data_sz => 16) |
|
259 | 259 | PORT MAP ( |
|
260 | 260 | clk => clk, |
|
261 | 261 | rstn => rstn, |
|
262 | 262 | |
|
263 | 263 | Read => demux_ren, |
|
264 | 264 | EmptyF0a => sample_f0_0_empty, |
|
265 | 265 | EmptyF0b => sample_f0_0_empty, |
|
266 | 266 | EmptyF1 => sample_f1_empty, |
|
267 | 267 | EmptyF2 => sample_f3_empty, |
|
268 | 268 | DataF0a => sample_f0_0_rdata, |
|
269 | 269 | DataF0b => sample_f0_1_rdata, |
|
270 | 270 | DataF1 => sample_f1_rdata, |
|
271 | 271 | DataF2 => sample_f3_rdata, |
|
272 | 272 | Read_DEMUX => sample_ren, |
|
273 | 273 | Empty => demux_empty, |
|
274 | 274 | Data => demux_data); |
|
275 | 275 | |
|
276 | 276 | FFT_1 : FFT |
|
277 | 277 | GENERIC MAP ( |
|
278 | 278 | Data_sz => 16, |
|
279 | 279 | NbData => 256) |
|
280 | 280 | PORT MAP ( |
|
281 | 281 | clkm => clk, |
|
282 | 282 | rstn => rstn, |
|
283 | 283 | FifoIN_Empty => demux_empty, |
|
284 | 284 | FifoIN_Data => demux_data, |
|
285 | 285 | FifoOUT_Full => fft_fifo_full, |
|
286 | 286 | Read => demux_ren, |
|
287 | 287 | Write => fft_fifo_wen, |
|
288 | 288 | ReUse => fft_fifo_reuse, |
|
289 | 289 | Data => fft_fifo_data); |
|
290 | 290 | |
|
291 | 291 | lppFIFO_fft : lppFIFOxN |
|
292 | 292 | GENERIC MAP ( |
|
293 | 293 | tech => tech, |
|
294 | 294 | Data_sz => 16, |
|
295 | 295 | FifoCnt => 5, |
|
296 | 296 | Enable_ReUse => '1') |
|
297 | 297 | PORT MAP ( |
|
298 | 298 | rst => rstn, |
|
299 | 299 | wclk => clk, |
|
300 | 300 | rclk => clk, |
|
301 | 301 | ReUse => fft_fifo_reuse, |
|
302 | 302 | wen => fft_fifo_wen, |
|
303 | 303 | ren => SP_fifo_ren, |
|
304 | 304 | wdata => fft_fifo_data, |
|
305 | 305 | rdata => SP_fifo_data, |
|
306 | 306 | full => fft_fifo_full, |
|
307 | 307 | empty => OPEN); |
|
308 | 308 | |
|
309 | 309 | MatriceSpectrale_1: MatriceSpectrale |
|
310 | 310 | GENERIC MAP ( |
|
311 | 311 | Input_SZ => 16, |
|
312 | 312 | Result_SZ => 32) |
|
313 | 313 | PORT MAP ( |
|
314 | 314 | clkm => clk, |
|
315 | 315 | rstn => rstn, |
|
316 | 316 | |
|
317 | 317 | FifoIN_Full => fft_fifo_full, |
|
318 | 318 | FifoOUT_Full => , -- TODO |
|
319 | 319 | Data_IN => SP_fifo_data, |
|
320 | 320 | ACQ => , -- TODO |
|
321 | 321 | FlagError => , -- TODO |
|
322 | 322 | Pong => , -- TODO |
|
323 | 323 | Write => , -- TODO |
|
324 | 324 | Read => SP_fifo_ren, |
|
325 | 325 | Data_OUT => ); -- TODO |
|
326 | 326 | |
|
327 | 327 | |
|
328 | 328 | ----------------------------------------------------------------------------- |
|
329 | 329 | -- DMA SPECTRAL MATRIX |
|
330 | 330 | ----------------------------------------------------------------------------- |
|
331 | 331 | lpp_dma_ip_1 : lpp_dma_ip |
|
332 | 332 | GENERIC MAP ( |
|
333 | 333 | tech => tech, |
|
334 | 334 | hindex => hindex_SpectralMatrix) |
|
335 | 335 | PORT MAP ( |
|
336 | 336 | HCLK => clk, |
|
337 | 337 | HRESETn => rstn, |
|
338 | 338 | AHB_Master_In => AHB_DMA_SpectralMatrix_In, |
|
339 | 339 | AHB_Master_Out => AHB_DMA_SpectralMatrix_Out, |
|
340 | 340 | |
|
341 | 341 | -- Connect to Spectral Matrix -- |
|
342 | 342 | fifo_data => fifo_data, |
|
343 | 343 | fifo_empty => fifo_empty, |
|
344 | 344 | fifo_ren => fifo_ren, |
|
345 | 345 | header => header, |
|
346 | 346 | header_val => header_val, |
|
347 | 347 | header_ack => header_ack, |
|
348 | 348 | |
|
349 | 349 | -- APB REG |
|
350 | 350 | |
|
351 | 351 | ready_matrix_f0_0 => ready_matrix_f0_0, |
|
352 | 352 | ready_matrix_f0_1 => ready_matrix_f0_1, |
|
353 | 353 | ready_matrix_f1 => ready_matrix_f1, |
|
354 | 354 | ready_matrix_f2 => ready_matrix_f2, |
|
355 | 355 | error_anticipating_empty_fifo => error_anticipating_empty_fifo, |
|
356 | 356 | error_bad_component_error => error_bad_component_error, |
|
357 | 357 | debug_reg => debug_reg, |
|
358 | 358 | status_ready_matrix_f0_0 => status_ready_matrix_f0_0, |
|
359 | 359 | status_ready_matrix_f0_1 => status_ready_matrix_f0_1, |
|
360 | 360 | status_ready_matrix_f1 => status_ready_matrix_f1, |
|
361 | 361 | status_ready_matrix_f2 => status_ready_matrix_f2, |
|
362 | 362 | status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo, |
|
363 | 363 | status_error_bad_component_error => status_error_bad_component_error, |
|
364 | 364 | config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, |
|
365 | 365 | config_active_interruption_onError => config_active_interruption_onError, |
|
366 | 366 | addr_matrix_f0_0 => addr_matrix_f0_0, |
|
367 | 367 | addr_matrix_f0_1 => addr_matrix_f0_1, |
|
368 | 368 | addr_matrix_f1 => addr_matrix_f1, |
|
369 | 369 | addr_matrix_f2 => addr_matrix_f2); |
|
370 | 370 | |
|
371 | 371 | lpp_top_apbreg_1 : lpp_top_apbreg |
|
372 | 372 | GENERIC MAP ( |
|
373 | 373 | pindex => pindex, |
|
374 | 374 | paddr => paddr, |
|
375 | 375 | pmask => pmask, |
|
376 | 376 | pirq => pirq) |
|
377 | 377 | PORT MAP ( |
|
378 | 378 | HCLK => clk, |
|
379 | 379 | HRESETn => rstn, |
|
380 | 380 | apbi => apbi, |
|
381 | 381 | apbo => apbo, |
|
382 | 382 | |
|
383 | 383 | ready_matrix_f0_0 => ready_matrix_f0_0, |
|
384 | 384 | ready_matrix_f0_1 => ready_matrix_f0_1, |
|
385 | 385 | ready_matrix_f1 => ready_matrix_f1, |
|
386 | 386 | ready_matrix_f2 => ready_matrix_f2, |
|
387 | 387 | error_anticipating_empty_fifo => error_anticipating_empty_fifo, |
|
388 | 388 | error_bad_component_error => error_bad_component_error, |
|
389 | 389 | debug_reg => debug_reg, |
|
390 | 390 | status_ready_matrix_f0_0 => status_ready_matrix_f0_0, |
|
391 | 391 | status_ready_matrix_f0_1 => status_ready_matrix_f0_1, |
|
392 | 392 | status_ready_matrix_f1 => status_ready_matrix_f1, |
|
393 | 393 | status_ready_matrix_f2 => status_ready_matrix_f2, |
|
394 | 394 | status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo, |
|
395 | 395 | status_error_bad_component_error => status_error_bad_component_error, |
|
396 | 396 | config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, |
|
397 | 397 | config_active_interruption_onError => config_active_interruption_onError, |
|
398 | 398 | addr_matrix_f0_0 => addr_matrix_f0_0, |
|
399 | 399 | addr_matrix_f0_1 => addr_matrix_f0_1, |
|
400 | 400 | addr_matrix_f1 => addr_matrix_f1, |
|
401 | 401 | addr_matrix_f2 => addr_matrix_f2); |
|
402 | 402 | |
|
403 | 403 | |
|
404 |
-- |
|
|
404 | --DONE : add the irq alert for DMA matrix transfert ending | |
|
405 | ||
|
405 | 406 |
|
|
407 | --TODO : data shiping | |
|
408 | ||
|
406 | 409 |
|
|
407 | 410 | --TODO : add DMA for WaveForms Picker |
|
408 | 411 | --TODO : add APB Reg to control WaveForms Picker |
|
409 | 412 | --TODO : add WaveForms Picker |
|
410 | 413 | |
|
411 | 414 | END tb; |
General Comments 0
You need to be logged in to leave comments.
Login now