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|
1 | ------------------------------------------------------------------------------ | |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
|
3 | -- Copyright (C) 2011, Laboratory of Plasmas Physic - CNRS | |
|
4 | -- | |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
|
6 | -- it under the terms of the GNU General Public License as published by | |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
|
8 | -- (at your option) any later version. | |
|
9 | -- | |
|
10 | -- This program is distributed in the hope that it will be useful, | |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
|
13 | -- GNU General Public License for more details. | |
|
14 | -- | |
|
15 | -- You should have received a copy of the GNU General Public License | |
|
16 | -- along with this program; if not, write to the Free Software | |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
|
18 | ------------------------------------------------------------------------------- | |
|
19 | -- Author : Alexis Jeandet | |
|
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr | |
|
21 | ------------------------------------------------------------------------------- | |
|
22 | library ieee; | |
|
23 | use ieee.std_logic_1164.all; | |
|
24 | library gaisler; | |
|
25 | use gaisler.misc.all; | |
|
26 | use gaisler.memctrl.all; | |
|
27 | library techmap; | |
|
28 | use techmap.gencomp.all; | |
|
29 | use techmap.allclkgen.all; | |
|
30 | ||
|
31 | ||
|
32 | ||
|
33 | ||
|
34 | entity ssram_plugin is | |
|
35 | generic (tech : integer := 0); | |
|
36 | port | |
|
37 | ( | |
|
38 | clk : in std_logic; | |
|
39 | mem_ctrlr_o : in memory_out_type; | |
|
40 | SSRAM_CLK : out std_logic; | |
|
41 | nBWa : out std_logic; | |
|
42 | nBWb : out std_logic; | |
|
43 | nBWc : out std_logic; | |
|
44 | nBWd : out std_logic; | |
|
45 | nBWE : out std_logic; | |
|
46 | nADSC : out std_logic; | |
|
47 | nADSP : out std_logic; | |
|
48 | nADV : out std_logic; | |
|
49 | nGW : out std_logic; | |
|
50 | nCE1 : out std_logic; | |
|
51 | CE2 : out std_logic; | |
|
52 | nCE3 : out std_logic; | |
|
53 | nOE : out std_logic; | |
|
54 | MODE : out std_logic; | |
|
55 | ZZ : out std_logic | |
|
56 | ); | |
|
57 | end entity; | |
|
58 | ||
|
59 | ||
|
60 | ||
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61 | ||
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62 | ||
|
63 | ||
|
64 | architecture ar_ssram_plugin of ssram_plugin is | |
|
65 | ||
|
66 | signal nADSPint : std_logic:='1'; | |
|
67 | signal nOEint : std_logic:='1'; | |
|
68 | signal RAMSN_reg: std_logic:='1'; | |
|
69 | signal OEreg : std_logic:='1'; | |
|
70 | signal nBWaint : std_logic:='1'; | |
|
71 | signal nBWbint : std_logic:='1'; | |
|
72 | signal nBWcint : std_logic:='1'; | |
|
73 | signal nBWdint : std_logic:='1'; | |
|
74 | signal nBWEint : std_logic:='1'; | |
|
75 | ||
|
76 | begin | |
|
77 | ||
|
78 | ||
|
79 | ||
|
80 | ssram_clk_pad : outpad generic map (tech => tech) | |
|
81 | port map (SSRAM_CLK,not clk); | |
|
82 | ||
|
83 | ||
|
84 | nBWaint <= mem_ctrlr_o.WRN(3)or mem_ctrlr_o.ramsn(0); | |
|
85 | nBWa_pad : outpad generic map (tech => tech) | |
|
86 | port map (nBWa,nBWaint); | |
|
87 | ||
|
88 | nBWbint <= mem_ctrlr_o.WRN(2)or mem_ctrlr_o.ramsn(0); | |
|
89 | nBWb_pad : outpad generic map (tech => tech) | |
|
90 | port map (nBWb, nBWbint); | |
|
91 | ||
|
92 | nBWcint <= mem_ctrlr_o.WRN(1)or mem_ctrlr_o.ramsn(0); | |
|
93 | nBWc_pad : outpad generic map (tech => tech) | |
|
94 | port map (nBWc, nBWcint); | |
|
95 | ||
|
96 | nBWdint <= mem_ctrlr_o.WRN(0)or mem_ctrlr_o.ramsn(0); | |
|
97 | nBWd_pad : outpad generic map (tech => tech) | |
|
98 | port map (nBWd, nBWdint); | |
|
99 | ||
|
100 | nBWEint <= mem_ctrlr_o.WRITEN or mem_ctrlr_o.ramsn(0); | |
|
101 | nBWE_pad : outpad generic map (tech => tech) | |
|
102 | port map (nBWE, nBWEint); | |
|
103 | ||
|
104 | nADSC_pad : outpad generic map (tech => tech) | |
|
105 | port map (nADSC, '1'); | |
|
106 | ||
|
107 | nADSPint <= not((RAMSN_reg xor mem_ctrlr_o.RAMSN(0)) and RAMSN_reg); | |
|
108 | process(clk) | |
|
109 | begin | |
|
110 | if clk'event and clk = '1' then | |
|
111 | RAMSN_reg <= mem_ctrlr_o.RAMSN(0); | |
|
112 | end if; | |
|
113 | end process; | |
|
114 | ||
|
115 | nADSP_pad : outpad generic map (tech => tech) | |
|
116 | port map (nADSP, nADSPint); | |
|
117 | ||
|
118 | nADV_pad : outpad generic map (tech => tech) | |
|
119 | port map (nADV, '1'); | |
|
120 | ||
|
121 | nGW_pad : outpad generic map (tech => tech) | |
|
122 | port map (nGW, '1'); | |
|
123 | ||
|
124 | nCE1_pad : outpad generic map (tech => tech) | |
|
125 | port map (nCE1, nADSPint); | |
|
126 | ||
|
127 | CE2_pad : outpad generic map (tech => tech) | |
|
128 | port map (CE2, '1'); | |
|
129 | ||
|
130 | nCE3_pad : outpad generic map (tech => tech) | |
|
131 | port map (nCE3, '0'); | |
|
132 | ||
|
133 | nOE_pad : outpad generic map (tech => tech) | |
|
134 | port map (nOE, nOEint); | |
|
135 | ||
|
136 | process(clk) | |
|
137 | begin | |
|
138 | if clk'event and clk = '1' then | |
|
139 | OEreg <= mem_ctrlr_o.OEN; | |
|
140 | end if; | |
|
141 | end process; | |
|
142 | ||
|
143 | ||
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144 | nOEint <= OEreg or mem_ctrlr_o.RAMOEN(0); | |
|
145 | ||
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146 | MODE_pad : outpad generic map (tech => tech) | |
|
147 | port map (MODE, '0'); | |
|
148 | ||
|
149 | ZZ_pad : outpad generic map (tech => tech) | |
|
150 | port map (ZZ, '0'); | |
|
151 | ||
|
152 | end architecture; No newline at end of file |
@@ -1,250 +1,275 | |||
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1 | 1 | ------------------------------------------------------------------------------ |
|
2 | 2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
3 | 3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
4 | 4 | -- |
|
5 | 5 | -- This program is free software; you can redistribute it and/or modify |
|
6 | 6 | -- it under the terms of the GNU General Public License as published by |
|
7 | 7 | -- the Free Software Foundation; either version 3 of the License, or |
|
8 | 8 | -- (at your option) any later version. |
|
9 | 9 | -- |
|
10 | 10 | -- This program is distributed in the hope that it will be useful, |
|
11 | 11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
12 | 12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
13 | 13 | -- GNU General Public License for more details. |
|
14 | 14 | -- |
|
15 | 15 | -- You should have received a copy of the GNU General Public License |
|
16 | 16 | -- along with this program; if not, write to the Free Software |
|
17 | 17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
18 | 18 | ------------------------------------------------------------------------------ |
|
19 | 19 | -- Author : Martin Morlot |
|
20 | 20 | -- Mail : martin.morlot@lpp.polytechnique.fr |
|
21 | 21 | ------------------------------------------------------------------------------ |
|
22 | 22 | library ieee; |
|
23 | 23 | use ieee.std_logic_1164.all; |
|
24 | 24 | library grlib; |
|
25 | 25 | use grlib.amba.all; |
|
26 | 26 | use std.textio.all; |
|
27 | 27 | library lpp; |
|
28 | 28 | use lpp.lpp_amba.all; |
|
29 | 29 | |
|
30 | 30 | --! Package contenant tous les programmes qui forment le composant intοΏ½grοΏ½ dans le lοΏ½on |
|
31 | 31 | |
|
32 | 32 | package lpp_memory is |
|
33 | 33 | |
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34 | 34 | --===========================================================| |
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35 | 35 | --=================== FIFO ComplοΏ½te =========================| |
|
36 | 36 | --===========================================================| |
|
37 | 37 | |
|
38 | 38 | component APB_FIFO is |
|
39 | 39 | generic ( |
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40 | 40 | pindex : integer := 0; |
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41 | 41 | paddr : integer := 0; |
|
42 | 42 | pmask : integer := 16#fff#; |
|
43 | 43 | pirq : integer := 0; |
|
44 | 44 | abits : integer := 8; |
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45 | 45 | Data_sz : integer := 16; |
|
46 | 46 | Addr_sz : integer := 8; |
|
47 | 47 | addr_max_int : integer := 256); |
|
48 | 48 | port ( |
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49 | 49 | clk : in std_logic; |
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50 | 50 | rst : in std_logic; |
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51 | 51 | apbi : in apb_slv_in_type; |
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52 | 52 | Full : out std_logic; |
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53 | 53 | Empty : out std_logic; |
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54 | 54 | WR : out std_logic; |
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55 | 55 | RE : out std_logic; |
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56 | 56 | apbo : out apb_slv_out_type |
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57 | 57 | ); |
|
58 | 58 | end component; |
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59 | 59 | |
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60 | 60 | |
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61 | 61 | component ApbDriver is |
|
62 | 62 | generic ( |
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63 | 63 | pindex : integer := 0; |
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64 | 64 | paddr : integer := 0; |
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65 | 65 | pmask : integer := 16#fff#; |
|
66 | 66 | pirq : integer := 0; |
|
67 | 67 | abits : integer := 8; |
|
68 | 68 | LPP_DEVICE : integer; |
|
69 | 69 | Data_sz : integer := 16; |
|
70 | 70 | Addr_sz : integer := 8; |
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71 | 71 | addr_max_int : integer := 256); |
|
72 | 72 | port ( |
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73 | 73 | clk : in std_logic; |
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74 | 74 | rst : in std_logic; |
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75 | 75 | ReadEnable : out std_logic; |
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76 | 76 | WriteEnable : out std_logic; |
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77 | 77 | FlagEmpty : in std_logic; |
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78 | 78 | FlagFull : in std_logic; |
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79 | 79 | ReUse : out std_logic; |
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80 | 80 | Lock : out std_logic; |
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81 | 81 | DataIn : out std_logic_vector(Data_sz-1 downto 0); |
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82 | 82 | DataOut : in std_logic_vector(Data_sz-1 downto 0); |
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83 | 83 | AddrIn : in std_logic_vector(Addr_sz-1 downto 0); |
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84 | 84 | AddrOut : in std_logic_vector(Addr_sz-1 downto 0); |
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85 | 85 | apbi : in apb_slv_in_type; |
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86 | 86 | apbo : out apb_slv_out_type |
|
87 | 87 | ); |
|
88 | 88 | end component; |
|
89 | 89 | |
|
90 | 90 | |
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91 | 91 | component Top_FIFO is |
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92 | 92 | generic( |
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93 | 93 | Data_sz : integer := 16; |
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94 | 94 | Addr_sz : integer := 8; |
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95 | 95 | addr_max_int : integer := 256 |
|
96 | 96 | ); |
|
97 | 97 | port( |
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98 | 98 | clk,raz : in std_logic; |
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99 | 99 | flag_RE : in std_logic; |
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100 | 100 | flag_WR : in std_logic; |
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101 | 101 | ReUse : in std_logic; |
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102 | 102 | Lock : in std_logic; |
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103 | 103 | Data_in : in std_logic_vector(Data_sz-1 downto 0); |
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104 | 104 | Addr_RE : out std_logic_vector(addr_sz-1 downto 0); |
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105 | 105 | Addr_WR : out std_logic_vector(addr_sz-1 downto 0); |
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106 | 106 | full : out std_logic; |
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107 | 107 | empty : out std_logic; |
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108 | 108 | Data_out : out std_logic_vector(Data_sz-1 downto 0) |
|
109 | 109 | ); |
|
110 | 110 | end component; |
|
111 | 111 | |
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112 | 112 | |
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113 | 113 | component Fifo_Read is |
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114 | 114 | generic( |
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115 | 115 | Addr_sz : integer := 8; |
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116 | 116 | addr_max_int : integer := 256); |
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117 | 117 | port( |
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118 | 118 | clk : in std_logic; |
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119 | 119 | raz : in std_logic; |
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120 | 120 | flag_RE : in std_logic; |
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121 | 121 | ReUse : in std_logic; |
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122 | 122 | Waddr : in std_logic_vector(addr_sz-1 downto 0); |
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123 | 123 | empty : out std_logic; |
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124 | 124 | Raddr : out std_logic_vector(addr_sz-1 downto 0) |
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125 | 125 | ); |
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126 | 126 | end component; |
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127 | 127 | |
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128 | 128 | |
|
129 | 129 | component Fifo_Write is |
|
130 | 130 | generic( |
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131 | 131 | Addr_sz : integer := 8; |
|
132 | 132 | addr_max_int : integer := 256); |
|
133 | 133 | port( |
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134 | 134 | clk : in std_logic; |
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135 | 135 | raz : in std_logic; |
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136 | 136 | flag_WR : in std_logic; |
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137 | 137 | Raddr : in std_logic_vector(addr_sz-1 downto 0); |
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138 | 138 | full : out std_logic; |
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139 | 139 | Waddr : out std_logic_vector(addr_sz-1 downto 0) |
|
140 | 140 | ); |
|
141 | 141 | end component; |
|
142 | 142 | |
|
143 | 143 | |
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144 | 144 | component Link_Reg is |
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145 | 145 | generic(Data_sz : integer := 16); |
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146 | 146 | port( |
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147 | 147 | clk,raz : in std_logic; |
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148 | 148 | Data_one : in std_logic_vector(Data_sz-1 downto 0); |
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149 | 149 | Data_two : in std_logic_vector(Data_sz-1 downto 0); |
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150 | 150 | ReUse : in std_logic; |
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151 | 151 | flag_RE : in std_logic; |
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152 | 152 | flag_WR : in std_logic; |
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153 | 153 | empty : in std_logic; |
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154 | 154 | Data_out : out std_logic_vector(Data_sz-1 downto 0) |
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155 | 155 | ); |
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156 | 156 | end component; |
|
157 | 157 | |
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158 | 158 | --===========================================================| |
|
159 | 159 | --================= Demi FIFO Ecriture ======================| |
|
160 | 160 | --===========================================================| |
|
161 | 161 | |
|
162 | 162 | component APB_FifoWrite is |
|
163 | 163 | generic ( |
|
164 | 164 | pindex : integer := 0; |
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165 | 165 | paddr : integer := 0; |
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166 | 166 | pmask : integer := 16#fff#; |
|
167 | 167 | pirq : integer := 0; |
|
168 | 168 | abits : integer := 8; |
|
169 | 169 | Data_sz : integer := 16; |
|
170 | 170 | Addr_sz : integer := 8; |
|
171 | 171 | addr_max_int : integer := 256); |
|
172 | 172 | port ( |
|
173 | 173 | clk : in std_logic; |
|
174 | 174 | rst : in std_logic; |
|
175 | 175 | apbi : in apb_slv_in_type; |
|
176 | 176 | ReadEnable : in std_logic; |
|
177 | 177 | Empty : out std_logic; |
|
178 | 178 | Full : out std_logic; |
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179 | 179 | DATA : out std_logic_vector(Data_sz-1 downto 0); |
|
180 | 180 | apbo : out apb_slv_out_type |
|
181 | 181 | ); |
|
182 | 182 | end component; |
|
183 | 183 | |
|
184 | 184 | |
|
185 | 185 | --component Top_FifoWrite is |
|
186 | 186 | -- generic( |
|
187 | 187 | -- Data_sz : integer := 16; |
|
188 | 188 | -- Addr_sz : integer := 8; |
|
189 | 189 | -- addr_max_int : integer := 256); |
|
190 | 190 | -- port( |
|
191 | 191 | -- clk : in std_logic; |
|
192 | 192 | -- raz : in std_logic; |
|
193 | 193 | -- flag_RE : in std_logic; |
|
194 | 194 | -- flag_WR : in std_logic; |
|
195 | 195 | -- Data_in : in std_logic_vector(Data_sz-1 downto 0); |
|
196 | 196 | -- Raddr : in std_logic_vector(addr_sz-1 downto 0); |
|
197 | 197 | -- full : out std_logic; |
|
198 | 198 | -- empty : out std_logic; |
|
199 | 199 | -- Waddr : out std_logic_vector(addr_sz-1 downto 0); |
|
200 | 200 | -- Data_out : out std_logic_vector(Data_sz-1 downto 0) |
|
201 | 201 | -- ); |
|
202 | 202 | --end component; |
|
203 | 203 | |
|
204 | 204 | --===========================================================| |
|
205 | 205 | --================== Demi FIFO Lecture ======================| |
|
206 | 206 | --===========================================================| |
|
207 | 207 | |
|
208 | 208 | component APB_FifoRead is |
|
209 | 209 | generic ( |
|
210 | 210 | pindex : integer := 0; |
|
211 | 211 | paddr : integer := 0; |
|
212 | 212 | pmask : integer := 16#fff#; |
|
213 | 213 | pirq : integer := 0; |
|
214 | 214 | abits : integer := 8; |
|
215 | 215 | Data_sz : integer := 16; |
|
216 | 216 | Addr_sz : integer := 8; |
|
217 | 217 | addr_max_int : integer := 256); |
|
218 | 218 | port ( |
|
219 | 219 | clk : in std_logic; |
|
220 | 220 | rst : in std_logic; |
|
221 | 221 | apbi : in apb_slv_in_type; |
|
222 | 222 | WriteEnable : in std_logic; |
|
223 | 223 | Full : out std_logic; |
|
224 | 224 | Empty : out std_logic; |
|
225 | 225 | DATA : in std_logic_vector(Data_sz-1 downto 0); |
|
226 | 226 | apbo : out apb_slv_out_type |
|
227 | 227 | ); |
|
228 | 228 | end component; |
|
229 | 229 | |
|
230 | 230 | |
|
231 | 231 | --component Top_FifoRead is |
|
232 | 232 | -- generic( |
|
233 | 233 | -- Data_sz : integer := 16; |
|
234 | 234 | -- Addr_sz : integer := 8; |
|
235 | 235 | -- addr_max_int : integer := 256); |
|
236 | 236 | -- port( |
|
237 | 237 | -- clk : in std_logic; |
|
238 | 238 | -- raz : in std_logic; |
|
239 | 239 | -- flag_RE : in std_logic; |
|
240 | 240 | -- flag_WR : in std_logic; |
|
241 | 241 | -- Data_in : in std_logic_vector(Data_sz-1 downto 0); |
|
242 | 242 | -- Waddr : in std_logic_vector(addr_sz-1 downto 0); |
|
243 | 243 | -- full : out std_logic; |
|
244 | 244 | -- empty : out std_logic; |
|
245 | 245 | -- Raddr : out std_logic_vector(addr_sz-1 downto 0); |
|
246 | 246 | -- Data_out : out std_logic_vector(Data_sz-1 downto 0) |
|
247 | 247 | -- ); |
|
248 | 248 | --end component; |
|
249 | 249 | |
|
250 | component ssram_plugin is | |
|
251 | generic (tech : integer := 0); | |
|
252 | port | |
|
253 | ( | |
|
254 | clk : in std_logic; | |
|
255 | mem_ctrlr_o : in memory_out_type; | |
|
256 | SSRAM_CLK : out std_logic; | |
|
257 | nBWa : out std_logic; | |
|
258 | nBWb : out std_logic; | |
|
259 | nBWc : out std_logic; | |
|
260 | nBWd : out std_logic; | |
|
261 | nBWE : out std_logic; | |
|
262 | nADSC : out std_logic; | |
|
263 | nADSP : out std_logic; | |
|
264 | nADV : out std_logic; | |
|
265 | nGW : out std_logic; | |
|
266 | nCE1 : out std_logic; | |
|
267 | CE2 : out std_logic; | |
|
268 | nCE3 : out std_logic; | |
|
269 | nOE : out std_logic; | |
|
270 | MODE : out std_logic; | |
|
271 | ZZ : out std_logic | |
|
272 | ); | |
|
273 | end component; | |
|
274 | ||
|
250 | 275 | end; |
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