# HG changeset patch
# User jeandet@PC-DE-JEANDET.lpp.polytechnique.fr
# Date 2011-10-18 06:45:46
# Node ID 6c2ce1d3393fb8fb40f073d6590f6a12fdd9694a
# Parent  850e54f169a0b457eb7f542398bb1665600d8019

Added SSRAM plugin for LFR developpement model

diff --git a/lib/lpp/lpp_memory/SSRAM_plugin.vhd b/lib/lpp/lpp_memory/SSRAM_plugin.vhd
new file mode 100644
--- /dev/null
+++ b/lib/lpp/lpp_memory/SSRAM_plugin.vhd
@@ -0,0 +1,152 @@
+------------------------------------------------------------------------------
+--  This file is a part of the LPP VHDL IP LIBRARY
+--  Copyright (C) 2011, Laboratory of Plasmas Physic - CNRS
+--
+--  This program is free software; you can redistribute it and/or modify
+--  it under the terms of the GNU General Public License as published by
+--  the Free Software Foundation; either version 3 of the License, or
+--  (at your option) any later version.
+--
+--  This program is distributed in the hope that it will be useful,
+--  but WITHOUT ANY WARRANTY; without even the implied warranty of
+--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+--  GNU General Public License for more details.
+--
+--  You should have received a copy of the GNU General Public License
+--  along with this program; if not, write to the Free Software
+--  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+-------------------------------------------------------------------------------
+--                    Author : Alexis Jeandet
+--                     Mail : alexis.jeandet@lpp.polytechnique.fr
+-------------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+library gaisler;
+use gaisler.misc.all;
+use gaisler.memctrl.all;
+library techmap;
+use techmap.gencomp.all;
+use techmap.allclkgen.all;
+
+
+
+
+entity ssram_plugin is 
+generic (tech : integer := 0);
+port
+(
+    clk             : in  std_logic;
+    mem_ctrlr_o     : in  memory_out_type;
+    SSRAM_CLK       : out std_logic;
+    nBWa            : out std_logic;
+    nBWb            : out std_logic;
+    nBWc            : out std_logic;
+    nBWd            : out std_logic;
+    nBWE            : out std_logic;
+    nADSC           : out std_logic;
+    nADSP           : out std_logic;
+    nADV            : out std_logic;
+    nGW             : out std_logic;
+    nCE1            : out std_logic;
+    CE2             : out std_logic;
+    nCE3            : out std_logic;
+    nOE             : out std_logic;
+    MODE            : out std_logic;
+    ZZ              : out std_logic
+);
+end entity;
+
+
+
+
+
+
+architecture ar_ssram_plugin of ssram_plugin is
+
+signal nADSPint : std_logic:='1';
+signal nOEint   : std_logic:='1';
+signal RAMSN_reg: std_logic:='1';
+signal OEreg    : std_logic:='1';
+signal nBWaint   : std_logic:='1';
+signal nBWbint   : std_logic:='1';
+signal nBWcint   : std_logic:='1';
+signal nBWdint   : std_logic:='1';
+signal nBWEint   : std_logic:='1';
+
+begin
+
+
+
+ssram_clk_pad : outpad generic map (tech => tech)
+    port map (SSRAM_CLK,not clk);
+
+
+nBWaint  <=  mem_ctrlr_o.WRN(3)or mem_ctrlr_o.ramsn(0);
+nBWa_pad : outpad generic map (tech => tech)
+    port map (nBWa,nBWaint);
+
+nBWbint  <=  mem_ctrlr_o.WRN(2)or mem_ctrlr_o.ramsn(0);
+nBWb_pad : outpad generic map (tech => tech)
+    port map (nBWb, nBWbint);
+
+nBWcint  <=  mem_ctrlr_o.WRN(1)or mem_ctrlr_o.ramsn(0);
+nBWc_pad : outpad generic map (tech => tech)
+    port map (nBWc, nBWcint);
+
+nBWdint  <=  mem_ctrlr_o.WRN(0)or mem_ctrlr_o.ramsn(0);
+nBWd_pad : outpad generic map (tech => tech)
+    port map (nBWd, nBWdint);
+
+nBWEint  <=  mem_ctrlr_o.WRITEN or mem_ctrlr_o.ramsn(0);
+nBWE_pad : outpad generic map (tech => tech)
+    port map (nBWE, nBWEint);
+
+nADSC_pad : outpad generic map (tech => tech)
+    port map (nADSC, '1');
+
+nADSPint    <=  not((RAMSN_reg xor mem_ctrlr_o.RAMSN(0)) and RAMSN_reg);
+process(clk)
+begin
+    if clk'event and clk = '1' then
+        RAMSN_reg   <=  mem_ctrlr_o.RAMSN(0);
+    end if;
+end process;
+
+nADSP_pad : outpad generic map (tech => tech)
+    port map (nADSP, nADSPint);
+
+nADV_pad : outpad generic map (tech => tech)
+    port map (nADV, '1');       
+
+nGW_pad : outpad generic map (tech => tech)
+    port map (nGW, '1');
+
+nCE1_pad : outpad generic map (tech => tech)
+    port map (nCE1, nADSPint);
+
+CE2_pad : outpad generic map (tech => tech)
+    port map (CE2, '1');
+
+nCE3_pad : outpad generic map (tech => tech)
+    port map (nCE3, '0');
+
+nOE_pad : outpad generic map (tech => tech)
+    port map (nOE, nOEint);
+
+process(clk)
+begin
+    if clk'event and clk = '1' then
+        OEreg   <=  mem_ctrlr_o.OEN;
+    end if;
+end process;
+
+ 
+nOEint  <=  OEreg or mem_ctrlr_o.RAMOEN(0);		
+ 
+MODE_pad : outpad generic map (tech => tech)
+    port map (MODE, '0');      
+
+ZZ_pad : outpad generic map (tech => tech)
+    port map (ZZ, '0');
+
+end architecture;
\ No newline at end of file
diff --git a/lib/lpp/lpp_memory/lpp_memory.vhd b/lib/lpp/lpp_memory/lpp_memory.vhd
--- a/lib/lpp/lpp_memory/lpp_memory.vhd
+++ b/lib/lpp/lpp_memory/lpp_memory.vhd
@@ -247,4 +247,29 @@ end component;
 --    );
 --end component;
 
+component ssram_plugin is
+generic (tech : integer := 0);
+port
+(
+    clk             : in  std_logic;
+    mem_ctrlr_o     : in  memory_out_type;
+    SSRAM_CLK       : out std_logic;
+    nBWa            : out std_logic;
+    nBWb            : out std_logic;
+    nBWc            : out std_logic;
+    nBWd            : out std_logic;
+    nBWE            : out std_logic;
+    nADSC           : out std_logic;
+    nADSP           : out std_logic;
+    nADV            : out std_logic;
+    nGW             : out std_logic;
+    nCE1            : out std_logic;
+    CE2             : out std_logic;
+    nCE3            : out std_logic;
+    nOE             : out std_logic;
+    MODE            : out std_logic;
+    ZZ              : out std_logic
+);
+end component;
+
 end;