@@ -0,0 +1,152 | |||
|
1 | ------------------------------------------------------------------------------ | |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
|
3 | -- Copyright (C) 2011, Laboratory of Plasmas Physic - CNRS | |
|
4 | -- | |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
|
6 | -- it under the terms of the GNU General Public License as published by | |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
|
8 | -- (at your option) any later version. | |
|
9 | -- | |
|
10 | -- This program is distributed in the hope that it will be useful, | |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
|
13 | -- GNU General Public License for more details. | |
|
14 | -- | |
|
15 | -- You should have received a copy of the GNU General Public License | |
|
16 | -- along with this program; if not, write to the Free Software | |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
|
18 | ------------------------------------------------------------------------------- | |
|
19 | -- Author : Alexis Jeandet | |
|
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr | |
|
21 | ------------------------------------------------------------------------------- | |
|
22 | library ieee; | |
|
23 | use ieee.std_logic_1164.all; | |
|
24 | library gaisler; | |
|
25 | use gaisler.misc.all; | |
|
26 | use gaisler.memctrl.all; | |
|
27 | library techmap; | |
|
28 | use techmap.gencomp.all; | |
|
29 | use techmap.allclkgen.all; | |
|
30 | ||
|
31 | ||
|
32 | ||
|
33 | ||
|
34 | entity ssram_plugin is | |
|
35 | generic (tech : integer := 0); | |
|
36 | port | |
|
37 | ( | |
|
38 | clk : in std_logic; | |
|
39 | mem_ctrlr_o : in memory_out_type; | |
|
40 | SSRAM_CLK : out std_logic; | |
|
41 | nBWa : out std_logic; | |
|
42 | nBWb : out std_logic; | |
|
43 | nBWc : out std_logic; | |
|
44 | nBWd : out std_logic; | |
|
45 | nBWE : out std_logic; | |
|
46 | nADSC : out std_logic; | |
|
47 | nADSP : out std_logic; | |
|
48 | nADV : out std_logic; | |
|
49 | nGW : out std_logic; | |
|
50 | nCE1 : out std_logic; | |
|
51 | CE2 : out std_logic; | |
|
52 | nCE3 : out std_logic; | |
|
53 | nOE : out std_logic; | |
|
54 | MODE : out std_logic; | |
|
55 | ZZ : out std_logic | |
|
56 | ); | |
|
57 | end entity; | |
|
58 | ||
|
59 | ||
|
60 | ||
|
61 | ||
|
62 | ||
|
63 | ||
|
64 | architecture ar_ssram_plugin of ssram_plugin is | |
|
65 | ||
|
66 | signal nADSPint : std_logic:='1'; | |
|
67 | signal nOEint : std_logic:='1'; | |
|
68 | signal RAMSN_reg: std_logic:='1'; | |
|
69 | signal OEreg : std_logic:='1'; | |
|
70 | signal nBWaint : std_logic:='1'; | |
|
71 | signal nBWbint : std_logic:='1'; | |
|
72 | signal nBWcint : std_logic:='1'; | |
|
73 | signal nBWdint : std_logic:='1'; | |
|
74 | signal nBWEint : std_logic:='1'; | |
|
75 | ||
|
76 | begin | |
|
77 | ||
|
78 | ||
|
79 | ||
|
80 | ssram_clk_pad : outpad generic map (tech => tech) | |
|
81 | port map (SSRAM_CLK,not clk); | |
|
82 | ||
|
83 | ||
|
84 | nBWaint <= mem_ctrlr_o.WRN(3)or mem_ctrlr_o.ramsn(0); | |
|
85 | nBWa_pad : outpad generic map (tech => tech) | |
|
86 | port map (nBWa,nBWaint); | |
|
87 | ||
|
88 | nBWbint <= mem_ctrlr_o.WRN(2)or mem_ctrlr_o.ramsn(0); | |
|
89 | nBWb_pad : outpad generic map (tech => tech) | |
|
90 | port map (nBWb, nBWbint); | |
|
91 | ||
|
92 | nBWcint <= mem_ctrlr_o.WRN(1)or mem_ctrlr_o.ramsn(0); | |
|
93 | nBWc_pad : outpad generic map (tech => tech) | |
|
94 | port map (nBWc, nBWcint); | |
|
95 | ||
|
96 | nBWdint <= mem_ctrlr_o.WRN(0)or mem_ctrlr_o.ramsn(0); | |
|
97 | nBWd_pad : outpad generic map (tech => tech) | |
|
98 | port map (nBWd, nBWdint); | |
|
99 | ||
|
100 | nBWEint <= mem_ctrlr_o.WRITEN or mem_ctrlr_o.ramsn(0); | |
|
101 | nBWE_pad : outpad generic map (tech => tech) | |
|
102 | port map (nBWE, nBWEint); | |
|
103 | ||
|
104 | nADSC_pad : outpad generic map (tech => tech) | |
|
105 | port map (nADSC, '1'); | |
|
106 | ||
|
107 | nADSPint <= not((RAMSN_reg xor mem_ctrlr_o.RAMSN(0)) and RAMSN_reg); | |
|
108 | process(clk) | |
|
109 | begin | |
|
110 | if clk'event and clk = '1' then | |
|
111 | RAMSN_reg <= mem_ctrlr_o.RAMSN(0); | |
|
112 | end if; | |
|
113 | end process; | |
|
114 | ||
|
115 | nADSP_pad : outpad generic map (tech => tech) | |
|
116 | port map (nADSP, nADSPint); | |
|
117 | ||
|
118 | nADV_pad : outpad generic map (tech => tech) | |
|
119 | port map (nADV, '1'); | |
|
120 | ||
|
121 | nGW_pad : outpad generic map (tech => tech) | |
|
122 | port map (nGW, '1'); | |
|
123 | ||
|
124 | nCE1_pad : outpad generic map (tech => tech) | |
|
125 | port map (nCE1, nADSPint); | |
|
126 | ||
|
127 | CE2_pad : outpad generic map (tech => tech) | |
|
128 | port map (CE2, '1'); | |
|
129 | ||
|
130 | nCE3_pad : outpad generic map (tech => tech) | |
|
131 | port map (nCE3, '0'); | |
|
132 | ||
|
133 | nOE_pad : outpad generic map (tech => tech) | |
|
134 | port map (nOE, nOEint); | |
|
135 | ||
|
136 | process(clk) | |
|
137 | begin | |
|
138 | if clk'event and clk = '1' then | |
|
139 | OEreg <= mem_ctrlr_o.OEN; | |
|
140 | end if; | |
|
141 | end process; | |
|
142 | ||
|
143 | ||
|
144 | nOEint <= OEreg or mem_ctrlr_o.RAMOEN(0); | |
|
145 | ||
|
146 | MODE_pad : outpad generic map (tech => tech) | |
|
147 | port map (MODE, '0'); | |
|
148 | ||
|
149 | ZZ_pad : outpad generic map (tech => tech) | |
|
150 | port map (ZZ, '0'); | |
|
151 | ||
|
152 | end architecture; No newline at end of file |
@@ -247,4 +247,29 end component; | |||
|
247 | 247 | -- ); |
|
248 | 248 | --end component; |
|
249 | 249 | |
|
250 | component ssram_plugin is | |
|
251 | generic (tech : integer := 0); | |
|
252 | port | |
|
253 | ( | |
|
254 | clk : in std_logic; | |
|
255 | mem_ctrlr_o : in memory_out_type; | |
|
256 | SSRAM_CLK : out std_logic; | |
|
257 | nBWa : out std_logic; | |
|
258 | nBWb : out std_logic; | |
|
259 | nBWc : out std_logic; | |
|
260 | nBWd : out std_logic; | |
|
261 | nBWE : out std_logic; | |
|
262 | nADSC : out std_logic; | |
|
263 | nADSP : out std_logic; | |
|
264 | nADV : out std_logic; | |
|
265 | nGW : out std_logic; | |
|
266 | nCE1 : out std_logic; | |
|
267 | CE2 : out std_logic; | |
|
268 | nCE3 : out std_logic; | |
|
269 | nOE : out std_logic; | |
|
270 | MODE : out std_logic; | |
|
271 | ZZ : out std_logic | |
|
272 | ); | |
|
273 | end component; | |
|
274 | ||
|
250 | 275 | end; |
General Comments 0
You need to be logged in to leave comments.
Login now