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1 | ------------------------------------------------------------------------------ | |||
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2 | -- This file is a part of the LPP VHDL IP LIBRARY | |||
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3 | -- Copyright (C) 2011, Laboratory of Plasmas Physic - CNRS | |||
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4 | -- | |||
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5 | -- This program is free software; you can redistribute it and/or modify | |||
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6 | -- it under the terms of the GNU General Public License as published by | |||
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7 | -- the Free Software Foundation; either version 3 of the License, or | |||
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8 | -- (at your option) any later version. | |||
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9 | -- | |||
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10 | -- This program is distributed in the hope that it will be useful, | |||
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11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
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12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
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13 | -- GNU General Public License for more details. | |||
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14 | -- | |||
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15 | -- You should have received a copy of the GNU General Public License | |||
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16 | -- along with this program; if not, write to the Free Software | |||
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17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
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18 | ------------------------------------------------------------------------------- | |||
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19 | -- Author : Alexis Jeandet | |||
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20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr | |||
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21 | ------------------------------------------------------------------------------- | |||
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22 | library ieee; | |||
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23 | use ieee.std_logic_1164.all; | |||
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24 | library gaisler; | |||
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25 | use gaisler.misc.all; | |||
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26 | use gaisler.memctrl.all; | |||
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27 | library techmap; | |||
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28 | use techmap.gencomp.all; | |||
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29 | use techmap.allclkgen.all; | |||
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30 | ||||
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31 | ||||
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32 | ||||
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33 | ||||
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34 | entity ssram_plugin is | |||
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35 | generic (tech : integer := 0); | |||
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36 | port | |||
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37 | ( | |||
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38 | clk : in std_logic; | |||
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39 | mem_ctrlr_o : in memory_out_type; | |||
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40 | SSRAM_CLK : out std_logic; | |||
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41 | nBWa : out std_logic; | |||
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42 | nBWb : out std_logic; | |||
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43 | nBWc : out std_logic; | |||
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44 | nBWd : out std_logic; | |||
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45 | nBWE : out std_logic; | |||
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46 | nADSC : out std_logic; | |||
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47 | nADSP : out std_logic; | |||
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48 | nADV : out std_logic; | |||
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49 | nGW : out std_logic; | |||
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50 | nCE1 : out std_logic; | |||
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51 | CE2 : out std_logic; | |||
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52 | nCE3 : out std_logic; | |||
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53 | nOE : out std_logic; | |||
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54 | MODE : out std_logic; | |||
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55 | ZZ : out std_logic | |||
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56 | ); | |||
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57 | end entity; | |||
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58 | ||||
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59 | ||||
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60 | ||||
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61 | ||||
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62 | ||||
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63 | ||||
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64 | architecture ar_ssram_plugin of ssram_plugin is | |||
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65 | ||||
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66 | signal nADSPint : std_logic:='1'; | |||
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67 | signal nOEint : std_logic:='1'; | |||
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68 | signal RAMSN_reg: std_logic:='1'; | |||
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69 | signal OEreg : std_logic:='1'; | |||
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70 | signal nBWaint : std_logic:='1'; | |||
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71 | signal nBWbint : std_logic:='1'; | |||
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72 | signal nBWcint : std_logic:='1'; | |||
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73 | signal nBWdint : std_logic:='1'; | |||
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74 | signal nBWEint : std_logic:='1'; | |||
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75 | ||||
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76 | begin | |||
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77 | ||||
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78 | ||||
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79 | ||||
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80 | ssram_clk_pad : outpad generic map (tech => tech) | |||
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81 | port map (SSRAM_CLK,not clk); | |||
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82 | ||||
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83 | ||||
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84 | nBWaint <= mem_ctrlr_o.WRN(3)or mem_ctrlr_o.ramsn(0); | |||
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85 | nBWa_pad : outpad generic map (tech => tech) | |||
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86 | port map (nBWa,nBWaint); | |||
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87 | ||||
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88 | nBWbint <= mem_ctrlr_o.WRN(2)or mem_ctrlr_o.ramsn(0); | |||
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89 | nBWb_pad : outpad generic map (tech => tech) | |||
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90 | port map (nBWb, nBWbint); | |||
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91 | ||||
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92 | nBWcint <= mem_ctrlr_o.WRN(1)or mem_ctrlr_o.ramsn(0); | |||
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93 | nBWc_pad : outpad generic map (tech => tech) | |||
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94 | port map (nBWc, nBWcint); | |||
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95 | ||||
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96 | nBWdint <= mem_ctrlr_o.WRN(0)or mem_ctrlr_o.ramsn(0); | |||
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97 | nBWd_pad : outpad generic map (tech => tech) | |||
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98 | port map (nBWd, nBWdint); | |||
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99 | ||||
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100 | nBWEint <= mem_ctrlr_o.WRITEN or mem_ctrlr_o.ramsn(0); | |||
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101 | nBWE_pad : outpad generic map (tech => tech) | |||
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102 | port map (nBWE, nBWEint); | |||
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103 | ||||
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104 | nADSC_pad : outpad generic map (tech => tech) | |||
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105 | port map (nADSC, '1'); | |||
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106 | ||||
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107 | nADSPint <= not((RAMSN_reg xor mem_ctrlr_o.RAMSN(0)) and RAMSN_reg); | |||
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108 | process(clk) | |||
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109 | begin | |||
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110 | if clk'event and clk = '1' then | |||
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111 | RAMSN_reg <= mem_ctrlr_o.RAMSN(0); | |||
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112 | end if; | |||
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113 | end process; | |||
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114 | ||||
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115 | nADSP_pad : outpad generic map (tech => tech) | |||
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116 | port map (nADSP, nADSPint); | |||
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117 | ||||
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118 | nADV_pad : outpad generic map (tech => tech) | |||
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119 | port map (nADV, '1'); | |||
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120 | ||||
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121 | nGW_pad : outpad generic map (tech => tech) | |||
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122 | port map (nGW, '1'); | |||
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123 | ||||
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124 | nCE1_pad : outpad generic map (tech => tech) | |||
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125 | port map (nCE1, nADSPint); | |||
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126 | ||||
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127 | CE2_pad : outpad generic map (tech => tech) | |||
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128 | port map (CE2, '1'); | |||
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129 | ||||
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130 | nCE3_pad : outpad generic map (tech => tech) | |||
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131 | port map (nCE3, '0'); | |||
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132 | ||||
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133 | nOE_pad : outpad generic map (tech => tech) | |||
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134 | port map (nOE, nOEint); | |||
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135 | ||||
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136 | process(clk) | |||
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137 | begin | |||
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138 | if clk'event and clk = '1' then | |||
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139 | OEreg <= mem_ctrlr_o.OEN; | |||
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140 | end if; | |||
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141 | end process; | |||
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142 | ||||
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143 | ||||
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144 | nOEint <= OEreg or mem_ctrlr_o.RAMOEN(0); | |||
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145 | ||||
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146 | MODE_pad : outpad generic map (tech => tech) | |||
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147 | port map (MODE, '0'); | |||
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148 | ||||
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149 | ZZ_pad : outpad generic map (tech => tech) | |||
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150 | port map (ZZ, '0'); | |||
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151 | ||||
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152 | end architecture; No newline at end of file |
@@ -247,4 +247,29 end component; | |||||
247 | -- ); |
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247 | -- ); | |
248 | --end component; |
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248 | --end component; | |
249 |
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249 | |||
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250 | component ssram_plugin is | |||
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251 | generic (tech : integer := 0); | |||
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252 | port | |||
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253 | ( | |||
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254 | clk : in std_logic; | |||
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255 | mem_ctrlr_o : in memory_out_type; | |||
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256 | SSRAM_CLK : out std_logic; | |||
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257 | nBWa : out std_logic; | |||
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258 | nBWb : out std_logic; | |||
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259 | nBWc : out std_logic; | |||
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260 | nBWd : out std_logic; | |||
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261 | nBWE : out std_logic; | |||
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262 | nADSC : out std_logic; | |||
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263 | nADSP : out std_logic; | |||
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264 | nADV : out std_logic; | |||
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265 | nGW : out std_logic; | |||
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266 | nCE1 : out std_logic; | |||
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267 | CE2 : out std_logic; | |||
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268 | nCE3 : out std_logic; | |||
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269 | nOE : out std_logic; | |||
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270 | MODE : out std_logic; | |||
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271 | ZZ : out std_logic | |||
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272 | ); | |||
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273 | end component; | |||
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274 | ||||
250 | end; |
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275 | end; |
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