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1 | ------------------------------------------------------------------------------ | |||
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2 | -- This file is a part of the LPP VHDL IP LIBRARY | |||
|
3 | -- Copyright (C) 2011, Laboratory of Plasmas Physic - CNRS | |||
|
4 | -- | |||
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5 | -- This program is free software; you can redistribute it and/or modify | |||
|
6 | -- it under the terms of the GNU General Public License as published by | |||
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |||
|
8 | -- (at your option) any later version. | |||
|
9 | -- | |||
|
10 | -- This program is distributed in the hope that it will be useful, | |||
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
|
13 | -- GNU General Public License for more details. | |||
|
14 | -- | |||
|
15 | -- You should have received a copy of the GNU General Public License | |||
|
16 | -- along with this program; if not, write to the Free Software | |||
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
|
18 | ------------------------------------------------------------------------------- | |||
|
19 | -- Author : Alexis Jeandet | |||
|
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr | |||
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21 | ------------------------------------------------------------------------------- | |||
|
22 | library ieee; | |||
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23 | use ieee.std_logic_1164.all; | |||
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24 | library gaisler; | |||
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25 | use gaisler.misc.all; | |||
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26 | use gaisler.memctrl.all; | |||
|
27 | library techmap; | |||
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28 | use techmap.gencomp.all; | |||
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29 | use techmap.allclkgen.all; | |||
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30 | ||||
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31 | ||||
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32 | ||||
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33 | ||||
|
34 | entity ssram_plugin is | |||
|
35 | generic (tech : integer := 0); | |||
|
36 | port | |||
|
37 | ( | |||
|
38 | clk : in std_logic; | |||
|
39 | mem_ctrlr_o : in memory_out_type; | |||
|
40 | SSRAM_CLK : out std_logic; | |||
|
41 | nBWa : out std_logic; | |||
|
42 | nBWb : out std_logic; | |||
|
43 | nBWc : out std_logic; | |||
|
44 | nBWd : out std_logic; | |||
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45 | nBWE : out std_logic; | |||
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46 | nADSC : out std_logic; | |||
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47 | nADSP : out std_logic; | |||
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48 | nADV : out std_logic; | |||
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49 | nGW : out std_logic; | |||
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50 | nCE1 : out std_logic; | |||
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51 | CE2 : out std_logic; | |||
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52 | nCE3 : out std_logic; | |||
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53 | nOE : out std_logic; | |||
|
54 | MODE : out std_logic; | |||
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55 | ZZ : out std_logic | |||
|
56 | ); | |||
|
57 | end entity; | |||
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58 | ||||
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59 | ||||
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60 | ||||
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61 | ||||
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62 | ||||
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63 | ||||
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64 | architecture ar_ssram_plugin of ssram_plugin is | |||
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65 | ||||
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66 | signal nADSPint : std_logic:='1'; | |||
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67 | signal nOEint : std_logic:='1'; | |||
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68 | signal RAMSN_reg: std_logic:='1'; | |||
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69 | signal OEreg : std_logic:='1'; | |||
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70 | signal nBWaint : std_logic:='1'; | |||
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71 | signal nBWbint : std_logic:='1'; | |||
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72 | signal nBWcint : std_logic:='1'; | |||
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73 | signal nBWdint : std_logic:='1'; | |||
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74 | signal nBWEint : std_logic:='1'; | |||
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75 | ||||
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76 | begin | |||
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77 | ||||
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78 | ||||
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79 | ||||
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80 | ssram_clk_pad : outpad generic map (tech => tech) | |||
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81 | port map (SSRAM_CLK,not clk); | |||
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82 | ||||
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83 | ||||
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84 | nBWaint <= mem_ctrlr_o.WRN(3)or mem_ctrlr_o.ramsn(0); | |||
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85 | nBWa_pad : outpad generic map (tech => tech) | |||
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86 | port map (nBWa,nBWaint); | |||
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87 | ||||
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88 | nBWbint <= mem_ctrlr_o.WRN(2)or mem_ctrlr_o.ramsn(0); | |||
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89 | nBWb_pad : outpad generic map (tech => tech) | |||
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90 | port map (nBWb, nBWbint); | |||
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91 | ||||
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92 | nBWcint <= mem_ctrlr_o.WRN(1)or mem_ctrlr_o.ramsn(0); | |||
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93 | nBWc_pad : outpad generic map (tech => tech) | |||
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94 | port map (nBWc, nBWcint); | |||
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95 | ||||
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96 | nBWdint <= mem_ctrlr_o.WRN(0)or mem_ctrlr_o.ramsn(0); | |||
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97 | nBWd_pad : outpad generic map (tech => tech) | |||
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98 | port map (nBWd, nBWdint); | |||
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99 | ||||
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100 | nBWEint <= mem_ctrlr_o.WRITEN or mem_ctrlr_o.ramsn(0); | |||
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101 | nBWE_pad : outpad generic map (tech => tech) | |||
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102 | port map (nBWE, nBWEint); | |||
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103 | ||||
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104 | nADSC_pad : outpad generic map (tech => tech) | |||
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105 | port map (nADSC, '1'); | |||
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106 | ||||
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107 | nADSPint <= not((RAMSN_reg xor mem_ctrlr_o.RAMSN(0)) and RAMSN_reg); | |||
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108 | process(clk) | |||
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109 | begin | |||
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110 | if clk'event and clk = '1' then | |||
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111 | RAMSN_reg <= mem_ctrlr_o.RAMSN(0); | |||
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112 | end if; | |||
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113 | end process; | |||
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114 | ||||
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115 | nADSP_pad : outpad generic map (tech => tech) | |||
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116 | port map (nADSP, nADSPint); | |||
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117 | ||||
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118 | nADV_pad : outpad generic map (tech => tech) | |||
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119 | port map (nADV, '1'); | |||
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120 | ||||
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121 | nGW_pad : outpad generic map (tech => tech) | |||
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122 | port map (nGW, '1'); | |||
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123 | ||||
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124 | nCE1_pad : outpad generic map (tech => tech) | |||
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125 | port map (nCE1, nADSPint); | |||
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126 | ||||
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127 | CE2_pad : outpad generic map (tech => tech) | |||
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128 | port map (CE2, '1'); | |||
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129 | ||||
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130 | nCE3_pad : outpad generic map (tech => tech) | |||
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131 | port map (nCE3, '0'); | |||
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132 | ||||
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133 | nOE_pad : outpad generic map (tech => tech) | |||
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134 | port map (nOE, nOEint); | |||
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135 | ||||
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136 | process(clk) | |||
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137 | begin | |||
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138 | if clk'event and clk = '1' then | |||
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139 | OEreg <= mem_ctrlr_o.OEN; | |||
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140 | end if; | |||
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141 | end process; | |||
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142 | ||||
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143 | ||||
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144 | nOEint <= OEreg or mem_ctrlr_o.RAMOEN(0); | |||
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145 | ||||
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146 | MODE_pad : outpad generic map (tech => tech) | |||
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147 | port map (MODE, '0'); | |||
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148 | ||||
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149 | ZZ_pad : outpad generic map (tech => tech) | |||
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150 | port map (ZZ, '0'); | |||
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151 | ||||
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152 | end architecture; No newline at end of file |
@@ -1,250 +1,275 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------ |
|
18 | ------------------------------------------------------------------------------ | |
19 | -- Author : Martin Morlot |
|
19 | -- Author : Martin Morlot | |
20 | -- Mail : martin.morlot@lpp.polytechnique.fr |
|
20 | -- Mail : martin.morlot@lpp.polytechnique.fr | |
21 | ------------------------------------------------------------------------------ |
|
21 | ------------------------------------------------------------------------------ | |
22 | library ieee; |
|
22 | library ieee; | |
23 | use ieee.std_logic_1164.all; |
|
23 | use ieee.std_logic_1164.all; | |
24 | library grlib; |
|
24 | library grlib; | |
25 | use grlib.amba.all; |
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25 | use grlib.amba.all; | |
26 | use std.textio.all; |
|
26 | use std.textio.all; | |
27 | library lpp; |
|
27 | library lpp; | |
28 | use lpp.lpp_amba.all; |
|
28 | use lpp.lpp_amba.all; | |
29 |
|
29 | |||
30 | --! Package contenant tous les programmes qui forment le composant intοΏ½grοΏ½ dans le lοΏ½on |
|
30 | --! Package contenant tous les programmes qui forment le composant intοΏ½grοΏ½ dans le lοΏ½on | |
31 |
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31 | |||
32 | package lpp_memory is |
|
32 | package lpp_memory is | |
33 |
|
33 | |||
34 | --===========================================================| |
|
34 | --===========================================================| | |
35 | --=================== FIFO ComplοΏ½te =========================| |
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35 | --=================== FIFO ComplοΏ½te =========================| | |
36 | --===========================================================| |
|
36 | --===========================================================| | |
37 |
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37 | |||
38 | component APB_FIFO is |
|
38 | component APB_FIFO is | |
39 | generic ( |
|
39 | generic ( | |
40 | pindex : integer := 0; |
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40 | pindex : integer := 0; | |
41 | paddr : integer := 0; |
|
41 | paddr : integer := 0; | |
42 | pmask : integer := 16#fff#; |
|
42 | pmask : integer := 16#fff#; | |
43 | pirq : integer := 0; |
|
43 | pirq : integer := 0; | |
44 | abits : integer := 8; |
|
44 | abits : integer := 8; | |
45 | Data_sz : integer := 16; |
|
45 | Data_sz : integer := 16; | |
46 | Addr_sz : integer := 8; |
|
46 | Addr_sz : integer := 8; | |
47 | addr_max_int : integer := 256); |
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47 | addr_max_int : integer := 256); | |
48 | port ( |
|
48 | port ( | |
49 | clk : in std_logic; |
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49 | clk : in std_logic; | |
50 | rst : in std_logic; |
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50 | rst : in std_logic; | |
51 | apbi : in apb_slv_in_type; |
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51 | apbi : in apb_slv_in_type; | |
52 | Full : out std_logic; |
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52 | Full : out std_logic; | |
53 | Empty : out std_logic; |
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53 | Empty : out std_logic; | |
54 | WR : out std_logic; |
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54 | WR : out std_logic; | |
55 | RE : out std_logic; |
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55 | RE : out std_logic; | |
56 | apbo : out apb_slv_out_type |
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56 | apbo : out apb_slv_out_type | |
57 | ); |
|
57 | ); | |
58 | end component; |
|
58 | end component; | |
59 |
|
59 | |||
60 |
|
60 | |||
61 | component ApbDriver is |
|
61 | component ApbDriver is | |
62 | generic ( |
|
62 | generic ( | |
63 | pindex : integer := 0; |
|
63 | pindex : integer := 0; | |
64 | paddr : integer := 0; |
|
64 | paddr : integer := 0; | |
65 | pmask : integer := 16#fff#; |
|
65 | pmask : integer := 16#fff#; | |
66 | pirq : integer := 0; |
|
66 | pirq : integer := 0; | |
67 | abits : integer := 8; |
|
67 | abits : integer := 8; | |
68 | LPP_DEVICE : integer; |
|
68 | LPP_DEVICE : integer; | |
69 | Data_sz : integer := 16; |
|
69 | Data_sz : integer := 16; | |
70 | Addr_sz : integer := 8; |
|
70 | Addr_sz : integer := 8; | |
71 | addr_max_int : integer := 256); |
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71 | addr_max_int : integer := 256); | |
72 | port ( |
|
72 | port ( | |
73 | clk : in std_logic; |
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73 | clk : in std_logic; | |
74 | rst : in std_logic; |
|
74 | rst : in std_logic; | |
75 | ReadEnable : out std_logic; |
|
75 | ReadEnable : out std_logic; | |
76 | WriteEnable : out std_logic; |
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76 | WriteEnable : out std_logic; | |
77 | FlagEmpty : in std_logic; |
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77 | FlagEmpty : in std_logic; | |
78 | FlagFull : in std_logic; |
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78 | FlagFull : in std_logic; | |
79 | ReUse : out std_logic; |
|
79 | ReUse : out std_logic; | |
80 | Lock : out std_logic; |
|
80 | Lock : out std_logic; | |
81 | DataIn : out std_logic_vector(Data_sz-1 downto 0); |
|
81 | DataIn : out std_logic_vector(Data_sz-1 downto 0); | |
82 | DataOut : in std_logic_vector(Data_sz-1 downto 0); |
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82 | DataOut : in std_logic_vector(Data_sz-1 downto 0); | |
83 | AddrIn : in std_logic_vector(Addr_sz-1 downto 0); |
|
83 | AddrIn : in std_logic_vector(Addr_sz-1 downto 0); | |
84 | AddrOut : in std_logic_vector(Addr_sz-1 downto 0); |
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84 | AddrOut : in std_logic_vector(Addr_sz-1 downto 0); | |
85 | apbi : in apb_slv_in_type; |
|
85 | apbi : in apb_slv_in_type; | |
86 | apbo : out apb_slv_out_type |
|
86 | apbo : out apb_slv_out_type | |
87 | ); |
|
87 | ); | |
88 | end component; |
|
88 | end component; | |
89 |
|
89 | |||
90 |
|
90 | |||
91 | component Top_FIFO is |
|
91 | component Top_FIFO is | |
92 | generic( |
|
92 | generic( | |
93 | Data_sz : integer := 16; |
|
93 | Data_sz : integer := 16; | |
94 | Addr_sz : integer := 8; |
|
94 | Addr_sz : integer := 8; | |
95 | addr_max_int : integer := 256 |
|
95 | addr_max_int : integer := 256 | |
96 | ); |
|
96 | ); | |
97 | port( |
|
97 | port( | |
98 | clk,raz : in std_logic; |
|
98 | clk,raz : in std_logic; | |
99 | flag_RE : in std_logic; |
|
99 | flag_RE : in std_logic; | |
100 | flag_WR : in std_logic; |
|
100 | flag_WR : in std_logic; | |
101 | ReUse : in std_logic; |
|
101 | ReUse : in std_logic; | |
102 | Lock : in std_logic; |
|
102 | Lock : in std_logic; | |
103 | Data_in : in std_logic_vector(Data_sz-1 downto 0); |
|
103 | Data_in : in std_logic_vector(Data_sz-1 downto 0); | |
104 | Addr_RE : out std_logic_vector(addr_sz-1 downto 0); |
|
104 | Addr_RE : out std_logic_vector(addr_sz-1 downto 0); | |
105 | Addr_WR : out std_logic_vector(addr_sz-1 downto 0); |
|
105 | Addr_WR : out std_logic_vector(addr_sz-1 downto 0); | |
106 | full : out std_logic; |
|
106 | full : out std_logic; | |
107 | empty : out std_logic; |
|
107 | empty : out std_logic; | |
108 | Data_out : out std_logic_vector(Data_sz-1 downto 0) |
|
108 | Data_out : out std_logic_vector(Data_sz-1 downto 0) | |
109 | ); |
|
109 | ); | |
110 | end component; |
|
110 | end component; | |
111 |
|
111 | |||
112 |
|
112 | |||
113 | component Fifo_Read is |
|
113 | component Fifo_Read is | |
114 | generic( |
|
114 | generic( | |
115 | Addr_sz : integer := 8; |
|
115 | Addr_sz : integer := 8; | |
116 | addr_max_int : integer := 256); |
|
116 | addr_max_int : integer := 256); | |
117 | port( |
|
117 | port( | |
118 | clk : in std_logic; |
|
118 | clk : in std_logic; | |
119 | raz : in std_logic; |
|
119 | raz : in std_logic; | |
120 | flag_RE : in std_logic; |
|
120 | flag_RE : in std_logic; | |
121 | ReUse : in std_logic; |
|
121 | ReUse : in std_logic; | |
122 | Waddr : in std_logic_vector(addr_sz-1 downto 0); |
|
122 | Waddr : in std_logic_vector(addr_sz-1 downto 0); | |
123 | empty : out std_logic; |
|
123 | empty : out std_logic; | |
124 | Raddr : out std_logic_vector(addr_sz-1 downto 0) |
|
124 | Raddr : out std_logic_vector(addr_sz-1 downto 0) | |
125 | ); |
|
125 | ); | |
126 | end component; |
|
126 | end component; | |
127 |
|
127 | |||
128 |
|
128 | |||
129 | component Fifo_Write is |
|
129 | component Fifo_Write is | |
130 | generic( |
|
130 | generic( | |
131 | Addr_sz : integer := 8; |
|
131 | Addr_sz : integer := 8; | |
132 | addr_max_int : integer := 256); |
|
132 | addr_max_int : integer := 256); | |
133 | port( |
|
133 | port( | |
134 | clk : in std_logic; |
|
134 | clk : in std_logic; | |
135 | raz : in std_logic; |
|
135 | raz : in std_logic; | |
136 | flag_WR : in std_logic; |
|
136 | flag_WR : in std_logic; | |
137 | Raddr : in std_logic_vector(addr_sz-1 downto 0); |
|
137 | Raddr : in std_logic_vector(addr_sz-1 downto 0); | |
138 | full : out std_logic; |
|
138 | full : out std_logic; | |
139 | Waddr : out std_logic_vector(addr_sz-1 downto 0) |
|
139 | Waddr : out std_logic_vector(addr_sz-1 downto 0) | |
140 | ); |
|
140 | ); | |
141 | end component; |
|
141 | end component; | |
142 |
|
142 | |||
143 |
|
143 | |||
144 | component Link_Reg is |
|
144 | component Link_Reg is | |
145 | generic(Data_sz : integer := 16); |
|
145 | generic(Data_sz : integer := 16); | |
146 | port( |
|
146 | port( | |
147 | clk,raz : in std_logic; |
|
147 | clk,raz : in std_logic; | |
148 | Data_one : in std_logic_vector(Data_sz-1 downto 0); |
|
148 | Data_one : in std_logic_vector(Data_sz-1 downto 0); | |
149 | Data_two : in std_logic_vector(Data_sz-1 downto 0); |
|
149 | Data_two : in std_logic_vector(Data_sz-1 downto 0); | |
150 | ReUse : in std_logic; |
|
150 | ReUse : in std_logic; | |
151 | flag_RE : in std_logic; |
|
151 | flag_RE : in std_logic; | |
152 | flag_WR : in std_logic; |
|
152 | flag_WR : in std_logic; | |
153 | empty : in std_logic; |
|
153 | empty : in std_logic; | |
154 | Data_out : out std_logic_vector(Data_sz-1 downto 0) |
|
154 | Data_out : out std_logic_vector(Data_sz-1 downto 0) | |
155 | ); |
|
155 | ); | |
156 | end component; |
|
156 | end component; | |
157 |
|
157 | |||
158 | --===========================================================| |
|
158 | --===========================================================| | |
159 | --================= Demi FIFO Ecriture ======================| |
|
159 | --================= Demi FIFO Ecriture ======================| | |
160 | --===========================================================| |
|
160 | --===========================================================| | |
161 |
|
161 | |||
162 | component APB_FifoWrite is |
|
162 | component APB_FifoWrite is | |
163 | generic ( |
|
163 | generic ( | |
164 | pindex : integer := 0; |
|
164 | pindex : integer := 0; | |
165 | paddr : integer := 0; |
|
165 | paddr : integer := 0; | |
166 | pmask : integer := 16#fff#; |
|
166 | pmask : integer := 16#fff#; | |
167 | pirq : integer := 0; |
|
167 | pirq : integer := 0; | |
168 | abits : integer := 8; |
|
168 | abits : integer := 8; | |
169 | Data_sz : integer := 16; |
|
169 | Data_sz : integer := 16; | |
170 | Addr_sz : integer := 8; |
|
170 | Addr_sz : integer := 8; | |
171 | addr_max_int : integer := 256); |
|
171 | addr_max_int : integer := 256); | |
172 | port ( |
|
172 | port ( | |
173 | clk : in std_logic; |
|
173 | clk : in std_logic; | |
174 | rst : in std_logic; |
|
174 | rst : in std_logic; | |
175 | apbi : in apb_slv_in_type; |
|
175 | apbi : in apb_slv_in_type; | |
176 | ReadEnable : in std_logic; |
|
176 | ReadEnable : in std_logic; | |
177 | Empty : out std_logic; |
|
177 | Empty : out std_logic; | |
178 | Full : out std_logic; |
|
178 | Full : out std_logic; | |
179 | DATA : out std_logic_vector(Data_sz-1 downto 0); |
|
179 | DATA : out std_logic_vector(Data_sz-1 downto 0); | |
180 | apbo : out apb_slv_out_type |
|
180 | apbo : out apb_slv_out_type | |
181 | ); |
|
181 | ); | |
182 | end component; |
|
182 | end component; | |
183 |
|
183 | |||
184 |
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184 | |||
185 | --component Top_FifoWrite is |
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185 | --component Top_FifoWrite is | |
186 | -- generic( |
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186 | -- generic( | |
187 | -- Data_sz : integer := 16; |
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187 | -- Data_sz : integer := 16; | |
188 | -- Addr_sz : integer := 8; |
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188 | -- Addr_sz : integer := 8; | |
189 | -- addr_max_int : integer := 256); |
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189 | -- addr_max_int : integer := 256); | |
190 | -- port( |
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190 | -- port( | |
191 | -- clk : in std_logic; |
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191 | -- clk : in std_logic; | |
192 | -- raz : in std_logic; |
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192 | -- raz : in std_logic; | |
193 | -- flag_RE : in std_logic; |
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193 | -- flag_RE : in std_logic; | |
194 | -- flag_WR : in std_logic; |
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194 | -- flag_WR : in std_logic; | |
195 | -- Data_in : in std_logic_vector(Data_sz-1 downto 0); |
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195 | -- Data_in : in std_logic_vector(Data_sz-1 downto 0); | |
196 | -- Raddr : in std_logic_vector(addr_sz-1 downto 0); |
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196 | -- Raddr : in std_logic_vector(addr_sz-1 downto 0); | |
197 | -- full : out std_logic; |
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197 | -- full : out std_logic; | |
198 | -- empty : out std_logic; |
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198 | -- empty : out std_logic; | |
199 | -- Waddr : out std_logic_vector(addr_sz-1 downto 0); |
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199 | -- Waddr : out std_logic_vector(addr_sz-1 downto 0); | |
200 | -- Data_out : out std_logic_vector(Data_sz-1 downto 0) |
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200 | -- Data_out : out std_logic_vector(Data_sz-1 downto 0) | |
201 | -- ); |
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201 | -- ); | |
202 | --end component; |
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202 | --end component; | |
203 |
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203 | |||
204 | --===========================================================| |
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204 | --===========================================================| | |
205 | --================== Demi FIFO Lecture ======================| |
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205 | --================== Demi FIFO Lecture ======================| | |
206 | --===========================================================| |
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206 | --===========================================================| | |
207 |
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207 | |||
208 | component APB_FifoRead is |
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208 | component APB_FifoRead is | |
209 | generic ( |
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209 | generic ( | |
210 | pindex : integer := 0; |
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210 | pindex : integer := 0; | |
211 | paddr : integer := 0; |
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211 | paddr : integer := 0; | |
212 | pmask : integer := 16#fff#; |
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212 | pmask : integer := 16#fff#; | |
213 | pirq : integer := 0; |
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213 | pirq : integer := 0; | |
214 | abits : integer := 8; |
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214 | abits : integer := 8; | |
215 | Data_sz : integer := 16; |
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215 | Data_sz : integer := 16; | |
216 | Addr_sz : integer := 8; |
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216 | Addr_sz : integer := 8; | |
217 | addr_max_int : integer := 256); |
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217 | addr_max_int : integer := 256); | |
218 | port ( |
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218 | port ( | |
219 | clk : in std_logic; |
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219 | clk : in std_logic; | |
220 | rst : in std_logic; |
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220 | rst : in std_logic; | |
221 | apbi : in apb_slv_in_type; |
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221 | apbi : in apb_slv_in_type; | |
222 | WriteEnable : in std_logic; |
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222 | WriteEnable : in std_logic; | |
223 | Full : out std_logic; |
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223 | Full : out std_logic; | |
224 | Empty : out std_logic; |
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224 | Empty : out std_logic; | |
225 | DATA : in std_logic_vector(Data_sz-1 downto 0); |
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225 | DATA : in std_logic_vector(Data_sz-1 downto 0); | |
226 | apbo : out apb_slv_out_type |
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226 | apbo : out apb_slv_out_type | |
227 | ); |
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227 | ); | |
228 | end component; |
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228 | end component; | |
229 |
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229 | |||
230 |
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230 | |||
231 | --component Top_FifoRead is |
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231 | --component Top_FifoRead is | |
232 | -- generic( |
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232 | -- generic( | |
233 | -- Data_sz : integer := 16; |
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233 | -- Data_sz : integer := 16; | |
234 | -- Addr_sz : integer := 8; |
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234 | -- Addr_sz : integer := 8; | |
235 | -- addr_max_int : integer := 256); |
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235 | -- addr_max_int : integer := 256); | |
236 | -- port( |
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236 | -- port( | |
237 | -- clk : in std_logic; |
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237 | -- clk : in std_logic; | |
238 | -- raz : in std_logic; |
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238 | -- raz : in std_logic; | |
239 | -- flag_RE : in std_logic; |
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239 | -- flag_RE : in std_logic; | |
240 | -- flag_WR : in std_logic; |
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240 | -- flag_WR : in std_logic; | |
241 | -- Data_in : in std_logic_vector(Data_sz-1 downto 0); |
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241 | -- Data_in : in std_logic_vector(Data_sz-1 downto 0); | |
242 | -- Waddr : in std_logic_vector(addr_sz-1 downto 0); |
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242 | -- Waddr : in std_logic_vector(addr_sz-1 downto 0); | |
243 | -- full : out std_logic; |
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243 | -- full : out std_logic; | |
244 | -- empty : out std_logic; |
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244 | -- empty : out std_logic; | |
245 | -- Raddr : out std_logic_vector(addr_sz-1 downto 0); |
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245 | -- Raddr : out std_logic_vector(addr_sz-1 downto 0); | |
246 | -- Data_out : out std_logic_vector(Data_sz-1 downto 0) |
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246 | -- Data_out : out std_logic_vector(Data_sz-1 downto 0) | |
247 | -- ); |
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247 | -- ); | |
248 | --end component; |
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248 | --end component; | |
249 |
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249 | |||
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250 | component ssram_plugin is | |||
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251 | generic (tech : integer := 0); | |||
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252 | port | |||
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253 | ( | |||
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254 | clk : in std_logic; | |||
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255 | mem_ctrlr_o : in memory_out_type; | |||
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256 | SSRAM_CLK : out std_logic; | |||
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257 | nBWa : out std_logic; | |||
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258 | nBWb : out std_logic; | |||
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259 | nBWc : out std_logic; | |||
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260 | nBWd : out std_logic; | |||
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261 | nBWE : out std_logic; | |||
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262 | nADSC : out std_logic; | |||
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263 | nADSP : out std_logic; | |||
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264 | nADV : out std_logic; | |||
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265 | nGW : out std_logic; | |||
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266 | nCE1 : out std_logic; | |||
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267 | CE2 : out std_logic; | |||
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268 | nCE3 : out std_logic; | |||
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269 | nOE : out std_logic; | |||
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270 | MODE : out std_logic; | |||
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271 | ZZ : out std_logic | |||
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272 | ); | |||
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273 | end component; | |||
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274 | ||||
250 | end; |
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275 | end; |
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