HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Commit - r84:6c2ce1d3393f

Added SSRAM plugin for LFR developpement model

jeandet@PC-DE-JEANDET.lpp.polytechnique.fr -

r84:6c2ce1d3393f alexis

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r84:6c2ce1d3393f

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lib/lpp/lpp_memory/SSRAM_plugin.vhd created 644 +152 0

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	1	------------------------------------------------------------------------------
	2	-- This file is a part of the LPP VHDL IP LIBRARY
	3	-- Copyright (C) 2011, Laboratory of Plasmas Physic - CNRS
	4	--
	5	-- This program is free software; you can redistribute it and/or modify
	6	-- it under the terms of the GNU General Public License as published by
	7	-- the Free Software Foundation; either version 3 of the License, or
	8	-- (at your option) any later version.
	9	--
	10	-- This program is distributed in the hope that it will be useful,
	11	-- but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	-- GNU General Public License for more details.
	14	--
	15	-- You should have received a copy of the GNU General Public License
	16	-- along with this program; if not, write to the Free Software
	17	-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18	-------------------------------------------------------------------------------
	19	-- Author : Alexis Jeandet
	20	-- Mail : alexis.jeandet@lpp.polytechnique.fr
	21	-------------------------------------------------------------------------------
	22	library ieee;
	23	use ieee.std_logic_1164.all;
	24	library gaisler;
	25	use gaisler.misc.all;
	26	use gaisler.memctrl.all;
	27	library techmap;
	28	use techmap.gencomp.all;
	29	use techmap.allclkgen.all;
	30
	31
	32
	33
	34	entity ssram_plugin is
	35	generic (tech : integer := 0);
	36	port
	37	(
	38	clk : in std_logic;
	39	mem_ctrlr_o : in memory_out_type;
	40	SSRAM_CLK : out std_logic;
	41	nBWa : out std_logic;
	42	nBWb : out std_logic;
	43	nBWc : out std_logic;
	44	nBWd : out std_logic;
	45	nBWE : out std_logic;
	46	nADSC : out std_logic;
	47	nADSP : out std_logic;
	48	nADV : out std_logic;
	49	nGW : out std_logic;
	50	nCE1 : out std_logic;
	51	CE2 : out std_logic;
	52	nCE3 : out std_logic;
	53	nOE : out std_logic;
	54	MODE : out std_logic;
	55	ZZ : out std_logic
	56	);
	57	end entity;
	58
	59
	60
	61
	62
	63
	64	architecture ar_ssram_plugin of ssram_plugin is
	65
	66	signal nADSPint : std_logic:='1';
	67	signal nOEint : std_logic:='1';
	68	signal RAMSN_reg: std_logic:='1';
	69	signal OEreg : std_logic:='1';
	70	signal nBWaint : std_logic:='1';
	71	signal nBWbint : std_logic:='1';
	72	signal nBWcint : std_logic:='1';
	73	signal nBWdint : std_logic:='1';
	74	signal nBWEint : std_logic:='1';
	75
	76	begin
	77
	78
	79
	80	ssram_clk_pad : outpad generic map (tech => tech)
	81	port map (SSRAM_CLK,not clk);
	82
	83
	84	nBWaint <= mem_ctrlr_o.WRN(3)or mem_ctrlr_o.ramsn(0);
	85	nBWa_pad : outpad generic map (tech => tech)
	86	port map (nBWa,nBWaint);
	87
	88	nBWbint <= mem_ctrlr_o.WRN(2)or mem_ctrlr_o.ramsn(0);
	89	nBWb_pad : outpad generic map (tech => tech)
	90	port map (nBWb, nBWbint);
	91
	92	nBWcint <= mem_ctrlr_o.WRN(1)or mem_ctrlr_o.ramsn(0);
	93	nBWc_pad : outpad generic map (tech => tech)
	94	port map (nBWc, nBWcint);
	95
	96	nBWdint <= mem_ctrlr_o.WRN(0)or mem_ctrlr_o.ramsn(0);
	97	nBWd_pad : outpad generic map (tech => tech)
	98	port map (nBWd, nBWdint);
	99
	100	nBWEint <= mem_ctrlr_o.WRITEN or mem_ctrlr_o.ramsn(0);
	101	nBWE_pad : outpad generic map (tech => tech)
	102	port map (nBWE, nBWEint);
	103
	104	nADSC_pad : outpad generic map (tech => tech)
	105	port map (nADSC, '1');
	106
	107	nADSPint <= not((RAMSN_reg xor mem_ctrlr_o.RAMSN(0)) and RAMSN_reg);
	108	process(clk)
	109	begin
	110	if clk'event and clk = '1' then
	111	RAMSN_reg <= mem_ctrlr_o.RAMSN(0);
	112	end if;
	113	end process;
	114
	115	nADSP_pad : outpad generic map (tech => tech)
	116	port map (nADSP, nADSPint);
	117
	118	nADV_pad : outpad generic map (tech => tech)
	119	port map (nADV, '1');
	120
	121	nGW_pad : outpad generic map (tech => tech)
	122	port map (nGW, '1');
	123
	124	nCE1_pad : outpad generic map (tech => tech)
	125	port map (nCE1, nADSPint);
	126
	127	CE2_pad : outpad generic map (tech => tech)
	128	port map (CE2, '1');
	129
	130	nCE3_pad : outpad generic map (tech => tech)
	131	port map (nCE3, '0');
	132
	133	nOE_pad : outpad generic map (tech => tech)
	134	port map (nOE, nOEint);
	135
	136	process(clk)
	137	begin
	138	if clk'event and clk = '1' then
	139	OEreg <= mem_ctrlr_o.OEN;
	140	end if;
	141	end process;
	142
	143
	144	nOEint <= OEreg or mem_ctrlr_o.RAMOEN(0);
	145
	146	MODE_pad : outpad generic map (tech => tech)
	147	port map (MODE, '0');
	148
	149	ZZ_pad : outpad generic map (tech => tech)
	150	port map (ZZ, '0');
	151
	152	end architecture; No newline at end of file

lib/lpp/lpp_memory/lpp_memory.vhd +25 0

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             ------------------------------------------------------------------------------
             --                    Author : Martin Morlot
             --                     Mail : martin.morlot@lpp.polytechnique.fr
             ------------------------------------------------------------------------------
             library ieee;
             use ieee.std_logic_1164.all;
             library grlib;
             use grlib.amba.all;
             use std.textio.all;
             library lpp;
             use lpp.lpp_amba.all;
             --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
             package lpp_memory is
             --===========================================================|
             --=================== FIFO Compl�te =========================|
             --===========================================================|
             component APB_FIFO is
               generic (
                 pindex       : integer := 0;
                 paddr        : integer := 0;
                 pmask        : integer := 16#fff#;
                 pirq         : integer := 0;
                 abits        : integer := 8;
                 Data_sz      : integer := 16;
                 Addr_sz      : integer := 8;
                 addr_max_int : integer := 256);
               port (
                 clk          : in  std_logic;
                 rst          : in  std_logic;
                 apbi         : in  apb_slv_in_type;
                 Full    : out std_logic;
                 Empty   : out std_logic;
                 WR : out std_logic;
                 RE : out std_logic;
                 apbo         : out apb_slv_out_type
                 );
             end component;
             component ApbDriver is
               generic (
                 pindex       : integer := 0;
                 paddr        : integer := 0;
                 pmask        : integer := 16#fff#;
                 pirq         : integer := 0;
                 abits        : integer := 8;
                 LPP_DEVICE   : integer;
                 Data_sz      : integer := 16;
                 Addr_sz      : integer := 8;
                 addr_max_int : integer := 256);
               port (
                 clk          : in  std_logic;
                 rst          : in  std_logic;
                 ReadEnable   : out std_logic;
                 WriteEnable  : out std_logic;
                 FlagEmpty    : in std_logic;
                 FlagFull     : in std_logic;
                 ReUse        : out std_logic;
                 Lock         : out std_logic;
                 DataIn       : out std_logic_vector(Data_sz-1 downto 0);
                 DataOut      : in std_logic_vector(Data_sz-1 downto 0);
                 AddrIn       : in std_logic_vector(Addr_sz-1 downto 0);
                 AddrOut      : in std_logic_vector(Addr_sz-1 downto 0);
                 apbi         : in  apb_slv_in_type;
                 apbo         : out apb_slv_out_type
                 );
             end component;
             component Top_FIFO is
               generic(
                 Data_sz      : integer := 16;
                 Addr_sz      : integer := 8;
                 addr_max_int : integer := 256
                 );
               port(
                 clk,raz  : in std_logic;
                 flag_RE  : in std_logic;
                 flag_WR  : in std_logic;
                 ReUse    : in std_logic;
                 Lock     : in std_logic;
                 Data_in  : in std_logic_vector(Data_sz-1 downto 0);
                 Addr_RE  : out std_logic_vector(addr_sz-1 downto 0);
                 Addr_WR  : out std_logic_vector(addr_sz-1 downto 0);
                 full     : out std_logic;
                 empty    : out std_logic;
                 Data_out : out std_logic_vector(Data_sz-1 downto 0)
                 );
             end component;
             component Fifo_Read is
               generic(
                 Addr_sz      : integer := 8;
                 addr_max_int : integer := 256);
               port(
                 clk          : in std_logic;
                 raz          : in std_logic;
                 flag_RE      : in std_logic;
                 ReUse        : in std_logic;
                 Waddr        : in std_logic_vector(addr_sz-1 downto 0);
                 empty        : out std_logic;
                 Raddr        : out std_logic_vector(addr_sz-1 downto 0)
                 );
             end component;
             component Fifo_Write is
               generic(
                 Addr_sz      : integer := 8;
                 addr_max_int : integer := 256);
               port(
                 clk          : in std_logic;
                 raz          : in std_logic;
                 flag_WR      : in std_logic;
                 Raddr        : in std_logic_vector(addr_sz-1 downto 0);
                 full         : out std_logic;
                 Waddr        : out std_logic_vector(addr_sz-1 downto 0)
                 );
             end component;
             component Link_Reg is
               generic(Data_sz : integer := 16);
               port(
                 clk,raz       : in std_logic;
                 Data_one      : in std_logic_vector(Data_sz-1 downto 0);
                 Data_two      : in std_logic_vector(Data_sz-1 downto 0);
                 ReUse         : in std_logic;
                 flag_RE       : in std_logic;
                 flag_WR       : in std_logic;
                 empty         : in std_logic;
                 Data_out      : out std_logic_vector(Data_sz-1 downto 0)
                 );
             end component;
             --===========================================================|
             --================= Demi FIFO Ecriture ======================|
             --===========================================================|
             component APB_FifoWrite is
               generic (
                 pindex       : integer := 0;
                 paddr        : integer := 0;
                 pmask        : integer := 16#fff#;
                 pirq         : integer := 0;
                 abits        : integer := 8;
                 Data_sz      : integer := 16;
                 Addr_sz      : integer := 8;
                 addr_max_int : integer := 256);
               port (
                 clk          : in  std_logic;
                 rst          : in  std_logic;
                 apbi         : in  apb_slv_in_type;
                 ReadEnable   : in  std_logic;
                 Empty        : out std_logic;
                 Full         : out std_logic;
                 DATA         : out std_logic_vector(Data_sz-1 downto 0);
                 apbo         : out apb_slv_out_type
                 );
             end component;
             --component Top_FifoWrite is
             --  generic(
             --    Data_sz      : integer := 16;
             --    Addr_sz      : integer := 8;
             --    addr_max_int : integer := 256);
             --  port(
             --    clk          : in std_logic;
             --    raz          : in std_logic;
             --    flag_RE      : in std_logic;
             --    flag_WR      : in std_logic;
             --    Data_in      : in std_logic_vector(Data_sz-1 downto 0);
             --    Raddr        : in std_logic_vector(addr_sz-1 downto 0);
             --    full         : out std_logic;
             --    empty        : out std_logic;
             --    Waddr        : out std_logic_vector(addr_sz-1 downto 0);
             --    Data_out     : out std_logic_vector(Data_sz-1 downto 0)
             --    );
             --end component;
             --===========================================================|
             --================== Demi FIFO Lecture ======================|
             --===========================================================|
             component APB_FifoRead is
               generic (
                 pindex       : integer := 0;
                 paddr        : integer := 0;
                 pmask        : integer := 16#fff#;
                 pirq         : integer := 0;
                 abits        : integer := 8;
                 Data_sz      : integer := 16;
                 Addr_sz      : integer := 8;
                 addr_max_int : integer := 256);
               port (
                 clk          : in  std_logic;
                 rst          : in  std_logic;
                 apbi         : in  apb_slv_in_type;
                 WriteEnable  : in std_logic;
                 Full         : out std_logic;
                 Empty        : out std_logic;
                 DATA         : in std_logic_vector(Data_sz-1 downto 0);
                 apbo         : out apb_slv_out_type
                 );
             end component;
             --component Top_FifoRead is
             --  generic(
             --    Data_sz      : integer := 16;
             --    Addr_sz      : integer := 8;
             --    addr_max_int : integer := 256);
             --  port(
             --    clk          : in std_logic;
             --    raz          : in std_logic;
             --    flag_RE      : in std_logic;
             --    flag_WR      : in std_logic;
             --    Data_in      : in std_logic_vector(Data_sz-1 downto 0);
             --    Waddr        : in std_logic_vector(addr_sz-1 downto 0);
             --    full         : out std_logic;
             --    empty        : out std_logic;
             --    Raddr        : out std_logic_vector(addr_sz-1 downto 0);
             --    Data_out     : out std_logic_vector(Data_sz-1 downto 0)
             --    );
             --end component;
+            component ssram_plugin is
+            generic (tech : integer := 0);
+            port
+            (
+                clk             : in  std_logic;
+                mem_ctrlr_o     : in  memory_out_type;
+                SSRAM_CLK       : out std_logic;
+                nBWa            : out std_logic;
+                nBWb            : out std_logic;
+                nBWc            : out std_logic;
+                nBWd            : out std_logic;
+                nBWE            : out std_logic;
+                nADSC           : out std_logic;
+                nADSP           : out std_logic;
+                nADV            : out std_logic;
+                nGW             : out std_logic;
+                nCE1            : out std_logic;
+                CE2             : out std_logic;
+                nCE3            : out std_logic;
+                nOE             : out std_logic;
+                MODE            : out std_logic;
+                ZZ              : out std_logic
+            );
+            end component;
             end;

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