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[WFP] Register the DMA "send" signal to permit the start of 2 burst consecutively.
pellion -
r302:6b992ec40bf9 WaveFormPicker-0-0-10 (MINI-LFR) JC
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@@ -20,4 +20,4 log -r *
20 20
21 21 do wave_waveform_longsim.do
22 22
23 run 500 ms
23 run 40 ms
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@@ -19,6 +19,7 USE ieee.std_logic_1164.ALL;
19 19 LIBRARY grlib;
20 20 USE grlib.amba.ALL;
21 21 USE grlib.stdlib.ALL;
22 USE grlib.AMBA_TestPackage.ALL;
22 23 LIBRARY gaisler;
23 24 USE gaisler.memctrl.ALL;
24 25 USE gaisler.leon3.ALL;
@@ -224,7 +225,7 ARCHITECTURE behav OF testbench IS
224 225 -----------------------------------------------------------------------------
225 226
226 227 SIGNAL current_data : INTEGER;
227 SIGNAL LIMIT_DATA : INTEGER := 194;
228 SIGNAL LIMIT_DATA : INTEGER := 64;
228 229
229 230 SIGNAL read_buffer_temp : STD_LOGIC;
230 231 SIGNAL read_buffer_temp_2 : STD_LOGIC;
@@ -367,6 +368,7 BEGIN
367 368 ADDR_BITS => 20,
368 369 DATA_BITS => 16,
369 370 depth => 1048576,
371 MEM_ARRAY_DEBUG => 194,
370 372 TimingInfo => TRUE,
371 373 TimingChecks => '1')
372 374 PORT MAP (
@@ -384,6 +386,7 BEGIN
384 386 ADDR_BITS => 20,
385 387 DATA_BITS => 16,
386 388 depth => 1048576,
389 MEM_ARRAY_DEBUG => 194,
387 390 TimingInfo => TRUE,
388 391 TimingChecks => '1')
389 392 PORT MAP (
@@ -435,11 +438,21 BEGIN
435 438 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F0_2 , X"00000007");--"00000007"
436 439 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F1 , X"00000062");--"00000019"
437 440 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F2 , X"00000001");--"00000001"
438
439 441 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_NB_DATA_IN_BUFFER , X"0000003f"); -- X"00000010"
440 442 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_NBSNAPSHOT , X"00000040");
441 443 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_START_DATE , X"00000001");
442 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_NB_WORD_IN_BUFFER , X"000000c2");
444 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_NB_WORD_IN_BUFFER , X"000000C2");-- 0xC2 = 64 * 3 + 2
445
446 --APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTASNAPSHOT , X"00000010");--"00000020"
447 --APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F0 , X"0000000C");--"00000019"
448 --APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F0_2 , X"00000007");--"00000007"
449 --APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F1 , X"0000000C");--"00000019"
450 --APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F2 , X"00000001");--"00000001"
451 --APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_NB_DATA_IN_BUFFER , X"00000007"); -- X"00000010"
452 --APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_NBSNAPSHOT , X"00000008");
453 --APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_START_DATE , X"00000001");
454 --APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_NB_WORD_IN_BUFFER , X"0000001A");-- 0xC2 = 8 * 3 + 2
455
443 456
444 457
445 458 WAIT UNTIL clk25MHz = '1';
@@ -526,6 +539,20 BEGIN
526 539 IF read_buffer = '1' THEN
527 540 state_read_buffer_on_going <= '1';
528 541
542 --AHBRead(X"40000000",time_mem_f0(31 DOWNTO 0),clk25MHz,
543 --constant Address: in Std_Logic_Vector(31 downto 0);
544 --variable Data: out Std_Logic_Vector(31 downto 0);
545 --signal HCLK: in Std_ULogic;
546
547 --signal AHBIn: out AHB_Slv_In_Type;
548 --signal AHBOut: in AHB_Slv_Out_Type;
549 --variable TP: inout Boolean;
550 --constant InstancePath: in String := "AHBRead";
551 --constant ScreenOutput: in Boolean := False;
552 --constant cBack2Back: in Boolean := False;
553 --constant HINDEX: in Integer := 0;
554 --constant HMBINDEX: in Integer := 0);
555
529 556 AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40000000", time_mem_f0(31 DOWNTO 0));
530 557 AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40020000", time_mem_f1(31 DOWNTO 0));
531 558 AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40040000", time_mem_f2(31 DOWNTO 0));
@@ -534,44 +561,42 BEGIN
534 561 AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40020004", time_mem_f1(63 DOWNTO 32));
535 562 AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40040004", time_mem_f2(63 DOWNTO 32));
536 563
537 current_data <= 8;
564 current_data <= 0;
538 565 ELSE
539 566 IF state_read_buffer_on_going = '1' THEN
540 567 -- READ ALL DATA in memory
541 AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40000000" + current_data, data_mem_f0);
542 AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40020000" + current_data, data_mem_f1);
543 AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40040000" + current_data, data_mem_f2);
568 AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40000000" + (current_data * 12) + 8, data_mem_f0);
569 AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40020000" + (current_data * 12) + 8, data_mem_f1);
570 AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40040000" + (current_data * 12) + 8, data_mem_f2);
544 571 data_0_f0 <= data_mem_f0(15 DOWNTO 0);
545 572 data_1_f0 <= data_mem_f0(31 DOWNTO 16);
546 573 data_0_f1 <= data_mem_f1(15 DOWNTO 0);
547 574 data_1_f1 <= data_mem_f1(31 DOWNTO 16);
548 575 data_0_f2 <= data_mem_f2(15 DOWNTO 0);
549 576 data_1_f2 <= data_mem_f2(31 DOWNTO 16);
550 current_data <= current_data + 4;
551 577
552 AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40000000" + current_data, data_mem_f0);
553 AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40020000" + current_data, data_mem_f1);
554 AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40040000" + current_data, data_mem_f2);
578 AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40000000" + (current_data * 12) + 4 + 8, data_mem_f0);
579 AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40020000" + (current_data * 12) + 4 + 8, data_mem_f1);
580 AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40040000" + (current_data * 12) + 4 + 8, data_mem_f2);
555 581 data_2_f0 <= data_mem_f0(15 DOWNTO 0);
556 582 data_3_f0 <= data_mem_f0(31 DOWNTO 16);
557 583 data_2_f1 <= data_mem_f1(15 DOWNTO 0);
558 584 data_3_f1 <= data_mem_f1(31 DOWNTO 16);
559 585 data_2_f2 <= data_mem_f2(15 DOWNTO 0);
560 586 data_3_f2 <= data_mem_f2(31 DOWNTO 16);
561 current_data <= current_data + 4;
562 587
563 AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40000000" + current_data, data_mem_f0);
564 AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40020000" + current_data, data_mem_f1);
565 AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40040000" + current_data, data_mem_f2);
588 AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40000000" + (current_data * 12) + 8 + 8, data_mem_f0);
589 AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40020000" + (current_data * 12) + 8 + 8, data_mem_f1);
590 AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40040000" + (current_data * 12) + 8 + 8, data_mem_f2);
566 591 data_4_f0 <= data_mem_f0(15 DOWNTO 0);
567 592 data_5_f0 <= data_mem_f0(31 DOWNTO 16);
568 593 data_4_f1 <= data_mem_f1(15 DOWNTO 0);
569 594 data_5_f1 <= data_mem_f1(31 DOWNTO 16);
570 595 data_4_f2 <= data_mem_f2(15 DOWNTO 0);
571 596 data_5_f2 <= data_mem_f2(31 DOWNTO 16);
572 current_data <= current_data + 4;
597 current_data <= current_data + 1;
573 598
574 IF current_data > LIMIT_DATA THEN
599 IF current_data >= LIMIT_DATA THEN
575 600 state_read_buffer_on_going <= '0';
576 601 time_mem_f0 <= (OTHERS => '0');
577 602 time_mem_f1 <= (OTHERS => '0');
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@@ -57,12 +57,14 PACKAGE BODY testbench_package IS
57 57 apbi.penable <= '1';
58 58 apbi.paddr <= paddr;
59 59 apbi.pwdata <= pwdata;
60 WAIT UNTIL clk = '0';
60 61 WAIT UNTIL clk = '1';
61 62 apbi.psel(pindex) <= '0';
62 63 apbi.pwrite <= '0';
63 64 apbi.penable <= '0';
64 65 apbi.paddr <= (OTHERS => '0');
65 66 apbi.pwdata <= (OTHERS => '0');
67 WAIT UNTIL clk = '0';
66 68 WAIT UNTIL clk = '1';
67 69
68 70 END APB_WRITE;
@@ -80,11 +82,13 PACKAGE BODY testbench_package IS
80 82 apbi.pwrite <= '0';
81 83 apbi.penable <= '1';
82 84 apbi.paddr <= paddr;
85 WAIT UNTIL clk = '0';
83 86 WAIT UNTIL clk = '1';
84 87 apbi.psel(pindex) <= '0';
85 88 apbi.pwrite <= '0';
86 89 apbi.penable <= '0';
87 90 apbi.paddr <= (OTHERS => '0');
91 WAIT UNTIL clk = '0';
88 92 WAIT UNTIL clk = '1';
89 93 prdata <= apbo.prdata;
90 94 END APB_READ;
@@ -98,6 +102,7 PACKAGE BODY testbench_package IS
98 102 SIGNAL hrdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
99 103 ) IS
100 104 BEGIN
105 WAIT UNTIL clk = '1';
101 106 ahbmo.HADDR <= haddr;
102 107 ahbmo.HPROT <= "0011";
103 108 ahbmo.HIRQ <= (OTHERS => '0');
@@ -109,12 +114,23 PACKAGE BODY testbench_package IS
109 114 ahbmo.HBURST <= HBURST_SINGLE;
110 115 ahbmo.HTRANS <= HTRANS_NONSEQ;
111 116 ahbmo.HWRITE <= '0';
112 WAIT UNTIL clk = '1' AND ahbmi.HREADY = '1' AND ahbmi.HGRANT(hindex) = '1';
113 hrdata <= ahbmi.HRDATA;
114 WAIT UNTIL clk = '1' AND ahbmi.HREADY = '1' AND ahbmi.HGRANT(hindex) = '1';
115 ahbmo.HTRANS <= HTRANS_IDLE;
117 WHILE ahbmi.HREADY = '0' LOOP
118 WAIT UNTIL clk = '1';
119 END LOOP;
120 WAIT UNTIL clk = '1';
121 --WAIT UNTIL clk = '1' AND ahbmi.HREADY = '1' AND ahbmi.HGRANT(hindex) = '1';
116 122 ahbmo.HBUSREQ <= '0';
117 123 ahbmo.HLOCK <= '0';
124 ahbmo.HTRANS <= HTRANS_IDLE;
125 WHILE ahbmi.HREADY = '0' LOOP
126 WAIT UNTIL clk = '1';
127 END LOOP;
128 WAIT UNTIL clk = '1';
129 hrdata <= ahbmi.HRDATA;
130 --WAIT UNTIL clk = '1' AND ahbmi.HREADY = '1' AND ahbmi.HGRANT(hindex) = '1';
131 ahbmo.HLOCK <= '0';
132 WAIT UNTIL clk = '1';
133
118 134 END AHB_READ;
119 135
120 136 END testbench_package;
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@@ -425,7 +425,7 BEGIN -- beh
425 425 pirq_ms => 6,
426 426 pirq_wfp => 14,
427 427 hindex => 2,
428 top_lfr_version => X"00000F") -- aa.bb.cc version
428 top_lfr_version => X"000010") -- aa.bb.cc version
429 429 PORT MAP (
430 430 clk => clk_25,
431 431 rstn => reset,
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@@ -95,6 +95,13 ARCHITECTURE Behavioral OF lpp_dma_singl
95 95 SIGNAL burst_ren : STD_LOGIC;
96 96 -----------------------------------------------------------------------------
97 97 SIGNAL data_2_halfword : STD_LOGIC_VECTOR(31 DOWNTO 0);
98 -----------------------------------------------------------------------------
99 -- \/ -- 20/02/2014 -- JC Pellion
100 SIGNAL send_reg : STD_LOGIC;
101 SIGNAL send_s : STD_LOGIC;
102 -- /\ --
103
104
98 105 BEGIN
99 106
100 107 debug_dmaout_okay <= DMAOut.OKAY;
@@ -121,14 +128,21 BEGIN
121 128 -----------------------------------------------------------------------------
122 129
123 130 -----------------------------------------------------------------------------
124 -----------------------------------------------------------------------------
125 -- LE PROBLEME EST LA !!!!!
126 -----------------------------------------------------------------------------
127 -----------------------------------------------------------------------------
128 -- C'est le signal valid_burst qui n'est pas assez long.
129 -----------------------------------------------------------------------------
130 single_send <= send WHEN valid_burst = '0' ELSE '0';
131 burst_send <= send WHEN valid_burst = '1' ELSE '0';
131 -- \/ -- 20/02/2014 -- JC Pellion
132 PROCESS (HCLK, HRESETn)
133 BEGIN
134 IF HRESETn = '0' THEN
135 send_reg <= '0';
136 ELSIF HCLK'event AND HCLK = '1' THEN
137 send_reg <= send;
138 END IF;
139 END PROCESS;
140 send_s <= send_reg;
141
142 single_send <= send_s WHEN valid_burst = '0' ELSE '0';
143 burst_send <= send_s WHEN valid_burst = '1' ELSE '0';
144 -- /\ --
145
132 146 DMAIn <= single_dmai WHEN valid_burst = '0' ELSE burst_dmai;
133 147
134 148 -- TODO : verifier
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@@ -29,6 +29,8 ENTITY CY7C1061DV33 IS
29 29 DATA_BITS : INTEGER := 16;
30 30 depth : INTEGER := 1048576;
31 31
32 MEM_ARRAY_DEBUG : INTEGER := 32;
33
32 34 TimingInfo : BOOLEAN := true;
33 35 TimingChecks : STD_LOGIC := '1'
34 36 );
@@ -68,7 +70,7 ARCHITECTURE behave_arch OF CY7C1061DV33
68 70 CONSTANT tskew : TIME := 1 ns;
69 71
70 72 -------------------------------------------------------------------------------JC\/
71 TYPE mem_array_type_t IS ARRAY (31 DOWNTO 0) OF STD_LOGIC_VECTOR(DATA_BITS-1 DOWNTO 0);
73 TYPE mem_array_type_t IS ARRAY (MEM_ARRAY_DEBUG-1 DOWNTO 0) OF STD_LOGIC_VECTOR(DATA_BITS-1 DOWNTO 0);
72 74 SIGNAL mem_array_0 : mem_array_type_t;
73 75 SIGNAL mem_array_1 : mem_array_type_t;
74 76 SIGNAL mem_array_2 : mem_array_type_t;
@@ -236,7 +238,7 BEGIN
236 238
237 239
238 240 -------------------------------------------------------------------------------JC\/
239 all_mem_array_obs: FOR I IN 0 TO 31 LOOP
241 all_mem_array_obs: FOR I IN 0 TO MEM_ARRAY_DEBUG-1 LOOP
240 242 IF I + ((2**15) *0) < depth THEN mem_array_0(I) <= mem_array(I+((2**15) *0)); END IF;
241 243 IF I + ((2**15) *1) < depth THEN mem_array_1(I) <= mem_array(I+((2**15) *1)); END IF;
242 244 IF I + ((2**15) *2) < depth THEN mem_array_2(I) <= mem_array(I+((2**15) *2)); END IF;
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