@@ -1,23 +1,23 | |||
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1 | 1 | vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_pkg.vhd |
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2 | 2 | vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/fifo_latency_correction.vhd |
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3 | 3 | vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma.vhd |
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4 | 4 | vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_ip.vhd |
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5 | 5 | vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_send_16word.vhd |
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6 | 6 | vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_send_1word.vhd |
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7 | 7 | vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_singleOrBurst.vhd |
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8 | 8 | |
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9 | 9 | vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_snapshot.vhd |
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10 | 10 | |
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11 | 11 | vcom -quiet -93 -work lpp ../../lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/RAM_CEL_N.vhd |
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12 | 12 | |
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13 | 13 | vcom -quiet -93 -work lpp testbench_package.vhd |
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14 | 14 | |
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15 | 15 | vcom -quiet -93 -work work tb_waveform.vhd |
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16 | 16 | |
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17 | 17 | vsim work.testbench |
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18 | 18 | |
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19 | 19 | log -r * |
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20 | 20 | |
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21 | 21 | do wave_waveform_longsim.do |
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22 | 22 | |
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23 |
run |
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23 | run 40 ms |
@@ -1,591 +1,616 | |||
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1 | 1 | ------------------------------------------------------------------------------ |
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2 | 2 | -- LEON3 Demonstration design test bench |
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3 | 3 | -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research |
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4 | 4 | ------------------------------------------------------------------------------ |
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5 | 5 | -- This file is a part of the GRLIB VHDL IP LIBRARY |
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6 | 6 | -- Copyright (C) 2013, Aeroflex Gaisler AB - all rights reserved. |
|
7 | 7 | -- |
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8 | 8 | -- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN |
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9 | 9 | -- ACCORDANCE WITH THE GAISLER LICENSE AGREEMENT AND MUST BE APPROVED |
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10 | 10 | -- IN ADVANCE IN WRITING. |
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11 | 11 | ------------------------------------------------------------------------------ |
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12 | 12 | |
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13 | 13 | LIBRARY ieee; |
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14 | 14 | USE ieee.std_logic_1164.ALL; |
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15 | 15 | |
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16 | 16 | --LIBRARY std; |
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17 | 17 | --USE std.textio.ALL; |
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18 | 18 | |
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19 | 19 | LIBRARY grlib; |
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20 | 20 | USE grlib.amba.ALL; |
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21 | 21 | USE grlib.stdlib.ALL; |
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22 | USE grlib.AMBA_TestPackage.ALL; | |
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22 | 23 | LIBRARY gaisler; |
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23 | 24 | USE gaisler.memctrl.ALL; |
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24 | 25 | USE gaisler.leon3.ALL; |
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25 | 26 | USE gaisler.uart.ALL; |
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26 | 27 | USE gaisler.misc.ALL; |
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27 | 28 | USE gaisler.libdcom.ALL; |
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28 | 29 | USE gaisler.sim.ALL; |
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29 | 30 | USE gaisler.jtagtst.ALL; |
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30 | 31 | USE gaisler.misc.ALL; |
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31 | 32 | LIBRARY techmap; |
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32 | 33 | USE techmap.gencomp.ALL; |
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33 | 34 | LIBRARY esa; |
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34 | 35 | USE esa.memoryctrl.ALL; |
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35 | 36 | --LIBRARY micron; |
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36 | 37 | --USE micron.components.ALL; |
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37 | 38 | LIBRARY lpp; |
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38 | 39 | USE lpp.lpp_waveform_pkg.ALL; |
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39 | 40 | USE lpp.lpp_memory.ALL; |
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40 | 41 | USE lpp.lpp_ad_conv.ALL; |
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41 | 42 | USE lpp.testbench_package.ALL; |
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42 | 43 | USE lpp.lpp_lfr_pkg.ALL; |
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43 | 44 | USE lpp.iir_filter.ALL; |
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44 | 45 | USE lpp.general_purpose.ALL; |
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45 | 46 | USE lpp.CY7C1061DV33_pkg.ALL; |
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46 | 47 | |
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47 | 48 | ENTITY testbench IS |
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48 | 49 | END; |
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49 | 50 | |
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50 | 51 | ARCHITECTURE behav OF testbench IS |
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51 | 52 | -- REG ADDRESS |
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52 | 53 | CONSTANT INDEX_WAVEFORM_PICKER : INTEGER := 15; |
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53 | 54 | CONSTANT ADDR_WAVEFORM_PICKER : INTEGER := 15; |
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54 | 55 | CONSTANT ADDR_WAVEFORM_PICKER_DATASHAPING : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F20"; |
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55 | 56 | CONSTANT ADDR_WAVEFORM_PICKER_CONTROL : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F24"; |
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56 | 57 | CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F28"; |
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57 | 58 | CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F2C"; |
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58 | 59 | CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F30"; |
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59 | 60 | CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F3 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F34"; |
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60 | 61 | CONSTANT ADDR_WAVEFORM_PICKER_STATUS : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F38"; |
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61 | 62 | CONSTANT ADDR_WAVEFORM_PICKER_DELTASNAPSHOT : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F3C"; |
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62 | 63 | CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F40"; |
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63 | 64 | CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F0_2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F44"; |
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64 | 65 | CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F48"; |
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65 | 66 | CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F4C"; |
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66 | 67 | CONSTANT ADDR_WAVEFORM_PICKER_NB_DATA_IN_BUFFER : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F50"; |
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67 | 68 | CONSTANT ADDR_WAVEFORM_PICKER_NBSNAPSHOT : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F54"; |
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68 | 69 | CONSTANT ADDR_WAVEFORM_PICKER_START_DATE : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F58"; |
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69 | 70 | CONSTANT ADDR_WAVEFORM_PICKER_NB_WORD_IN_BUFFER : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F5C"; |
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70 | 71 | -- RAM ADDRESS |
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71 | 72 | CONSTANT AHB_RAM_ADDR_0 : INTEGER := 16#100#; |
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72 | 73 | CONSTANT AHB_RAM_ADDR_1 : INTEGER := 16#200#; |
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73 | 74 | CONSTANT AHB_RAM_ADDR_2 : INTEGER := 16#300#; |
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74 | 75 | CONSTANT AHB_RAM_ADDR_3 : INTEGER := 16#400#; |
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75 | 76 | |
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76 | 77 | |
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77 | 78 | -- Common signal |
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78 | 79 | SIGNAL clk49_152MHz : STD_LOGIC := '0'; |
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79 | 80 | SIGNAL clk25MHz : STD_LOGIC := '0'; |
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80 | 81 | SIGNAL rstn : STD_LOGIC := '0'; |
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81 | 82 | |
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82 | 83 | -- ADC interface |
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83 | 84 | SIGNAL ADC_OEB_bar_CH : STD_LOGIC_VECTOR(7 DOWNTO 0); -- OUT |
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84 | 85 | SIGNAL ADC_smpclk : STD_LOGIC; -- OUT |
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85 | 86 | SIGNAL ADC_data : STD_LOGIC_VECTOR(13 DOWNTO 0); -- IN |
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86 | 87 | |
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87 | 88 | -- AD Converter RHF1401 |
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88 | 89 | SIGNAL sample : Samples14v(7 DOWNTO 0); |
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89 | 90 | SIGNAL sample_val : STD_LOGIC; |
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90 | 91 | |
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91 | 92 | -- AHB/APB SIGNAL |
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92 | 93 | SIGNAL apbi : apb_slv_in_type; |
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93 | 94 | SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none); |
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94 | 95 | SIGNAL ahbsi : ahb_slv_in_type; |
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95 | 96 | SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none); |
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96 | 97 | SIGNAL ahbmi : ahb_mst_in_type; |
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97 | 98 | SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none); |
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98 | 99 | |
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99 | 100 | SIGNAL bias_fail_bw : STD_LOGIC; |
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100 | 101 | |
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101 | 102 | ----------------------------------------------------------------------------- |
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102 | 103 | -- LPP_WAVEFORM |
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103 | 104 | ----------------------------------------------------------------------------- |
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104 | 105 | CONSTANT data_size : INTEGER := 96; |
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105 | 106 | CONSTANT nb_burst_available_size : INTEGER := 50; |
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106 | 107 | CONSTANT nb_snapshot_param_size : INTEGER := 2; |
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107 | 108 | CONSTANT delta_vector_size : INTEGER := 2; |
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108 | 109 | CONSTANT delta_vector_size_f0_2 : INTEGER := 2; |
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109 | 110 | |
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110 | 111 | SIGNAL reg_run : STD_LOGIC; |
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111 | 112 | SIGNAL reg_start_date : STD_LOGIC_VECTOR(30 DOWNTO 0); |
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112 | 113 | SIGNAL reg_delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
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113 | 114 | SIGNAL reg_delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
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114 | 115 | SIGNAL reg_delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); |
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115 | 116 | SIGNAL reg_delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
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116 | 117 | SIGNAL reg_delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
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117 | 118 | SIGNAL enable_f0 : STD_LOGIC; |
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118 | 119 | SIGNAL enable_f1 : STD_LOGIC; |
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119 | 120 | SIGNAL enable_f2 : STD_LOGIC; |
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120 | 121 | SIGNAL enable_f3 : STD_LOGIC; |
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121 | 122 | SIGNAL burst_f0 : STD_LOGIC; |
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122 | 123 | SIGNAL burst_f1 : STD_LOGIC; |
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123 | 124 | SIGNAL burst_f2 : STD_LOGIC; |
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124 | 125 | SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); |
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125 | 126 | SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); |
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126 | 127 | SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); |
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127 | 128 | SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0); |
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128 | 129 | SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); |
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129 | 130 | SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); |
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130 | 131 | SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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131 | 132 | SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); |
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132 | 133 | SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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133 | 134 | SIGNAL data_f0_in_valid : STD_LOGIC; |
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134 | 135 | SIGNAL data_f0_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
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135 | 136 | SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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136 | 137 | SIGNAL data_f1_in_valid : STD_LOGIC; |
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137 | 138 | SIGNAL data_f1_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
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138 | 139 | SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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139 | 140 | SIGNAL data_f2_in_valid : STD_LOGIC; |
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140 | 141 | SIGNAL data_f2_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
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141 | 142 | SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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142 | 143 | SIGNAL data_f3_in_valid : STD_LOGIC; |
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143 | 144 | SIGNAL data_f3_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
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144 | 145 | SIGNAL data_f0_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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145 | 146 | SIGNAL data_f0_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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146 | 147 | SIGNAL data_f0_data_out_valid : STD_LOGIC; |
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147 | 148 | SIGNAL data_f0_data_out_valid_burst : STD_LOGIC; |
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148 | 149 | SIGNAL data_f0_data_out_ack : STD_LOGIC; |
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149 | 150 | SIGNAL data_f1_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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150 | 151 | SIGNAL data_f1_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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151 | 152 | SIGNAL data_f1_data_out_valid : STD_LOGIC; |
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152 | 153 | SIGNAL data_f1_data_out_valid_burst : STD_LOGIC; |
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153 | 154 | SIGNAL data_f1_data_out_ack : STD_LOGIC; |
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154 | 155 | SIGNAL data_f2_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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155 | 156 | SIGNAL data_f2_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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156 | 157 | SIGNAL data_f2_data_out_valid : STD_LOGIC; |
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157 | 158 | SIGNAL data_f2_data_out_valid_burst : STD_LOGIC; |
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158 | 159 | SIGNAL data_f2_data_out_ack : STD_LOGIC; |
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159 | 160 | SIGNAL data_f3_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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160 | 161 | SIGNAL data_f3_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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161 | 162 | SIGNAL data_f3_data_out_valid : STD_LOGIC; |
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162 | 163 | SIGNAL data_f3_data_out_valid_burst : STD_LOGIC; |
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163 | 164 | SIGNAL data_f3_data_out_ack : STD_LOGIC; |
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164 | 165 | |
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165 | 166 | --MEM CTRLR |
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166 | 167 | SIGNAL memi : memory_in_type; |
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167 | 168 | SIGNAL memo : memory_out_type; |
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168 | 169 | SIGNAL wpo : wprot_out_type; |
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169 | 170 | SIGNAL sdo : sdram_out_type; |
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170 | 171 | |
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171 | 172 | SIGNAL address : STD_LOGIC_VECTOR(19 DOWNTO 0); |
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172 | 173 | SIGNAL data : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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173 | 174 | SIGNAL nSRAM_BE0 : STD_LOGIC; |
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174 | 175 | SIGNAL nSRAM_BE1 : STD_LOGIC; |
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175 | 176 | SIGNAL nSRAM_BE2 : STD_LOGIC; |
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176 | 177 | SIGNAL nSRAM_BE3 : STD_LOGIC; |
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177 | 178 | SIGNAL nSRAM_WE : STD_LOGIC; |
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178 | 179 | SIGNAL nSRAM_CE : STD_LOGIC; |
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179 | 180 | SIGNAL nSRAM_OE : STD_LOGIC; |
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180 | 181 | |
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181 | 182 | CONSTANT padtech : INTEGER := inferred; |
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182 | 183 | SIGNAL not_ramsn_0 : STD_LOGIC; |
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183 | 184 | |
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184 | 185 | ----------------------------------------------------------------------------- |
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185 | 186 | SIGNAL status : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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186 | 187 | SIGNAL read_buffer : STD_LOGIC; |
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187 | 188 | ----------------------------------------------------------------------------- |
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188 | 189 | SIGNAL run_test_waveform_picker : STD_LOGIC := '1'; |
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189 | 190 | SIGNAL state_read_buffer_on_going : STD_LOGIC; |
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190 | 191 | CONSTANT hindex : INTEGER := 1; |
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191 | 192 | SIGNAL time_mem_f0 : STD_LOGIC_VECTOR(63 DOWNTO 0); |
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192 | 193 | SIGNAL time_mem_f1 : STD_LOGIC_VECTOR(63 DOWNTO 0); |
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193 | 194 | SIGNAL time_mem_f2 : STD_LOGIC_VECTOR(63 DOWNTO 0); |
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194 | 195 | SIGNAL time_mem_f3 : STD_LOGIC_VECTOR(63 DOWNTO 0); |
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195 | 196 | |
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196 | 197 | SIGNAL data_mem_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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197 | 198 | SIGNAL data_mem_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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198 | 199 | SIGNAL data_mem_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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199 | 200 | SIGNAL data_mem_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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200 | 201 | |
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201 | 202 | SIGNAL data_0_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
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202 | 203 | SIGNAL data_0_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
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203 | 204 | SIGNAL data_0_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
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204 | 205 | |
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205 | 206 | SIGNAL data_1_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
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206 | 207 | SIGNAL data_1_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
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207 | 208 | SIGNAL data_1_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
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208 | 209 | |
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209 | 210 | SIGNAL data_2_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
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210 | 211 | SIGNAL data_2_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
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211 | 212 | SIGNAL data_2_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
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212 | 213 | |
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213 | 214 | SIGNAL data_3_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
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214 | 215 | SIGNAL data_3_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
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215 | 216 | SIGNAL data_3_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
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216 | 217 | |
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217 | 218 | SIGNAL data_4_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
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218 | 219 | SIGNAL data_4_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
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219 | 220 | SIGNAL data_4_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
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220 | 221 | |
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221 | 222 | SIGNAL data_5_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
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222 | 223 | SIGNAL data_5_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
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223 | 224 | SIGNAL data_5_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
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224 | 225 | ----------------------------------------------------------------------------- |
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225 | 226 | |
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226 | 227 | SIGNAL current_data : INTEGER; |
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227 |
SIGNAL LIMIT_DATA : INTEGER := |
|
|
228 | SIGNAL LIMIT_DATA : INTEGER := 64; | |
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228 | 229 | |
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229 | 230 | SIGNAL read_buffer_temp : STD_LOGIC; |
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230 | 231 | SIGNAL read_buffer_temp_2 : STD_LOGIC; |
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231 | 232 | |
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232 | 233 | |
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233 | 234 | BEGIN |
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234 | 235 | |
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235 | 236 | ----------------------------------------------------------------------------- |
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236 | 237 | |
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237 | 238 | clk49_152MHz <= NOT clk49_152MHz AFTER 10173 ps; -- 49.152/2 MHz |
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238 | 239 | clk25MHz <= NOT clk25MHz AFTER 5 ns; -- 100 MHz |
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239 | 240 | |
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240 | 241 | ----------------------------------------------------------------------------- |
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241 | 242 | |
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242 | 243 | MODULE_RHF1401 : FOR I IN 0 TO 7 GENERATE |
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243 | 244 | TestModule_RHF1401_1 : TestModule_RHF1401 |
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244 | 245 | GENERIC MAP ( |
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245 | 246 | freq => 24*(I+1), |
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246 | 247 | amplitude => 8000/(I+1), |
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247 | 248 | impulsion => 0) |
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248 | 249 | PORT MAP ( |
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249 | 250 | ADC_smpclk => ADC_smpclk, |
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250 | 251 | ADC_OEB_bar => ADC_OEB_bar_CH(I), |
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251 | 252 | ADC_data => ADC_data); |
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252 | 253 | END GENERATE MODULE_RHF1401; |
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253 | 254 | |
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254 | 255 | ----------------------------------------------------------------------------- |
|
255 | 256 | |
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256 | 257 | top_ad_conv_RHF1401_1 : top_ad_conv_RHF1401 |
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257 | 258 | GENERIC MAP ( |
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258 | 259 | ChanelCount => 8, |
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259 | 260 | ncycle_cnv_high => 79, |
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260 | 261 | ncycle_cnv => 500) |
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261 | 262 | PORT MAP ( |
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262 | 263 | cnv_clk => clk49_152MHz, |
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263 | 264 | cnv_rstn => rstn, |
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264 | 265 | cnv => ADC_smpclk, |
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265 | 266 | clk => clk25MHz, |
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266 | 267 | rstn => rstn, |
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267 | 268 | ADC_data => ADC_data, |
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268 | 269 | ADC_nOE => ADC_OEB_bar_CH, |
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269 | 270 | sample => sample, |
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270 | 271 | sample_val => sample_val); |
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271 | 272 | |
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272 | 273 | ----------------------------------------------------------------------------- |
|
273 | 274 | |
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274 | 275 | lpp_lfr_1 : lpp_lfr |
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275 | 276 | GENERIC MAP ( |
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276 | 277 | Mem_use => use_CEL, -- use_RAM |
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277 | 278 | nb_data_by_buffer_size => 32, |
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278 | 279 | nb_word_by_buffer_size => 30, |
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279 | 280 | nb_snapshot_param_size => 32, |
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280 | 281 | delta_vector_size => 32, |
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281 | 282 | delta_vector_size_f0_2 => 32, |
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282 | 283 | pindex => INDEX_WAVEFORM_PICKER, |
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283 | 284 | paddr => ADDR_WAVEFORM_PICKER, |
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284 | 285 | pmask => 16#fff#, |
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285 | 286 | pirq_ms => 6, |
|
286 | 287 | pirq_wfp => 14, |
|
287 | 288 | hindex => 0, |
|
288 | 289 | top_lfr_version => X"000001") |
|
289 | 290 | PORT MAP ( |
|
290 | 291 | clk => clk25MHz, |
|
291 | 292 | rstn => rstn, |
|
292 | 293 | sample_B => sample(2 DOWNTO 0), |
|
293 | 294 | sample_E => sample(7 DOWNTO 3), |
|
294 | 295 | sample_val => sample_val, |
|
295 | 296 | apbi => apbi, |
|
296 | 297 | apbo => apbo(15), |
|
297 | 298 | ahbi => ahbmi, |
|
298 | 299 | ahbo => ahbmo(0), |
|
299 | 300 | coarse_time => coarse_time, |
|
300 | 301 | fine_time => fine_time, |
|
301 | 302 | data_shaping_BW => bias_fail_bw); |
|
302 | 303 | |
|
303 | 304 | ----------------------------------------------------------------------------- |
|
304 | 305 | --- AHB CONTROLLER ------------------------------------------------- |
|
305 | 306 | ahb0 : ahbctrl -- AHB arbiter/multiplexer |
|
306 | 307 | GENERIC MAP (defmast => 0, split => 0, |
|
307 | 308 | rrobin => 1, ioaddr => 16#FFF#, |
|
308 | 309 | ioen => 0, nahbm => 2, nahbs => 1) |
|
309 | 310 | PORT MAP (rstn, clk25MHz, ahbmi, ahbmo, ahbsi, ahbso); |
|
310 | 311 | |
|
311 | 312 | --- AHB RAM ---------------------------------------------------------- |
|
312 | 313 | --ahbram0 : ahbram |
|
313 | 314 | -- GENERIC MAP (hindex => 0, haddr => AHB_RAM_ADDR_0, tech => inferred, kbytes => 1, pipe => 0) |
|
314 | 315 | -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(0)); |
|
315 | 316 | --ahbram1 : ahbram |
|
316 | 317 | -- GENERIC MAP (hindex => 1, haddr => AHB_RAM_ADDR_1, tech => inferred, kbytes => 1, pipe => 0) |
|
317 | 318 | -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(1)); |
|
318 | 319 | --ahbram2 : ahbram |
|
319 | 320 | -- GENERIC MAP (hindex => 2, haddr => AHB_RAM_ADDR_2, tech => inferred, kbytes => 1, pipe => 0) |
|
320 | 321 | -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(2)); |
|
321 | 322 | --ahbram3 : ahbram |
|
322 | 323 | -- GENERIC MAP (hindex => 3, haddr => AHB_RAM_ADDR_3, tech => inferred, kbytes => 1, pipe => 0) |
|
323 | 324 | -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(3)); |
|
324 | 325 | |
|
325 | 326 | ----------------------------------------------------------------------------- |
|
326 | 327 | ---------------------------------------------------------------------- |
|
327 | 328 | --- Memory controllers --------------------------------------------- |
|
328 | 329 | ---------------------------------------------------------------------- |
|
329 | 330 | memctrlr : mctrl GENERIC MAP ( |
|
330 | 331 | hindex => 0, |
|
331 | 332 | pindex => 0, |
|
332 | 333 | paddr => 0, |
|
333 | 334 | srbanks => 1 |
|
334 | 335 | ) |
|
335 | 336 | PORT MAP (rstn, clk25MHz, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo); |
|
336 | 337 | |
|
337 | 338 | memi.brdyn <= '1'; |
|
338 | 339 | memi.bexcn <= '1'; |
|
339 | 340 | memi.writen <= '1'; |
|
340 | 341 | memi.wrn <= "1111"; |
|
341 | 342 | memi.bwidth <= "10"; |
|
342 | 343 | |
|
343 | 344 | bdr : FOR i IN 0 TO 3 GENERATE |
|
344 | 345 | data_pad : iopadv GENERIC MAP (tech => padtech, width => 8) |
|
345 | 346 | PORT MAP ( |
|
346 | 347 | data(31-i*8 DOWNTO 24-i*8), |
|
347 | 348 | memo.data(31-i*8 DOWNTO 24-i*8), |
|
348 | 349 | memo.bdrive(i), |
|
349 | 350 | memi.data(31-i*8 DOWNTO 24-i*8)); |
|
350 | 351 | END GENERATE; |
|
351 | 352 | |
|
352 | 353 | addr_pad : outpadv GENERIC MAP (width => 20, tech => padtech) |
|
353 | 354 | PORT MAP (address, memo.address(21 DOWNTO 2)); |
|
354 | 355 | |
|
355 | 356 | not_ramsn_0 <= NOT(memo.ramsn(0)); |
|
356 | 357 | |
|
357 | 358 | rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, not_ramsn_0); |
|
358 | 359 | oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0)); |
|
359 | 360 | nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen); |
|
360 | 361 | nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3)); |
|
361 | 362 | nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2)); |
|
362 | 363 | nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1)); |
|
363 | 364 | nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0)); |
|
364 | 365 | |
|
365 | 366 | async_1Mx16_0: CY7C1061DV33 |
|
366 | 367 | GENERIC MAP ( |
|
367 | 368 | ADDR_BITS => 20, |
|
368 | 369 | DATA_BITS => 16, |
|
369 | 370 | depth => 1048576, |
|
371 | MEM_ARRAY_DEBUG => 194, | |
|
370 | 372 | TimingInfo => TRUE, |
|
371 | 373 | TimingChecks => '1') |
|
372 | 374 | PORT MAP ( |
|
373 | 375 | CE1_b => '0', |
|
374 | 376 | CE2 => nSRAM_CE, |
|
375 | 377 | WE_b => nSRAM_WE, |
|
376 | 378 | OE_b => nSRAM_OE, |
|
377 | 379 | BHE_b => nSRAM_BE1, |
|
378 | 380 | BLE_b => nSRAM_BE0, |
|
379 | 381 | A => address, |
|
380 | 382 | DQ => data(15 DOWNTO 0)); |
|
381 | 383 | |
|
382 | 384 | async_1Mx16_1: CY7C1061DV33 |
|
383 | 385 | GENERIC MAP ( |
|
384 | 386 | ADDR_BITS => 20, |
|
385 | 387 | DATA_BITS => 16, |
|
386 | 388 | depth => 1048576, |
|
389 | MEM_ARRAY_DEBUG => 194, | |
|
387 | 390 | TimingInfo => TRUE, |
|
388 | 391 | TimingChecks => '1') |
|
389 | 392 | PORT MAP ( |
|
390 | 393 | CE1_b => '0', |
|
391 | 394 | CE2 => nSRAM_CE, |
|
392 | 395 | WE_b => nSRAM_WE, |
|
393 | 396 | OE_b => nSRAM_OE, |
|
394 | 397 | BHE_b => nSRAM_BE3, |
|
395 | 398 | BLE_b => nSRAM_BE2, |
|
396 | 399 | A => address, |
|
397 | 400 | DQ => data(31 DOWNTO 16)); |
|
398 | 401 | |
|
399 | 402 | |
|
400 | 403 | |
|
401 | 404 | ----------------------------------------------------------------------------- |
|
402 | 405 | |
|
403 | 406 | WaveGen_Proc : PROCESS |
|
404 | 407 | BEGIN |
|
405 | 408 | |
|
406 | 409 | -- insert signal assignments here |
|
407 | 410 | WAIT UNTIL clk25MHz = '1'; |
|
408 | 411 | rstn <= '0'; |
|
409 | 412 | apbi.psel(15) <= '0'; |
|
410 | 413 | apbi.pwrite <= '0'; |
|
411 | 414 | apbi.penable <= '0'; |
|
412 | 415 | apbi.paddr <= (OTHERS => '0'); |
|
413 | 416 | apbi.pwdata <= (OTHERS => '0'); |
|
414 | 417 | fine_time <= (OTHERS => '0'); |
|
415 | 418 | coarse_time <= (OTHERS => '0'); |
|
416 | 419 | WAIT UNTIL clk25MHz = '1'; |
|
417 | 420 | -- ahbmi.HGRANT(2) <= '1'; |
|
418 | 421 | -- ahbmi.HREADY <= '1'; |
|
419 | 422 | -- ahbmi.HRESP <= HRESP_OKAY; |
|
420 | 423 | |
|
421 | 424 | WAIT UNTIL clk25MHz = '1'; |
|
422 | 425 | WAIT UNTIL clk25MHz = '1'; |
|
423 | 426 | rstn <= '1'; |
|
424 | 427 | WAIT UNTIL clk25MHz = '1'; |
|
425 | 428 | WAIT UNTIL clk25MHz = '1'; |
|
426 | 429 | --------------------------------------------------------------------------- |
|
427 | 430 | -- CONFIGURATION STEP |
|
428 | 431 | APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F0 , X"40000000"); |
|
429 | 432 | APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F1 , X"40020000"); |
|
430 | 433 | APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F2 , X"40040000"); |
|
431 | 434 | APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F3 , X"40060000"); |
|
432 | 435 | |
|
433 | APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTASNAPSHOT, X"00000080");--"00000020" | |
|
434 | APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F0 , X"00000060");--"00000019" | |
|
435 | APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F0_2 , X"00000007");--"00000007" | |
|
436 | APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F1 , X"00000062");--"00000019" | |
|
437 | APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F2 , X"00000001");--"00000001" | |
|
438 | ||
|
436 | APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTASNAPSHOT , X"00000080");--"00000020" | |
|
437 | APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F0 , X"00000060");--"00000019" | |
|
438 | APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F0_2 , X"00000007");--"00000007" | |
|
439 | APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F1 , X"00000062");--"00000019" | |
|
440 | APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F2 , X"00000001");--"00000001" | |
|
439 | 441 | APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_NB_DATA_IN_BUFFER , X"0000003f"); -- X"00000010" |
|
440 | 442 | APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_NBSNAPSHOT , X"00000040"); |
|
441 | 443 | APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_START_DATE , X"00000001"); |
|
442 |
APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_NB_WORD_IN_BUFFER , X"000000 |
|
|
444 | APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_NB_WORD_IN_BUFFER , X"000000C2");-- 0xC2 = 64 * 3 + 2 | |
|
445 | ||
|
446 | --APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTASNAPSHOT , X"00000010");--"00000020" | |
|
447 | --APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F0 , X"0000000C");--"00000019" | |
|
448 | --APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F0_2 , X"00000007");--"00000007" | |
|
449 | --APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F1 , X"0000000C");--"00000019" | |
|
450 | --APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F2 , X"00000001");--"00000001" | |
|
451 | --APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_NB_DATA_IN_BUFFER , X"00000007"); -- X"00000010" | |
|
452 | --APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_NBSNAPSHOT , X"00000008"); | |
|
453 | --APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_START_DATE , X"00000001"); | |
|
454 | --APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_NB_WORD_IN_BUFFER , X"0000001A");-- 0xC2 = 8 * 3 + 2 | |
|
455 | ||
|
443 | 456 | |
|
444 | 457 | |
|
445 | 458 | WAIT UNTIL clk25MHz = '1'; |
|
446 | 459 | WAIT UNTIL clk25MHz = '1'; |
|
447 | 460 | APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000087"); |
|
448 | 461 | WAIT UNTIL clk25MHz = '1'; |
|
449 | 462 | WAIT UNTIL clk25MHz = '1'; |
|
450 | 463 | WAIT UNTIL clk25MHz = '1'; |
|
451 | 464 | WAIT UNTIL clk25MHz = '1'; |
|
452 | 465 | WAIT UNTIL clk25MHz = '1'; |
|
453 | 466 | WAIT UNTIL clk25MHz = '1'; |
|
454 | 467 | WAIT FOR 1 us; |
|
455 | 468 | coarse_time <= X"00000001"; |
|
456 | 469 | |
|
457 | 470 | WAIT UNTIL clk25MHz = '1'; |
|
458 | 471 | |
|
459 | 472 | while_loop: WHILE run_test_waveform_picker = '1' LOOP |
|
460 | 473 | WAIT UNTIL apbo(INDEX_WAVEFORM_PICKER).pirq(14) = '1'; |
|
461 | 474 | APB_READ(clk25MHz,INDEX_WAVEFORM_PICKER,apbi,apbo(INDEX_WAVEFORM_PICKER),ADDR_WAVEFORM_PICKER_STATUS,status); |
|
462 | 475 | |
|
463 | 476 | IF status(2 DOWNTO 0) = "111" THEN |
|
464 | 477 | APB_WRITE(clk25MHz,INDEX_WAVEFORM_PICKER,apbi,ADDR_WAVEFORM_PICKER_STATUS,X"00000000"); |
|
465 | 478 | END IF; |
|
466 | 479 | WAIT UNTIL clk25MHz = '1'; |
|
467 | 480 | END LOOP while_loop; |
|
468 | 481 | |
|
469 | 482 | |
|
470 | 483 | --------------------------------------------------------------------------- |
|
471 | 484 | -- RUN STEP |
|
472 | 485 | WAIT FOR 20000 ms; |
|
473 | 486 | REPORT "*** END simulation ***" SEVERITY failure; |
|
474 | 487 | --APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000000"); |
|
475 | 488 | --APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_START_DATE, X"00000010"); |
|
476 | 489 | --WAIT FOR 10 us; |
|
477 | 490 | --WAIT UNTIL clk25MHz = '1'; |
|
478 | 491 | --WAIT UNTIL clk25MHz = '1'; |
|
479 | 492 | --APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"000000FF"); |
|
480 | 493 | --WAIT UNTIL clk25MHz = '1'; |
|
481 | 494 | --coarse_time <= X"00000010"; |
|
482 | 495 | --WAIT FOR 100 ms; |
|
483 | 496 | --APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000000"); |
|
484 | 497 | --WAIT FOR 10 us; |
|
485 | 498 | --APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"000000AF"); |
|
486 | 499 | --WAIT FOR 200 ms; |
|
487 | 500 | --REPORT "*** END simulation ***" SEVERITY failure; |
|
488 | 501 | |
|
489 | 502 | |
|
490 | 503 | |
|
491 | 504 | WAIT; |
|
492 | 505 | |
|
493 | 506 | END PROCESS WaveGen_Proc; |
|
494 | 507 | ----------------------------------------------------------------------------- |
|
495 | 508 | |
|
496 | 509 | read_buffer_temp <= '1' WHEN status(2 DOWNTO 0) = "111" ELSE '0'; |
|
497 | 510 | PROCESS (clk25MHz, rstn) |
|
498 | 511 | BEGIN -- PROCESS |
|
499 | 512 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
500 | 513 | read_buffer <= '0'; |
|
501 | 514 | read_buffer_temp_2 <= '0'; |
|
502 | 515 | ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge |
|
503 | 516 | read_buffer_temp_2 <= read_buffer_temp; |
|
504 | 517 | read_buffer <= read_buffer_temp AND NOT read_buffer_temp_2; |
|
505 | 518 | END IF; |
|
506 | 519 | END PROCESS; |
|
507 | 520 | |
|
508 | 521 | ----------------------------------------------------------------------------- |
|
509 | 522 | -- IRQ |
|
510 | 523 | ----------------------------------------------------------------------------- |
|
511 | 524 | PROCESS |
|
512 | 525 | BEGIN -- PROCESS |
|
513 | 526 | state_read_buffer_on_going <= '0'; |
|
514 | 527 | current_data <= 0; |
|
515 | 528 | time_mem_f0 <= (OTHERS => '0'); |
|
516 | 529 | time_mem_f1 <= (OTHERS => '0'); |
|
517 | 530 | time_mem_f2 <= (OTHERS => '0'); |
|
518 | 531 | time_mem_f3 <= (OTHERS => '0'); |
|
519 | 532 | data_mem_f0 <= (OTHERS => '0'); |
|
520 | 533 | data_mem_f1 <= (OTHERS => '0'); |
|
521 | 534 | data_mem_f2 <= (OTHERS => '0'); |
|
522 | 535 | data_mem_f3 <= (OTHERS => '0'); |
|
523 | 536 | |
|
524 | 537 | while_loop2: WHILE run_test_waveform_picker = '1' LOOP |
|
525 | 538 | WAIT UNTIL clk25MHz = '1'; |
|
526 | 539 | IF read_buffer = '1' THEN |
|
527 | 540 | state_read_buffer_on_going <= '1'; |
|
541 | ||
|
542 | --AHBRead(X"40000000",time_mem_f0(31 DOWNTO 0),clk25MHz, | |
|
543 | --constant Address: in Std_Logic_Vector(31 downto 0); | |
|
544 | --variable Data: out Std_Logic_Vector(31 downto 0); | |
|
545 | --signal HCLK: in Std_ULogic; | |
|
546 | ||
|
547 | --signal AHBIn: out AHB_Slv_In_Type; | |
|
548 | --signal AHBOut: in AHB_Slv_Out_Type; | |
|
549 | --variable TP: inout Boolean; | |
|
550 | --constant InstancePath: in String := "AHBRead"; | |
|
551 | --constant ScreenOutput: in Boolean := False; | |
|
552 | --constant cBack2Back: in Boolean := False; | |
|
553 | --constant HINDEX: in Integer := 0; | |
|
554 | --constant HMBINDEX: in Integer := 0); | |
|
528 | 555 | |
|
529 | 556 | AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40000000", time_mem_f0(31 DOWNTO 0)); |
|
530 | 557 | AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40020000", time_mem_f1(31 DOWNTO 0)); |
|
531 | 558 | AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40040000", time_mem_f2(31 DOWNTO 0)); |
|
532 | 559 | |
|
533 | 560 | AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40000004", time_mem_f0(63 DOWNTO 32)); |
|
534 | 561 | AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40020004", time_mem_f1(63 DOWNTO 32)); |
|
535 | 562 | AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40040004", time_mem_f2(63 DOWNTO 32)); |
|
536 | 563 | |
|
537 |
current_data <= |
|
|
564 | current_data <= 0; | |
|
538 | 565 | ELSE |
|
539 | 566 | IF state_read_buffer_on_going = '1' THEN |
|
540 | 567 | -- READ ALL DATA in memory |
|
541 | AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40000000" + current_data, data_mem_f0); | |
|
542 | AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40020000" + current_data, data_mem_f1); | |
|
543 | AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40040000" + current_data, data_mem_f2); | |
|
568 | AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40000000" + (current_data * 12) + 8, data_mem_f0); | |
|
569 | AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40020000" + (current_data * 12) + 8, data_mem_f1); | |
|
570 | AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40040000" + (current_data * 12) + 8, data_mem_f2); | |
|
544 | 571 | data_0_f0 <= data_mem_f0(15 DOWNTO 0); |
|
545 | 572 | data_1_f0 <= data_mem_f0(31 DOWNTO 16); |
|
546 | 573 | data_0_f1 <= data_mem_f1(15 DOWNTO 0); |
|
547 | 574 | data_1_f1 <= data_mem_f1(31 DOWNTO 16); |
|
548 | 575 | data_0_f2 <= data_mem_f2(15 DOWNTO 0); |
|
549 | 576 | data_1_f2 <= data_mem_f2(31 DOWNTO 16); |
|
550 | current_data <= current_data + 4; | |
|
551 | 577 | |
|
552 | AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40000000" + current_data, data_mem_f0); | |
|
553 | AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40020000" + current_data, data_mem_f1); | |
|
554 | AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40040000" + current_data, data_mem_f2); | |
|
578 | AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40000000" + (current_data * 12) + 4 + 8, data_mem_f0); | |
|
579 | AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40020000" + (current_data * 12) + 4 + 8, data_mem_f1); | |
|
580 | AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40040000" + (current_data * 12) + 4 + 8, data_mem_f2); | |
|
555 | 581 | data_2_f0 <= data_mem_f0(15 DOWNTO 0); |
|
556 | 582 | data_3_f0 <= data_mem_f0(31 DOWNTO 16); |
|
557 | 583 | data_2_f1 <= data_mem_f1(15 DOWNTO 0); |
|
558 | 584 | data_3_f1 <= data_mem_f1(31 DOWNTO 16); |
|
559 | 585 | data_2_f2 <= data_mem_f2(15 DOWNTO 0); |
|
560 | 586 | data_3_f2 <= data_mem_f2(31 DOWNTO 16); |
|
561 | current_data <= current_data + 4; | |
|
562 | 587 | |
|
563 | AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40000000" + current_data, data_mem_f0); | |
|
564 | AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40020000" + current_data, data_mem_f1); | |
|
565 | AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40040000" + current_data, data_mem_f2); | |
|
588 | AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40000000" + (current_data * 12) + 8 + 8, data_mem_f0); | |
|
589 | AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40020000" + (current_data * 12) + 8 + 8, data_mem_f1); | |
|
590 | AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40040000" + (current_data * 12) + 8 + 8, data_mem_f2); | |
|
566 | 591 | data_4_f0 <= data_mem_f0(15 DOWNTO 0); |
|
567 | 592 | data_5_f0 <= data_mem_f0(31 DOWNTO 16); |
|
568 | 593 | data_4_f1 <= data_mem_f1(15 DOWNTO 0); |
|
569 | 594 | data_5_f1 <= data_mem_f1(31 DOWNTO 16); |
|
570 | 595 | data_4_f2 <= data_mem_f2(15 DOWNTO 0); |
|
571 | 596 | data_5_f2 <= data_mem_f2(31 DOWNTO 16); |
|
572 |
current_data <= current_data + |
|
|
597 | current_data <= current_data + 1; | |
|
573 | 598 | |
|
574 | IF current_data > LIMIT_DATA THEN | |
|
599 | IF current_data >= LIMIT_DATA THEN | |
|
575 | 600 | state_read_buffer_on_going <= '0'; |
|
576 | 601 | time_mem_f0 <= (OTHERS => '0'); |
|
577 | 602 | time_mem_f1 <= (OTHERS => '0'); |
|
578 | 603 | time_mem_f2 <= (OTHERS => '0'); |
|
579 | 604 | time_mem_f3 <= (OTHERS => '0'); |
|
580 | 605 | data_mem_f0 <= (OTHERS => '0'); |
|
581 | 606 | data_mem_f1 <= (OTHERS => '0'); |
|
582 | 607 | data_mem_f2 <= (OTHERS => '0'); |
|
583 | 608 | data_mem_f3 <= (OTHERS => '0'); |
|
584 | 609 | END IF; |
|
585 | 610 | END IF; |
|
586 | 611 | END IF; |
|
587 | 612 | END LOOP while_loop2; |
|
588 | 613 | END PROCESS; |
|
589 | 614 | ----------------------------------------------------------------------------- |
|
590 | 615 | |
|
591 | 616 | END; |
@@ -1,120 +1,136 | |||
|
1 | ||
|
2 | LIBRARY ieee; | |
|
3 | USE ieee.std_logic_1164.ALL; | |
|
4 | LIBRARY grlib; | |
|
5 | USE grlib.amba.ALL; | |
|
6 | USE grlib.stdlib.ALL; | |
|
7 | --LIBRARY gaisler; | |
|
8 | --USE gaisler.libdcom.ALL; | |
|
9 | --USE gaisler.sim.ALL; | |
|
10 | --USE gaisler.jtagtst.ALL; | |
|
11 | --LIBRARY techmap; | |
|
12 | --USE techmap.gencomp.ALL; | |
|
13 | ||
|
14 | ||
|
15 | PACKAGE testbench_package IS | |
|
16 | ||
|
17 | PROCEDURE APB_WRITE ( | |
|
18 | SIGNAL clk : IN STD_LOGIC; | |
|
19 | CONSTANT pindex : IN INTEGER; | |
|
20 | SIGNAL apbi : OUT apb_slv_in_type; | |
|
21 | CONSTANT paddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
22 | CONSTANT pwdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0) | |
|
23 | ); | |
|
24 | ||
|
25 | PROCEDURE APB_READ ( | |
|
26 | SIGNAL clk : IN STD_LOGIC; | |
|
27 | CONSTANT pindex : IN INTEGER; | |
|
28 | SIGNAL apbi : OUT apb_slv_in_type; | |
|
29 | SIGNAL apbo : IN apb_slv_out_type; | |
|
30 | CONSTANT paddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
31 | SIGNAL prdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) | |
|
32 | ); | |
|
33 | ||
|
34 | PROCEDURE AHB_READ ( | |
|
35 | SIGNAL clk : IN STD_LOGIC; | |
|
36 | CONSTANT hindex : IN INTEGER; | |
|
37 | SIGNAL ahbmi : IN ahb_mst_in_type; | |
|
38 | SIGNAL ahbmo : OUT ahb_mst_out_type; | |
|
39 | CONSTANT haddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
40 | SIGNAL hrdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) | |
|
41 | ); | |
|
42 | ||
|
43 | END testbench_package; | |
|
44 | ||
|
45 | PACKAGE BODY testbench_package IS | |
|
46 | ||
|
47 | PROCEDURE APB_WRITE ( | |
|
48 | SIGNAL clk : IN STD_LOGIC; | |
|
49 | CONSTANT pindex : IN INTEGER; | |
|
50 | SIGNAL apbi : OUT apb_slv_in_type; | |
|
51 | CONSTANT paddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
52 | CONSTANT pwdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0) | |
|
53 | ) IS | |
|
54 | BEGIN | |
|
55 | apbi.psel(pindex) <= '1'; | |
|
56 | apbi.pwrite <= '1'; | |
|
57 | apbi.penable <= '1'; | |
|
58 | apbi.paddr <= paddr; | |
|
59 | apbi.pwdata <= pwdata; | |
|
60 |
WAIT UNTIL clk = ' |
|
|
61 | apbi.psel(pindex) <= '0'; | |
|
62 |
apbi.p |
|
|
63 |
apbi.p |
|
|
64 |
apbi.p |
|
|
65 |
apbi.p |
|
|
66 | WAIT UNTIL clk = '1'; | |
|
67 | ||
|
68 | END APB_WRITE; | |
|
69 | ||
|
70 | PROCEDURE APB_READ ( | |
|
71 | SIGNAL clk : IN STD_LOGIC; | |
|
72 | CONSTANT pindex : IN INTEGER; | |
|
73 | SIGNAL apbi : OUT apb_slv_in_type; | |
|
74 | SIGNAL apbo : IN apb_slv_out_type; | |
|
75 | CONSTANT paddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
76 | SIGNAL prdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) | |
|
77 | ) IS | |
|
78 | BEGIN | |
|
79 | apbi.psel(pindex) <= '1'; | |
|
80 | apbi.pwrite <= '0'; | |
|
81 |
apbi.p |
|
|
82 |
apbi.p |
|
|
83 | WAIT UNTIL clk = '1'; | |
|
84 | apbi.psel(pindex) <= '0'; | |
|
85 | apbi.pwrite <= '0'; | |
|
86 | apbi.penable <= '0'; | |
|
87 | apbi.paddr <= (OTHERS => '0'); | |
|
88 | WAIT UNTIL clk = '1'; | |
|
89 | prdata <= apbo.prdata; | |
|
90 | END APB_READ; | |
|
91 | ||
|
92 | PROCEDURE AHB_READ ( | |
|
93 | SIGNAL clk : IN STD_LOGIC; | |
|
94 | CONSTANT hindex : IN INTEGER; | |
|
95 | SIGNAL ahbmi : IN ahb_mst_in_type; | |
|
96 | SIGNAL ahbmo : OUT ahb_mst_out_type; | |
|
97 | CONSTANT haddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
98 | SIGNAL hrdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) | |
|
99 | ) IS | |
|
100 | BEGIN | |
|
101 | ahbmo.HADDR <= haddr; | |
|
102 | ahbmo.HPROT <= "0011"; | |
|
103 | ahbmo.HIRQ <= (OTHERS => '0'); | |
|
104 | ahbmo.HCONFIG <= (0 => (OTHERS => '0'), OTHERS => (OTHERS => '0')); | |
|
105 | ahbmo.HINDEX <= hindex; | |
|
106 |
ahbmo.H |
|
|
107 |
ahbmo.H |
|
|
108 |
ahbmo.H |
|
|
109 | ahbmo.HBURST <= HBURST_SINGLE; | |
|
110 | ahbmo.HTRANS <= HTRANS_NONSEQ; | |
|
111 |
ahbmo.H |
|
|
112 | WAIT UNTIL clk = '1' AND ahbmi.HREADY = '1' AND ahbmi.HGRANT(hindex) = '1'; | |
|
113 | hrdata <= ahbmi.HRDATA; | |
|
114 | WAIT UNTIL clk = '1' AND ahbmi.HREADY = '1' AND ahbmi.HGRANT(hindex) = '1'; | |
|
115 |
ahbmo.HTRANS <= HTRANS_ |
|
|
116 |
ahbmo.H |
|
|
117 | ahbmo.HLOCK <= '0'; | |
|
118 | END AHB_READ; | |
|
119 | ||
|
120 | END testbench_package; | |
|
1 | ||
|
2 | LIBRARY ieee; | |
|
3 | USE ieee.std_logic_1164.ALL; | |
|
4 | LIBRARY grlib; | |
|
5 | USE grlib.amba.ALL; | |
|
6 | USE grlib.stdlib.ALL; | |
|
7 | --LIBRARY gaisler; | |
|
8 | --USE gaisler.libdcom.ALL; | |
|
9 | --USE gaisler.sim.ALL; | |
|
10 | --USE gaisler.jtagtst.ALL; | |
|
11 | --LIBRARY techmap; | |
|
12 | --USE techmap.gencomp.ALL; | |
|
13 | ||
|
14 | ||
|
15 | PACKAGE testbench_package IS | |
|
16 | ||
|
17 | PROCEDURE APB_WRITE ( | |
|
18 | SIGNAL clk : IN STD_LOGIC; | |
|
19 | CONSTANT pindex : IN INTEGER; | |
|
20 | SIGNAL apbi : OUT apb_slv_in_type; | |
|
21 | CONSTANT paddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
22 | CONSTANT pwdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0) | |
|
23 | ); | |
|
24 | ||
|
25 | PROCEDURE APB_READ ( | |
|
26 | SIGNAL clk : IN STD_LOGIC; | |
|
27 | CONSTANT pindex : IN INTEGER; | |
|
28 | SIGNAL apbi : OUT apb_slv_in_type; | |
|
29 | SIGNAL apbo : IN apb_slv_out_type; | |
|
30 | CONSTANT paddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
31 | SIGNAL prdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) | |
|
32 | ); | |
|
33 | ||
|
34 | PROCEDURE AHB_READ ( | |
|
35 | SIGNAL clk : IN STD_LOGIC; | |
|
36 | CONSTANT hindex : IN INTEGER; | |
|
37 | SIGNAL ahbmi : IN ahb_mst_in_type; | |
|
38 | SIGNAL ahbmo : OUT ahb_mst_out_type; | |
|
39 | CONSTANT haddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
40 | SIGNAL hrdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) | |
|
41 | ); | |
|
42 | ||
|
43 | END testbench_package; | |
|
44 | ||
|
45 | PACKAGE BODY testbench_package IS | |
|
46 | ||
|
47 | PROCEDURE APB_WRITE ( | |
|
48 | SIGNAL clk : IN STD_LOGIC; | |
|
49 | CONSTANT pindex : IN INTEGER; | |
|
50 | SIGNAL apbi : OUT apb_slv_in_type; | |
|
51 | CONSTANT paddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
52 | CONSTANT pwdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0) | |
|
53 | ) IS | |
|
54 | BEGIN | |
|
55 | apbi.psel(pindex) <= '1'; | |
|
56 | apbi.pwrite <= '1'; | |
|
57 | apbi.penable <= '1'; | |
|
58 | apbi.paddr <= paddr; | |
|
59 | apbi.pwdata <= pwdata; | |
|
60 | WAIT UNTIL clk = '0'; | |
|
61 | WAIT UNTIL clk = '1'; | |
|
62 | apbi.psel(pindex) <= '0'; | |
|
63 | apbi.pwrite <= '0'; | |
|
64 | apbi.penable <= '0'; | |
|
65 | apbi.paddr <= (OTHERS => '0'); | |
|
66 | apbi.pwdata <= (OTHERS => '0'); | |
|
67 | WAIT UNTIL clk = '0'; | |
|
68 | WAIT UNTIL clk = '1'; | |
|
69 | ||
|
70 | END APB_WRITE; | |
|
71 | ||
|
72 | PROCEDURE APB_READ ( | |
|
73 | SIGNAL clk : IN STD_LOGIC; | |
|
74 | CONSTANT pindex : IN INTEGER; | |
|
75 | SIGNAL apbi : OUT apb_slv_in_type; | |
|
76 | SIGNAL apbo : IN apb_slv_out_type; | |
|
77 | CONSTANT paddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
78 | SIGNAL prdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) | |
|
79 | ) IS | |
|
80 | BEGIN | |
|
81 | apbi.psel(pindex) <= '1'; | |
|
82 | apbi.pwrite <= '0'; | |
|
83 | apbi.penable <= '1'; | |
|
84 | apbi.paddr <= paddr; | |
|
85 | WAIT UNTIL clk = '0'; | |
|
86 | WAIT UNTIL clk = '1'; | |
|
87 | apbi.psel(pindex) <= '0'; | |
|
88 | apbi.pwrite <= '0'; | |
|
89 | apbi.penable <= '0'; | |
|
90 | apbi.paddr <= (OTHERS => '0'); | |
|
91 | WAIT UNTIL clk = '0'; | |
|
92 | WAIT UNTIL clk = '1'; | |
|
93 | prdata <= apbo.prdata; | |
|
94 | END APB_READ; | |
|
95 | ||
|
96 | PROCEDURE AHB_READ ( | |
|
97 | SIGNAL clk : IN STD_LOGIC; | |
|
98 | CONSTANT hindex : IN INTEGER; | |
|
99 | SIGNAL ahbmi : IN ahb_mst_in_type; | |
|
100 | SIGNAL ahbmo : OUT ahb_mst_out_type; | |
|
101 | CONSTANT haddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
102 | SIGNAL hrdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) | |
|
103 | ) IS | |
|
104 | BEGIN | |
|
105 | WAIT UNTIL clk = '1'; | |
|
106 | ahbmo.HADDR <= haddr; | |
|
107 | ahbmo.HPROT <= "0011"; | |
|
108 | ahbmo.HIRQ <= (OTHERS => '0'); | |
|
109 | ahbmo.HCONFIG <= (0 => (OTHERS => '0'), OTHERS => (OTHERS => '0')); | |
|
110 | ahbmo.HINDEX <= hindex; | |
|
111 | ahbmo.HBUSREQ <= '1'; | |
|
112 | ahbmo.HLOCK <= '1'; | |
|
113 | ahbmo.HSIZE <= HSIZE_WORD; | |
|
114 | ahbmo.HBURST <= HBURST_SINGLE; | |
|
115 | ahbmo.HTRANS <= HTRANS_NONSEQ; | |
|
116 | ahbmo.HWRITE <= '0'; | |
|
117 | WHILE ahbmi.HREADY = '0' LOOP | |
|
118 | WAIT UNTIL clk = '1'; | |
|
119 | END LOOP; | |
|
120 | WAIT UNTIL clk = '1'; | |
|
121 | --WAIT UNTIL clk = '1' AND ahbmi.HREADY = '1' AND ahbmi.HGRANT(hindex) = '1'; | |
|
122 | ahbmo.HBUSREQ <= '0'; | |
|
123 | ahbmo.HLOCK <= '0'; | |
|
124 | ahbmo.HTRANS <= HTRANS_IDLE; | |
|
125 | WHILE ahbmi.HREADY = '0' LOOP | |
|
126 | WAIT UNTIL clk = '1'; | |
|
127 | END LOOP; | |
|
128 | WAIT UNTIL clk = '1'; | |
|
129 | hrdata <= ahbmi.HRDATA; | |
|
130 | --WAIT UNTIL clk = '1' AND ahbmi.HREADY = '1' AND ahbmi.HGRANT(hindex) = '1'; | |
|
131 | ahbmo.HLOCK <= '0'; | |
|
132 | WAIT UNTIL clk = '1'; | |
|
133 | ||
|
134 | END AHB_READ; | |
|
135 | ||
|
136 | END testbench_package; |
@@ -1,580 +1,580 | |||
|
1 | 1 | ------------------------------------------------------------------------------ |
|
2 | 2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
3 | 3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
4 | 4 | -- |
|
5 | 5 | -- This program is free software; you can redistribute it and/or modify |
|
6 | 6 | -- it under the terms of the GNU General Public License as published by |
|
7 | 7 | -- the Free Software Foundation; either version 3 of the License, or |
|
8 | 8 | -- (at your option) any later version. |
|
9 | 9 | -- |
|
10 | 10 | -- This program is distributed in the hope that it will be useful, |
|
11 | 11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
12 | 12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
13 | 13 | -- GNU General Public License for more details. |
|
14 | 14 | -- |
|
15 | 15 | -- You should have received a copy of the GNU General Public License |
|
16 | 16 | -- along with this program; if not, write to the Free Software |
|
17 | 17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
18 | 18 | ------------------------------------------------------------------------------- |
|
19 | 19 | -- Author : Jean-christophe Pellion |
|
20 | 20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
|
21 | 21 | ------------------------------------------------------------------------------- |
|
22 | 22 | LIBRARY IEEE; |
|
23 | 23 | USE IEEE.numeric_std.ALL; |
|
24 | 24 | USE IEEE.std_logic_1164.ALL; |
|
25 | 25 | LIBRARY grlib; |
|
26 | 26 | USE grlib.amba.ALL; |
|
27 | 27 | USE grlib.stdlib.ALL; |
|
28 | 28 | LIBRARY techmap; |
|
29 | 29 | USE techmap.gencomp.ALL; |
|
30 | 30 | LIBRARY gaisler; |
|
31 | 31 | USE gaisler.memctrl.ALL; |
|
32 | 32 | USE gaisler.leon3.ALL; |
|
33 | 33 | USE gaisler.uart.ALL; |
|
34 | 34 | USE gaisler.misc.ALL; |
|
35 | 35 | USE gaisler.spacewire.ALL; |
|
36 | 36 | LIBRARY esa; |
|
37 | 37 | USE esa.memoryctrl.ALL; |
|
38 | 38 | LIBRARY lpp; |
|
39 | 39 | USE lpp.lpp_memory.ALL; |
|
40 | 40 | USE lpp.lpp_ad_conv.ALL; |
|
41 | 41 | USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib |
|
42 | 42 | USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker |
|
43 | 43 | USE lpp.iir_filter.ALL; |
|
44 | 44 | USE lpp.general_purpose.ALL; |
|
45 | 45 | USE lpp.lpp_lfr_time_management.ALL; |
|
46 | 46 | USE lpp.lpp_leon3_soc_pkg.ALL; |
|
47 | 47 | |
|
48 | 48 | ENTITY MINI_LFR_top IS |
|
49 | 49 | |
|
50 | 50 | PORT ( |
|
51 | 51 | clk_50 : IN STD_LOGIC; |
|
52 | 52 | clk_49 : IN STD_LOGIC; |
|
53 | 53 | reset : IN STD_LOGIC; |
|
54 | 54 | --BPs |
|
55 | 55 | BP0 : IN STD_LOGIC; |
|
56 | 56 | BP1 : IN STD_LOGIC; |
|
57 | 57 | --LEDs |
|
58 | 58 | LED0 : OUT STD_LOGIC; |
|
59 | 59 | LED1 : OUT STD_LOGIC; |
|
60 | 60 | LED2 : OUT STD_LOGIC; |
|
61 | 61 | --UARTs |
|
62 | 62 | TXD1 : IN STD_LOGIC; |
|
63 | 63 | RXD1 : OUT STD_LOGIC; |
|
64 | 64 | nCTS1 : OUT STD_LOGIC; |
|
65 | 65 | nRTS1 : IN STD_LOGIC; |
|
66 | 66 | |
|
67 | 67 | TXD2 : IN STD_LOGIC; |
|
68 | 68 | RXD2 : OUT STD_LOGIC; |
|
69 | 69 | nCTS2 : OUT STD_LOGIC; |
|
70 | 70 | nDTR2 : IN STD_LOGIC; |
|
71 | 71 | nRTS2 : IN STD_LOGIC; |
|
72 | 72 | nDCD2 : OUT STD_LOGIC; |
|
73 | 73 | |
|
74 | 74 | --EXT CONNECTOR |
|
75 | 75 | IO0 : INOUT STD_LOGIC; |
|
76 | 76 | IO1 : INOUT STD_LOGIC; |
|
77 | 77 | IO2 : INOUT STD_LOGIC; |
|
78 | 78 | IO3 : INOUT STD_LOGIC; |
|
79 | 79 | IO4 : INOUT STD_LOGIC; |
|
80 | 80 | IO5 : INOUT STD_LOGIC; |
|
81 | 81 | IO6 : INOUT STD_LOGIC; |
|
82 | 82 | IO7 : INOUT STD_LOGIC; |
|
83 | 83 | IO8 : INOUT STD_LOGIC; |
|
84 | 84 | IO9 : INOUT STD_LOGIC; |
|
85 | 85 | IO10 : INOUT STD_LOGIC; |
|
86 | 86 | IO11 : INOUT STD_LOGIC; |
|
87 | 87 | |
|
88 | 88 | --SPACE WIRE |
|
89 | 89 | SPW_EN : OUT STD_LOGIC; -- 0 => off |
|
90 | 90 | SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK |
|
91 | 91 | SPW_NOM_SIN : IN STD_LOGIC; |
|
92 | 92 | SPW_NOM_DOUT : OUT STD_LOGIC; |
|
93 | 93 | SPW_NOM_SOUT : OUT STD_LOGIC; |
|
94 | 94 | SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK |
|
95 | 95 | SPW_RED_SIN : IN STD_LOGIC; |
|
96 | 96 | SPW_RED_DOUT : OUT STD_LOGIC; |
|
97 | 97 | SPW_RED_SOUT : OUT STD_LOGIC; |
|
98 | 98 | -- MINI LFR ADC INPUTS |
|
99 | 99 | ADC_nCS : OUT STD_LOGIC; |
|
100 | 100 | ADC_CLK : OUT STD_LOGIC; |
|
101 | 101 | ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0); |
|
102 | 102 | |
|
103 | 103 | -- SRAM |
|
104 | 104 | SRAM_nWE : OUT STD_LOGIC; |
|
105 | 105 | SRAM_CE : OUT STD_LOGIC; |
|
106 | 106 | SRAM_nOE : OUT STD_LOGIC; |
|
107 | 107 | SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
108 | 108 | SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); |
|
109 | 109 | SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0) |
|
110 | 110 | ); |
|
111 | 111 | |
|
112 | 112 | END MINI_LFR_top; |
|
113 | 113 | |
|
114 | 114 | |
|
115 | 115 | ARCHITECTURE beh OF MINI_LFR_top IS |
|
116 | 116 | SIGNAL clk_50_s : STD_LOGIC := '0'; |
|
117 | 117 | SIGNAL clk_25 : STD_LOGIC := '0'; |
|
118 | 118 | SIGNAL clk_24 : STD_LOGIC := '0'; |
|
119 | 119 | ----------------------------------------------------------------------------- |
|
120 | 120 | SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
121 | 121 | SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
122 | 122 | -- |
|
123 | 123 | SIGNAL errorn : STD_LOGIC; |
|
124 | 124 | -- UART AHB --------------------------------------------------------------- |
|
125 | 125 | SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data |
|
126 | 126 | SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data |
|
127 | 127 | |
|
128 | 128 | -- UART APB --------------------------------------------------------------- |
|
129 | 129 | SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data |
|
130 | 130 | SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data |
|
131 | 131 | -- |
|
132 | 132 | SIGNAL I00_s : STD_LOGIC; |
|
133 | 133 | |
|
134 | 134 | -- CONSTANTS |
|
135 | 135 | CONSTANT CFG_PADTECH : INTEGER := inferred; |
|
136 | 136 | -- |
|
137 | 137 | CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f |
|
138 | 138 | CONSTANT NB_AHB_SLAVE : INTEGER := 1; |
|
139 | 139 | CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker |
|
140 | 140 | |
|
141 | 141 | SIGNAL apbi_ext : apb_slv_in_type; |
|
142 | 142 | SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none); |
|
143 | 143 | SIGNAL ahbi_s_ext : ahb_slv_in_type; |
|
144 | 144 | SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none); |
|
145 | 145 | SIGNAL ahbi_m_ext : AHB_Mst_In_Type; |
|
146 | 146 | SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none); |
|
147 | 147 | |
|
148 | 148 | -- Spacewire signals |
|
149 | 149 | SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
150 | 150 | SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
151 | 151 | SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
152 | 152 | SIGNAL spw_rxtxclk : STD_ULOGIC; |
|
153 | 153 | SIGNAL spw_rxclkn : STD_ULOGIC; |
|
154 | 154 | SIGNAL spw_clk : STD_LOGIC; |
|
155 | 155 | SIGNAL swni : grspw_in_type; |
|
156 | 156 | SIGNAL swno : grspw_out_type; |
|
157 | 157 | -- SIGNAL clkmn : STD_ULOGIC; |
|
158 | 158 | -- SIGNAL txclk : STD_ULOGIC; |
|
159 | 159 | |
|
160 | 160 | --GPIO |
|
161 | 161 | SIGNAL gpioi : gpio_in_type; |
|
162 | 162 | SIGNAL gpioo : gpio_out_type; |
|
163 | 163 | |
|
164 | 164 | -- AD Converter ADS7886 |
|
165 | 165 | SIGNAL sample : Samples14v(7 DOWNTO 0); |
|
166 | 166 | SIGNAL sample_val : STD_LOGIC; |
|
167 | 167 | SIGNAL ADC_nCS_sig : STD_LOGIC; |
|
168 | 168 | SIGNAL ADC_CLK_sig : STD_LOGIC; |
|
169 | 169 | SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0); |
|
170 | 170 | |
|
171 | 171 | SIGNAL bias_fail_sw_sig : STD_LOGIC; |
|
172 | 172 | |
|
173 | 173 | ----------------------------------------------------------------------------- |
|
174 | 174 | SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
175 | 175 | |
|
176 | 176 | BEGIN -- beh |
|
177 | 177 | |
|
178 | 178 | ----------------------------------------------------------------------------- |
|
179 | 179 | -- CLK |
|
180 | 180 | ----------------------------------------------------------------------------- |
|
181 | 181 | |
|
182 | 182 | PROCESS(clk_50) |
|
183 | 183 | BEGIN |
|
184 | 184 | IF clk_50'EVENT AND clk_50 = '1' THEN |
|
185 | 185 | clk_50_s <= NOT clk_50_s; |
|
186 | 186 | END IF; |
|
187 | 187 | END PROCESS; |
|
188 | 188 | |
|
189 | 189 | PROCESS(clk_50_s) |
|
190 | 190 | BEGIN |
|
191 | 191 | IF clk_50_s'EVENT AND clk_50_s = '1' THEN |
|
192 | 192 | clk_25 <= NOT clk_25; |
|
193 | 193 | END IF; |
|
194 | 194 | END PROCESS; |
|
195 | 195 | |
|
196 | 196 | PROCESS(clk_49) |
|
197 | 197 | BEGIN |
|
198 | 198 | IF clk_49'EVENT AND clk_49 = '1' THEN |
|
199 | 199 | clk_24 <= NOT clk_24; |
|
200 | 200 | END IF; |
|
201 | 201 | END PROCESS; |
|
202 | 202 | |
|
203 | 203 | ----------------------------------------------------------------------------- |
|
204 | 204 | |
|
205 | 205 | PROCESS (clk_25, reset) |
|
206 | 206 | BEGIN -- PROCESS |
|
207 | 207 | IF reset = '0' THEN -- asynchronous reset (active low) |
|
208 | 208 | LED0 <= '0'; |
|
209 | 209 | LED1 <= '0'; |
|
210 | 210 | LED2 <= '0'; |
|
211 | 211 | --IO1 <= '0'; |
|
212 | 212 | --IO2 <= '1'; |
|
213 | 213 | --IO3 <= '0'; |
|
214 | 214 | --IO4 <= '0'; |
|
215 | 215 | --IO5 <= '0'; |
|
216 | 216 | --IO6 <= '0'; |
|
217 | 217 | --IO7 <= '0'; |
|
218 | 218 | --IO8 <= '0'; |
|
219 | 219 | --IO9 <= '0'; |
|
220 | 220 | --IO10 <= '0'; |
|
221 | 221 | --IO11 <= '0'; |
|
222 | 222 | ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge |
|
223 | 223 | LED0 <= '0'; |
|
224 | 224 | LED1 <= '1'; |
|
225 | 225 | LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1; |
|
226 | 226 | --IO1 <= '1'; |
|
227 | 227 | --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN; |
|
228 | 228 | --IO3 <= ADC_SDO(0); |
|
229 | 229 | --IO4 <= ADC_SDO(1); |
|
230 | 230 | --IO5 <= ADC_SDO(2); |
|
231 | 231 | --IO6 <= ADC_SDO(3); |
|
232 | 232 | --IO7 <= ADC_SDO(4); |
|
233 | 233 | --IO8 <= ADC_SDO(5); |
|
234 | 234 | --IO9 <= ADC_SDO(6); |
|
235 | 235 | --IO10 <= ADC_SDO(7); |
|
236 | 236 | --IO11 <= ; |
|
237 | 237 | END IF; |
|
238 | 238 | END PROCESS; |
|
239 | 239 | |
|
240 | 240 | PROCESS (clk_24, reset) |
|
241 | 241 | BEGIN -- PROCESS |
|
242 | 242 | IF reset = '0' THEN -- asynchronous reset (active low) |
|
243 | 243 | I00_s <= '0'; |
|
244 | 244 | ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge |
|
245 | 245 | I00_s <= NOT I00_s; |
|
246 | 246 | END IF; |
|
247 | 247 | END PROCESS; |
|
248 | 248 | -- IO0 <= I00_s; |
|
249 | 249 | |
|
250 | 250 | --UARTs |
|
251 | 251 | nCTS1 <= '1'; |
|
252 | 252 | nCTS2 <= '1'; |
|
253 | 253 | nDCD2 <= '1'; |
|
254 | 254 | |
|
255 | 255 | --EXT CONNECTOR |
|
256 | 256 | |
|
257 | 257 | --SPACE WIRE |
|
258 | 258 | |
|
259 | 259 | leon3_soc_1 : leon3_soc |
|
260 | 260 | GENERIC MAP ( |
|
261 | 261 | fabtech => apa3e, |
|
262 | 262 | memtech => apa3e, |
|
263 | 263 | padtech => inferred, |
|
264 | 264 | clktech => inferred, |
|
265 | 265 | disas => 0, |
|
266 | 266 | dbguart => 0, |
|
267 | 267 | pclow => 2, |
|
268 | 268 | clk_freq => 25000, |
|
269 | 269 | NB_CPU => 1, |
|
270 | 270 | ENABLE_FPU => 1, |
|
271 | 271 | FPU_NETLIST => 0, |
|
272 | 272 | ENABLE_DSU => 1, |
|
273 | 273 | ENABLE_AHB_UART => 1, |
|
274 | 274 | ENABLE_APB_UART => 1, |
|
275 | 275 | ENABLE_IRQMP => 1, |
|
276 | 276 | ENABLE_GPT => 1, |
|
277 | 277 | NB_AHB_MASTER => NB_AHB_MASTER, |
|
278 | 278 | NB_AHB_SLAVE => NB_AHB_SLAVE, |
|
279 | 279 | NB_APB_SLAVE => NB_APB_SLAVE) |
|
280 | 280 | PORT MAP ( |
|
281 | 281 | clk => clk_25, |
|
282 | 282 | reset => reset, |
|
283 | 283 | errorn => errorn, |
|
284 | 284 | ahbrxd => TXD1, |
|
285 | 285 | ahbtxd => RXD1, |
|
286 | 286 | urxd1 => TXD2, |
|
287 | 287 | utxd1 => RXD2, |
|
288 | 288 | address => SRAM_A, |
|
289 | 289 | data => SRAM_DQ, |
|
290 | 290 | nSRAM_BE0 => SRAM_nBE(0), |
|
291 | 291 | nSRAM_BE1 => SRAM_nBE(1), |
|
292 | 292 | nSRAM_BE2 => SRAM_nBE(2), |
|
293 | 293 | nSRAM_BE3 => SRAM_nBE(3), |
|
294 | 294 | nSRAM_WE => SRAM_nWE, |
|
295 | 295 | nSRAM_CE => SRAM_CE, |
|
296 | 296 | nSRAM_OE => SRAM_nOE, |
|
297 | 297 | |
|
298 | 298 | apbi_ext => apbi_ext, |
|
299 | 299 | apbo_ext => apbo_ext, |
|
300 | 300 | ahbi_s_ext => ahbi_s_ext, |
|
301 | 301 | ahbo_s_ext => ahbo_s_ext, |
|
302 | 302 | ahbi_m_ext => ahbi_m_ext, |
|
303 | 303 | ahbo_m_ext => ahbo_m_ext); |
|
304 | 304 | |
|
305 | 305 | ------------------------------------------------------------------------------- |
|
306 | 306 | -- APB_LFR_TIME_MANAGEMENT ---------------------------------------------------- |
|
307 | 307 | ------------------------------------------------------------------------------- |
|
308 | 308 | apb_lfr_time_management_1 : apb_lfr_time_management |
|
309 | 309 | GENERIC MAP ( |
|
310 | 310 | pindex => 6, |
|
311 | 311 | paddr => 6, |
|
312 | 312 | pmask => 16#fff#, |
|
313 | 313 | pirq => 12, |
|
314 | 314 | nb_wait_pediod => 375) -- (49.152/2) /2^16 = 375 |
|
315 | 315 | PORT MAP ( |
|
316 | 316 | clk25MHz => clk_25, |
|
317 | 317 | clk49_152MHz => clk_24, -- 49.152MHz/2 |
|
318 | 318 | resetn => reset, |
|
319 | 319 | grspw_tick => swno.tickout, |
|
320 | 320 | apbi => apbi_ext, |
|
321 | 321 | apbo => apbo_ext(6), |
|
322 | 322 | coarse_time => coarse_time, |
|
323 | 323 | fine_time => fine_time); |
|
324 | 324 | |
|
325 | 325 | ----------------------------------------------------------------------- |
|
326 | 326 | --- SpaceWire -------------------------------------------------------- |
|
327 | 327 | ----------------------------------------------------------------------- |
|
328 | 328 | |
|
329 | 329 | SPW_EN <= '1'; |
|
330 | 330 | |
|
331 | 331 | spw_clk <= clk_50_s; |
|
332 | 332 | spw_rxtxclk <= spw_clk; |
|
333 | 333 | spw_rxclkn <= NOT spw_rxtxclk; |
|
334 | 334 | |
|
335 | 335 | -- PADS for SPW1 |
|
336 | 336 | spw1_rxd_pad : inpad GENERIC MAP (tech => inferred) |
|
337 | 337 | PORT MAP (SPW_NOM_DIN, dtmp(0)); |
|
338 | 338 | spw1_rxs_pad : inpad GENERIC MAP (tech => inferred) |
|
339 | 339 | PORT MAP (SPW_NOM_SIN, stmp(0)); |
|
340 | 340 | spw1_txd_pad : outpad GENERIC MAP (tech => inferred) |
|
341 | 341 | PORT MAP (SPW_NOM_DOUT, swno.d(0)); |
|
342 | 342 | spw1_txs_pad : outpad GENERIC MAP (tech => inferred) |
|
343 | 343 | PORT MAP (SPW_NOM_SOUT, swno.s(0)); |
|
344 | 344 | -- PADS FOR SPW2 |
|
345 | 345 | spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ |
|
346 | 346 | PORT MAP (SPW_RED_SIN, dtmp(1)); |
|
347 | 347 | spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ |
|
348 | 348 | PORT MAP (SPW_RED_DIN, stmp(1)); |
|
349 | 349 | spw2_txd_pad : outpad GENERIC MAP (tech => inferred) |
|
350 | 350 | PORT MAP (SPW_RED_DOUT, swno.d(1)); |
|
351 | 351 | spw2_txs_pad : outpad GENERIC MAP (tech => inferred) |
|
352 | 352 | PORT MAP (SPW_RED_SOUT, swno.s(1)); |
|
353 | 353 | |
|
354 | 354 | -- GRSPW PHY |
|
355 | 355 | --spw1_input: if CFG_SPW_GRSPW = 1 generate |
|
356 | 356 | spw_inputloop : FOR j IN 0 TO 1 GENERATE |
|
357 | 357 | spw_phy0 : grspw_phy |
|
358 | 358 | GENERIC MAP( |
|
359 | 359 | tech => apa3e, |
|
360 | 360 | rxclkbuftype => 1, |
|
361 | 361 | scantest => 0) |
|
362 | 362 | PORT MAP( |
|
363 | 363 | rxrst => swno.rxrst, |
|
364 | 364 | di => dtmp(j), |
|
365 | 365 | si => stmp(j), |
|
366 | 366 | rxclko => spw_rxclk(j), |
|
367 | 367 | do => swni.d(j), |
|
368 | 368 | ndo => swni.nd(j*5+4 DOWNTO j*5), |
|
369 | 369 | dconnect => swni.dconnect(j*2+1 DOWNTO j*2)); |
|
370 | 370 | END GENERATE spw_inputloop; |
|
371 | 371 | |
|
372 | 372 | -- SPW core |
|
373 | 373 | sw0 : grspwm GENERIC MAP( |
|
374 | 374 | tech => apa3e, |
|
375 | 375 | hindex => 1, |
|
376 | 376 | pindex => 5, |
|
377 | 377 | paddr => 5, |
|
378 | 378 | pirq => 11, |
|
379 | 379 | sysfreq => 25000, -- CPU_FREQ |
|
380 | 380 | rmap => 1, |
|
381 | 381 | rmapcrc => 1, |
|
382 | 382 | fifosize1 => 16, |
|
383 | 383 | fifosize2 => 16, |
|
384 | 384 | rxclkbuftype => 1, |
|
385 | 385 | rxunaligned => 0, |
|
386 | 386 | rmapbufs => 4, |
|
387 | 387 | ft => 0, |
|
388 | 388 | netlist => 0, |
|
389 | 389 | ports => 2, |
|
390 | 390 | --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1 |
|
391 | 391 | memtech => apa3e, |
|
392 | 392 | destkey => 2, |
|
393 | 393 | spwcore => 1 |
|
394 | 394 | --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1 |
|
395 | 395 | --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1 |
|
396 | 396 | --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1 |
|
397 | 397 | ) |
|
398 | 398 | PORT MAP(reset, clk_25, spw_rxclk(0), |
|
399 | 399 | spw_rxclk(1), spw_rxtxclk, spw_rxtxclk, |
|
400 | 400 | ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5), |
|
401 | 401 | swni, swno); |
|
402 | 402 | |
|
403 | 403 | swni.tickin <= '0'; |
|
404 | 404 | swni.rmapen <= '1'; |
|
405 | 405 | swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz |
|
406 | 406 | swni.tickinraw <= '0'; |
|
407 | 407 | swni.timein <= (OTHERS => '0'); |
|
408 | 408 | swni.dcrstval <= (OTHERS => '0'); |
|
409 | 409 | swni.timerrstval <= (OTHERS => '0'); |
|
410 | 410 | |
|
411 | 411 | ------------------------------------------------------------------------------- |
|
412 | 412 | -- LFR ------------------------------------------------------------------------ |
|
413 | 413 | ------------------------------------------------------------------------------- |
|
414 | 414 | lpp_lfr_1 : lpp_lfr |
|
415 | 415 | GENERIC MAP ( |
|
416 | 416 | Mem_use => use_RAM, |
|
417 | 417 | nb_data_by_buffer_size => 32, |
|
418 | 418 | nb_word_by_buffer_size => 30, |
|
419 | 419 | nb_snapshot_param_size => 32, |
|
420 | 420 | delta_vector_size => 32, |
|
421 | 421 | delta_vector_size_f0_2 => 7, -- log2(96) |
|
422 | 422 | pindex => 15, |
|
423 | 423 | paddr => 15, |
|
424 | 424 | pmask => 16#fff#, |
|
425 | 425 | pirq_ms => 6, |
|
426 | 426 | pirq_wfp => 14, |
|
427 | 427 | hindex => 2, |
|
428 |
top_lfr_version => X"00000 |
|
|
428 | top_lfr_version => X"000010") -- aa.bb.cc version | |
|
429 | 429 | PORT MAP ( |
|
430 | 430 | clk => clk_25, |
|
431 | 431 | rstn => reset, |
|
432 | 432 | sample_B => sample(2 DOWNTO 0), |
|
433 | 433 | sample_E => sample(7 DOWNTO 3), |
|
434 | 434 | sample_val => sample_val, |
|
435 | 435 | apbi => apbi_ext, |
|
436 | 436 | apbo => apbo_ext(15), |
|
437 | 437 | ahbi => ahbi_m_ext, |
|
438 | 438 | ahbo => ahbo_m_ext(2), |
|
439 | 439 | coarse_time => coarse_time, |
|
440 | 440 | fine_time => fine_time, |
|
441 | 441 | data_shaping_BW => bias_fail_sw_sig, |
|
442 | 442 | observation_reg => observation_reg); |
|
443 | 443 | |
|
444 | 444 | top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2 |
|
445 | 445 | GENERIC MAP( |
|
446 | 446 | ChannelCount => 8, |
|
447 | 447 | SampleNbBits => 14, |
|
448 | 448 | ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5 |
|
449 | 449 | ncycle_cnv => 249) -- 49 152 000 / 98304 /2 |
|
450 | 450 | PORT MAP ( |
|
451 | 451 | -- CONV |
|
452 | 452 | cnv_clk => clk_24, |
|
453 | 453 | cnv_rstn => reset, |
|
454 | 454 | cnv => ADC_nCS_sig, |
|
455 | 455 | -- DATA |
|
456 | 456 | clk => clk_25, |
|
457 | 457 | rstn => reset, |
|
458 | 458 | sck => ADC_CLK_sig, |
|
459 | 459 | sdo => ADC_SDO_sig, |
|
460 | 460 | -- SAMPLE |
|
461 | 461 | sample => sample, |
|
462 | 462 | sample_val => sample_val); |
|
463 | 463 | |
|
464 | 464 | --IO10 <= ADC_SDO_sig(5); |
|
465 | 465 | --IO9 <= ADC_SDO_sig(4); |
|
466 | 466 | --IO8 <= ADC_SDO_sig(3); |
|
467 | 467 | |
|
468 | 468 | ADC_nCS <= ADC_nCS_sig; |
|
469 | 469 | ADC_CLK <= ADC_CLK_sig; |
|
470 | 470 | ADC_SDO_sig <= ADC_SDO; |
|
471 | 471 | |
|
472 | 472 | ---------------------------------------------------------------------- |
|
473 | 473 | --- GPIO ----------------------------------------------------------- |
|
474 | 474 | ---------------------------------------------------------------------- |
|
475 | 475 | |
|
476 | 476 | grgpio0 : grgpio |
|
477 | 477 | GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8) |
|
478 | 478 | PORT MAP(reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo); |
|
479 | 479 | |
|
480 | 480 | --pio_pad_0 : iopad |
|
481 | 481 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
482 | 482 | -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0)); |
|
483 | 483 | --pio_pad_1 : iopad |
|
484 | 484 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
485 | 485 | -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1)); |
|
486 | 486 | --pio_pad_2 : iopad |
|
487 | 487 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
488 | 488 | -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2)); |
|
489 | 489 | --pio_pad_3 : iopad |
|
490 | 490 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
491 | 491 | -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3)); |
|
492 | 492 | --pio_pad_4 : iopad |
|
493 | 493 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
494 | 494 | -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4)); |
|
495 | 495 | --pio_pad_5 : iopad |
|
496 | 496 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
497 | 497 | -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5)); |
|
498 | 498 | --pio_pad_6 : iopad |
|
499 | 499 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
500 | 500 | -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6)); |
|
501 | 501 | --pio_pad_7 : iopad |
|
502 | 502 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
503 | 503 | -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7)); |
|
504 | 504 | |
|
505 | 505 | PROCESS (clk_25, reset) |
|
506 | 506 | BEGIN -- PROCESS |
|
507 | 507 | IF reset = '0' THEN -- asynchronous reset (active low) |
|
508 | 508 | IO0 <= '0'; |
|
509 | 509 | IO1 <= '0'; |
|
510 | 510 | IO2 <= '0'; |
|
511 | 511 | IO3 <= '0'; |
|
512 | 512 | IO4 <= '0'; |
|
513 | 513 | IO5 <= '0'; |
|
514 | 514 | IO6 <= '0'; |
|
515 | 515 | IO7 <= '0'; |
|
516 | 516 | IO8 <= '0'; |
|
517 | 517 | IO9 <= '0'; |
|
518 | 518 | IO10 <= '0'; |
|
519 | 519 | IO11 <= '0'; |
|
520 | 520 | ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge |
|
521 | 521 | CASE gpioo.dout(1 DOWNTO 0) IS |
|
522 | 522 | WHEN "00" => |
|
523 | 523 | IO0 <= observation_reg(0 ); |
|
524 | 524 | IO1 <= observation_reg(1 ); |
|
525 | 525 | IO2 <= observation_reg(2 ); |
|
526 | 526 | IO3 <= observation_reg(3 ); |
|
527 | 527 | IO4 <= observation_reg(4 ); |
|
528 | 528 | IO5 <= observation_reg(5 ); |
|
529 | 529 | IO6 <= observation_reg(6 ); |
|
530 | 530 | IO7 <= observation_reg(7 ); |
|
531 | 531 | IO8 <= observation_reg(8 ); |
|
532 | 532 | IO9 <= observation_reg(9 ); |
|
533 | 533 | IO10 <= observation_reg(10); |
|
534 | 534 | IO11 <= observation_reg(11); |
|
535 | 535 | WHEN "01" => |
|
536 | 536 | IO0 <= observation_reg(0 + 12); |
|
537 | 537 | IO1 <= observation_reg(1 + 12); |
|
538 | 538 | IO2 <= observation_reg(2 + 12); |
|
539 | 539 | IO3 <= observation_reg(3 + 12); |
|
540 | 540 | IO4 <= observation_reg(4 + 12); |
|
541 | 541 | IO5 <= observation_reg(5 + 12); |
|
542 | 542 | IO6 <= observation_reg(6 + 12); |
|
543 | 543 | IO7 <= observation_reg(7 + 12); |
|
544 | 544 | IO8 <= observation_reg(8 + 12); |
|
545 | 545 | IO9 <= observation_reg(9 + 12); |
|
546 | 546 | IO10 <= observation_reg(10 + 12); |
|
547 | 547 | IO11 <= observation_reg(11 + 12); |
|
548 | 548 | WHEN "10" => |
|
549 | 549 | IO0 <= observation_reg(0 + 12 + 12); |
|
550 | 550 | IO1 <= observation_reg(1 + 12 + 12); |
|
551 | 551 | IO2 <= observation_reg(2 + 12 + 12); |
|
552 | 552 | IO3 <= observation_reg(3 + 12 + 12); |
|
553 | 553 | IO4 <= observation_reg(4 + 12 + 12); |
|
554 | 554 | IO5 <= observation_reg(5 + 12 + 12); |
|
555 | 555 | IO6 <= observation_reg(6 + 12 + 12); |
|
556 | 556 | IO7 <= observation_reg(7 + 12 + 12); |
|
557 | 557 | IO8 <= '0'; |
|
558 | 558 | IO9 <= '0'; |
|
559 | 559 | IO10 <= '0'; |
|
560 | 560 | IO11 <= '0'; |
|
561 | 561 | WHEN "11" => |
|
562 | 562 | IO0 <= '0'; |
|
563 | 563 | IO1 <= '0'; |
|
564 | 564 | IO2 <= '0'; |
|
565 | 565 | IO3 <= '0'; |
|
566 | 566 | IO4 <= '0'; |
|
567 | 567 | IO5 <= '0'; |
|
568 | 568 | IO6 <= '0'; |
|
569 | 569 | IO7 <= '0'; |
|
570 | 570 | IO8 <= '0'; |
|
571 | 571 | IO9 <= '0'; |
|
572 | 572 | IO10 <= '0'; |
|
573 | 573 | IO11 <= '0'; |
|
574 | 574 | WHEN OTHERS => NULL; |
|
575 | 575 | END CASE; |
|
576 | 576 | |
|
577 | 577 | END IF; |
|
578 | 578 | END PROCESS; |
|
579 | 579 | |
|
580 | 580 | END beh; No newline at end of file |
@@ -1,191 +1,205 | |||
|
1 | 1 | |
|
2 | 2 | ------------------------------------------------------------------------------ |
|
3 | 3 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
4 | 4 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
5 | 5 | -- |
|
6 | 6 | -- This program is free software; you can redistribute it and/or modify |
|
7 | 7 | -- it under the terms of the GNU General Public License as published by |
|
8 | 8 | -- the Free Software Foundation; either version 3 of the License, or |
|
9 | 9 | -- (at your option) any later version. |
|
10 | 10 | -- |
|
11 | 11 | -- This program is distributed in the hope that it will be useful, |
|
12 | 12 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
13 | 13 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
14 | 14 | -- GNU General Public License for more details. |
|
15 | 15 | -- |
|
16 | 16 | -- You should have received a copy of the GNU General Public License |
|
17 | 17 | -- along with this program; if not, write to the Free Software |
|
18 | 18 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
19 | 19 | ------------------------------------------------------------------------------- |
|
20 | 20 | -- Author : Jean-christophe Pellion |
|
21 | 21 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
|
22 | 22 | -- jean-christophe.pellion@easii-ic.com |
|
23 | 23 | ------------------------------------------------------------------------------- |
|
24 | 24 | -- 1.0 - initial version |
|
25 | 25 | -- 1.1 - (01/11/2013) FIX boundary error (1kB address should not be crossed by BURSTS) |
|
26 | 26 | ------------------------------------------------------------------------------- |
|
27 | 27 | LIBRARY ieee; |
|
28 | 28 | USE ieee.std_logic_1164.ALL; |
|
29 | 29 | USE ieee.numeric_std.ALL; |
|
30 | 30 | LIBRARY grlib; |
|
31 | 31 | USE grlib.amba.ALL; |
|
32 | 32 | USE grlib.stdlib.ALL; |
|
33 | 33 | USE grlib.devices.ALL; |
|
34 | 34 | USE GRLIB.DMA2AHB_Package.ALL; |
|
35 | 35 | LIBRARY lpp; |
|
36 | 36 | USE lpp.lpp_amba.ALL; |
|
37 | 37 | USE lpp.apb_devices_list.ALL; |
|
38 | 38 | USE lpp.lpp_memory.ALL; |
|
39 | 39 | USE lpp.lpp_dma_pkg.ALL; |
|
40 | 40 | USE lpp.lpp_waveform_pkg.ALL; |
|
41 | 41 | LIBRARY techmap; |
|
42 | 42 | USE techmap.gencomp.ALL; |
|
43 | 43 | |
|
44 | 44 | |
|
45 | 45 | ENTITY lpp_dma_singleOrBurst IS |
|
46 | 46 | GENERIC ( |
|
47 | 47 | tech : INTEGER := inferred; |
|
48 | 48 | hindex : INTEGER := 2 |
|
49 | 49 | ); |
|
50 | 50 | PORT ( |
|
51 | 51 | -- AMBA AHB system signals |
|
52 | 52 | HCLK : IN STD_ULOGIC; |
|
53 | 53 | HRESETn : IN STD_ULOGIC; |
|
54 | 54 | -- |
|
55 | 55 | run : IN STD_LOGIC; |
|
56 | 56 | -- AMBA AHB Master Interface |
|
57 | 57 | AHB_Master_In : IN AHB_Mst_In_Type; |
|
58 | 58 | AHB_Master_Out : OUT AHB_Mst_Out_Type; |
|
59 | 59 | -- |
|
60 | 60 | send : IN STD_LOGIC; |
|
61 | 61 | valid_burst : IN STD_LOGIC; -- (1 => BURST , 0 => SINGLE) |
|
62 | 62 | done : OUT STD_LOGIC; |
|
63 | 63 | ren : OUT STD_LOGIC; |
|
64 | 64 | address : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
65 | 65 | data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
66 | 66 | -- |
|
67 | 67 | debug_dmaout_okay : OUT STD_LOGIC |
|
68 | 68 | |
|
69 | 69 | ); |
|
70 | 70 | END; |
|
71 | 71 | |
|
72 | 72 | ARCHITECTURE Behavioral OF lpp_dma_singleOrBurst IS |
|
73 | 73 | ----------------------------------------------------------------------------- |
|
74 | 74 | SIGNAL DMAIn : DMA_In_Type; |
|
75 | 75 | SIGNAL DMAOut : DMA_OUt_Type; |
|
76 | 76 | ----------------------------------------------------------------------------- |
|
77 | 77 | ----------------------------------------------------------------------------- |
|
78 | 78 | -- CONTROL |
|
79 | 79 | SIGNAL single_send : STD_LOGIC; |
|
80 | 80 | SIGNAL burst_send : STD_LOGIC; |
|
81 | 81 | |
|
82 | 82 | ----------------------------------------------------------------------------- |
|
83 | 83 | -- SEND SINGLE MODULE |
|
84 | 84 | SIGNAL single_dmai : DMA_In_Type; |
|
85 | 85 | |
|
86 | 86 | SIGNAL single_send_ok : STD_LOGIC; |
|
87 | 87 | SIGNAL single_send_ko : STD_LOGIC; |
|
88 | 88 | SIGNAL single_ren : STD_LOGIC; |
|
89 | 89 | ----------------------------------------------------------------------------- |
|
90 | 90 | -- SEND SINGLE MODULE |
|
91 | 91 | SIGNAL burst_dmai : DMA_In_Type; |
|
92 | 92 | |
|
93 | 93 | SIGNAL burst_send_ok : STD_LOGIC; |
|
94 | 94 | SIGNAL burst_send_ko : STD_LOGIC; |
|
95 | 95 | SIGNAL burst_ren : STD_LOGIC; |
|
96 | 96 | ----------------------------------------------------------------------------- |
|
97 | 97 | SIGNAL data_2_halfword : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
98 | ----------------------------------------------------------------------------- | |
|
99 | -- \/ -- 20/02/2014 -- JC Pellion | |
|
100 | SIGNAL send_reg : STD_LOGIC; | |
|
101 | SIGNAL send_s : STD_LOGIC; | |
|
102 | -- /\ -- | |
|
103 | ||
|
104 | ||
|
98 | 105 | BEGIN |
|
99 | 106 | |
|
100 | 107 | debug_dmaout_okay <= DMAOut.OKAY; |
|
101 | 108 | |
|
102 | 109 | |
|
103 | 110 | ----------------------------------------------------------------------------- |
|
104 | 111 | -- DMA to AHB interface |
|
105 | 112 | DMA2AHB_1 : DMA2AHB |
|
106 | 113 | GENERIC MAP ( |
|
107 | 114 | hindex => hindex, |
|
108 | 115 | vendorid => VENDOR_LPP, |
|
109 | 116 | deviceid => 10, |
|
110 | 117 | version => 0, |
|
111 | 118 | syncrst => 1, |
|
112 | 119 | boundary => 1) -- FIX 11/01/2013 |
|
113 | 120 | PORT MAP ( |
|
114 | 121 | HCLK => HCLK, |
|
115 | 122 | HRESETn => HRESETn, |
|
116 | 123 | DMAIn => DMAIn, |
|
117 | 124 | DMAOut => DMAOut, |
|
118 | 125 | |
|
119 | 126 | AHBIn => AHB_Master_In, |
|
120 | 127 | AHBOut => AHB_Master_Out); |
|
121 | 128 | ----------------------------------------------------------------------------- |
|
122 | 129 | |
|
123 | 130 | ----------------------------------------------------------------------------- |
|
124 | ----------------------------------------------------------------------------- | |
|
125 | -- LE PROBLEME EST LA !!!!! | |
|
126 | ----------------------------------------------------------------------------- | |
|
127 | ----------------------------------------------------------------------------- | |
|
128 | -- C'est le signal valid_burst qui n'est pas assez long. | |
|
129 | ----------------------------------------------------------------------------- | |
|
130 | single_send <= send WHEN valid_burst = '0' ELSE '0'; | |
|
131 | burst_send <= send WHEN valid_burst = '1' ELSE '0'; | |
|
131 | -- \/ -- 20/02/2014 -- JC Pellion | |
|
132 | PROCESS (HCLK, HRESETn) | |
|
133 | BEGIN | |
|
134 | IF HRESETn = '0' THEN | |
|
135 | send_reg <= '0'; | |
|
136 | ELSIF HCLK'event AND HCLK = '1' THEN | |
|
137 | send_reg <= send; | |
|
138 | END IF; | |
|
139 | END PROCESS; | |
|
140 | send_s <= send_reg; | |
|
141 | ||
|
142 | single_send <= send_s WHEN valid_burst = '0' ELSE '0'; | |
|
143 | burst_send <= send_s WHEN valid_burst = '1' ELSE '0'; | |
|
144 | -- /\ -- | |
|
145 | ||
|
132 | 146 | DMAIn <= single_dmai WHEN valid_burst = '0' ELSE burst_dmai; |
|
133 | 147 | |
|
134 | 148 | -- TODO : verifier |
|
135 | 149 | done <= single_send_ok OR single_send_ko OR burst_send_ok OR burst_send_ko; |
|
136 | 150 | --done <= single_send_ok OR single_send_ko WHEN valid_burst = '0' ELSE |
|
137 | 151 | -- burst_send_ok OR burst_send_ko; |
|
138 | 152 | |
|
139 | 153 | --ren <= burst_ren WHEN valid_burst = '1' ELSE |
|
140 | 154 | -- NOT single_send_ok; |
|
141 | 155 | --ren <= burst_ren AND single_ren; |
|
142 | 156 | |
|
143 | 157 | -- \/ JC - 20/01/2014 \/ |
|
144 | 158 | ren <= burst_ren WHEN valid_burst = '1' ELSE |
|
145 | 159 | single_ren; |
|
146 | 160 | |
|
147 | 161 | |
|
148 | 162 | --ren <= '0' WHEN DMAOut.OKAY = '1' ELSE |
|
149 | 163 | -- '1'; |
|
150 | 164 | -- /\ JC - 20/01/2014 /\ |
|
151 | 165 | |
|
152 | 166 | ----------------------------------------------------------------------------- |
|
153 | 167 | -- SEND 1 word by DMA |
|
154 | 168 | ----------------------------------------------------------------------------- |
|
155 | 169 | lpp_dma_send_1word_1 : lpp_dma_send_1word |
|
156 | 170 | PORT MAP ( |
|
157 | 171 | HCLK => HCLK, |
|
158 | 172 | HRESETn => HRESETn, |
|
159 | 173 | DMAIn => single_dmai, |
|
160 | 174 | DMAOut => DMAOut, |
|
161 | 175 | |
|
162 | 176 | send => single_send, |
|
163 | 177 | address => address, |
|
164 | 178 | data => data_2_halfword, |
|
165 | 179 | ren => single_ren, |
|
166 | 180 | |
|
167 | 181 | send_ok => single_send_ok, -- TODO |
|
168 | 182 | send_ko => single_send_ko -- TODO |
|
169 | 183 | ); |
|
170 | 184 | |
|
171 | 185 | ----------------------------------------------------------------------------- |
|
172 | 186 | -- SEND 16 word by DMA (in burst mode) |
|
173 | 187 | ----------------------------------------------------------------------------- |
|
174 | 188 | data_2_halfword(31 DOWNTO 0) <= data(15 DOWNTO 0) & data (31 DOWNTO 16); |
|
175 | 189 | |
|
176 | 190 | lpp_dma_send_16word_1 : lpp_dma_send_16word |
|
177 | 191 | PORT MAP ( |
|
178 | 192 | HCLK => HCLK, |
|
179 | 193 | HRESETn => HRESETn, |
|
180 | 194 | DMAIn => burst_dmai, |
|
181 | 195 | DMAOut => DMAOut, |
|
182 | 196 | |
|
183 | 197 | send => burst_send, |
|
184 | 198 | address => address, |
|
185 | 199 | data => data_2_halfword, |
|
186 | 200 | ren => burst_ren, |
|
187 | 201 | |
|
188 | 202 | send_ok => burst_send_ok, |
|
189 | 203 | send_ko => burst_send_ko); |
|
190 | 204 | |
|
191 | 205 | END Behavioral; |
@@ -1,662 +1,664 | |||
|
1 | 1 | --************************************************************************ |
|
2 | 2 | --** MODEL : async_1Mx16.vhd ** |
|
3 | 3 | --** COMPANY : Cypress Semiconductor ** |
|
4 | 4 | --** REVISION: 1.0 Created new base model ** |
|
5 | 5 | --************************************************************************ |
|
6 | 6 | |
|
7 | 7 | -------------------------------------------------------------------------------JC\/ |
|
8 | 8 | --Library ieee,work; |
|
9 | 9 | LIBRARY ieee; |
|
10 | 10 | -------------------------------------------------------------------------------JC/\ |
|
11 | 11 | USE IEEE.Std_Logic_1164.ALL; |
|
12 | 12 | USE IEEE.Std_Logic_unsigned.ALL; |
|
13 | 13 | |
|
14 | 14 | -------------------------------------------------------------------------------JC\/ |
|
15 | 15 | --use work.package_timing.all; |
|
16 | 16 | --use work.package_utility.all; |
|
17 | 17 | LIBRARY lpp; |
|
18 | 18 | USE lpp.package_timing.ALL; |
|
19 | 19 | USE lpp.package_utility.ALL; |
|
20 | 20 | -------------------------------------------------------------------------------JC/\ |
|
21 | 21 | |
|
22 | 22 | ------------------------ |
|
23 | 23 | -- Entity Description |
|
24 | 24 | ------------------------ |
|
25 | 25 | |
|
26 | 26 | ENTITY CY7C1061DV33 IS |
|
27 | 27 | GENERIC |
|
28 | 28 | (ADDR_BITS : INTEGER := 20; |
|
29 | 29 | DATA_BITS : INTEGER := 16; |
|
30 | 30 | depth : INTEGER := 1048576; |
|
31 | 31 | |
|
32 | MEM_ARRAY_DEBUG : INTEGER := 32; | |
|
33 | ||
|
32 | 34 |
|
|
33 | 35 | TimingChecks : STD_LOGIC := '1' |
|
34 | 36 | ); |
|
35 | 37 | PORT ( |
|
36 | 38 | CE1_b : IN STD_LOGIC; -- Chip Enable CE1# |
|
37 | 39 | CE2 : IN STD_LOGIC; -- Chip Enable CE2 |
|
38 | 40 | WE_b : IN STD_LOGIC; -- Write Enable WE# |
|
39 | 41 | OE_b : IN STD_LOGIC; -- Output Enable OE# |
|
40 | 42 | BHE_b : IN STD_LOGIC; -- Byte Enable High BHE# |
|
41 | 43 | BLE_b : IN STD_LOGIC; -- Byte Enable Low BLE# |
|
42 | 44 | A : IN STD_LOGIC_VECTOR(addr_bits-1 DOWNTO 0); -- Address Inputs A |
|
43 | 45 | DQ : INOUT STD_LOGIC_VECTOR(DATA_BITS-1 DOWNTO 0) := (OTHERS => 'Z')-- Read/Write Data IO; |
|
44 | 46 | ); |
|
45 | 47 | END CY7C1061DV33; |
|
46 | 48 | |
|
47 | 49 | ----------------------------- |
|
48 | 50 | -- End Entity Description |
|
49 | 51 | ----------------------------- |
|
50 | 52 | ----------------------------- |
|
51 | 53 | -- Architecture Description |
|
52 | 54 | ----------------------------- |
|
53 | 55 | |
|
54 | 56 | ARCHITECTURE behave_arch OF CY7C1061DV33 IS |
|
55 | 57 | |
|
56 | 58 | TYPE mem_array_type IS ARRAY (depth-1 DOWNTO 0) OF STD_LOGIC_VECTOR(DATA_BITS-1 DOWNTO 0); |
|
57 | 59 | |
|
58 | 60 | SIGNAL write_enable : STD_LOGIC; |
|
59 | 61 | SIGNAL read_enable : STD_LOGIC; |
|
60 | 62 | SIGNAL byte_enable : STD_LOGIC; |
|
61 | 63 | SIGNAL CE_b : STD_LOGIC; |
|
62 | 64 | |
|
63 | 65 | SIGNAL data_skew : STD_LOGIC_VECTOR(DATA_BITS-1 DOWNTO 0); |
|
64 | 66 | |
|
65 | 67 | SIGNAL address_internal, address_skew : STD_LOGIC_VECTOR(addr_bits-1 DOWNTO 0); |
|
66 | 68 | |
|
67 | 69 | CONSTANT tSD_dataskew : TIME := tSD - 1 ns; |
|
68 | 70 | CONSTANT tskew : TIME := 1 ns; |
|
69 | 71 | |
|
70 | 72 | -------------------------------------------------------------------------------JC\/ |
|
71 |
TYPE mem_array_type_t IS ARRAY ( |
|
|
73 | TYPE mem_array_type_t IS ARRAY (MEM_ARRAY_DEBUG-1 DOWNTO 0) OF STD_LOGIC_VECTOR(DATA_BITS-1 DOWNTO 0); | |
|
72 | 74 | SIGNAL mem_array_0 : mem_array_type_t; |
|
73 | 75 | SIGNAL mem_array_1 : mem_array_type_t; |
|
74 | 76 | SIGNAL mem_array_2 : mem_array_type_t; |
|
75 | 77 | SIGNAL mem_array_3 : mem_array_type_t; |
|
76 | 78 | -------------------------------------------------------------------------------JC/\ |
|
77 | 79 | |
|
78 | 80 | |
|
79 | 81 | |
|
80 | 82 | BEGIN |
|
81 | 83 | CE_b <= CE1_b OR NOT(CE2); |
|
82 | 84 | byte_enable <= NOT(BHE_b AND BLE_b); |
|
83 | 85 | write_enable <= NOT(CE1_b) AND CE2 AND NOT(WE_b) AND NOT(BHE_b AND BLE_b); |
|
84 | 86 | read_enable <= NOT(CE1_b) AND CE2 AND (WE_b) AND NOT(OE_b) AND NOT(BHE_b AND BLE_b); |
|
85 | 87 | |
|
86 | 88 | data_skew <= DQ AFTER 1 ns; -- changed on feb 15 |
|
87 | 89 | address_skew <= A AFTER 1 ns; |
|
88 | 90 | |
|
89 | 91 | PROCESS (OE_b) |
|
90 | 92 | BEGIN |
|
91 | 93 | IF (OE_b'EVENT AND OE_b = '1' AND write_enable /= '1') THEN |
|
92 | 94 | DQ <= (OTHERS => 'Z') after tHZOE; |
|
93 | 95 | END IF; |
|
94 | 96 | END PROCESS; |
|
95 | 97 | |
|
96 | 98 | PROCESS (CE_b) |
|
97 | 99 | BEGIN |
|
98 | 100 | IF (CE_b'EVENT AND CE_b = '1') THEN |
|
99 | 101 | DQ <= (OTHERS => 'Z') after tHZCE; |
|
100 | 102 | END IF; |
|
101 | 103 | END PROCESS; |
|
102 | 104 | |
|
103 | 105 | PROCESS (write_enable'DELAYED(tHA)) |
|
104 | 106 | BEGIN |
|
105 | 107 | IF (write_enable'DELAYED(tHA) = '0' AND TimingInfo) THEN |
|
106 | 108 | ASSERT (A'LAST_EVENT = 0 ns) OR (A'LAST_EVENT > tHA) |
|
107 | 109 | REPORT "Address hold time tHA violated"; |
|
108 | 110 | END IF; |
|
109 | 111 | END PROCESS; |
|
110 | 112 | |
|
111 | 113 | PROCESS (write_enable'DELAYED(tHD)) |
|
112 | 114 | BEGIN |
|
113 | 115 | IF (write_enable'DELAYED(tHD) = '0' AND TimingInfo) THEN |
|
114 | 116 | ASSERT (DQ'LAST_EVENT > tHD) OR (DQ'LAST_EVENT = 0 ns) |
|
115 | 117 | REPORT "Data hold time tHD violated"; |
|
116 | 118 | END IF; |
|
117 | 119 | END PROCESS; |
|
118 | 120 | |
|
119 | 121 | -- main process |
|
120 | 122 | PROCESS |
|
121 | 123 | |
|
122 | 124 | VARIABLE mem_array : mem_array_type; |
|
123 | 125 | |
|
124 | 126 | --- Variables for timing checks |
|
125 | 127 | VARIABLE tPWE_chk : TIME := -10 ns; |
|
126 | 128 | VARIABLE tAW_chk : TIME := -10 ns; |
|
127 | 129 | VARIABLE tSD_chk : TIME := -10 ns; |
|
128 | 130 | VARIABLE tRC_chk : TIME := 0 ns; |
|
129 | 131 | VARIABLE tBAW_chk : TIME := 0 ns; |
|
130 | 132 | VARIABLE tBBW_chk : TIME := 0 ns; |
|
131 | 133 | VARIABLE tBCW_chk : TIME := 0 ns; |
|
132 | 134 | VARIABLE tBDW_chk : TIME := 0 ns; |
|
133 | 135 | VARIABLE tSA_chk : TIME := 0 ns; |
|
134 | 136 | VARIABLE tSA_skew : TIME := 0 ns; |
|
135 | 137 | VARIABLE tAint_chk : TIME := -10 ns; |
|
136 | 138 | |
|
137 | 139 | VARIABLE write_flag : BOOLEAN := true; |
|
138 | 140 | |
|
139 | 141 | VARIABLE accesstime : TIME := 0 ns; |
|
140 | 142 | |
|
141 | 143 | BEGIN |
|
142 | 144 | IF (address_skew'EVENT) THEN |
|
143 | 145 | tSA_skew := NOW; |
|
144 | 146 | END IF; |
|
145 | 147 | |
|
146 | 148 | -- start of write |
|
147 | 149 | IF (write_enable = '1' AND write_enable'EVENT) THEN |
|
148 | 150 | |
|
149 | 151 | DQ(DATA_BITS-1 DOWNTO 0) <= (OTHERS => 'Z') after tHZWE; |
|
150 | 152 | |
|
151 | 153 | IF (A'LAST_EVENT >= tSA) THEN |
|
152 | 154 | address_internal <= A; |
|
153 | 155 | tPWE_chk := NOW; |
|
154 | 156 | tAW_chk := A'LAST_EVENT; |
|
155 | 157 | tAint_chk := NOW; |
|
156 | 158 | write_flag := true; |
|
157 | 159 | |
|
158 | 160 | ELSE |
|
159 | 161 | IF (TimingInfo) THEN |
|
160 | 162 | ASSERT false |
|
161 | 163 | REPORT "Address setup violated"; |
|
162 | 164 | END IF; |
|
163 | 165 | write_flag := false; |
|
164 | 166 | |
|
165 | 167 | END IF; |
|
166 | 168 | |
|
167 | 169 | -- end of write (with CE high or WE high) |
|
168 | 170 | ELSIF (write_enable = '0' AND write_enable'EVENT) THEN |
|
169 | 171 | |
|
170 | 172 | --- check for pulse width |
|
171 | 173 | IF (NOW - tPWE_chk >= tPWE OR NOW - tPWE_chk <= 0.1 ns OR NOW = 0 ns) THEN |
|
172 | 174 | --- pulse width OK, do nothing |
|
173 | 175 | ELSE |
|
174 | 176 | IF (TimingInfo) THEN |
|
175 | 177 | ASSERT false |
|
176 | 178 | REPORT "Pulse Width violation"; |
|
177 | 179 | END IF; |
|
178 | 180 | |
|
179 | 181 | write_flag := false; |
|
180 | 182 | END IF; |
|
181 | 183 | |
|
182 | 184 | |
|
183 | 185 | IF (NOW > 0 ns) THEN |
|
184 | 186 | IF (tSA_skew - tAint_chk > tskew) THEN |
|
185 | 187 | ASSERT false |
|
186 | 188 | REPORT "Negative address setup"; |
|
187 | 189 | write_flag := false; |
|
188 | 190 | END IF; |
|
189 | 191 | END IF; |
|
190 | 192 | |
|
191 | 193 | --- check for address setup with write end, i.e., tAW |
|
192 | 194 | IF (NOW - tAW_chk >= tAW OR NOW = 0 ns) THEN |
|
193 | 195 | --- tAW OK, do nothing |
|
194 | 196 | ELSE |
|
195 | 197 | IF (TimingInfo) THEN |
|
196 | 198 | ASSERT false |
|
197 | 199 | REPORT "Address setup tAW violation"; |
|
198 | 200 | END IF; |
|
199 | 201 | |
|
200 | 202 | write_flag := false; |
|
201 | 203 | END IF; |
|
202 | 204 | |
|
203 | 205 | --- check for data setup with write end, i.e., tSD |
|
204 | 206 | IF (NOW - tSD_chk >= tSD_dataskew OR NOW - tSD_chk <= 0.1 ns OR NOW = 0 ns) THEN |
|
205 | 207 | --- tSD OK, do nothing |
|
206 | 208 | ELSE |
|
207 | 209 | IF (TimingInfo) THEN |
|
208 | 210 | ASSERT false |
|
209 | 211 | REPORT "Data setup tSD violation"; |
|
210 | 212 | END IF; |
|
211 | 213 | write_flag := false; |
|
212 | 214 | END IF; |
|
213 | 215 | |
|
214 | 216 | -- perform write operation if no violations |
|
215 | 217 | IF (write_flag = true) THEN |
|
216 | 218 | |
|
217 | 219 | IF (BLE_b = '1' AND BLE_b'LAST_EVENT = write_enable'LAST_EVENT AND NOW /= 0 ns) THEN |
|
218 | 220 | mem_array(conv_integer1(address_internal))(7 DOWNTO 0) := data_skew(7 DOWNTO 0); |
|
219 | 221 | END IF; |
|
220 | 222 | |
|
221 | 223 | IF (BHE_b = '1' AND BHE_b'LAST_EVENT = write_enable'LAST_EVENT AND NOW /= 0 ns) THEN |
|
222 | 224 | mem_array(conv_integer1(address_internal))(15 DOWNTO 8) := data_skew(15 DOWNTO 8); |
|
223 | 225 | END IF; |
|
224 | 226 | |
|
225 | 227 | IF (BLE_b = '0' AND NOW - tBAW_chk >= tBW) THEN |
|
226 | 228 | mem_array(conv_integer1(address_internal))(7 DOWNTO 0) := data_skew(7 DOWNTO 0); |
|
227 | 229 | ELSIF (NOW - tBAW_chk < tBW AND NOW - tBAW_chk > 0.1 ns AND NOW > 0 ns) THEN |
|
228 | 230 | ASSERT false REPORT "Insufficient pulse width for lower byte to be written"; |
|
229 | 231 | END IF; |
|
230 | 232 | |
|
231 | 233 | IF (BHE_b = '0' AND NOW - tBBW_chk >= tBW) THEN |
|
232 | 234 | mem_array(conv_integer1(address_internal))(15 DOWNTO 8) := data_skew(15 DOWNTO 8); |
|
233 | 235 | ELSIF (NOW - tBBW_chk < tBW AND NOW - tBBW_chk > 0.1 ns AND NOW > 0 ns) THEN |
|
234 | 236 | ASSERT false REPORT "Insufficient pulse width for higher byte to be written"; |
|
235 | 237 | END IF; |
|
236 | 238 | |
|
237 | 239 | |
|
238 | 240 | -------------------------------------------------------------------------------JC\/ |
|
239 |
all_mem_array_obs: FOR I IN 0 TO |
|
|
241 | all_mem_array_obs: FOR I IN 0 TO MEM_ARRAY_DEBUG-1 LOOP | |
|
240 | 242 | IF I + ((2**15) *0) < depth THEN mem_array_0(I) <= mem_array(I+((2**15) *0)); END IF; |
|
241 | 243 | IF I + ((2**15) *1) < depth THEN mem_array_1(I) <= mem_array(I+((2**15) *1)); END IF; |
|
242 | 244 | IF I + ((2**15) *2) < depth THEN mem_array_2(I) <= mem_array(I+((2**15) *2)); END IF; |
|
243 | 245 | IF I + ((2**15) *3) < depth THEN mem_array_3(I) <= mem_array(I+((2**15) *3)); END IF; |
|
244 | 246 | END LOOP all_mem_array_obs; |
|
245 | 247 | -------------------------------------------------------------------------------JC/\ |
|
246 | 248 | |
|
247 | 249 | END IF; |
|
248 | 250 | |
|
249 | 251 | -- end of write (with BLE high) |
|
250 | 252 | ELSIF (BLE_b'EVENT AND NOT(BHE_b'EVENT) AND write_enable = '1') THEN |
|
251 | 253 | |
|
252 | 254 | IF (BLE_b = '0') THEN |
|
253 | 255 | |
|
254 | 256 | --- Reset timing variables |
|
255 | 257 | tAW_chk := A'LAST_EVENT; |
|
256 | 258 | tBAW_chk := NOW; |
|
257 | 259 | write_flag := true; |
|
258 | 260 | |
|
259 | 261 | ELSIF (BLE_b = '1') THEN |
|
260 | 262 | |
|
261 | 263 | --- check for pulse width |
|
262 | 264 | IF (NOW - tPWE_chk >= tPWE) THEN |
|
263 | 265 | --- tPWE OK, do nothing |
|
264 | 266 | ELSE |
|
265 | 267 | IF (TimingInfo) THEN |
|
266 | 268 | ASSERT false |
|
267 | 269 | REPORT "Pulse Width violation"; |
|
268 | 270 | END IF; |
|
269 | 271 | |
|
270 | 272 | write_flag := false; |
|
271 | 273 | END IF; |
|
272 | 274 | |
|
273 | 275 | --- check for address setup with write end, i.e., tAW |
|
274 | 276 | IF (NOW - tAW_chk >= tAW) THEN |
|
275 | 277 | --- tAW OK, do nothing |
|
276 | 278 | ELSE |
|
277 | 279 | IF (TimingInfo) THEN |
|
278 | 280 | ASSERT false |
|
279 | 281 | REPORT "Address setup tAW violation for Lower Byte Write"; |
|
280 | 282 | END IF; |
|
281 | 283 | |
|
282 | 284 | write_flag := false; |
|
283 | 285 | END IF; |
|
284 | 286 | |
|
285 | 287 | --- check for byte write setup with write end, i.e., tBW |
|
286 | 288 | IF (NOW - tBAW_chk >= tBW) THEN |
|
287 | 289 | --- tBW OK, do nothing |
|
288 | 290 | ELSE |
|
289 | 291 | IF (TimingInfo) THEN |
|
290 | 292 | ASSERT false |
|
291 | 293 | REPORT "Lower Byte setup tBW violation"; |
|
292 | 294 | END IF; |
|
293 | 295 | |
|
294 | 296 | write_flag := false; |
|
295 | 297 | END IF; |
|
296 | 298 | |
|
297 | 299 | --- check for data setup with write end, i.e., tSD |
|
298 | 300 | IF (NOW - tSD_chk >= tSD_dataskew OR NOW - tSD_chk <= 0.1 ns OR NOW = 0 ns) THEN |
|
299 | 301 | --- tSD OK, do nothing |
|
300 | 302 | ELSE |
|
301 | 303 | IF (TimingInfo) THEN |
|
302 | 304 | ASSERT false |
|
303 | 305 | REPORT "Data setup tSD violation for Lower Byte Write"; |
|
304 | 306 | END IF; |
|
305 | 307 | |
|
306 | 308 | write_flag := false; |
|
307 | 309 | END IF; |
|
308 | 310 | |
|
309 | 311 | --- perform WRITE operation if no violations |
|
310 | 312 | IF (write_flag = true) THEN |
|
311 | 313 | mem_array(conv_integer1(address_internal))(7 DOWNTO 0) := data_skew(7 DOWNTO 0); |
|
312 | 314 | IF (BHE_b = '0') THEN |
|
313 | 315 | mem_array(conv_integer1(address_internal))(15 DOWNTO 8) := data_skew(15 DOWNTO 8); |
|
314 | 316 | END IF; |
|
315 | 317 | END IF; |
|
316 | 318 | |
|
317 | 319 | --- Reset timing variables |
|
318 | 320 | tAW_chk := A'LAST_EVENT; |
|
319 | 321 | tBAW_chk := NOW; |
|
320 | 322 | write_flag := true; |
|
321 | 323 | |
|
322 | 324 | END IF; |
|
323 | 325 | |
|
324 | 326 | -- end of write (with BHE high) |
|
325 | 327 | ELSIF (BHE_b'EVENT AND NOT(BLE_b'EVENT) AND write_enable = '1') THEN |
|
326 | 328 | |
|
327 | 329 | IF (BHE_b = '0') THEN |
|
328 | 330 | |
|
329 | 331 | --- Reset timing variables |
|
330 | 332 | tAW_chk := A'LAST_EVENT; |
|
331 | 333 | tBBW_chk := NOW; |
|
332 | 334 | write_flag := true; |
|
333 | 335 | |
|
334 | 336 | ELSIF (BHE_b = '1') THEN |
|
335 | 337 | |
|
336 | 338 | --- check for pulse width |
|
337 | 339 | IF (NOW - tPWE_chk >= tPWE) THEN |
|
338 | 340 | --- tPWE OK, do nothing |
|
339 | 341 | ELSE |
|
340 | 342 | IF (TimingInfo) THEN |
|
341 | 343 | ASSERT false |
|
342 | 344 | REPORT "Pulse Width violation"; |
|
343 | 345 | END IF; |
|
344 | 346 | |
|
345 | 347 | write_flag := false; |
|
346 | 348 | END IF; |
|
347 | 349 | |
|
348 | 350 | --- check for address setup with write end, i.e., tAW |
|
349 | 351 | IF (NOW - tAW_chk >= tAW) THEN |
|
350 | 352 | --- tAW OK, do nothing |
|
351 | 353 | ELSE |
|
352 | 354 | IF (TimingInfo) THEN |
|
353 | 355 | ASSERT false |
|
354 | 356 | REPORT "Address setup tAW violation for Upper Byte Write"; |
|
355 | 357 | END IF; |
|
356 | 358 | write_flag := false; |
|
357 | 359 | END IF; |
|
358 | 360 | |
|
359 | 361 | --- check for byte setup with write end, i.e., tBW |
|
360 | 362 | IF (NOW - tBBW_chk >= tBW) THEN |
|
361 | 363 | --- tBW OK, do nothing |
|
362 | 364 | ELSE |
|
363 | 365 | IF (TimingInfo) THEN |
|
364 | 366 | ASSERT false |
|
365 | 367 | REPORT "Upper Byte setup tBW violation"; |
|
366 | 368 | END IF; |
|
367 | 369 | |
|
368 | 370 | write_flag := false; |
|
369 | 371 | END IF; |
|
370 | 372 | |
|
371 | 373 | --- check for data setup with write end, i.e., tSD |
|
372 | 374 | IF (NOW - tSD_chk >= tSD_dataskew OR NOW - tSD_chk <= 0.1 ns OR NOW = 0 ns) THEN |
|
373 | 375 | --- tSD OK, do nothing |
|
374 | 376 | ELSE |
|
375 | 377 | IF (TimingInfo) THEN |
|
376 | 378 | ASSERT false |
|
377 | 379 | REPORT "Data setup tSD violation for Upper Byte Write"; |
|
378 | 380 | END IF; |
|
379 | 381 | |
|
380 | 382 | write_flag := false; |
|
381 | 383 | END IF; |
|
382 | 384 | |
|
383 | 385 | --- perform WRITE operation if no violations |
|
384 | 386 | |
|
385 | 387 | IF (write_flag = true) THEN |
|
386 | 388 | mem_array(conv_integer1(address_internal))(15 DOWNTO 8) := data_skew(15 DOWNTO 8); |
|
387 | 389 | IF (BLE_b = '0') THEN |
|
388 | 390 | mem_array(conv_integer1(address_internal))(7 DOWNTO 0) := data_skew(7 DOWNTO 0); |
|
389 | 391 | END IF; |
|
390 | 392 | |
|
391 | 393 | END IF; |
|
392 | 394 | |
|
393 | 395 | --- Reset timing variables |
|
394 | 396 | tAW_chk := A'LAST_EVENT; |
|
395 | 397 | tBBW_chk := NOW; |
|
396 | 398 | write_flag := true; |
|
397 | 399 | |
|
398 | 400 | END IF; |
|
399 | 401 | |
|
400 | 402 | END IF; |
|
401 | 403 | --- END OF WRITE |
|
402 | 404 | |
|
403 | 405 | IF (data_skew'EVENT AND read_enable /= '1') THEN |
|
404 | 406 | tSD_chk := NOW; |
|
405 | 407 | END IF; |
|
406 | 408 | |
|
407 | 409 | --- START of READ |
|
408 | 410 | |
|
409 | 411 | --- Tri-state the data bus if CE or OE disabled |
|
410 | 412 | IF (read_enable = '0' AND read_enable'EVENT) THEN |
|
411 | 413 | IF (OE_b'LAST_EVENT >= CE_b'LAST_EVENT) THEN |
|
412 | 414 | DQ <= (OTHERS => 'Z') after tHZCE; |
|
413 | 415 | ELSIF (CE_b'LAST_EVENT > OE_b'LAST_EVENT) THEN |
|
414 | 416 | DQ <= (OTHERS => 'Z') after tHZOE; |
|
415 | 417 | END IF; |
|
416 | 418 | END IF; |
|
417 | 419 | |
|
418 | 420 | --- Address-controlled READ operation |
|
419 | 421 | IF (A'EVENT) THEN |
|
420 | 422 | IF (A'LAST_EVENT = CE_b'LAST_EVENT AND CE_b = '1') THEN |
|
421 | 423 | DQ <= (OTHERS => 'Z') after tHZCE; |
|
422 | 424 | END IF; |
|
423 | 425 | |
|
424 | 426 | IF (NOW - tRC_chk >= tRC OR NOW - tRC_chk <= 0.1 ns OR tRC_chk = 0 ns) THEN |
|
425 | 427 | --- tRC OK, do nothing |
|
426 | 428 | ELSE |
|
427 | 429 | |
|
428 | 430 | IF (TimingInfo) THEN |
|
429 | 431 | ASSERT false |
|
430 | 432 | REPORT "Read Cycle time tRC violation"; |
|
431 | 433 | END IF; |
|
432 | 434 | |
|
433 | 435 | END IF; |
|
434 | 436 | |
|
435 | 437 | IF (read_enable = '1') THEN |
|
436 | 438 | |
|
437 | 439 | IF (BLE_b = '0') THEN |
|
438 | 440 | DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A))(7 DOWNTO 0) AFTER tAA; |
|
439 | 441 | END IF; |
|
440 | 442 | |
|
441 | 443 | IF (BHE_b = '0') THEN |
|
442 | 444 | DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A))(15 DOWNTO 8) AFTER tAA; |
|
443 | 445 | END IF; |
|
444 | 446 | |
|
445 | 447 | tRC_chk := NOW; |
|
446 | 448 | |
|
447 | 449 | END IF; |
|
448 | 450 | |
|
449 | 451 | IF (write_enable = '1') THEN |
|
450 | 452 | --- do nothing |
|
451 | 453 | END IF; |
|
452 | 454 | |
|
453 | 455 | END IF; |
|
454 | 456 | |
|
455 | 457 | IF (read_enable = '0' AND read_enable'EVENT) THEN |
|
456 | 458 | DQ <= (OTHERS => 'Z') after tHZCE; |
|
457 | 459 | IF (NOW - tRC_chk >= tRC OR tRC_chk = 0 ns OR A'LAST_EVENT = read_enable'LAST_EVENT) THEN |
|
458 | 460 | --- tRC_chk needs to be reset when read ends |
|
459 | 461 | tRC_CHK := 0 ns; |
|
460 | 462 | ELSE |
|
461 | 463 | IF (TimingInfo) THEN |
|
462 | 464 | ASSERT false |
|
463 | 465 | REPORT "Read Cycle time tRC violation"; |
|
464 | 466 | END IF; |
|
465 | 467 | tRC_CHK := 0 ns; |
|
466 | 468 | END IF; |
|
467 | 469 | |
|
468 | 470 | END IF; |
|
469 | 471 | |
|
470 | 472 | --- READ operation triggered by CE/OE/BHE/BLE |
|
471 | 473 | IF (read_enable = '1' AND read_enable'EVENT) THEN |
|
472 | 474 | |
|
473 | 475 | tRC_chk := NOW; |
|
474 | 476 | |
|
475 | 477 | --- CE triggered READ |
|
476 | 478 | IF (CE_b'LAST_EVENT = read_enable'LAST_EVENT) THEN -- changed rev2 |
|
477 | 479 | |
|
478 | 480 | IF (BLE_b = '0') THEN |
|
479 | 481 | DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER tACE; |
|
480 | 482 | END IF; |
|
481 | 483 | |
|
482 | 484 | IF (BHE_b = '0') THEN |
|
483 | 485 | DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER tACE; |
|
484 | 486 | END IF; |
|
485 | 487 | |
|
486 | 488 | END IF; |
|
487 | 489 | |
|
488 | 490 | |
|
489 | 491 | --- OE triggered READ |
|
490 | 492 | IF (OE_b'LAST_EVENT = read_enable'LAST_EVENT) THEN |
|
491 | 493 | |
|
492 | 494 | -- if address or CE changes before OE such that tAA/tACE > tDOE |
|
493 | 495 | IF (CE_b'LAST_EVENT < tACE - tDOE AND A'LAST_EVENT < tAA - tDOE) THEN |
|
494 | 496 | |
|
495 | 497 | IF (A'LAST_EVENT < CE_b'LAST_EVENT) THEN |
|
496 | 498 | |
|
497 | 499 | accesstime := tAA-A'LAST_EVENT; |
|
498 | 500 | IF (BLE_b = '0') THEN |
|
499 | 501 | DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER accesstime; |
|
500 | 502 | END IF; |
|
501 | 503 | |
|
502 | 504 | IF (BHE_b = '0') THEN |
|
503 | 505 | DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER accesstime; |
|
504 | 506 | END IF; |
|
505 | 507 | |
|
506 | 508 | ELSE |
|
507 | 509 | accesstime := tACE-CE_b'LAST_EVENT; |
|
508 | 510 | IF (BLE_b = '0') THEN |
|
509 | 511 | DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER accesstime; |
|
510 | 512 | END IF; |
|
511 | 513 | |
|
512 | 514 | IF (BHE_b = '0') THEN |
|
513 | 515 | DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER accesstime; |
|
514 | 516 | END IF; |
|
515 | 517 | END IF; |
|
516 | 518 | |
|
517 | 519 | -- if address changes before OE such that tAA > tDOE |
|
518 | 520 | ELSIF (A'LAST_EVENT < tAA - tDOE) THEN |
|
519 | 521 | |
|
520 | 522 | accesstime := tAA-A'LAST_EVENT; |
|
521 | 523 | IF (BLE_b = '0') THEN |
|
522 | 524 | DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER accesstime; |
|
523 | 525 | END IF; |
|
524 | 526 | |
|
525 | 527 | IF (BHE_b = '0') THEN |
|
526 | 528 | DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER accesstime; |
|
527 | 529 | END IF; |
|
528 | 530 | |
|
529 | 531 | -- if CE changes before OE such that tACE > tDOE |
|
530 | 532 | ELSIF (CE_b'LAST_EVENT < tACE - tDOE) THEN |
|
531 | 533 | |
|
532 | 534 | accesstime := tACE-CE_b'LAST_EVENT; |
|
533 | 535 | IF (BLE_b = '0') THEN |
|
534 | 536 | DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER accesstime; |
|
535 | 537 | END IF; |
|
536 | 538 | |
|
537 | 539 | IF (BHE_b = '0') THEN |
|
538 | 540 | DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER accesstime; |
|
539 | 541 | END IF; |
|
540 | 542 | |
|
541 | 543 | -- if OE changes such that tDOE > tAA/tACE |
|
542 | 544 | ELSE |
|
543 | 545 | IF (BLE_b = '0') THEN |
|
544 | 546 | DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER tDOE; |
|
545 | 547 | END IF; |
|
546 | 548 | |
|
547 | 549 | IF (BHE_b = '0') THEN |
|
548 | 550 | DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER tDOE; |
|
549 | 551 | END IF; |
|
550 | 552 | |
|
551 | 553 | END IF; |
|
552 | 554 | |
|
553 | 555 | END IF; |
|
554 | 556 | --- END of OE triggered READ |
|
555 | 557 | |
|
556 | 558 | --- BLE/BHE triggered READ |
|
557 | 559 | IF (BLE_b'LAST_EVENT = read_enable'LAST_EVENT OR BHE_b'LAST_EVENT = read_enable'LAST_EVENT) THEN |
|
558 | 560 | |
|
559 | 561 | -- if address or CE changes before BHE/BLE such that tAA/tACE > tDBE |
|
560 | 562 | IF (CE_b'LAST_EVENT < tACE - tDBE AND A'LAST_EVENT < tAA - tDBE) THEN |
|
561 | 563 | |
|
562 | 564 | IF (A'LAST_EVENT < BLE_b'LAST_EVENT) THEN |
|
563 | 565 | accesstime := tAA-A'LAST_EVENT; |
|
564 | 566 | |
|
565 | 567 | IF (BLE_b = '0') THEN |
|
566 | 568 | DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER accesstime; |
|
567 | 569 | END IF; |
|
568 | 570 | |
|
569 | 571 | IF (BHE_b = '0') THEN |
|
570 | 572 | DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER accesstime; |
|
571 | 573 | END IF; |
|
572 | 574 | |
|
573 | 575 | ELSE |
|
574 | 576 | accesstime := tACE-CE_b'LAST_EVENT; |
|
575 | 577 | |
|
576 | 578 | IF (BLE_b = '0') THEN |
|
577 | 579 | DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER accesstime; |
|
578 | 580 | END IF; |
|
579 | 581 | |
|
580 | 582 | IF (BHE_b = '0') THEN |
|
581 | 583 | DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER accesstime; |
|
582 | 584 | END IF; |
|
583 | 585 | END IF; |
|
584 | 586 | |
|
585 | 587 | -- if address changes before BHE/BLE such that tAA > tDBE |
|
586 | 588 | ELSIF (A'LAST_EVENT < tAA - tDBE) THEN |
|
587 | 589 | accesstime := tAA-A'LAST_EVENT; |
|
588 | 590 | |
|
589 | 591 | IF (BLE_b = '0') THEN |
|
590 | 592 | DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER accesstime; |
|
591 | 593 | END IF; |
|
592 | 594 | |
|
593 | 595 | IF (BHE_b = '0') THEN |
|
594 | 596 | DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER accesstime; |
|
595 | 597 | END IF; |
|
596 | 598 | |
|
597 | 599 | -- if CE changes before BHE/BLE such that tACE > tDBE |
|
598 | 600 | ELSIF (CE_b'LAST_EVENT < tACE - tDBE) THEN |
|
599 | 601 | accesstime := tACE-CE_b'LAST_EVENT; |
|
600 | 602 | |
|
601 | 603 | IF (BLE_b = '0') THEN |
|
602 | 604 | DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER accesstime; |
|
603 | 605 | END IF; |
|
604 | 606 | |
|
605 | 607 | IF (BHE_b = '0') THEN |
|
606 | 608 | DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER accesstime; |
|
607 | 609 | END IF; |
|
608 | 610 | |
|
609 | 611 | -- if BHE/BLE changes such that tDBE > tAA/tACE |
|
610 | 612 | ELSE |
|
611 | 613 | IF (BLE_b = '0') THEN |
|
612 | 614 | DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER tDBE; |
|
613 | 615 | END IF; |
|
614 | 616 | |
|
615 | 617 | IF (BHE_b = '0') THEN |
|
616 | 618 | DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER tDBE; |
|
617 | 619 | END IF; |
|
618 | 620 | |
|
619 | 621 | END IF; |
|
620 | 622 | |
|
621 | 623 | END IF; |
|
622 | 624 | -- END of BHE/BLE controlled READ |
|
623 | 625 | |
|
624 | 626 | IF (WE_b'LAST_EVENT = read_enable'LAST_EVENT) THEN |
|
625 | 627 | |
|
626 | 628 | IF (BLE_b = '0') THEN |
|
627 | 629 | DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER tACE; |
|
628 | 630 | END IF; |
|
629 | 631 | |
|
630 | 632 | IF (BHE_b = '0') THEN |
|
631 | 633 | DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER tACE; |
|
632 | 634 | END IF; |
|
633 | 635 | |
|
634 | 636 | END IF; |
|
635 | 637 | |
|
636 | 638 | END IF; |
|
637 | 639 | --- END OF CE/OE/BHE/BLE controlled READ |
|
638 | 640 | |
|
639 | 641 | --- If either BHE or BLE toggle during read mode |
|
640 | 642 | IF (BLE_b'EVENT AND BLE_b = '0' AND read_enable = '1' AND NOT(read_enable'EVENT)) THEN |
|
641 | 643 | DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER tDBE; |
|
642 | 644 | END IF; |
|
643 | 645 | |
|
644 | 646 | IF (BHE_b'EVENT AND BHE_b = '0' AND read_enable = '1' AND NOT(read_enable'EVENT)) THEN |
|
645 | 647 | DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER tDBE; |
|
646 | 648 | END IF; |
|
647 | 649 | |
|
648 | 650 | --- tri-state bus depending on BHE/BLE |
|
649 | 651 | IF (BLE_b'EVENT AND BLE_b = '1') THEN |
|
650 | 652 | DQ (7 DOWNTO 0) <= (OTHERS => 'Z') after tHZBE; |
|
651 | 653 | END IF; |
|
652 | 654 | |
|
653 | 655 | IF (BHE_b'EVENT AND BHE_b = '1') THEN |
|
654 | 656 | DQ (15 DOWNTO 8) <= (OTHERS => 'Z') after tHZBE; |
|
655 | 657 | END IF; |
|
656 | 658 | |
|
657 | 659 | WAIT ON write_enable, A, read_enable, DQ, BLE_b, BHE_b, data_skew, address_skew; |
|
658 | 660 | |
|
659 | 661 | END PROCESS; |
|
660 | 662 | |
|
661 | 663 | |
|
662 | 664 | END behave_arch; |
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