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EQM debug
pellion -
r566:69ac13e4d137 JC
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1 LIBRARY ieee;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
2 USE ieee.std_logic_1164.ALL;
3 USE ieee.numeric_std.ALL;
3 USE ieee.numeric_std.ALL;
4 use IEEE.std_logic_textio.all;
4 use IEEE.std_logic_textio.all;
5 LIBRARY STD;
5 LIBRARY STD;
6 use std.textio.all;
6 use std.textio.all;
7
7
8 LIBRARY grlib;
8 LIBRARY grlib;
9 USE grlib.stdlib.ALL;
9 USE grlib.stdlib.ALL;
10 LIBRARY gaisler;
10 LIBRARY gaisler;
11 USE gaisler.libdcom.ALL;
11 USE gaisler.libdcom.ALL;
12 USE gaisler.sim.ALL;
12 USE gaisler.sim.ALL;
13 USE gaisler.jtagtst.ALL;
13 USE gaisler.jtagtst.ALL;
14 LIBRARY techmap;
14 LIBRARY techmap;
15 USE techmap.gencomp.ALL;
15 USE techmap.gencomp.ALL;
16
16
17 LIBRARY lpp;
17 LIBRARY lpp;
18 USE lpp.lpp_sim_pkg.ALL;
18 USE lpp.lpp_sim_pkg.ALL;
19 USE lpp.lpp_lfr_sim_pkg.ALL;
19 USE lpp.lpp_lfr_sim_pkg.ALL;
20 USE lpp.lpp_lfr_apbreg_pkg.ALL;
20 USE lpp.lpp_lfr_apbreg_pkg.ALL;
21 USE lpp.lpp_lfr_time_management_apbreg_pkg.ALL;
21 USE lpp.lpp_lfr_management_apbreg_pkg.ALL;
22
22
23
23
24 ENTITY testbench IS
24 ENTITY testbench IS
25 END;
25 END;
26
26
27 ARCHITECTURE behav OF testbench IS
27 ARCHITECTURE behav OF testbench IS
28
28
29 COMPONENT MINI_LFR_top
29 COMPONENT MINI_LFR_top
30 PORT (
30 PORT (
31 clk_50 : IN STD_LOGIC;
31 clk_50 : IN STD_LOGIC;
32 clk_49 : IN STD_LOGIC;
32 clk_49 : IN STD_LOGIC;
33 reset : IN STD_LOGIC;
33 reset : IN STD_LOGIC;
34 BP0 : IN STD_LOGIC;
34 BP0 : IN STD_LOGIC;
35 BP1 : IN STD_LOGIC;
35 BP1 : IN STD_LOGIC;
36 LED0 : OUT STD_LOGIC;
36 LED0 : OUT STD_LOGIC;
37 LED1 : OUT STD_LOGIC;
37 LED1 : OUT STD_LOGIC;
38 LED2 : OUT STD_LOGIC;
38 LED2 : OUT STD_LOGIC;
39 TXD1 : IN STD_LOGIC;
39 TXD1 : IN STD_LOGIC;
40 RXD1 : OUT STD_LOGIC;
40 RXD1 : OUT STD_LOGIC;
41 nCTS1 : OUT STD_LOGIC;
41 nCTS1 : OUT STD_LOGIC;
42 nRTS1 : IN STD_LOGIC;
42 nRTS1 : IN STD_LOGIC;
43 TXD2 : IN STD_LOGIC;
43 TXD2 : IN STD_LOGIC;
44 RXD2 : OUT STD_LOGIC;
44 RXD2 : OUT STD_LOGIC;
45 nCTS2 : OUT STD_LOGIC;
45 nCTS2 : OUT STD_LOGIC;
46 nDTR2 : IN STD_LOGIC;
46 nDTR2 : IN STD_LOGIC;
47 nRTS2 : IN STD_LOGIC;
47 nRTS2 : IN STD_LOGIC;
48 nDCD2 : OUT STD_LOGIC;
48 nDCD2 : OUT STD_LOGIC;
49 IO0 : INOUT STD_LOGIC;
49 IO0 : INOUT STD_LOGIC;
50 IO1 : INOUT STD_LOGIC;
50 IO1 : INOUT STD_LOGIC;
51 IO2 : INOUT STD_LOGIC;
51 IO2 : INOUT STD_LOGIC;
52 IO3 : INOUT STD_LOGIC;
52 IO3 : INOUT STD_LOGIC;
53 IO4 : INOUT STD_LOGIC;
53 IO4 : INOUT STD_LOGIC;
54 IO5 : INOUT STD_LOGIC;
54 IO5 : INOUT STD_LOGIC;
55 IO6 : INOUT STD_LOGIC;
55 IO6 : INOUT STD_LOGIC;
56 IO7 : INOUT STD_LOGIC;
56 IO7 : INOUT STD_LOGIC;
57 IO8 : INOUT STD_LOGIC;
57 IO8 : INOUT STD_LOGIC;
58 IO9 : INOUT STD_LOGIC;
58 IO9 : INOUT STD_LOGIC;
59 IO10 : INOUT STD_LOGIC;
59 IO10 : INOUT STD_LOGIC;
60 IO11 : INOUT STD_LOGIC;
60 IO11 : INOUT STD_LOGIC;
61 SPW_EN : OUT STD_LOGIC;
61 SPW_EN : OUT STD_LOGIC;
62 SPW_NOM_DIN : IN STD_LOGIC;
62 SPW_NOM_DIN : IN STD_LOGIC;
63 SPW_NOM_SIN : IN STD_LOGIC;
63 SPW_NOM_SIN : IN STD_LOGIC;
64 SPW_NOM_DOUT : OUT STD_LOGIC;
64 SPW_NOM_DOUT : OUT STD_LOGIC;
65 SPW_NOM_SOUT : OUT STD_LOGIC;
65 SPW_NOM_SOUT : OUT STD_LOGIC;
66 SPW_RED_DIN : IN STD_LOGIC;
66 SPW_RED_DIN : IN STD_LOGIC;
67 SPW_RED_SIN : IN STD_LOGIC;
67 SPW_RED_SIN : IN STD_LOGIC;
68 SPW_RED_DOUT : OUT STD_LOGIC;
68 SPW_RED_DOUT : OUT STD_LOGIC;
69 SPW_RED_SOUT : OUT STD_LOGIC;
69 SPW_RED_SOUT : OUT STD_LOGIC;
70 ADC_nCS : OUT STD_LOGIC;
70 ADC_nCS : OUT STD_LOGIC;
71 ADC_CLK : OUT STD_LOGIC;
71 ADC_CLK : OUT STD_LOGIC;
72 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
72 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
73 SRAM_nWE : OUT STD_LOGIC;
73 SRAM_nWE : OUT STD_LOGIC;
74 SRAM_CE : OUT STD_LOGIC;
74 SRAM_CE : OUT STD_LOGIC;
75 SRAM_nOE : OUT STD_LOGIC;
75 SRAM_nOE : OUT STD_LOGIC;
76 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
76 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
77 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
77 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
78 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0));
78 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0));
79 END COMPONENT;
79 END COMPONENT;
80
80
81 -----------------------------------------------------------------------------
81 -----------------------------------------------------------------------------
82 SIGNAL clk_50 : STD_LOGIC := '0';
82 SIGNAL clk_50 : STD_LOGIC := '0';
83 SIGNAL clk_49 : STD_LOGIC := '0';
83 SIGNAL clk_49 : STD_LOGIC := '0';
84 SIGNAL reset : STD_LOGIC;
84 SIGNAL reset : STD_LOGIC;
85 SIGNAL BP0 : STD_LOGIC;
85 SIGNAL BP0 : STD_LOGIC;
86 SIGNAL BP1 : STD_LOGIC;
86 SIGNAL BP1 : STD_LOGIC;
87 SIGNAL LED0 : STD_LOGIC;
87 SIGNAL LED0 : STD_LOGIC;
88 SIGNAL LED1 : STD_LOGIC;
88 SIGNAL LED1 : STD_LOGIC;
89 SIGNAL LED2 : STD_LOGIC;
89 SIGNAL LED2 : STD_LOGIC;
90 SIGNAL TXD1 : STD_LOGIC;
90 SIGNAL TXD1 : STD_LOGIC;
91 SIGNAL RXD1 : STD_LOGIC;
91 SIGNAL RXD1 : STD_LOGIC;
92 SIGNAL nCTS1 : STD_LOGIC;
92 SIGNAL nCTS1 : STD_LOGIC;
93 SIGNAL nRTS1 : STD_LOGIC;
93 SIGNAL nRTS1 : STD_LOGIC;
94 SIGNAL TXD2 : STD_LOGIC;
94 SIGNAL TXD2 : STD_LOGIC;
95 SIGNAL RXD2 : STD_LOGIC;
95 SIGNAL RXD2 : STD_LOGIC;
96 SIGNAL nCTS2 : STD_LOGIC;
96 SIGNAL nCTS2 : STD_LOGIC;
97 SIGNAL nDTR2 : STD_LOGIC;
97 SIGNAL nDTR2 : STD_LOGIC;
98 SIGNAL nRTS2 : STD_LOGIC;
98 SIGNAL nRTS2 : STD_LOGIC;
99 SIGNAL nDCD2 : STD_LOGIC;
99 SIGNAL nDCD2 : STD_LOGIC;
100 SIGNAL IO0 : STD_LOGIC;
100 SIGNAL IO0 : STD_LOGIC;
101 SIGNAL IO1 : STD_LOGIC;
101 SIGNAL IO1 : STD_LOGIC;
102 SIGNAL IO2 : STD_LOGIC;
102 SIGNAL IO2 : STD_LOGIC;
103 SIGNAL IO3 : STD_LOGIC;
103 SIGNAL IO3 : STD_LOGIC;
104 SIGNAL IO4 : STD_LOGIC;
104 SIGNAL IO4 : STD_LOGIC;
105 SIGNAL IO5 : STD_LOGIC;
105 SIGNAL IO5 : STD_LOGIC;
106 SIGNAL IO6 : STD_LOGIC;
106 SIGNAL IO6 : STD_LOGIC;
107 SIGNAL IO7 : STD_LOGIC;
107 SIGNAL IO7 : STD_LOGIC;
108 SIGNAL IO8 : STD_LOGIC;
108 SIGNAL IO8 : STD_LOGIC;
109 SIGNAL IO9 : STD_LOGIC;
109 SIGNAL IO9 : STD_LOGIC;
110 SIGNAL IO10 : STD_LOGIC;
110 SIGNAL IO10 : STD_LOGIC;
111 SIGNAL IO11 : STD_LOGIC;
111 SIGNAL IO11 : STD_LOGIC;
112 SIGNAL SPW_EN : STD_LOGIC;
112 SIGNAL SPW_EN : STD_LOGIC;
113 SIGNAL SPW_NOM_DIN : STD_LOGIC;
113 SIGNAL SPW_NOM_DIN : STD_LOGIC;
114 SIGNAL SPW_NOM_SIN : STD_LOGIC;
114 SIGNAL SPW_NOM_SIN : STD_LOGIC;
115 SIGNAL SPW_NOM_DOUT : STD_LOGIC;
115 SIGNAL SPW_NOM_DOUT : STD_LOGIC;
116 SIGNAL SPW_NOM_SOUT : STD_LOGIC;
116 SIGNAL SPW_NOM_SOUT : STD_LOGIC;
117 SIGNAL SPW_RED_DIN : STD_LOGIC;
117 SIGNAL SPW_RED_DIN : STD_LOGIC;
118 SIGNAL SPW_RED_SIN : STD_LOGIC;
118 SIGNAL SPW_RED_SIN : STD_LOGIC;
119 SIGNAL SPW_RED_DOUT : STD_LOGIC;
119 SIGNAL SPW_RED_DOUT : STD_LOGIC;
120 SIGNAL SPW_RED_SOUT : STD_LOGIC;
120 SIGNAL SPW_RED_SOUT : STD_LOGIC;
121 SIGNAL ADC_nCS : STD_LOGIC;
121 SIGNAL ADC_nCS : STD_LOGIC;
122 SIGNAL ADC_CLK : STD_LOGIC;
122 SIGNAL ADC_CLK : STD_LOGIC;
123 SIGNAL ADC_SDO : STD_LOGIC_VECTOR(7 DOWNTO 0);
123 SIGNAL ADC_SDO : STD_LOGIC_VECTOR(7 DOWNTO 0);
124 SIGNAL SRAM_nWE : STD_LOGIC;
124 SIGNAL SRAM_nWE : STD_LOGIC;
125 SIGNAL SRAM_CE : STD_LOGIC;
125 SIGNAL SRAM_CE : STD_LOGIC;
126 SIGNAL SRAM_nOE : STD_LOGIC;
126 SIGNAL SRAM_nOE : STD_LOGIC;
127 SIGNAL SRAM_nBE : STD_LOGIC_VECTOR(3 DOWNTO 0);
127 SIGNAL SRAM_nBE : STD_LOGIC_VECTOR(3 DOWNTO 0);
128 SIGNAL SRAM_A : STD_LOGIC_VECTOR(19 DOWNTO 0);
128 SIGNAL SRAM_A : STD_LOGIC_VECTOR(19 DOWNTO 0);
129 SIGNAL SRAM_DQ : STD_LOGIC_VECTOR(31 DOWNTO 0);
129 SIGNAL SRAM_DQ : STD_LOGIC_VECTOR(31 DOWNTO 0);
130 -----------------------------------------------------------------------------
130 -----------------------------------------------------------------------------
131
131
132 CONSTANT ADDR_BASE_LFR : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000F";
132 CONSTANT ADDR_BASE_LFR : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000F";
133 CONSTANT ADDR_BASE_TIME_MANAGMENT : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"800006";
133 CONSTANT ADDR_BASE_TIME_MANAGMENT : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"800006";
134 CONSTANT ADDR_BASE_GPIO : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000B";
134 CONSTANT ADDR_BASE_GPIO : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000B";
135
135
136
136
137 SIGNAL message_simu : STRING(1 TO 15) := "---------------";
137 SIGNAL message_simu : STRING(1 TO 15) := "---------------";
138 SIGNAL data_message : STRING(1 TO 15) := "---------------";
138 SIGNAL data_message : STRING(1 TO 15) := "---------------";
139 SIGNAL data_read : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
139 SIGNAL data_read : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
140
140
141 BEGIN
141 BEGIN
142
142
143 -----------------------------------------------------------------------------
143 -----------------------------------------------------------------------------
144 -- TB
144 -- TB
145 -----------------------------------------------------------------------------
145 -----------------------------------------------------------------------------
146 PROCESS
146 PROCESS
147 CONSTANT txp : TIME := 320 ns;
147 CONSTANT txp : TIME := 320 ns;
148 VARIABLE data_read_v : STD_LOGIC_VECTOR(31 DOWNTO 0);
148 VARIABLE data_read_v : STD_LOGIC_VECTOR(31 DOWNTO 0);
149 BEGIN -- PROCESS
149 BEGIN -- PROCESS
150 TXD1 <= '1';
150 TXD1 <= '1';
151 reset <= '0';
151 reset <= '0';
152 WAIT FOR 500 ns;
152 WAIT FOR 500 ns;
153 reset <= '1';
153 reset <= '1';
154 WAIT FOR 10000 ns;
154 WAIT FOR 10000 ns;
155 message_simu <= "0 - UART init ";
155 message_simu <= "0 - UART init ";
156 UART_INIT(TXD1,txp);
156 UART_INIT(TXD1,txp);
157
157
158 message_simu <= "1 - UART test ";
158 message_simu <= "1 - UART test ";
159 UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000010",X"0000FFFF");
159 UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000010",X"0000FFFF");
160 UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000001",X"00000A0A");
160 UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000001",X"00000A0A");
161 UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000001",X"00000B0B");
161 UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000001",X"00000B0B");
162 UART_READ(TXD1,RXD1,txp,ADDR_BASE_GPIO & "000001",data_read_v);
162 UART_READ(TXD1,RXD1,txp,ADDR_BASE_GPIO & "000001",data_read_v);
163 data_read <= data_read_v;
163 data_read <= data_read_v;
164 data_message <= "GPIO_data_write";
164 data_message <= "GPIO_data_write";
165
165
166 -- UNSET the LFR reset
166 -- UNSET the LFR reset
167 message_simu <= "2 - LFR UNRESET";
167 message_simu <= "2 - LFR UNRESET";
168 UNRESET_LFR(TXD1,txp,ADDR_BASE_TIME_MANAGMENT);
168 UNRESET_LFR(TXD1,txp,ADDR_BASE_TIME_MANAGMENT);
169 --UART_WRITE(TXD1,txp,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_CONTROL , X"00000000");
169 --UART_WRITE(TXD1,txp,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_CONTROL , X"00000000");
170 --UART_WRITE(TXD1,txp,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_TIME_LOAD , X"00000000");
170 --UART_WRITE(TXD1,txp,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_TIME_LOAD , X"00000000");
171 --
171 --
172 message_simu <= "3 - LFR CONFIG ";
172 message_simu <= "3 - LFR CONFIG ";
173 --UART_WRITE(TXD1,txp,ADDR_BASE_LFR & ADDR_LFR_SM_F0_0_ADDR , X"00000B0B");
173 --UART_WRITE(TXD1,txp,ADDR_BASE_LFR & ADDR_LFR_SM_F0_0_ADDR , X"00000B0B");
174 LAUNCH_SPECTRAL_MATRIX(TXD1,RXD1,txp,ADDR_BASE_LFR,
174 LAUNCH_SPECTRAL_MATRIX(TXD1,RXD1,txp,ADDR_BASE_LFR,
175 X"40000000",
175 X"40000000",
176 X"40001000",
176 X"40001000",
177 X"40002000",
177 X"40002000",
178 X"40003000",
178 X"40003000",
179 X"40004000",
179 X"40004000",
180 X"40005000");
180 X"40005000");
181
181
182
182
183 LAUNCH_WAVEFORM_PICKER(TXD1,RXD1,txp,
183 LAUNCH_WAVEFORM_PICKER(TXD1,RXD1,txp,
184 LFR_MODE_SBM1,
184 LFR_MODE_SBM1,
185 X"7FFFFFFF", -- START DATE
185 X"7FFFFFFF", -- START DATE
186
186
187 "00000",--DATA_SHAPING ( 4 DOWNTO 0)
187 "00000",--DATA_SHAPING ( 4 DOWNTO 0)
188 X"00012BFF",--DELTA_SNAPSHOT(31 DOWNTO 0)
188 X"00012BFF",--DELTA_SNAPSHOT(31 DOWNTO 0)
189 X"0001280A",--DELTA_F0 (31 DOWNTO 0)
189 X"0001280A",--DELTA_F0 (31 DOWNTO 0)
190 X"00000007",--DELTA_F0_2 (31 DOWNTO 0)
190 X"00000007",--DELTA_F0_2 (31 DOWNTO 0)
191 X"0001283F",--DELTA_F1 (31 DOWNTO 0)
191 X"0001283F",--DELTA_F1 (31 DOWNTO 0)
192 X"000127FF",--DELTA_F2 (31 DOWNTO 0)
192 X"000127FF",--DELTA_F2 (31 DOWNTO 0)
193
193
194 ADDR_BASE_LFR,
194 ADDR_BASE_LFR,
195 X"40006000",
195 X"40006000",
196 X"40007000",
196 X"40007000",
197 X"40008000",
197 X"40008000",
198 X"40009000",
198 X"40009000",
199 X"4000A000",
199 X"4000A000",
200 X"4000B000",
200 X"4000B000",
201 X"4000C000",
201 X"4000C000",
202 X"4000D000");
202 X"4000D000");
203
203
204 UART_WRITE(TXD1 ,txp,ADDR_BASE_LFR & ADDR_LFR_WP_LENGTH, X"0000000F");
204 UART_WRITE(TXD1 ,txp,ADDR_BASE_LFR & ADDR_LFR_WP_LENGTH, X"0000000F");
205 UART_WRITE(TXD1 ,txp,ADDR_BASE_LFR & ADDR_LFR_WP_DATA_IN_BUFFER, X"00000050");
205 UART_WRITE(TXD1 ,txp,ADDR_BASE_LFR & ADDR_LFR_WP_DATA_IN_BUFFER, X"00000050");
206
206
207 message_simu <= "4 - GO GO GO !!";
207 message_simu <= "4 - GO GO GO !!";
208 UART_WRITE (TXD1 ,txp,ADDR_BASE_LFR & ADDR_LFR_WP_START_DATE,X"00000000");
208 UART_WRITE (TXD1 ,txp,ADDR_BASE_LFR & ADDR_LFR_WP_START_DATE,X"00000000");
209
209
210 READ_STATUS: LOOP
210 READ_STATUS: LOOP
211 WAIT FOR 2 ms;
211 WAIT FOR 2 ms;
212 data_message <= "READ_NEW_STATUS";
212 data_message <= "READ_NEW_STATUS";
213 UART_READ(TXD1,RXD1,txp,ADDR_BASE_LFR & ADDR_LFR_SM_STATUS,data_read_v);
213 UART_READ(TXD1,RXD1,txp,ADDR_BASE_LFR & ADDR_LFR_SM_STATUS,data_read_v);
214 data_read <= data_read_v;
214 data_read <= data_read_v;
215 UART_WRITE(TXD1, txp,ADDR_BASE_LFR & ADDR_LFR_SM_STATUS,data_read_v);
215 UART_WRITE(TXD1, txp,ADDR_BASE_LFR & ADDR_LFR_SM_STATUS,data_read_v);
216
216
217 UART_READ(TXD1,RXD1,txp,ADDR_BASE_LFR & ADDR_LFR_WP_STATUS,data_read_v);
217 UART_READ(TXD1,RXD1,txp,ADDR_BASE_LFR & ADDR_LFR_WP_STATUS,data_read_v);
218 data_read <= data_read_v;
218 data_read <= data_read_v;
219 UART_WRITE(TXD1, txp,ADDR_BASE_LFR & ADDR_LFR_WP_STATUS,data_read_v);
219 UART_WRITE(TXD1, txp,ADDR_BASE_LFR & ADDR_LFR_WP_STATUS,data_read_v);
220 END LOOP READ_STATUS;
220 END LOOP READ_STATUS;
221
221
222 WAIT;
222 WAIT;
223 END PROCESS;
223 END PROCESS;
224
224
225 -----------------------------------------------------------------------------
225 -----------------------------------------------------------------------------
226 -- CLOCK
226 -- CLOCK
227 -----------------------------------------------------------------------------
227 -----------------------------------------------------------------------------
228 clk_50 <= NOT clk_50 AFTER 5 ns;
228 clk_50 <= NOT clk_50 AFTER 5 ns;
229 clk_49 <= NOT clk_49 AFTER 10172 ps;
229 clk_49 <= NOT clk_49 AFTER 10172 ps;
230
230
231 -----------------------------------------------------------------------------
231 -----------------------------------------------------------------------------
232 -- DON'T CARE
232 -- DON'T CARE
233 -----------------------------------------------------------------------------
233 -----------------------------------------------------------------------------
234 BP0 <= '0';
234 BP0 <= '0';
235 BP1 <= '0';
235 BP1 <= '0';
236 nRTS1 <= '0' ;
236 nRTS1 <= '0' ;
237
237
238 TXD2 <= '1';
238 TXD2 <= '1';
239 nRTS2 <= '1';
239 nRTS2 <= '1';
240 nDTR2 <= '1';
240 nDTR2 <= '1';
241
241
242 SPW_NOM_DIN <= '1';
242 SPW_NOM_DIN <= '1';
243 SPW_NOM_SIN <= '1';
243 SPW_NOM_SIN <= '1';
244 SPW_RED_DIN <= '1';
244 SPW_RED_DIN <= '1';
245 SPW_RED_SIN <= '1';
245 SPW_RED_SIN <= '1';
246
246
247 ADC_SDO <= x"AA";
247 ADC_SDO <= x"AA";
248
248
249 SRAM_DQ <= (OTHERS => 'Z');
249 SRAM_DQ <= (OTHERS => 'Z');
250 --IO0 <= 'Z';
250 --IO0 <= 'Z';
251 --IO1 <= 'Z';
251 --IO1 <= 'Z';
252 --IO2 <= 'Z';
252 --IO2 <= 'Z';
253 --IO3 <= 'Z';
253 --IO3 <= 'Z';
254 --IO4 <= 'Z';
254 --IO4 <= 'Z';
255 --IO5 <= 'Z';
255 --IO5 <= 'Z';
256 --IO6 <= 'Z';
256 --IO6 <= 'Z';
257 --IO7 <= 'Z';
257 --IO7 <= 'Z';
258 --IO8 <= 'Z';
258 --IO8 <= 'Z';
259 --IO9 <= 'Z';
259 --IO9 <= 'Z';
260 --IO10 <= 'Z';
260 --IO10 <= 'Z';
261 --IO11 <= 'Z';
261 --IO11 <= 'Z';
262
262
263 -----------------------------------------------------------------------------
263 -----------------------------------------------------------------------------
264 -- DUT
264 -- DUT
265 -----------------------------------------------------------------------------
265 -----------------------------------------------------------------------------
266 MINI_LFR_top_1: MINI_LFR_top
266 MINI_LFR_top_1: MINI_LFR_top
267 PORT MAP (
267 PORT MAP (
268 clk_50 => clk_50,
268 clk_50 => clk_50,
269 clk_49 => clk_49,
269 clk_49 => clk_49,
270 reset => reset,
270 reset => reset,
271
271
272 BP0 => BP0,
272 BP0 => BP0,
273 BP1 => BP1,
273 BP1 => BP1,
274
274
275 LED0 => LED0,
275 LED0 => LED0,
276 LED1 => LED1,
276 LED1 => LED1,
277 LED2 => LED2,
277 LED2 => LED2,
278
278
279 TXD1 => TXD1,
279 TXD1 => TXD1,
280 RXD1 => RXD1,
280 RXD1 => RXD1,
281 nCTS1 => nCTS1,
281 nCTS1 => nCTS1,
282 nRTS1 => nRTS1,
282 nRTS1 => nRTS1,
283
283
284 TXD2 => TXD2,
284 TXD2 => TXD2,
285 RXD2 => RXD2,
285 RXD2 => RXD2,
286 nCTS2 => nCTS2,
286 nCTS2 => nCTS2,
287 nDTR2 => nDTR2,
287 nDTR2 => nDTR2,
288 nRTS2 => nRTS2,
288 nRTS2 => nRTS2,
289 nDCD2 => nDCD2,
289 nDCD2 => nDCD2,
290
290
291 IO0 => IO0,
291 IO0 => IO0,
292 IO1 => IO1,
292 IO1 => IO1,
293 IO2 => IO2,
293 IO2 => IO2,
294 IO3 => IO3,
294 IO3 => IO3,
295 IO4 => IO4,
295 IO4 => IO4,
296 IO5 => IO5,
296 IO5 => IO5,
297 IO6 => IO6,
297 IO6 => IO6,
298 IO7 => IO7,
298 IO7 => IO7,
299 IO8 => IO8,
299 IO8 => IO8,
300 IO9 => IO9,
300 IO9 => IO9,
301 IO10 => IO10,
301 IO10 => IO10,
302 IO11 => IO11,
302 IO11 => IO11,
303
303
304 SPW_EN => SPW_EN,
304 SPW_EN => SPW_EN,
305 SPW_NOM_DIN => SPW_NOM_DIN,
305 SPW_NOM_DIN => SPW_NOM_DIN,
306 SPW_NOM_SIN => SPW_NOM_SIN,
306 SPW_NOM_SIN => SPW_NOM_SIN,
307 SPW_NOM_DOUT => SPW_NOM_DOUT,
307 SPW_NOM_DOUT => SPW_NOM_DOUT,
308 SPW_NOM_SOUT => SPW_NOM_SOUT,
308 SPW_NOM_SOUT => SPW_NOM_SOUT,
309 SPW_RED_DIN => SPW_RED_DIN,
309 SPW_RED_DIN => SPW_RED_DIN,
310 SPW_RED_SIN => SPW_RED_SIN,
310 SPW_RED_SIN => SPW_RED_SIN,
311 SPW_RED_DOUT => SPW_RED_DOUT,
311 SPW_RED_DOUT => SPW_RED_DOUT,
312 SPW_RED_SOUT => SPW_RED_SOUT,
312 SPW_RED_SOUT => SPW_RED_SOUT,
313
313
314 ADC_nCS => ADC_nCS,
314 ADC_nCS => ADC_nCS,
315 ADC_CLK => ADC_CLK,
315 ADC_CLK => ADC_CLK,
316 ADC_SDO => ADC_SDO,
316 ADC_SDO => ADC_SDO,
317
317
318 SRAM_nWE => SRAM_nWE,
318 SRAM_nWE => SRAM_nWE,
319 SRAM_CE => SRAM_CE,
319 SRAM_CE => SRAM_CE,
320 SRAM_nOE => SRAM_nOE,
320 SRAM_nOE => SRAM_nOE,
321 SRAM_nBE => SRAM_nBE,
321 SRAM_nBE => SRAM_nBE,
322 SRAM_A => SRAM_A,
322 SRAM_A => SRAM_A,
323 SRAM_DQ => SRAM_DQ);
323 SRAM_DQ => SRAM_DQ);
324
324
325
325
326 END;
326 END;
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@@ -1,467 +1,467
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22
22
23 LIBRARY ieee;
23 LIBRARY ieee;
24 USE ieee.std_logic_1164.ALL;
24 USE ieee.std_logic_1164.ALL;
25 USE ieee.numeric_std.ALL;
25 USE ieee.numeric_std.ALL;
26 LIBRARY grlib;
26 LIBRARY grlib;
27 USE grlib.stdlib.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY gaisler;
28 LIBRARY gaisler;
29 USE gaisler.libdcom.ALL;
29 USE gaisler.libdcom.ALL;
30 USE gaisler.sim.ALL;
30 USE gaisler.sim.ALL;
31 USE gaisler.jtagtst.ALL;
31 USE gaisler.jtagtst.ALL;
32 LIBRARY techmap;
32 LIBRARY techmap;
33 USE techmap.gencomp.ALL;
33 USE techmap.gencomp.ALL;
34 LIBRARY lpp;
34 LIBRARY lpp;
35 USE lpp.lpp_sim_pkg.ALL;
35 USE lpp.lpp_sim_pkg.ALL;
36 USE lpp.lpp_lfr_apbreg_pkg.ALL;
36 USE lpp.lpp_lfr_apbreg_pkg.ALL;
37 USE lpp.lpp_lfr_time_management_apbreg_pkg.ALL;
37 USE lpp.lpp_lfr_management_apbreg_pkg.ALL;
38
38
39 PACKAGE lpp_lfr_sim_pkg IS
39 PACKAGE lpp_lfr_sim_pkg IS
40
40
41 CONSTANT LFR_MODE_STANDBY : STD_LOGIC_VECTOR(2 DOWNTO 0) := "000";
41 CONSTANT LFR_MODE_STANDBY : STD_LOGIC_VECTOR(2 DOWNTO 0) := "000";
42 CONSTANT LFR_MODE_NORMAL : STD_LOGIC_VECTOR(2 DOWNTO 0) := "001";
42 CONSTANT LFR_MODE_NORMAL : STD_LOGIC_VECTOR(2 DOWNTO 0) := "001";
43 CONSTANT LFR_MODE_BURST : STD_LOGIC_VECTOR(2 DOWNTO 0) := "010";
43 CONSTANT LFR_MODE_BURST : STD_LOGIC_VECTOR(2 DOWNTO 0) := "010";
44 CONSTANT LFR_MODE_SBM1 : STD_LOGIC_VECTOR(2 DOWNTO 0) := "011";
44 CONSTANT LFR_MODE_SBM1 : STD_LOGIC_VECTOR(2 DOWNTO 0) := "011";
45 CONSTANT LFR_MODE_SBM2 : STD_LOGIC_VECTOR(2 DOWNTO 0) := "100";
45 CONSTANT LFR_MODE_SBM2 : STD_LOGIC_VECTOR(2 DOWNTO 0) := "100";
46
46
47 PROCEDURE UNRESET_LFR (
47 PROCEDURE UNRESET_LFR (
48 SIGNAL TX : OUT STD_LOGIC;
48 SIGNAL TX : OUT STD_LOGIC;
49 CONSTANT tx_period : IN TIME;
49 CONSTANT tx_period : IN TIME;
50 CONSTANT ADDR_BASE_TIME_MANAGMENT : IN STD_LOGIC_VECTOR(31 DOWNTO 8)
50 CONSTANT ADDR_BASE_TIME_MANAGMENT : IN STD_LOGIC_VECTOR(31 DOWNTO 8)
51 );
51 );
52
52
53 PROCEDURE LAUNCH_SPECTRAL_MATRIX(
53 PROCEDURE LAUNCH_SPECTRAL_MATRIX(
54 SIGNAL TX : OUT STD_LOGIC;
54 SIGNAL TX : OUT STD_LOGIC;
55 SIGNAL RX : IN STD_LOGIC;
55 SIGNAL RX : IN STD_LOGIC;
56 CONSTANT tx_period : IN TIME;
56 CONSTANT tx_period : IN TIME;
57
57
58 CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8);
58 CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8);
59 CONSTANT PARAM_SM_f0_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
59 CONSTANT PARAM_SM_f0_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
60 CONSTANT PARAM_SM_f0_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
60 CONSTANT PARAM_SM_f0_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
61 CONSTANT PARAM_SM_f1_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
61 CONSTANT PARAM_SM_f1_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
62 CONSTANT PARAM_SM_f1_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
62 CONSTANT PARAM_SM_f1_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
63 CONSTANT PARAM_SM_f2_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
63 CONSTANT PARAM_SM_f2_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
64 CONSTANT PARAM_SM_f2_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
64 CONSTANT PARAM_SM_f2_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
65 );
65 );
66
66
67 PROCEDURE LAUNCH_WAVEFORM_PICKER(
67 PROCEDURE LAUNCH_WAVEFORM_PICKER(
68 SIGNAL TX : OUT STD_LOGIC;
68 SIGNAL TX : OUT STD_LOGIC;
69 SIGNAL RX : IN STD_LOGIC;
69 SIGNAL RX : IN STD_LOGIC;
70 CONSTANT tx_period : IN TIME;
70 CONSTANT tx_period : IN TIME;
71
71
72 CONSTANT LFR_MODE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
72 CONSTANT LFR_MODE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
73 CONSTANT TRANSITION_COARSE_TIME : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
73 CONSTANT TRANSITION_COARSE_TIME : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
74
74
75 CONSTANT DATA_SHAPING : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
75 CONSTANT DATA_SHAPING : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
76 CONSTANT DELTA_SNAPSHOT : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
76 CONSTANT DELTA_SNAPSHOT : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
77 CONSTANT DELTA_F0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
77 CONSTANT DELTA_F0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
78 CONSTANT DELTA_F0_2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
78 CONSTANT DELTA_F0_2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
79 CONSTANT DELTA_F1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
79 CONSTANT DELTA_F1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
80 CONSTANT DELTA_F2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
80 CONSTANT DELTA_F2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
81
81
82 CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8);
82 CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8);
83
83
84 CONSTANT PARAM_WP_f0_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
84 CONSTANT PARAM_WP_f0_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
85 CONSTANT PARAM_WP_f0_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
85 CONSTANT PARAM_WP_f0_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
86 CONSTANT PARAM_WP_f1_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
86 CONSTANT PARAM_WP_f1_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
87 CONSTANT PARAM_WP_f1_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
87 CONSTANT PARAM_WP_f1_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
88 CONSTANT PARAM_WP_f2_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
88 CONSTANT PARAM_WP_f2_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
89 CONSTANT PARAM_WP_f2_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
89 CONSTANT PARAM_WP_f2_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
90 CONSTANT PARAM_WP_f3_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
90 CONSTANT PARAM_WP_f3_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
91 CONSTANT PARAM_WP_f3_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
91 CONSTANT PARAM_WP_f3_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
92 );
92 );
93
93
94 -----------------------------------------------------------------------------
94 -----------------------------------------------------------------------------
95 -- SM function
95 -- SM function
96 -----------------------------------------------------------------------------
96 -----------------------------------------------------------------------------
97
97
98 PROCEDURE RESET_SPECTRAL_MATRIX_REGS(
98 PROCEDURE RESET_SPECTRAL_MATRIX_REGS(
99 SIGNAL TX : OUT STD_LOGIC;
99 SIGNAL TX : OUT STD_LOGIC;
100 SIGNAL RX : IN STD_LOGIC;
100 SIGNAL RX : IN STD_LOGIC;
101 CONSTANT tx_period : IN TIME;
101 CONSTANT tx_period : IN TIME;
102 CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8);
102 CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8);
103 CONSTANT PARAM_SM_f0_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
103 CONSTANT PARAM_SM_f0_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
104 CONSTANT PARAM_SM_f0_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
104 CONSTANT PARAM_SM_f0_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
105 CONSTANT PARAM_SM_f1_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
105 CONSTANT PARAM_SM_f1_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
106 CONSTANT PARAM_SM_f1_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
106 CONSTANT PARAM_SM_f1_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
107 CONSTANT PARAM_SM_f2_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
107 CONSTANT PARAM_SM_f2_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
108 CONSTANT PARAM_SM_f2_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
108 CONSTANT PARAM_SM_f2_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
109 );
109 );
110
110
111 PROCEDURE SET_SM_IRQ_onNewMatrix(
111 PROCEDURE SET_SM_IRQ_onNewMatrix(
112 SIGNAL TX : OUT STD_LOGIC;
112 SIGNAL TX : OUT STD_LOGIC;
113 SIGNAL RX : IN STD_LOGIC;
113 SIGNAL RX : IN STD_LOGIC;
114 CONSTANT tx_period : IN TIME;
114 CONSTANT tx_period : IN TIME;
115 CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8);
115 CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8);
116 CONSTANT PARAM_value : IN STD_LOGIC
116 CONSTANT PARAM_value : IN STD_LOGIC
117 );
117 );
118
118
119 PROCEDURE SET_SM_IRQ_ERROR(
119 PROCEDURE SET_SM_IRQ_ERROR(
120 SIGNAL TX : OUT STD_LOGIC;
120 SIGNAL TX : OUT STD_LOGIC;
121 SIGNAL RX : IN STD_LOGIC;
121 SIGNAL RX : IN STD_LOGIC;
122 CONSTANT tx_period : IN TIME;
122 CONSTANT tx_period : IN TIME;
123 CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8);
123 CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8);
124 CONSTANT PARAM_value : IN STD_LOGIC
124 CONSTANT PARAM_value : IN STD_LOGIC
125 );
125 );
126
126
127 PROCEDURE RESET_SM_STATUS(
127 PROCEDURE RESET_SM_STATUS(
128 SIGNAL TX : OUT STD_LOGIC;
128 SIGNAL TX : OUT STD_LOGIC;
129 SIGNAL RX : IN STD_LOGIC;
129 SIGNAL RX : IN STD_LOGIC;
130 CONSTANT tx_period : IN TIME;
130 CONSTANT tx_period : IN TIME;
131 CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8)
131 CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8)
132 );
132 );
133
133
134 -----------------------------------------------------------------------------
134 -----------------------------------------------------------------------------
135 -- WP function
135 -- WP function
136 -----------------------------------------------------------------------------
136 -----------------------------------------------------------------------------
137
137
138 PROCEDURE RESET_WAVEFORM_PICKER_REGS(
138 PROCEDURE RESET_WAVEFORM_PICKER_REGS(
139 SIGNAL TX : OUT STD_LOGIC;
139 SIGNAL TX : OUT STD_LOGIC;
140 SIGNAL RX : IN STD_LOGIC;
140 SIGNAL RX : IN STD_LOGIC;
141 CONSTANT tx_period : IN TIME;
141 CONSTANT tx_period : IN TIME;
142 CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8);
142 CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8);
143
143
144 CONSTANT DATA_SHAPING : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
144 CONSTANT DATA_SHAPING : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
145 CONSTANT DELTA_SNAPSHOT : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
145 CONSTANT DELTA_SNAPSHOT : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
146 CONSTANT DELTA_F0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
146 CONSTANT DELTA_F0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
147 CONSTANT DELTA_F0_2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
147 CONSTANT DELTA_F0_2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
148 CONSTANT DELTA_F1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
148 CONSTANT DELTA_F1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
149 CONSTANT DELTA_F2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
149 CONSTANT DELTA_F2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
150
150
151 CONSTANT PARAM_WP_f0_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
151 CONSTANT PARAM_WP_f0_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
152 CONSTANT PARAM_WP_f0_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
152 CONSTANT PARAM_WP_f0_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
153 CONSTANT PARAM_WP_f1_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
153 CONSTANT PARAM_WP_f1_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
154 CONSTANT PARAM_WP_f1_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
154 CONSTANT PARAM_WP_f1_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
155 CONSTANT PARAM_WP_f2_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
155 CONSTANT PARAM_WP_f2_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
156 CONSTANT PARAM_WP_f2_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
156 CONSTANT PARAM_WP_f2_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
157 CONSTANT PARAM_WP_f3_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
157 CONSTANT PARAM_WP_f3_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
158 CONSTANT PARAM_WP_f3_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
158 CONSTANT PARAM_WP_f3_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
159 );
159 );
160
160
161 PROCEDURE SET_WFP_DATA_SHAPING(
161 PROCEDURE SET_WFP_DATA_SHAPING(
162 SIGNAL TX : OUT STD_LOGIC;
162 SIGNAL TX : OUT STD_LOGIC;
163 CONSTANT tx_period : IN TIME;
163 CONSTANT tx_period : IN TIME;
164 CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8);
164 CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8);
165 CONSTANT DATA_SHAPING : IN STD_LOGIC_VECTOR(4 DOWNTO 0));
165 CONSTANT DATA_SHAPING : IN STD_LOGIC_VECTOR(4 DOWNTO 0));
166
166
167 PROCEDURE RESET_WFP_BURST_ENABLE(
167 PROCEDURE RESET_WFP_BURST_ENABLE(
168 SIGNAL TX : OUT STD_LOGIC;
168 SIGNAL TX : OUT STD_LOGIC;
169 SIGNAL RX : IN STD_LOGIC;
169 SIGNAL RX : IN STD_LOGIC;
170 CONSTANT tx_period : IN TIME;
170 CONSTANT tx_period : IN TIME;
171 CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8));
171 CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8));
172
172
173 PROCEDURE RESET_WFP_STATUS(
173 PROCEDURE RESET_WFP_STATUS(
174 SIGNAL TX : OUT STD_LOGIC;
174 SIGNAL TX : OUT STD_LOGIC;
175 CONSTANT tx_period : IN TIME;
175 CONSTANT tx_period : IN TIME;
176 CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8));
176 CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8));
177
177
178 PROCEDURE SET_WFP_BURST_ENABLE_REGISTER(
178 PROCEDURE SET_WFP_BURST_ENABLE_REGISTER(
179 SIGNAL TX : OUT STD_LOGIC;
179 SIGNAL TX : OUT STD_LOGIC;
180 SIGNAL RX : IN STD_LOGIC;
180 SIGNAL RX : IN STD_LOGIC;
181 CONSTANT tx_period : IN TIME;
181 CONSTANT tx_period : IN TIME;
182 CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8);
182 CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8);
183 CONSTANT LFR_MODE : IN STD_LOGIC_VECTOR(2 DOWNTO 0)
183 CONSTANT LFR_MODE : IN STD_LOGIC_VECTOR(2 DOWNTO 0)
184 );
184 );
185
185
186 END lpp_lfr_sim_pkg;
186 END lpp_lfr_sim_pkg;
187
187
188
188
189
189
190 PACKAGE BODY lpp_lfr_sim_pkg IS
190 PACKAGE BODY lpp_lfr_sim_pkg IS
191
191
192 PROCEDURE UNRESET_LFR (
192 PROCEDURE UNRESET_LFR (
193 SIGNAL TX : OUT STD_LOGIC;
193 SIGNAL TX : OUT STD_LOGIC;
194 CONSTANT tx_period : IN TIME;
194 CONSTANT tx_period : IN TIME;
195 CONSTANT ADDR_BASE_TIME_MANAGMENT : IN STD_LOGIC_VECTOR(31 DOWNTO 8))
195 CONSTANT ADDR_BASE_TIME_MANAGMENT : IN STD_LOGIC_VECTOR(31 DOWNTO 8))
196 IS
196 IS
197 BEGIN
197 BEGIN
198 UART_WRITE(TX,tx_period,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_CONTROL , X"00000000");
198 UART_WRITE(TX,tx_period,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_MANAGMENT_CONTROL , X"00000000");
199 UART_WRITE(TX,tx_period,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_TIME_LOAD , X"00000000");
199 UART_WRITE(TX,tx_period,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_MANAGMENT_TIME_LOAD , X"00000000");
200 END;
200 END;
201
201
202 PROCEDURE LAUNCH_SPECTRAL_MATRIX(
202 PROCEDURE LAUNCH_SPECTRAL_MATRIX(
203 SIGNAL TX : OUT STD_LOGIC;
203 SIGNAL TX : OUT STD_LOGIC;
204 SIGNAL RX : IN STD_LOGIC;
204 SIGNAL RX : IN STD_LOGIC;
205 CONSTANT tx_period : IN TIME;
205 CONSTANT tx_period : IN TIME;
206 CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8);
206 CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8);
207 CONSTANT PARAM_SM_f0_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
207 CONSTANT PARAM_SM_f0_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
208 CONSTANT PARAM_SM_f0_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
208 CONSTANT PARAM_SM_f0_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
209 CONSTANT PARAM_SM_f1_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
209 CONSTANT PARAM_SM_f1_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
210 CONSTANT PARAM_SM_f1_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
210 CONSTANT PARAM_SM_f1_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
211 CONSTANT PARAM_SM_f2_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
211 CONSTANT PARAM_SM_f2_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
212 CONSTANT PARAM_SM_f2_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
212 CONSTANT PARAM_SM_f2_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
213 )
213 )
214 IS
214 IS
215 BEGIN
215 BEGIN
216 RESET_SPECTRAL_MATRIX_REGS(TX,RX,tx_period,ADDR_BASE_LFR,
216 RESET_SPECTRAL_MATRIX_REGS(TX,RX,tx_period,ADDR_BASE_LFR,
217 PARAM_SM_f0_0_addr, PARAM_SM_f0_1_addr, PARAM_SM_f1_0_addr,
217 PARAM_SM_f0_0_addr, PARAM_SM_f0_1_addr, PARAM_SM_f1_0_addr,
218 PARAM_SM_f1_1_addr, PARAM_SM_f2_0_addr, PARAM_SM_f2_1_addr);
218 PARAM_SM_f1_1_addr, PARAM_SM_f2_0_addr, PARAM_SM_f2_1_addr);
219 SET_SM_IRQ_onNewMatrix (TX,RX,tx_period,ADDR_BASE_LFR,
219 SET_SM_IRQ_onNewMatrix (TX,RX,tx_period,ADDR_BASE_LFR,
220 '1');
220 '1');
221 END;
221 END;
222
222
223
223
224 PROCEDURE LAUNCH_WAVEFORM_PICKER(
224 PROCEDURE LAUNCH_WAVEFORM_PICKER(
225 SIGNAL TX : OUT STD_LOGIC;
225 SIGNAL TX : OUT STD_LOGIC;
226 SIGNAL RX : IN STD_LOGIC;
226 SIGNAL RX : IN STD_LOGIC;
227 CONSTANT tx_period : IN TIME;
227 CONSTANT tx_period : IN TIME;
228
228
229 CONSTANT LFR_MODE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
229 CONSTANT LFR_MODE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
230 CONSTANT TRANSITION_COARSE_TIME : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
230 CONSTANT TRANSITION_COARSE_TIME : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
231
231
232 CONSTANT DATA_SHAPING : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
232 CONSTANT DATA_SHAPING : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
233 CONSTANT DELTA_SNAPSHOT : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
233 CONSTANT DELTA_SNAPSHOT : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
234 CONSTANT DELTA_F0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
234 CONSTANT DELTA_F0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
235 CONSTANT DELTA_F0_2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
235 CONSTANT DELTA_F0_2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
236 CONSTANT DELTA_F1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
236 CONSTANT DELTA_F1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
237 CONSTANT DELTA_F2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
237 CONSTANT DELTA_F2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
238
238
239 CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8);
239 CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8);
240 CONSTANT PARAM_WP_f0_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
240 CONSTANT PARAM_WP_f0_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
241 CONSTANT PARAM_WP_f0_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
241 CONSTANT PARAM_WP_f0_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
242 CONSTANT PARAM_WP_f1_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
242 CONSTANT PARAM_WP_f1_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
243 CONSTANT PARAM_WP_f1_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
243 CONSTANT PARAM_WP_f1_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
244 CONSTANT PARAM_WP_f2_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
244 CONSTANT PARAM_WP_f2_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
245 CONSTANT PARAM_WP_f2_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
245 CONSTANT PARAM_WP_f2_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
246 CONSTANT PARAM_WP_f3_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
246 CONSTANT PARAM_WP_f3_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
247 CONSTANT PARAM_WP_f3_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
247 CONSTANT PARAM_WP_f3_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
248 -- CONSTANT PARAM_SM_f0_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
248 -- CONSTANT PARAM_SM_f0_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
249 -- CONSTANT PARAM_SM_f0_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
249 -- CONSTANT PARAM_SM_f0_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
250 -- CONSTANT PARAM_SM_f1_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
250 -- CONSTANT PARAM_SM_f1_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
251 -- CONSTANT PARAM_SM_f1_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
251 -- CONSTANT PARAM_SM_f1_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
252 -- CONSTANT PARAM_SM_f2_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
252 -- CONSTANT PARAM_SM_f2_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
253 -- CONSTANT PARAM_SM_f2_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
253 -- CONSTANT PARAM_SM_f2_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
254 )
254 )
255 IS
255 IS
256 BEGIN
256 BEGIN
257 RESET_WAVEFORM_PICKER_REGS(TX,RX,tx_period,ADDR_BASE_LFR,
257 RESET_WAVEFORM_PICKER_REGS(TX,RX,tx_period,ADDR_BASE_LFR,
258 DATA_SHAPING ,
258 DATA_SHAPING ,
259 DELTA_SNAPSHOT,
259 DELTA_SNAPSHOT,
260 DELTA_F0 ,
260 DELTA_F0 ,
261 DELTA_F0_2 ,
261 DELTA_F0_2 ,
262 DELTA_F1 ,
262 DELTA_F1 ,
263 DELTA_F2 ,
263 DELTA_F2 ,
264 PARAM_WP_f0_0_addr, PARAM_WP_f0_1_addr,
264 PARAM_WP_f0_0_addr, PARAM_WP_f0_1_addr,
265 PARAM_WP_f1_0_addr, PARAM_WP_f1_1_addr,
265 PARAM_WP_f1_0_addr, PARAM_WP_f1_1_addr,
266 PARAM_WP_f2_0_addr, PARAM_WP_f2_1_addr,
266 PARAM_WP_f2_0_addr, PARAM_WP_f2_1_addr,
267 PARAM_WP_f3_0_addr, PARAM_WP_f3_1_addr);
267 PARAM_WP_f3_0_addr, PARAM_WP_f3_1_addr);
268
268
269 SET_WFP_BURST_ENABLE_REGISTER(TX, RX, tx_period, ADDR_BASE_LFR, LFR_MODE);
269 SET_WFP_BURST_ENABLE_REGISTER(TX, RX, tx_period, ADDR_BASE_LFR, LFR_MODE);
270
270
271 UART_WRITE(TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_WP_START_DATE, TRANSITION_COARSE_TIME);
271 UART_WRITE(TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_WP_START_DATE, TRANSITION_COARSE_TIME);
272
272
273 END;
273 END;
274
274
275
275
276 -----------------------------------------------------------------------------
276 -----------------------------------------------------------------------------
277 -- SM function
277 -- SM function
278 -----------------------------------------------------------------------------
278 -----------------------------------------------------------------------------
279 PROCEDURE RESET_SPECTRAL_MATRIX_REGS(
279 PROCEDURE RESET_SPECTRAL_MATRIX_REGS(
280 SIGNAL TX : OUT STD_LOGIC;
280 SIGNAL TX : OUT STD_LOGIC;
281 SIGNAL RX : IN STD_LOGIC;
281 SIGNAL RX : IN STD_LOGIC;
282 CONSTANT tx_period : IN TIME;
282 CONSTANT tx_period : IN TIME;
283 CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8);
283 CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8);
284 CONSTANT PARAM_SM_f0_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
284 CONSTANT PARAM_SM_f0_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
285 CONSTANT PARAM_SM_f0_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
285 CONSTANT PARAM_SM_f0_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
286 CONSTANT PARAM_SM_f1_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
286 CONSTANT PARAM_SM_f1_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
287 CONSTANT PARAM_SM_f1_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
287 CONSTANT PARAM_SM_f1_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
288 CONSTANT PARAM_SM_f2_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
288 CONSTANT PARAM_SM_f2_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
289 CONSTANT PARAM_SM_f2_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
289 CONSTANT PARAM_SM_f2_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
290 )
290 )
291 IS
291 IS
292 BEGIN
292 BEGIN
293 SET_SM_IRQ_ERROR (TX,RX,tx_period,ADDR_BASE_LFR,'0');
293 SET_SM_IRQ_ERROR (TX,RX,tx_period,ADDR_BASE_LFR,'0');
294 SET_SM_IRQ_onNewMatrix(TX,RX,tx_period,ADDR_BASE_LFR,'0');
294 SET_SM_IRQ_onNewMatrix(TX,RX,tx_period,ADDR_BASE_LFR,'0');
295 RESET_SM_STATUS (TX,RX,tx_period,ADDR_BASE_LFR);
295 RESET_SM_STATUS (TX,RX,tx_period,ADDR_BASE_LFR);
296 UART_WRITE (TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_F0_0_ADDR,PARAM_SM_f0_0_addr);
296 UART_WRITE (TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_F0_0_ADDR,PARAM_SM_f0_0_addr);
297 UART_WRITE (TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_F0_1_ADDR,PARAM_SM_f0_1_addr);
297 UART_WRITE (TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_F0_1_ADDR,PARAM_SM_f0_1_addr);
298 UART_WRITE (TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_F1_0_ADDR,PARAM_SM_f1_0_addr);
298 UART_WRITE (TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_F1_0_ADDR,PARAM_SM_f1_0_addr);
299 UART_WRITE (TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_F1_1_ADDR,PARAM_SM_f1_1_addr);
299 UART_WRITE (TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_F1_1_ADDR,PARAM_SM_f1_1_addr);
300 UART_WRITE (TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_F2_0_ADDR,PARAM_SM_f2_0_addr);
300 UART_WRITE (TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_F2_0_ADDR,PARAM_SM_f2_0_addr);
301 UART_WRITE (TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_F2_1_ADDR,PARAM_SM_f2_1_addr);
301 UART_WRITE (TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_F2_1_ADDR,PARAM_SM_f2_1_addr);
302 UART_WRITE (TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_LENGTH ,X"000000C8");
302 UART_WRITE (TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_LENGTH ,X"000000C8");
303 END;
303 END;
304
304
305 PROCEDURE SET_SM_IRQ_onNewMatrix(
305 PROCEDURE SET_SM_IRQ_onNewMatrix(
306 SIGNAL TX : OUT STD_LOGIC;
306 SIGNAL TX : OUT STD_LOGIC;
307 SIGNAL RX : IN STD_LOGIC;
307 SIGNAL RX : IN STD_LOGIC;
308 CONSTANT tx_period : IN TIME;
308 CONSTANT tx_period : IN TIME;
309 CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8) ;
309 CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8) ;
310 CONSTANT PARAM_value : IN STD_LOGIC
310 CONSTANT PARAM_value : IN STD_LOGIC
311 )
311 )
312 IS
312 IS
313 VARIABLE data_read : STD_LOGIC_VECTOR(31 DOWNTO 0);
313 VARIABLE data_read : STD_LOGIC_VECTOR(31 DOWNTO 0);
314 BEGIN
314 BEGIN
315 UART_READ(TX,RX,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_CONFIG, data_read);
315 UART_READ(TX,RX,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_CONFIG, data_read);
316 IF PARAM_value = '1' THEN
316 IF PARAM_value = '1' THEN
317 UART_WRITE(TX,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_CONFIG , data_read(31 DOWNTO 1) & '1' );
317 UART_WRITE(TX,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_CONFIG , data_read(31 DOWNTO 1) & '1' );
318 ELSE
318 ELSE
319 UART_WRITE(TX,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_CONFIG , data_read(31 DOWNTO 1) & '0' );
319 UART_WRITE(TX,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_CONFIG , data_read(31 DOWNTO 1) & '0' );
320 END IF;
320 END IF;
321 END;
321 END;
322
322
323 PROCEDURE SET_SM_IRQ_ERROR(
323 PROCEDURE SET_SM_IRQ_ERROR(
324 SIGNAL TX : OUT STD_LOGIC;
324 SIGNAL TX : OUT STD_LOGIC;
325 SIGNAL RX : IN STD_LOGIC;
325 SIGNAL RX : IN STD_LOGIC;
326 CONSTANT tx_period : IN TIME;
326 CONSTANT tx_period : IN TIME;
327 CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8) ;
327 CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8) ;
328 CONSTANT PARAM_value : IN STD_LOGIC
328 CONSTANT PARAM_value : IN STD_LOGIC
329 )
329 )
330 IS
330 IS
331 VARIABLE data_read : STD_LOGIC_VECTOR(31 DOWNTO 0);
331 VARIABLE data_read : STD_LOGIC_VECTOR(31 DOWNTO 0);
332 BEGIN
332 BEGIN
333 UART_READ(TX,RX,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_CONFIG, data_read);
333 UART_READ(TX,RX,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_CONFIG, data_read);
334 IF PARAM_value = '1' THEN
334 IF PARAM_value = '1' THEN
335 UART_WRITE(TX,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_CONFIG , data_read(31 DOWNTO 2) & '1' & data_read(0) );
335 UART_WRITE(TX,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_CONFIG , data_read(31 DOWNTO 2) & '1' & data_read(0) );
336 ELSE
336 ELSE
337 UART_WRITE(TX,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_CONFIG , data_read(31 DOWNTO 2) & '0' & data_read(0) );
337 UART_WRITE(TX,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_CONFIG , data_read(31 DOWNTO 2) & '0' & data_read(0) );
338 END IF;
338 END IF;
339 END;
339 END;
340
340
341 PROCEDURE RESET_SM_STATUS(
341 PROCEDURE RESET_SM_STATUS(
342 SIGNAL TX : OUT STD_LOGIC;
342 SIGNAL TX : OUT STD_LOGIC;
343 SIGNAL RX : IN STD_LOGIC;
343 SIGNAL RX : IN STD_LOGIC;
344 CONSTANT tx_period : IN TIME;
344 CONSTANT tx_period : IN TIME;
345 CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8)
345 CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8)
346 )
346 )
347 IS
347 IS
348 BEGIN
348 BEGIN
349 UART_WRITE(TX,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_STATUS, X"000007FF");
349 UART_WRITE(TX,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_STATUS, X"000007FF");
350 END;
350 END;
351
351
352 -----------------------------------------------------------------------------
352 -----------------------------------------------------------------------------
353 -- WP function
353 -- WP function
354 -----------------------------------------------------------------------------
354 -----------------------------------------------------------------------------
355
355
356 PROCEDURE RESET_WAVEFORM_PICKER_REGS(
356 PROCEDURE RESET_WAVEFORM_PICKER_REGS(
357 SIGNAL TX : OUT STD_LOGIC;
357 SIGNAL TX : OUT STD_LOGIC;
358 SIGNAL RX : IN STD_LOGIC;
358 SIGNAL RX : IN STD_LOGIC;
359 CONSTANT tx_period : IN TIME;
359 CONSTANT tx_period : IN TIME;
360 CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8);
360 CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8);
361
361
362 CONSTANT DATA_SHAPING : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
362 CONSTANT DATA_SHAPING : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
363 CONSTANT DELTA_SNAPSHOT : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
363 CONSTANT DELTA_SNAPSHOT : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
364 CONSTANT DELTA_F0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
364 CONSTANT DELTA_F0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
365 CONSTANT DELTA_F0_2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
365 CONSTANT DELTA_F0_2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
366 CONSTANT DELTA_F1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
366 CONSTANT DELTA_F1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
367 CONSTANT DELTA_F2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
367 CONSTANT DELTA_F2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
368
368
369 CONSTANT PARAM_WP_f0_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
369 CONSTANT PARAM_WP_f0_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
370 CONSTANT PARAM_WP_f0_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
370 CONSTANT PARAM_WP_f0_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
371 CONSTANT PARAM_WP_f1_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
371 CONSTANT PARAM_WP_f1_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
372 CONSTANT PARAM_WP_f1_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
372 CONSTANT PARAM_WP_f1_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
373 CONSTANT PARAM_WP_f2_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
373 CONSTANT PARAM_WP_f2_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
374 CONSTANT PARAM_WP_f2_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
374 CONSTANT PARAM_WP_f2_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
375 CONSTANT PARAM_WP_f3_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
375 CONSTANT PARAM_WP_f3_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
376 CONSTANT PARAM_WP_f3_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
376 CONSTANT PARAM_WP_f3_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
377 )
377 )
378 IS
378 IS
379 BEGIN
379 BEGIN
380 SET_WFP_DATA_SHAPING (TX, tx_period, ADDR_BASE_LFR, DATA_SHAPING);
380 SET_WFP_DATA_SHAPING (TX, tx_period, ADDR_BASE_LFR, DATA_SHAPING);
381 RESET_WFP_BURST_ENABLE(TX, RX, tx_period, ADDR_BASE_LFR);
381 RESET_WFP_BURST_ENABLE(TX, RX, tx_period, ADDR_BASE_LFR);
382 UART_WRITE (TX, tx_period, ADDR_BASE_LFR & ADDR_LFR_WP_F0_0_ADDR, PARAM_WP_f0_0_addr);
382 UART_WRITE (TX, tx_period, ADDR_BASE_LFR & ADDR_LFR_WP_F0_0_ADDR, PARAM_WP_f0_0_addr);
383 UART_WRITE (TX, tx_period, ADDR_BASE_LFR & ADDR_LFR_WP_F0_1_ADDR, PARAM_WP_f0_1_addr);
383 UART_WRITE (TX, tx_period, ADDR_BASE_LFR & ADDR_LFR_WP_F0_1_ADDR, PARAM_WP_f0_1_addr);
384 UART_WRITE (TX, tx_period, ADDR_BASE_LFR & ADDR_LFR_WP_F1_0_ADDR, PARAM_WP_f1_0_addr);
384 UART_WRITE (TX, tx_period, ADDR_BASE_LFR & ADDR_LFR_WP_F1_0_ADDR, PARAM_WP_f1_0_addr);
385 UART_WRITE (TX, tx_period, ADDR_BASE_LFR & ADDR_LFR_WP_F1_1_ADDR, PARAM_WP_f1_1_addr);
385 UART_WRITE (TX, tx_period, ADDR_BASE_LFR & ADDR_LFR_WP_F1_1_ADDR, PARAM_WP_f1_1_addr);
386 UART_WRITE (TX, tx_period, ADDR_BASE_LFR & ADDR_LFR_WP_F2_0_ADDR, PARAM_WP_f2_0_addr);
386 UART_WRITE (TX, tx_period, ADDR_BASE_LFR & ADDR_LFR_WP_F2_0_ADDR, PARAM_WP_f2_0_addr);
387 UART_WRITE (TX, tx_period, ADDR_BASE_LFR & ADDR_LFR_WP_F2_1_ADDR, PARAM_WP_f2_1_addr);
387 UART_WRITE (TX, tx_period, ADDR_BASE_LFR & ADDR_LFR_WP_F2_1_ADDR, PARAM_WP_f2_1_addr);
388 UART_WRITE (TX, tx_period, ADDR_BASE_LFR & ADDR_LFR_WP_F3_0_ADDR, PARAM_WP_f3_0_addr);
388 UART_WRITE (TX, tx_period, ADDR_BASE_LFR & ADDR_LFR_WP_F3_0_ADDR, PARAM_WP_f3_0_addr);
389 UART_WRITE (TX, tx_period, ADDR_BASE_LFR & ADDR_LFR_WP_F3_1_ADDR, PARAM_WP_f3_1_addr);
389 UART_WRITE (TX, tx_period, ADDR_BASE_LFR & ADDR_LFR_WP_F3_1_ADDR, PARAM_WP_f3_1_addr);
390 RESET_WFP_STATUS (TX, tx_period, ADDR_BASE_LFR);
390 RESET_WFP_STATUS (TX, tx_period, ADDR_BASE_LFR);
391 UART_WRITE(TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_WP_DELTASNAPSHOT, DELTA_SNAPSHOT);
391 UART_WRITE(TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_WP_DELTASNAPSHOT, DELTA_SNAPSHOT);
392 UART_WRITE(TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_WP_DELTA_F0, DELTA_F0);
392 UART_WRITE(TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_WP_DELTA_F0, DELTA_F0);
393 UART_WRITE(TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_WP_DELTA_F0_2, DELTA_F0_2);
393 UART_WRITE(TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_WP_DELTA_F0_2, DELTA_F0_2);
394 UART_WRITE(TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_WP_DELTA_F1, DELTA_F1);
394 UART_WRITE(TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_WP_DELTA_F1, DELTA_F1);
395 UART_WRITE(TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_WP_DELTA_F2, DELTA_F2);
395 UART_WRITE(TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_WP_DELTA_F2, DELTA_F2);
396
396
397 UART_WRITE(TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_WP_DATA_IN_BUFFER, X"00000A7F");
397 UART_WRITE(TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_WP_DATA_IN_BUFFER, X"00000A7F");
398 UART_WRITE(TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_WP_NBSNAPSHOT, X"00000A80");
398 UART_WRITE(TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_WP_NBSNAPSHOT, X"00000A80");
399 UART_WRITE(TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_WP_START_DATE, X"7FFFFFFF");
399 UART_WRITE(TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_WP_START_DATE, X"7FFFFFFF");
400 UART_WRITE(TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_WP_LENGTH, X"000001F8");
400 UART_WRITE(TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_WP_LENGTH, X"000001F8");
401
401
402 END;
402 END;
403
403
404 PROCEDURE SET_WFP_DATA_SHAPING(
404 PROCEDURE SET_WFP_DATA_SHAPING(
405 SIGNAL TX : OUT STD_LOGIC;
405 SIGNAL TX : OUT STD_LOGIC;
406 CONSTANT tx_period : IN TIME;
406 CONSTANT tx_period : IN TIME;
407 CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8);
407 CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8);
408 CONSTANT DATA_SHAPING : IN STD_LOGIC_VECTOR(4 DOWNTO 0))
408 CONSTANT DATA_SHAPING : IN STD_LOGIC_VECTOR(4 DOWNTO 0))
409 IS
409 IS
410 BEGIN
410 BEGIN
411 UART_WRITE(TX,tx_period,ADDR_BASE_LFR & ADDR_LFR_WP_DATASHAPING, X"000000" & "000" & DATA_SHAPING);
411 UART_WRITE(TX,tx_period,ADDR_BASE_LFR & ADDR_LFR_WP_DATASHAPING, X"000000" & "000" & DATA_SHAPING);
412 END;
412 END;
413
413
414 PROCEDURE RESET_WFP_BURST_ENABLE(
414 PROCEDURE RESET_WFP_BURST_ENABLE(
415 SIGNAL TX : OUT STD_LOGIC;
415 SIGNAL TX : OUT STD_LOGIC;
416 SIGNAL RX : IN STD_LOGIC;
416 SIGNAL RX : IN STD_LOGIC;
417 CONSTANT tx_period : IN TIME;
417 CONSTANT tx_period : IN TIME;
418 CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8))
418 CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8))
419 IS
419 IS
420 VARIABLE data_read_v : STD_LOGIC_VECTOR(31 DOWNTO 0);
420 VARIABLE data_read_v : STD_LOGIC_VECTOR(31 DOWNTO 0);
421 BEGIN
421 BEGIN
422 UART_READ (TX,RX,tx_period,ADDR_BASE_LFR & ADDR_LFR_WP_CONTROL, data_read_v);
422 UART_READ (TX,RX,tx_period,ADDR_BASE_LFR & ADDR_LFR_WP_CONTROL, data_read_v);
423 UART_WRITE(TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_WP_CONTROL, X"000000" & data_read_v(7) & "0000000");
423 UART_WRITE(TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_WP_CONTROL, X"000000" & data_read_v(7) & "0000000");
424 END;
424 END;
425
425
426 PROCEDURE RESET_WFP_STATUS(
426 PROCEDURE RESET_WFP_STATUS(
427 SIGNAL TX : OUT STD_LOGIC;
427 SIGNAL TX : OUT STD_LOGIC;
428 CONSTANT tx_period : IN TIME;
428 CONSTANT tx_period : IN TIME;
429 CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8))
429 CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8))
430 IS
430 IS
431 BEGIN
431 BEGIN
432 UART_WRITE(TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_WP_STATUS, X"0000FFFF");
432 UART_WRITE(TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_WP_STATUS, X"0000FFFF");
433 END;
433 END;
434
434
435 PROCEDURE SET_WFP_BURST_ENABLE_REGISTER(
435 PROCEDURE SET_WFP_BURST_ENABLE_REGISTER(
436 SIGNAL TX : OUT STD_LOGIC;
436 SIGNAL TX : OUT STD_LOGIC;
437 SIGNAL RX : IN STD_LOGIC;
437 SIGNAL RX : IN STD_LOGIC;
438 CONSTANT tx_period : IN TIME;
438 CONSTANT tx_period : IN TIME;
439 CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8);
439 CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8);
440 CONSTANT LFR_MODE : IN STD_LOGIC_VECTOR(2 DOWNTO 0))
440 CONSTANT LFR_MODE : IN STD_LOGIC_VECTOR(2 DOWNTO 0))
441 IS
441 IS
442 VARIABLE data_read_v : STD_LOGIC_VECTOR(31 DOWNTO 0);
442 VARIABLE data_read_v : STD_LOGIC_VECTOR(31 DOWNTO 0);
443 BEGIN
443 BEGIN
444 CASE LFR_MODE IS
444 CASE LFR_MODE IS
445 WHEN LFR_MODE_STANDBY =>
445 WHEN LFR_MODE_STANDBY =>
446 UART_WRITE(TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_WP_CONTROL, X"00000000");
446 UART_WRITE(TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_WP_CONTROL, X"00000000");
447 WHEN LFR_MODE_NORMAL =>
447 WHEN LFR_MODE_NORMAL =>
448 UART_WRITE(TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_WP_CONTROL, X"00000000");
448 UART_WRITE(TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_WP_CONTROL, X"00000000");
449 UART_WRITE(TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_WP_CONTROL, X"0000000F");
449 UART_WRITE(TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_WP_CONTROL, X"0000000F");
450 WHEN LFR_MODE_BURST =>
450 WHEN LFR_MODE_BURST =>
451 UART_WRITE(TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_WP_CONTROL, X"00000040");
451 UART_WRITE(TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_WP_CONTROL, X"00000040");
452 UART_READ (TX,RX,tx_period,ADDR_BASE_LFR & ADDR_LFR_WP_CONTROL, data_read_v);
452 UART_READ (TX,RX,tx_period,ADDR_BASE_LFR & ADDR_LFR_WP_CONTROL, data_read_v);
453 UART_WRITE(TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_WP_CONTROL, data_read_v(31 DOWNTO 4) & "11" & data_read_v(1 DOWNTO 0));
453 UART_WRITE(TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_WP_CONTROL, data_read_v(31 DOWNTO 4) & "11" & data_read_v(1 DOWNTO 0));
454 WHEN LFR_MODE_SBM1 =>
454 WHEN LFR_MODE_SBM1 =>
455 UART_WRITE(TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_WP_CONTROL, X"00000020");
455 UART_WRITE(TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_WP_CONTROL, X"00000020");
456 UART_READ (TX,RX,tx_period,ADDR_BASE_LFR & ADDR_LFR_WP_CONTROL, data_read_v);
456 UART_READ (TX,RX,tx_period,ADDR_BASE_LFR & ADDR_LFR_WP_CONTROL, data_read_v);
457 UART_WRITE(TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_WP_CONTROL, data_read_v(31 DOWNTO 4) & "1111");
457 UART_WRITE(TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_WP_CONTROL, data_read_v(31 DOWNTO 4) & "1111");
458 WHEN LFR_MODE_SBM2 =>
458 WHEN LFR_MODE_SBM2 =>
459 UART_WRITE(TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_WP_CONTROL, X"00000040");
459 UART_WRITE(TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_WP_CONTROL, X"00000040");
460 UART_READ (TX,RX,tx_period,ADDR_BASE_LFR & ADDR_LFR_WP_CONTROL, data_read_v);
460 UART_READ (TX,RX,tx_period,ADDR_BASE_LFR & ADDR_LFR_WP_CONTROL, data_read_v);
461 UART_WRITE(TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_WP_CONTROL, data_read_v(31 DOWNTO 4) & "1111");
461 UART_WRITE(TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_WP_CONTROL, data_read_v(31 DOWNTO 4) & "1111");
462 WHEN OTHERS =>
462 WHEN OTHERS =>
463 UART_WRITE(TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_WP_CONTROL, X"00000000");
463 UART_WRITE(TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_WP_CONTROL, X"00000000");
464 END CASE;
464 END CASE;
465 END;
465 END;
466
466
467 END lpp_lfr_sim_pkg;
467 END lpp_lfr_sim_pkg;
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