HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Commit - r354:668500b2114b

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lib/VHDLIB/AMBA_Peripherals/vhdlsyn.txt created 644 +3 0

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	1	AMBA_Peripherals.vhd
	2	apb_devices_list.vhd
	3

lib/VHDLIB/DSP/filters/vhdlsyn.txt created 644 +1 0

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				1	filters.vhd

lib/VHDLIB/SOC/vhdlsyn.txt created 644 +1 0

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				1	SOC.vhd

lib/VHDLIB/boards/vhdlsyn.txt created 644 +1 0

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				1	boards.vhd

lib/VHDLIB/communication/vhdlsyn.txt created 644 +1 0

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				1	communication.vhd

lib/VHDLIB/data_converters/vhdlsyn.txt created 644 +1 0

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				1	data_converters.vhd

lib/VHDLIB/dirs.txt created 644 +7 0

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	1	AMBA_Peripherals
	2	sample_type
	3	general_purpose
	4	data_converters
	5	SOC
	6	DSP/filters
	7	memory

lib/VHDLIB/general_purpose/vhdlsyn.txt created 644 +1 0

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				1	general_purpose.vhd

lib/VHDLIB/memory/vhdlsyn.txt created 644 +1 0

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				1	memory.vhd

.hgignore 0 -2

             # use glob syntax.
             syntax: glob
             *.tex
             *.html
             *log*
             *.png
             *.dot
             *.css
             *.md5
             *.eps
             *.pdf
             *.toc
             *.map
             *.sty
             *.3
             *.js
             *.aux
             *.idx
             *doc*
             *Doc*
-            *vhdlsyn.txt
-            *dirs.txt
             *.orig
             *.o
             *.a
             *.bin
             *~
             apb_devices_list.h
             apb_devices_list.vhd
             twiddle.vhd
             primitives.vhd
             fftSm.vhd
             fftDp.vhd
             fft_components.vhd
             CoreFFT.vhd
             actram.vhd
             actar.vhd

APB_DEVICES/apb_devices_list.txt +7 0

             vendor VENDOR_LPP 19
             device ROCKET_TM 1
             device otherCore 2
             device LPP_SIMPLE_DIODE 3
             device LPP_MULTI_DIODE 4
             device LPP_LCD_CTRLR 5
             device LPP_UART 6
             device LPP_CNA 7
             device LPP_APB_ADC 8
             device LPP_CHENILLARD 9
             device LPP_IIR_CEL_FILTER 10
             device LPP_FIFO_PID 11
             device LPP_FFT 12
             device LPP_MATRIX 13
             device LPP_DELAY 14
             device LPP_USB 15
             device LPP_BALISE 16
+            device LPP_DMA_TYPE 17
+            device LPP_BOOTLOADER_TYPE 18
+            device LPP_LFR 19
+            device LPP_CLKSETTING 20
+            device LPP_DEBUG_DMA A0
+            device LPP_DEBUG_LFR A1
+            device LPP_DEBUG_LFR_ID A2

lib/staging/LPP/JCP/AMBA_Peripherals/AHB_DMA/lpp_dma_singleOrBurst.vhd +3 0

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             -------------------------------------------------------------------------------
             -- Author : Jean-christophe Pellion
             -- Mail   : jean-christophe.pellion@lpp.polytechnique.fr
             --          jean-christophe.pellion@easii-ic.com
             -------------------------------------------------------------------------------
             -- 1.0 - initial version
             -- 1.1 - (01/11/2013) FIX boundary error (1kB address should not be crossed by BURSTS)
             -------------------------------------------------------------------------------
             LIBRARY ieee;
             USE ieee.std_logic_1164.ALL;
             USE ieee.numeric_std.ALL;
             LIBRARY grlib;
             USE grlib.amba.ALL;
             USE grlib.stdlib.ALL;
             USE grlib.devices.ALL;
             USE GRLIB.DMA2AHB_Package.ALL;
             LIBRARY techmap;
             USE techmap.gencomp.ALL;
+            LIBRARY VHDLIB;
+            USE VHDLIB.apb_devices_list.ALL;
             LIBRARY staging;
             USE staging.lpp_dma_pkg_LPP_JCP.ALL;
             ENTITY lpp_dma_singleOrBurst_LPP_JCP IS
               GENERIC (
                 tech                    : INTEGER := inferred;
                 hindex                  : INTEGER := 2
                 );
               PORT (
                 -- AMBA AHB system signals
                 HCLK               : IN  STD_ULOGIC;
                 HRESETn            : IN  STD_ULOGIC;
                 --
                 run : IN STD_LOGIC;
                 -- AMBA AHB Master Interface
                 AHB_Master_In      : IN  AHB_Mst_In_Type;
                 AHB_Master_Out     : OUT AHB_Mst_Out_Type;
                 --
                 send               : IN  STD_LOGIC;
                 valid_burst        : IN  STD_LOGIC;  -- (1 => BURST , 0 => SINGLE)
                 done               : OUT STD_LOGIC;
                 ren                : OUT STD_LOGIC;
                 address            : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                 data               : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                 --
                 debug_dmaout_okay : OUT STD_LOGIC
                 );
             END;
             ARCHITECTURE Behavioral OF lpp_dma_singleOrBurst_LPP_JCP IS
               -----------------------------------------------------------------------------
               SIGNAL DMAIn  : DMA_In_Type;
               SIGNAL DMAOut : DMA_OUt_Type;
               -----------------------------------------------------------------------------
               -----------------------------------------------------------------------------
               -- CONTROL
               SIGNAL single_send : STD_LOGIC;
               SIGNAL burst_send  : STD_LOGIC;
               -----------------------------------------------------------------------------
               -- SEND SINGLE MODULE
               SIGNAL single_dmai            : DMA_In_Type;
               SIGNAL single_send_ok         : STD_LOGIC;
               SIGNAL single_send_ko         : STD_LOGIC;
               SIGNAL single_ren             : STD_LOGIC;
               -----------------------------------------------------------------------------
               -- SEND SINGLE MODULE
               SIGNAL burst_dmai            : DMA_In_Type;
               SIGNAL burst_send_ok         : STD_LOGIC;
               SIGNAL burst_send_ko         : STD_LOGIC;
               SIGNAL burst_ren             : STD_LOGIC;
               -----------------------------------------------------------------------------
               SIGNAL data_2_halfword      : STD_LOGIC_VECTOR(31 DOWNTO 0);
               -----------------------------------------------------------------------------
               SIGNAL send_reg : STD_LOGIC;
               SIGNAL send_s   : STD_LOGIC;
             BEGIN
               debug_dmaout_okay <= DMAOut.OKAY;
               -----------------------------------------------------------------------------
               -- DMA to AHB interface
               DMA2AHB_1 : DMA2AHB
                 GENERIC MAP (
                   hindex   => hindex,
                   vendorid => VENDOR_LPP,
                   deviceid => 10,
                   version  => 0,
                   syncrst  => 1,
                   boundary => 1)
                 PORT MAP (
                   HCLK    => HCLK,
                   HRESETn => HRESETn,
                   DMAIn   => DMAIn,
                   DMAOut  => DMAOut,
                   AHBIn   => AHB_Master_In,
                   AHBOut  => AHB_Master_Out);
               -----------------------------------------------------------------------------
               -----------------------------------------------------------------------------
               PROCESS (HCLK, HRESETn)
               BEGIN
                 IF HRESETn = '0' THEN
                   send_reg <= '0';
                 ELSIF HCLK'event AND HCLK = '1' THEN
                   send_reg <= send;
                 END IF;
               END PROCESS;
               send_s <= send_reg;
               single_send   <= send_s  WHEN valid_burst = '0' ELSE '0';
               burst_send    <= send_s  WHEN valid_burst = '1' ELSE '0';
               DMAIn         <= single_dmai      WHEN valid_burst = '0' ELSE burst_dmai;
               done  <= single_send_ok OR single_send_ko OR burst_send_ok  OR burst_send_ko;
               ren   <= burst_ren    WHEN valid_burst = '1' ELSE
                        single_ren;
               -----------------------------------------------------------------------------
               -- SEND 1 word by DMA
               -----------------------------------------------------------------------------
               lpp_dma_send_1word_1 : lpp_dma_send_1word_LPP_JCP
                 PORT MAP (
                   HCLK    => HCLK,
                   HRESETn => HRESETn,
                   DMAIn   => single_dmai,
                   DMAOut  => DMAOut,
                   send    => single_send,
                   address => address,
                   data    => data_2_halfword,
                   ren     => single_ren,
                   send_ok => single_send_ok,
                   send_ko => single_send_ko
                   );
               -----------------------------------------------------------------------------
               -- SEND 16 word by DMA (in burst mode)
               -----------------------------------------------------------------------------
               data_2_halfword(31 DOWNTO 0) <= data(15 DOWNTO 0) & data (31 DOWNTO 16);
               lpp_dma_send_16word_1 : lpp_dma_send_16word_LPP_JCP
                 PORT MAP (
                   HCLK    => HCLK,
                   HRESETn => HRESETn,
                   DMAIn   => burst_dmai,
                   DMAOut  => DMAOut,
                   send    => burst_send,
                   address => address,
                   data    => data_2_halfword,
                   ren     => burst_ren,
                   send_ok => burst_send_ok,
                   send_ko => burst_send_ko);
             END Behavioral;

lib/staging/LPP/JCP/AMBA_Peripherals/lpp_lfr/lpp_lfr_apbreg.vhd +4 -1

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             -------------------------------------------------------------------------------
             -- Author : Jean-christophe Pellion
             -- Mail   : jean-christophe.pellion@lpp.polytechnique.fr
             --          jean-christophe.pellion@easii-ic.com
             ----------------------------------------------------------------------------
             LIBRARY ieee;
             USE ieee.std_logic_1164.ALL;
             USE ieee.numeric_std.ALL;
             LIBRARY grlib;
             USE grlib.amba.ALL;
             USE grlib.stdlib.ALL;
             USE grlib.devices.ALL;
             LIBRARY techmap;
             USE techmap.gencomp.ALL;
+            LIBRARY VHDLIB;
+            USE VHDLIB.apb_devices_list.ALL;
             ENTITY lpp_lfr_apbreg_LPP_JCP IS
               GENERIC (
                 nb_data_by_buffer_size : INTEGER := 11;
                 nb_word_by_buffer_size : INTEGER := 11;
                 nb_snapshot_param_size  : INTEGER := 11;
                 delta_vector_size       : INTEGER := 20;
                 delta_vector_size_f0_2  : INTEGER := 3;
                 pindex   : INTEGER := 4;
                 paddr    : INTEGER := 4;
                 pmask    : INTEGER := 16#fff#;
                 pirq_ms  : INTEGER := 0;
                 pirq_wfp : INTEGER := 1;
                 top_lfr_version    : STD_LOGIC_VECTOR(23 DOWNTO 0));
               PORT (
                 -- AMBA AHB system signals
                 HCLK    : IN STD_ULOGIC;
                 HRESETn : IN STD_ULOGIC;
                 -- AMBA APB Slave Interface
                 apbi : IN  apb_slv_in_type;
                 apbo : OUT apb_slv_out_type;
                 ---------------------------------------------------------------------------
                 -- Spectral Matrix Reg
                 -- IN
                 ready_matrix_f0_0             : IN STD_LOGIC;
                 ready_matrix_f0_1             : IN STD_LOGIC;
                 ready_matrix_f1               : IN STD_LOGIC;
                 ready_matrix_f2               : IN STD_LOGIC;
                 error_anticipating_empty_fifo : IN STD_LOGIC;
                 error_bad_component_error     : IN STD_LOGIC;
                 debug_reg                     : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
                 -- OUT
                 status_ready_matrix_f0_0             : OUT STD_LOGIC;
                 status_ready_matrix_f0_1             : OUT STD_LOGIC;
                 status_ready_matrix_f1               : OUT STD_LOGIC;
                 status_ready_matrix_f2               : OUT STD_LOGIC;
                 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
                 status_error_bad_component_error     : OUT STD_LOGIC;
                 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
                 config_active_interruption_onError     : OUT STD_LOGIC;
                 addr_matrix_f0_0                       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                 addr_matrix_f0_1                       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                 addr_matrix_f1                         : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                 addr_matrix_f2                         : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                 ---------------------------------------------------------------------------
                 ---------------------------------------------------------------------------
                 -- WaveForm picker Reg
                 status_full                            : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
                 status_full_ack                        : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
                 status_full_err                        : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
                 status_new_err                         : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
                 -- OUT
                 data_shaping_BW  : OUT STD_LOGIC;
                 data_shaping_SP0 : OUT STD_LOGIC;
                 data_shaping_SP1 : OUT STD_LOGIC;
                 data_shaping_R0  : OUT STD_LOGIC;
                 data_shaping_R1  : OUT STD_LOGIC;
                 delta_snapshot     : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
                 delta_f0           : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
                 delta_f0_2         : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
                 delta_f1           : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
                 delta_f2           : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
                 nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
                 nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
                 nb_snapshot_param  : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
                 enable_f0 : OUT STD_LOGIC;
                 enable_f1 : OUT STD_LOGIC;
                 enable_f2 : OUT STD_LOGIC;
                 enable_f3 : OUT STD_LOGIC;
                 burst_f0 : OUT STD_LOGIC;
                 burst_f1 : OUT STD_LOGIC;
                 burst_f2 : OUT STD_LOGIC;
                 run : OUT STD_LOGIC;
                 addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                 addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                 start_date   : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
                 ---------------------------------------------------------------------------
                 debug_reg0   : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
                 debug_reg1   : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
                 debug_reg2   : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
                 debug_reg3   : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
                 debug_reg4   : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
                 debug_reg5   : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
                 debug_reg6   : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
                 debug_reg7   : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
                 ---------------------------------------------------------------------------
                 );
             END lpp_lfr_apbreg_LPP_JCP;
             ARCHITECTURE beh OF lpp_lfr_apbreg_LPP_JCP IS
               CONSTANT REVISION : INTEGER := 1;
               CONSTANT pconfig : apb_config_type := (
 => ahb_device_reg (VENDOR_LPP, LPP_LFR, 0, REVISION, pirq_wfp),
 => apb_iobar(paddr, pmask));
               TYPE lpp_SpectralMatrix_regs IS RECORD
                 config_active_interruption_onNewMatrix : STD_LOGIC;
                 config_active_interruption_onError     : STD_LOGIC;
                 status_ready_matrix_f0_0               : STD_LOGIC;
                 status_ready_matrix_f0_1               : STD_LOGIC;
                 status_ready_matrix_f1                 : STD_LOGIC;
                 status_ready_matrix_f2                 : STD_LOGIC;
                 status_error_anticipating_empty_fifo   : STD_LOGIC;
                 status_error_bad_component_error       : STD_LOGIC;
                 addr_matrix_f0_0                       : STD_LOGIC_VECTOR(31 DOWNTO 0);
                 addr_matrix_f0_1                       : STD_LOGIC_VECTOR(31 DOWNTO 0);
                 addr_matrix_f1                         : STD_LOGIC_VECTOR(31 DOWNTO 0);
                 addr_matrix_f2                         : STD_LOGIC_VECTOR(31 DOWNTO 0);
               END RECORD;
               SIGNAL reg_sp : lpp_SpectralMatrix_regs;
               TYPE lpp_WaveformPicker_regs IS RECORD
                 status_full        : STD_LOGIC_VECTOR(3 DOWNTO 0);
                 status_full_err    : STD_LOGIC_VECTOR(3 DOWNTO 0);
                 status_new_err     : STD_LOGIC_VECTOR(3 DOWNTO 0);
                 data_shaping_BW    : STD_LOGIC;
                 data_shaping_SP0   : STD_LOGIC;
                 data_shaping_SP1   : STD_LOGIC;
                 data_shaping_R0    : STD_LOGIC;
                 data_shaping_R1    : STD_LOGIC;
                 delta_snapshot     : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
                 delta_f0           : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
                 delta_f0_2        : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
                 delta_f1           : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
                 delta_f2           : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
                 nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
                 nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
                 nb_snapshot_param  : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
                 enable_f0          : STD_LOGIC;
                 enable_f1          : STD_LOGIC;
                 enable_f2          : STD_LOGIC;
                 enable_f3          : STD_LOGIC;
                 burst_f0           : STD_LOGIC;
                 burst_f1           : STD_LOGIC;
                 burst_f2           : STD_LOGIC;
                 run                : STD_LOGIC;
                 addr_data_f0       : STD_LOGIC_VECTOR(31 DOWNTO 0);
                 addr_data_f1       : STD_LOGIC_VECTOR(31 DOWNTO 0);
                 addr_data_f2       : STD_LOGIC_VECTOR(31 DOWNTO 0);
                 addr_data_f3       : STD_LOGIC_VECTOR(31 DOWNTO 0);
                 start_date         : STD_LOGIC_VECTOR(30 DOWNTO 0);
               END RECORD;
               SIGNAL reg_wp : lpp_WaveformPicker_regs;
               SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
               -----------------------------------------------------------------------------
               -- IRQ
               -----------------------------------------------------------------------------
               CONSTANT IRQ_WFP_SIZE : INTEGER := 12;
               SIGNAL irq_wfp_ZERO  : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
               SIGNAL irq_wfp_reg_s : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
               SIGNAL irq_wfp_reg   : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
               SIGNAL irq_wfp       : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
               SIGNAL ored_irq_wfp  : STD_LOGIC;
             BEGIN  -- beh
               status_ready_matrix_f0_0             <= reg_sp.status_ready_matrix_f0_0;
               status_ready_matrix_f0_1             <= reg_sp.status_ready_matrix_f0_1;
               status_ready_matrix_f1               <= reg_sp.status_ready_matrix_f1;
               status_ready_matrix_f2               <= reg_sp.status_ready_matrix_f2;
               status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo;
               status_error_bad_component_error     <= reg_sp.status_error_bad_component_error;
               config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix;
               config_active_interruption_onError     <= reg_sp.config_active_interruption_onError;
               addr_matrix_f0_0                       <= reg_sp.addr_matrix_f0_0;
               addr_matrix_f0_1                       <= reg_sp.addr_matrix_f0_1;
               addr_matrix_f1                         <= reg_sp.addr_matrix_f1;
               addr_matrix_f2                         <= reg_sp.addr_matrix_f2;
               data_shaping_BW  <= NOT reg_wp.data_shaping_BW;
               data_shaping_SP0 <= reg_wp.data_shaping_SP0;
               data_shaping_SP1 <= reg_wp.data_shaping_SP1;
               data_shaping_R0  <= reg_wp.data_shaping_R0;
               data_shaping_R1  <= reg_wp.data_shaping_R1;
               delta_snapshot     <= reg_wp.delta_snapshot;
               delta_f0           <= reg_wp.delta_f0;
               delta_f0_2         <= reg_wp.delta_f0_2;
               delta_f1           <= reg_wp.delta_f1;
               delta_f2           <= reg_wp.delta_f2;
               nb_data_by_buffer <= reg_wp.nb_data_by_buffer;
               nb_word_by_buffer <= reg_wp.nb_word_by_buffer;
               nb_snapshot_param  <= reg_wp.nb_snapshot_param;
               enable_f0 <= reg_wp.enable_f0;
               enable_f1 <= reg_wp.enable_f1;
               enable_f2 <= reg_wp.enable_f2;
               enable_f3 <= reg_wp.enable_f3;
               burst_f0 <= reg_wp.burst_f0;
               burst_f1 <= reg_wp.burst_f1;
               burst_f2 <= reg_wp.burst_f2;
               run <= reg_wp.run;
               addr_data_f0 <= reg_wp.addr_data_f0;
               addr_data_f1 <= reg_wp.addr_data_f1;
               addr_data_f2 <= reg_wp.addr_data_f2;
               addr_data_f3 <= reg_wp.addr_data_f3;
               start_date <= reg_wp.start_date;
               lpp_lfr_apbreg : PROCESS (HCLK, HRESETn)
                 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
               BEGIN  -- PROCESS lpp_dma_top
                 IF HRESETn = '0' THEN               -- asynchronous reset (active low)
                   reg_sp.config_active_interruption_onNewMatrix <= '0';
                   reg_sp.config_active_interruption_onError     <= '0';
                   reg_sp.status_ready_matrix_f0_0               <= '0';
                   reg_sp.status_ready_matrix_f0_1               <= '0';
                   reg_sp.status_ready_matrix_f1                 <= '0';
                   reg_sp.status_ready_matrix_f2                 <= '0';
                   reg_sp.status_error_anticipating_empty_fifo   <= '0';
                   reg_sp.status_error_bad_component_error       <= '0';
                   reg_sp.addr_matrix_f0_0                       <= (OTHERS => '0');
                   reg_sp.addr_matrix_f0_1                       <= (OTHERS => '0');
                   reg_sp.addr_matrix_f1                         <= (OTHERS => '0');
                   reg_sp.addr_matrix_f2                         <= (OTHERS => '0');
                   prdata                                        <= (OTHERS => '0');
                   apbo.pirq <= (OTHERS => '0');
                   status_full_ack <= (OTHERS => '0');
                   reg_wp.data_shaping_BW    <= '0';
                   reg_wp.data_shaping_SP0   <= '0';
                   reg_wp.data_shaping_SP1   <= '0';
                   reg_wp.data_shaping_R0    <= '0';
                   reg_wp.data_shaping_R1    <= '0';
                   reg_wp.enable_f0          <= '0';
                   reg_wp.enable_f1          <= '0';
                   reg_wp.enable_f2          <= '0';
                   reg_wp.enable_f3          <= '0';
                   reg_wp.burst_f0           <= '0';
                   reg_wp.burst_f1           <= '0';
                   reg_wp.burst_f2           <= '0';
                   reg_wp.run                <= '0';
                   reg_wp.addr_data_f0       <= (OTHERS => '0');
                   reg_wp.addr_data_f1       <= (OTHERS => '0');
                   reg_wp.addr_data_f2       <= (OTHERS => '0');
                   reg_wp.addr_data_f3       <= (OTHERS => '0');
                   reg_wp.status_full        <= (OTHERS => '0');
                   reg_wp.status_full_err    <= (OTHERS => '0');
                   reg_wp.status_new_err     <= (OTHERS => '0');
                   reg_wp.delta_snapshot     <= (OTHERS => '0');
                   reg_wp.delta_f0           <= (OTHERS => '0');
                   reg_wp.delta_f0_2         <= (OTHERS => '0');
                   reg_wp.delta_f1           <= (OTHERS => '0');
                   reg_wp.delta_f2           <= (OTHERS => '0');
                   reg_wp.nb_data_by_buffer <= (OTHERS => '0');
                   reg_wp.nb_snapshot_param  <= (OTHERS => '0');
                   reg_wp.start_date         <= (OTHERS => '0');
                 ELSIF HCLK'EVENT AND HCLK = '1' THEN  -- rising clock edge
                   status_full_ack <= (OTHERS => '0');
                   reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR ready_matrix_f0_0;
                   reg_sp.status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1 OR ready_matrix_f0_1;
                   reg_sp.status_ready_matrix_f1   <= reg_sp.status_ready_matrix_f1 OR ready_matrix_f1;
                   reg_sp.status_ready_matrix_f2   <= reg_sp.status_ready_matrix_f2 OR ready_matrix_f2;
                   reg_sp.status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo OR error_anticipating_empty_fifo;
                   reg_sp.status_error_bad_component_error     <= reg_sp.status_error_bad_component_error OR error_bad_component_error;
                   all_status: FOR I IN 3 DOWNTO 0 LOOP
                     --reg_wp.status_full(I)     <= (reg_wp.status_full(I) OR status_full(I)) AND reg_wp.run;
                     --reg_wp.status_full_err(I) <= (reg_wp.status_full_err(I) OR status_full_err(I))  AND reg_wp.run;
                     --reg_wp.status_new_err(I)  <= (reg_wp.status_new_err(I) OR status_new_err(I)) AND reg_wp.run ;
                     reg_wp.status_full(I)     <= status_full(I) AND reg_wp.run;
                     reg_wp.status_full_err(I) <= status_full_err(I)  AND reg_wp.run;
                     reg_wp.status_new_err(I)  <= status_new_err(I) AND reg_wp.run ;
                   END LOOP all_status;
                   paddr             := "000000";
                   paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
                   prdata            <= (OTHERS => '0');
                   IF apbi.psel(pindex) = '1' THEN
                     -- APB DMA READ  --
                     CASE paddr(7 DOWNTO 2) IS
                       --
                       WHEN "000000" => prdata(0) <= reg_sp.config_active_interruption_onNewMatrix;
                                        prdata(1) <= reg_sp.config_active_interruption_onError;
                       WHEN "000001" => prdata(0) <= reg_sp.status_ready_matrix_f0_0;
                                        prdata(1) <= reg_sp.status_ready_matrix_f0_1;
                                        prdata(2) <= reg_sp.status_ready_matrix_f1;
                                        prdata(3) <= reg_sp.status_ready_matrix_f2;
                                        prdata(4) <= reg_sp.status_error_anticipating_empty_fifo;
                                        prdata(5) <= reg_sp.status_error_bad_component_error;
                       WHEN "000010" => prdata    <= reg_sp.addr_matrix_f0_0;
                       WHEN "000011" => prdata    <= reg_sp.addr_matrix_f0_1;
                       WHEN "000100" => prdata    <= reg_sp.addr_matrix_f1;
                       WHEN "000101" => prdata    <= reg_sp.addr_matrix_f2;
                       WHEN "000110" => prdata    <= debug_reg;
                                        --
                       WHEN "001000" => prdata(0) <= reg_wp.data_shaping_BW;
                                        prdata(1) <= reg_wp.data_shaping_SP0;
                                        prdata(2) <= reg_wp.data_shaping_SP1;
                                        prdata(3) <= reg_wp.data_shaping_R0;
                                        prdata(4) <= reg_wp.data_shaping_R1;
                       WHEN "001001" => prdata(0) <= reg_wp.enable_f0;
                                        prdata(1) <= reg_wp.enable_f1;
                                        prdata(2) <= reg_wp.enable_f2;
                                        prdata(3) <= reg_wp.enable_f3;
                                        prdata(4) <= reg_wp.burst_f0;
                                        prdata(5) <= reg_wp.burst_f1;
                                        prdata(6) <= reg_wp.burst_f2;
                                        prdata(7) <= reg_wp.run;
                       WHEN "001010" => prdata             <= reg_wp.addr_data_f0;
                       WHEN "001011" => prdata             <= reg_wp.addr_data_f1;
                       WHEN "001100" => prdata             <= reg_wp.addr_data_f2;
                       WHEN "001101" => prdata             <= reg_wp.addr_data_f3;
                       WHEN "001110" => prdata(3 DOWNTO 0) <= reg_wp.status_full;
                                        prdata(7 DOWNTO 4)  <= reg_wp.status_full_err;
                                        prdata(11 DOWNTO 8) <= reg_wp.status_new_err;
                       WHEN "001111" => prdata(delta_vector_size-1 DOWNTO 0)     <= reg_wp.delta_snapshot;
                       WHEN "010000" => prdata(delta_vector_size-1 DOWNTO 0)       <= reg_wp.delta_f0;
                       WHEN "010001" => prdata(delta_vector_size_f0_2-1 DOWNTO 0)  <= reg_wp.delta_f0_2;
                       WHEN "010010" => prdata(delta_vector_size-1 DOWNTO 0)       <= reg_wp.delta_f1;
                       WHEN "010011" => prdata(delta_vector_size-1 DOWNTO 0)       <= reg_wp.delta_f2;
                       WHEN "010100" => prdata(nb_data_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_data_by_buffer;
                       WHEN "010101" => prdata(nb_snapshot_param_size-1 DOWNTO 0)  <= reg_wp.nb_snapshot_param;
                       WHEN "010110" => prdata(30 DOWNTO 0)                        <= reg_wp.start_date;
                       WHEN "010111" => prdata(nb_word_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_word_by_buffer;
                       ----------------------------------------------------
                       WHEN "100000" => prdata(31 DOWNTO 0) <= debug_reg0(31 DOWNTO 0);
                       WHEN "100001" => prdata(31 DOWNTO 0) <= debug_reg1(31 DOWNTO 0);
                       WHEN "100010" => prdata(31 DOWNTO 0) <= debug_reg2(31 DOWNTO 0);
                       WHEN "100011" => prdata(31 DOWNTO 0) <= debug_reg3(31 DOWNTO 0);
                       WHEN "100100" => prdata(31 DOWNTO 0) <= debug_reg4(31 DOWNTO 0);
                       WHEN "100101" => prdata(31 DOWNTO 0) <= debug_reg5(31 DOWNTO 0);
                       WHEN "100110" => prdata(31 DOWNTO 0) <= debug_reg6(31 DOWNTO 0);
                       WHEN "100111" => prdata(31 DOWNTO 0) <= debug_reg7(31 DOWNTO 0);
                       ----------------------------------------------------
                       WHEN "111100" => prdata(23 DOWNTO 0) <= top_lfr_version(23 DOWNTO 0);
                       WHEN OTHERS   => NULL;
                     END CASE;
                     IF (apbi.pwrite AND apbi.penable) = '1' THEN
                       -- APB DMA WRITE --
                       CASE paddr(7 DOWNTO 2) IS
                         --
                         WHEN "000000" => reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0);
                                          reg_sp.config_active_interruption_onError <= apbi.pwdata(1);
                         WHEN "000001" => reg_sp.status_ready_matrix_f0_0 <= apbi.pwdata(0);
                                          reg_sp.status_ready_matrix_f0_1             <= apbi.pwdata(1);
                                          reg_sp.status_ready_matrix_f1               <= apbi.pwdata(2);
                                          reg_sp.status_ready_matrix_f2               <= apbi.pwdata(3);
                                          reg_sp.status_error_anticipating_empty_fifo <= apbi.pwdata(4);
                                          reg_sp.status_error_bad_component_error     <= apbi.pwdata(5);
                         WHEN "000010" => reg_sp.addr_matrix_f0_0 <= apbi.pwdata;
                         WHEN "000011" => reg_sp.addr_matrix_f0_1 <= apbi.pwdata;
                         WHEN "000100" => reg_sp.addr_matrix_f1   <= apbi.pwdata;
                         WHEN "000101" => reg_sp.addr_matrix_f2   <= apbi.pwdata;
                                          --
                         WHEN "001000" => reg_wp.data_shaping_BW  <= apbi.pwdata(0);
                                          reg_wp.data_shaping_SP0 <= apbi.pwdata(1);
                                          reg_wp.data_shaping_SP1 <= apbi.pwdata(2);
                                          reg_wp.data_shaping_R0  <= apbi.pwdata(3);
                                          reg_wp.data_shaping_R1  <= apbi.pwdata(4);
                         WHEN "001001" => reg_wp.enable_f0 <= apbi.pwdata(0);
                                          reg_wp.enable_f1 <= apbi.pwdata(1);
                                          reg_wp.enable_f2 <= apbi.pwdata(2);
                                          reg_wp.enable_f3 <= apbi.pwdata(3);
                                          reg_wp.burst_f0  <= apbi.pwdata(4);
                                          reg_wp.burst_f1  <= apbi.pwdata(5);
                                          reg_wp.burst_f2  <= apbi.pwdata(6);
                                          reg_wp.run       <= apbi.pwdata(7);
                         WHEN "001010" => reg_wp.addr_data_f0 <= apbi.pwdata;
                         WHEN "001011" => reg_wp.addr_data_f1 <= apbi.pwdata;
                         WHEN "001100" => reg_wp.addr_data_f2 <= apbi.pwdata;
                         WHEN "001101" => reg_wp.addr_data_f3 <= apbi.pwdata;
                         WHEN "001110" => reg_wp.status_full  <= apbi.pwdata(3 DOWNTO 0);
                                          reg_wp.status_full_err <= apbi.pwdata(7 DOWNTO 4);
                                          reg_wp.status_new_err  <= apbi.pwdata(11 DOWNTO 8);
                                          status_full_ack(0)     <= reg_wp.status_full(0) AND NOT apbi.pwdata(0);
                                          status_full_ack(1)     <= reg_wp.status_full(1) AND NOT apbi.pwdata(1);
                                          status_full_ack(2)     <= reg_wp.status_full(2) AND NOT apbi.pwdata(2);
                                          status_full_ack(3)     <= reg_wp.status_full(3) AND NOT apbi.pwdata(3);
                         WHEN "001111" => reg_wp.delta_snapshot     <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
                         WHEN "010000" => reg_wp.delta_f0           <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
                         WHEN "010001" => reg_wp.delta_f0_2         <= apbi.pwdata(delta_vector_size_f0_2-1 DOWNTO 0);
                         WHEN "010010" => reg_wp.delta_f1           <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
                         WHEN "010011" => reg_wp.delta_f2           <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
                         WHEN "010100" => reg_wp.nb_data_by_buffer <= apbi.pwdata(nb_data_by_buffer_size-1 DOWNTO 0);
                         WHEN "010101" => reg_wp.nb_snapshot_param  <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0);
                         WHEN "010110" => reg_wp.start_date         <= apbi.pwdata(30 DOWNTO 0);
                         WHEN "010111" => reg_wp.nb_word_by_buffer <= apbi.pwdata(nb_word_by_buffer_size-1 DOWNTO 0);
                                          --
                         WHEN OTHERS   => NULL;
                       END CASE;
                     END IF;
                   END IF;
                   apbo.pirq(pirq_ms) <= ((reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0_0 OR
                                                                                              ready_matrix_f0_1 OR
                                                                                              ready_matrix_f1 OR
                                                                                              ready_matrix_f2)
                                          )
                                         OR
                                         (reg_sp.config_active_interruption_onError AND (error_anticipating_empty_fifo OR
                                                                                         error_bad_component_error)
                                          ));
                   --apbo.pirq(pirq_wfp) <= (status_full(0) OR status_full_err(0) OR status_new_err(0) OR
                   --                        status_full(1) OR status_full_err(1) OR status_new_err(1) OR
                   --                        status_full(2) OR status_full_err(2) OR status_new_err(2) OR
                   --                        status_full(3) OR status_full_err(3) OR status_new_err(3)
                   --                        );
                   apbo.pirq(pirq_wfp) <= ored_irq_wfp;
                 END IF;
               END PROCESS lpp_lfr_apbreg;
               apbo.pindex  <= pindex;
               apbo.pconfig <= pconfig;
               apbo.prdata  <= prdata;
               -----------------------------------------------------------------------------
               -- IRQ
               -----------------------------------------------------------------------------
               irq_wfp_reg_s <= status_full & status_full_err & status_new_err;
               PROCESS (HCLK, HRESETn)
               BEGIN  -- PROCESS
                 IF HRESETn = '0' THEN               -- asynchronous reset (active low)
                   irq_wfp_reg     <= (OTHERS => '0');
                 ELSIF HCLK'event AND HCLK = '1' THEN  -- rising clock edge
                   irq_wfp_reg <= irq_wfp_reg_s;
                 END IF;
               END PROCESS;
               all_irq_wfp: FOR I IN IRQ_WFP_SIZE-1 DOWNTO 0 GENERATE
                 irq_wfp(I) <= (NOT irq_wfp_reg(I)) AND irq_wfp_reg_s(I);
               END GENERATE all_irq_wfp;
               irq_wfp_ZERO <= (OTHERS => '0');
               ored_irq_wfp <= '0' WHEN irq_wfp = irq_wfp_ZERO ELSE '1';
-            END beh;
+            END beh;
  No newline at end of file

lib/staging/LPP/JCP/AMBA_Peripherals/lpp_lfr/lpp_lfr_pkg.vhd +44 0

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2013, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 2 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             -------------------------------------------------------------------------------
             -- Author : Jean-christophe Pellion
             -- Mail   : jean-christophe.pellion@lpp.polytechnique.fr
             --          jean-christophe.pellion@easii-ic.com
             -------------------------------------------------------------------------------
             LIBRARY ieee;
             USE ieee.std_logic_1164.ALL;
             LIBRARY grlib;
             USE grlib.amba.ALL;
             USE grlib.stdlib.ALL;
             USE grlib.devices.ALL;
             LIBRARY staging;
             USE staging.sample_type_LPP_JCP.ALL;
             PACKAGE lpp_lfr_pkg_LPP_JCP IS
               COMPONENT lpp_lfr_apbreg_LPP_JCP
                 GENERIC (
                   nb_data_by_buffer_size : INTEGER;
                   nb_word_by_buffer_size : INTEGER;
                   nb_snapshot_param_size : INTEGER;
                   delta_vector_size      : INTEGER;
                   delta_vector_size_f0_2 : INTEGER;
                   pindex                 : INTEGER;
                   paddr                  : INTEGER;
                   pmask                  : INTEGER;
                   pirq_ms                : INTEGER;
                   pirq_wfp               : INTEGER;
                   top_lfr_version        : STD_LOGIC_VECTOR(23 DOWNTO 0));
                 PORT (
                   HCLK                                   : IN  STD_ULOGIC;
                   HRESETn                                : IN  STD_ULOGIC;
                   apbi                                   : IN  apb_slv_in_type;
                   apbo                                   : OUT apb_slv_out_type;
                   ready_matrix_f0_0                      : IN  STD_LOGIC;
                   ready_matrix_f0_1                      : IN  STD_LOGIC;
                   ready_matrix_f1                        : IN  STD_LOGIC;
                   ready_matrix_f2                        : IN  STD_LOGIC;
                   error_anticipating_empty_fifo          : IN  STD_LOGIC;
                   error_bad_component_error              : IN  STD_LOGIC;
                   debug_reg                              : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   status_ready_matrix_f0_0               : OUT STD_LOGIC;
                   status_ready_matrix_f0_1               : OUT STD_LOGIC;
                   status_ready_matrix_f1                 : OUT STD_LOGIC;
                   status_ready_matrix_f2                 : OUT STD_LOGIC;
                   status_error_anticipating_empty_fifo   : OUT STD_LOGIC;
                   status_error_bad_component_error       : OUT STD_LOGIC;
                   config_active_interruption_onNewMatrix : OUT STD_LOGIC;
                   config_active_interruption_onError     : OUT STD_LOGIC;
                   addr_matrix_f0_0                       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   addr_matrix_f0_1                       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   addr_matrix_f1                         : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   addr_matrix_f2                         : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   status_full                            : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
                   status_full_ack                        : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
                   status_full_err                        : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
                   status_new_err                         : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
                   data_shaping_BW                        : OUT STD_LOGIC;
                   data_shaping_SP0                       : OUT STD_LOGIC;
                   data_shaping_SP1                       : OUT STD_LOGIC;
                   data_shaping_R0                        : OUT STD_LOGIC;
                   data_shaping_R1                        : OUT STD_LOGIC;
                   delta_snapshot                         : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
                   delta_f0                               : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
                   delta_f0_2                             : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
                   delta_f1                               : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
                   delta_f2                               : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
                   nb_data_by_buffer                      : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
                   nb_word_by_buffer                      : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
                   nb_snapshot_param                      : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
                   enable_f0                              : OUT STD_LOGIC;
                   enable_f1                              : OUT STD_LOGIC;
                   enable_f2                              : OUT STD_LOGIC;
                   enable_f3                              : OUT STD_LOGIC;
                   burst_f0                               : OUT STD_LOGIC;
                   burst_f1                               : OUT STD_LOGIC;
                   burst_f2                               : OUT STD_LOGIC;
                   run                                    : OUT STD_LOGIC;
                   addr_data_f0                           : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   addr_data_f1                           : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   addr_data_f2                           : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   addr_data_f3                           : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   start_date                             : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
                   debug_reg0                             : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   debug_reg1                             : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   debug_reg2                             : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   debug_reg3                             : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   debug_reg4                             : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   debug_reg5                             : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   debug_reg6                             : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   debug_reg7                             : IN  STD_LOGIC_VECTOR(31 DOWNTO 0));
               END COMPONENT;
               -----------------------------------------------------------------------------
               -- lpp_filter
               -----------------------------------------------------------------------------
               COMPONENT lpp_lfr_filter_LPP_JCP
                 GENERIC (
                   Mem_use : INTEGER);
                 PORT (
                   sample           : IN  Samples(7 DOWNTO 0);
                   sample_val       : IN  STD_LOGIC;
                   clk              : IN  STD_LOGIC;
                   rstn             : IN  STD_LOGIC;
                   data_shaping_SP0 : IN  STD_LOGIC;
                   data_shaping_SP1 : IN  STD_LOGIC;
                   data_shaping_R0  : IN  STD_LOGIC;
                   data_shaping_R1  : IN  STD_LOGIC;
                   sample_f0_val    : OUT STD_LOGIC;
                   sample_f1_val    : OUT STD_LOGIC;
                   sample_f2_val    : OUT STD_LOGIC;
                   sample_f3_val    : OUT STD_LOGIC;
                   sample_f0_wdata  : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
                   sample_f1_wdata  : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
                   sample_f2_wdata  : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
                   sample_f3_wdata  : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0));
               END COMPONENT;
               -----------------------------------------------------------------------------
               -- lpp_waveform
               -----------------------------------------------------------------------------
               COMPONENT lpp_waveform_LPP_JCP
                 GENERIC (
                   tech                   : INTEGER;
                   data_size              : INTEGER;
                   nb_data_by_buffer_size : INTEGER;
                   nb_word_by_buffer_size : INTEGER;
                   nb_snapshot_param_size : INTEGER;
                   delta_vector_size      : INTEGER;
                   delta_vector_size_f0_2 : INTEGER);
                 PORT (
                   clk                          : IN  STD_LOGIC;
                   rstn                         : IN  STD_LOGIC;
                   reg_run                      : IN  STD_LOGIC;
                   reg_start_date               : IN  STD_LOGIC_VECTOR(30 DOWNTO 0);
                   reg_delta_snapshot           : IN  STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
                   reg_delta_f0                 : IN  STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
                   reg_delta_f0_2               : IN  STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
                   reg_delta_f1                 : IN  STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
                   reg_delta_f2                 : IN  STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
                   enable_f0                    : IN  STD_LOGIC;
                   enable_f1                    : IN  STD_LOGIC;
                   enable_f2                    : IN  STD_LOGIC;
                   enable_f3                    : IN  STD_LOGIC;
                   burst_f0                     : IN  STD_LOGIC;
                   burst_f1                     : IN  STD_LOGIC;
                   burst_f2                     : IN  STD_LOGIC;
                   nb_data_by_buffer            : IN  STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
                   nb_word_by_buffer            : IN  STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
                   nb_snapshot_param            : IN  STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
                   status_full                  : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
                   status_full_ack              : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
                   status_full_err              : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
                   status_new_err               : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
                   coarse_time                  : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   fine_time                    : IN  STD_LOGIC_VECTOR(15 DOWNTO 0);
                   addr_data_f0                 : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   data_f0_in_valid             : IN  STD_LOGIC;
                   data_f0_in                   : IN  STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
                   addr_data_f1                 : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   data_f1_in_valid             : IN  STD_LOGIC;
                   data_f1_in                   : IN  STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
                   addr_data_f2                 : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   data_f2_in_valid             : IN  STD_LOGIC;
                   data_f2_in                   : IN  STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
                   addr_data_f3                 : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   data_f3_in_valid             : IN  STD_LOGIC;
                   data_f3_in                   : IN  STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
                   data_f0_addr_out             : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   data_f0_data_out             : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   data_f0_data_out_valid       : OUT STD_LOGIC;
                   data_f0_data_out_valid_burst : OUT STD_LOGIC;
                   data_f0_data_out_ren         : IN  STD_LOGIC;
                   data_f1_addr_out             : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   data_f1_data_out             : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   data_f1_data_out_valid       : OUT STD_LOGIC;
                   data_f1_data_out_valid_burst : OUT STD_LOGIC;
                   data_f1_data_out_ren         : IN  STD_LOGIC;
                   data_f2_addr_out             : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   data_f2_data_out             : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   data_f2_data_out_valid       : OUT STD_LOGIC;
                   data_f2_data_out_valid_burst : OUT STD_LOGIC;
                   data_f2_data_out_ren         : IN  STD_LOGIC;
                   data_f3_addr_out             : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   data_f3_data_out             : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   data_f3_data_out_valid       : OUT STD_LOGIC;
                   data_f3_data_out_valid_burst : OUT STD_LOGIC;
                   data_f3_data_out_ren         : IN  STD_LOGIC;
                   observation_reg              : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
               END COMPONENT;
+              -----------------------------------------------------------------------------
+              -- lpp_matrix_spectral
+              -----------------------------------------------------------------------------
+              COMPONENT lpp_lfr_ms_LPP_JCP
+                GENERIC (
+                  Mem_use : INTEGER);
+                PORT (
+                  clk                                    : IN  STD_LOGIC;
+                  rstn                                   : IN  STD_LOGIC;
+                  coarse_time                            : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
+                  fine_time                              : IN  STD_LOGIC_VECTOR(15 DOWNTO 0);
+                  sample_f0_wen                          : IN  STD_LOGIC_VECTOR(4 DOWNTO 0);
+                  sample_f0_wdata                        : IN  STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
+                  sample_f1_wen                          : IN  STD_LOGIC_VECTOR(4 DOWNTO 0);
+                  sample_f1_wdata                        : IN  STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
+                  sample_f3_wen                          : IN  STD_LOGIC_VECTOR(4 DOWNTO 0);
+                  sample_f3_wdata                        : IN  STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
+                  dma_addr                               : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+                  dma_data                               : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+                  dma_valid                              : OUT STD_LOGIC;
+                  dma_valid_burst                        : OUT STD_LOGIC;
+                  dma_ren                                : IN  STD_LOGIC;
+                  dma_done                               : IN  STD_LOGIC;
+                  ready_matrix_f0_0                      : OUT STD_LOGIC;
+                  ready_matrix_f0_1                      : OUT STD_LOGIC;
+                  ready_matrix_f1                        : OUT STD_LOGIC;
+                  ready_matrix_f2                        : OUT STD_LOGIC;
+                  error_anticipating_empty_fifo          : OUT STD_LOGIC;
+                  error_bad_component_error              : OUT STD_LOGIC;
+                  debug_reg                              : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+                  status_ready_matrix_f0_0               : IN  STD_LOGIC;
+                  status_ready_matrix_f0_1               : IN  STD_LOGIC;
+                  status_ready_matrix_f1                 : IN  STD_LOGIC;
+                  status_ready_matrix_f2                 : IN  STD_LOGIC;
+                  status_error_anticipating_empty_fifo   : IN  STD_LOGIC;
+                  status_error_bad_component_error       : IN  STD_LOGIC;
+                  config_active_interruption_onNewMatrix : IN  STD_LOGIC;
+                  config_active_interruption_onError     : IN  STD_LOGIC;
+                  addr_matrix_f0_0                       : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
+                  addr_matrix_f0_1                       : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
+                  addr_matrix_f1                         : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
+                  addr_matrix_f2                         : IN  STD_LOGIC_VECTOR(31 DOWNTO 0));
+              END COMPONENT;
             END;

lib/staging/LPP/JCP/AMBA_Peripherals/vhdlsyn.txt +1 0

             AMBA_Peripherals.vhd
             apb_lfr_time_managment/lpp_lfr_time_management.vhd
             apb_lfr_time_managment/apb_lfr_time_management.vhd
             apb_lfr_time_managment/lfr_time_management.vhd
             apb_lfr_time_managment/lpp_counter.vhd
             lpp_lfr/lpp_lfr_pkg.vhd
             lpp_lfr/lpp_lfr.vhd
             lpp_lfr/lpp_lfr_apbreg.vhd
             lpp_lfr/lpp_filter/FILTERcfg.vhd
             lpp_lfr/lpp_filter/lpp_lfr_filter.vhd
             lpp_lfr/lpp_waveform/lpp_waveform_pkg.vhd
             lpp_lfr/lpp_waveform/lpp_waveform.vhd
             lpp_lfr/lpp_waveform/lpp_waveform_burst.vhd
             lpp_lfr/lpp_waveform/lpp_waveform_snapshot.vhd
             lpp_lfr/lpp_waveform/lpp_waveform_snapshot_controler.vhd
             lpp_lfr/lpp_waveform/lpp_waveform_dma_genvalid.vhd
             lpp_lfr/lpp_waveform/lpp_waveform_fifo_arbiter.vhd
             lpp_lfr/lpp_waveform/lpp_waveform_fifo_arbiter_reg.vhd
             lpp_lfr/lpp_waveform/lpp_waveform_genaddress.vhd
+            lpp_lfr/lpp_matrix_spectral/lpp_lfr_ms.vhd
             AHB_DMA/lpp_dma_pkg.vhd
             AHB_DMA/lpp_dma_send_1word.vhd
             AHB_DMA/lpp_dma_send_16word.vhd
             AHB_DMA/lpp_dma_singleOrBurst.vhd

scripts/APB_DEV_UPDATER.sh +1 -1

             echo  "======================================================================================="
             echo  "---------------------------------------------------------------------------------------"
             echo  "                            LPP VHDL APB Devices List Updater		        	"
             echo  "                    Copyright (C) 2010 Laboratory of Plasmas Physic.			"
             echo  "======================================================================================="
             echo  '----------------------------------------------------------------------------------------
                         This file is a part of the LPP VHDL IP LIBRARY
                         Copyright (C) 2010, Laboratory of Plasmas Physic - CNRS
                         This program is free software; you can redistribute it and/or modify
                         it under the terms of the GNU General Public License as published by
                         the Free Software Foundation; either version 3 of the License, or
                         (at your option) any later version.
                         This program is distributed in the hope that it will be useful,
                         but WITHOUT ANY WARRANTY; without even the implied warranty of
                         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
                         GNU General Public License for more details.
                         You should have received a copy of the GNU General Public License
                         along with this program; if not, write to the Free Software
                         Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             ----------------------------------------------------------------------------------------'
             echo
             echo
             echo
             LPP_PATCHPATH=`pwd -L`
             cd $LPP_PATCHPATH/lib/lpp
             VHDFileStart=$LPP_PATCHPATH/APB_DEVICES/VHDListSTART
             VHDFileEnd=$LPP_PATCHPATH/APB_DEVICES/VHDListEND
             CFileStart=$LPP_PATCHPATH/APB_DEVICES/CListSTART
             CFileEnd=$LPP_PATCHPATH/APB_DEVICES/CListEND
             ListFILE=$LPP_PATCHPATH/APB_DEVICES/apb_devices_list.txt
-            VHDListFILE=$LPP_PATCHPATH/lib/lpp/lpp_amba/apb_devices_list.vhd
+            VHDListFILE=$LPP_PATCHPATH/lib/VHDLIB/AMBA_Peripherals/apb_devices_list.vhd
             CListFILE=$LPP_PATCHPATH/LPP_drivers/libsrc/AMBA/apb_devices_list.h
             cat $VHDFileStart>$VHDListFILE
             cat $CFileStart>$CListFILE
             grep vendor $ListFILE | sed "s/vendor /constant /" | sed "s/.* /&  : amba_vendor_type := 16#/" | sed "s/.*#*/&#;/" >> $VHDListFILE
             grep vendor $ListFILE | sed "s/vendor /#define /" | sed "s/.* /& 0x/" >> $CListFILE
             echo " ">>$VHDListFILE
             echo " ">>$CListFILE
             grep device $ListFILE | sed "s/device /constant /" |  sed "s/.* /&  : amba_device_type := 16#/" | sed "s/.*#*/&#;/"   >> $VHDListFILE
             grep device $ListFILE | sed "s/device /#define /" | sed "s/.* /& 0x/" >> $CListFILE
             cat $VHDFileEnd>>$VHDListFILE
             cat $CFileEnd>>$CListFILE
             sh $LPP_PATCHPATH/scripts/GPL_Patcher.sh vhd $LPP_PATCHPATH/lib/lpp/lpp_amba/
             sh $LPP_PATCHPATH/scripts/GPL_Patcher.sh h $LPP_PATCHPATH/LPP_drivers/libsrc/AMBA/
             cd $LPP_PATCHPATH

scripts/linklibs.sh +1 -1

             echo  "======================================================================================="
             echo  "---------------------------------------------------------------------------------------"
             echo  "                                LPP's GRLIB GLOBAL PATCHER				"
             echo  "                    Copyright (C) 2013 Laboratory of Plasmas Physic.			"
             echo  "======================================================================================="
             echo '------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             -------------------------------------------------------------------------------'
             echo
             echo
             echo
             VHDLIB_LIB_PATH=`pwd -L`
             source $VHDLIB_LIB_PATH/scripts/lpp_bash_functions.sh
             GRLIBPATH=$1
             if [ -d "$GRLIBPATH" ]; then
                     LPP_PATCHPATH=`relpath $GRLIBPATH/lib $VHDLIB_LIB_PATH`
                     echo $LPP_PATCHPATH
             	if [ -d "$GRLIBPATH/lib" ]; then
             		if [ -d "$GRLIBPATH/designs" ]; then
             			if [ -d "$GRLIBPATH/boards" ]; then
             				echo "Patch $1/lib/libs.txt..."
             				if(grep -q $LPP_PATCHPATH/lib/lpp $1/lib/libs.txt); then
             					echo "No need to Patch $1/lib/libs.txt..."
             				else
-            					echo $LPP_PATCHPATH/lib/lpp >>$1/lib/libs.txt
+            					echo $LPP_PATCHPATH/lib/VHDLIB >>$1/lib/libs.txt
             				fi
             				if(grep -q $LPP_PATCHPATH/lib/staging $1/lib/libs.txt); then
             					echo "No need to Patch $1/lib/libs.txt..."
             				else
             					echo $LPP_PATCHPATH/lib/staging >>$1/lib/libs.txt
             				fi
             				echo
             				echo
             				echo
             			else
             				echo "I can't find GRLIB in             $1"
             			fi
             		else
             			echo "I can't find GRLIB in             $1"
             		fi
             	else
             		echo "I can't find GRLIB in             $1"
             	fi
             else
             	echo "I can't find GRLIB in             $1"
             fi

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