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Preliminary working IAP Memctrlr integration....
pellion -
r483:6448706d4a4e JC
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1 VHDLIB=../..
2 SCRIPTSDIR=$(VHDLIB)/scripts/
3 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
4 TOP=UT8ER1M32_test_board_top
5 BOARD=UT8ER1M32-test-board
6 include $(VHDLIB)/boards/$(BOARD)/Makefile.inc
7 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
8 UCF=$(VHDLIB)/boards/$(BOARD)/$(TOP).ucf
9 QSF=$(VHDLIB)/boards/$(BOARD)/$(TOP).qsf
10 EFFORT=high
11 XSTOPT=
12 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
13 VHDLSYNFILES= UT8ER1M32-test-board_top.vhd
14
15 PDC=$(VHDLIB)/boards/$(BOARD)/default.pdc
16 BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut
17 CLEAN=soft-clean
18
19 TECHLIBS = proasic3e
20
21 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
22 tmtc openchip hynix ihp gleichmann micron usbhc
23
24 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
25 pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
26 ./amba_lcd_16x2_ctrlr \
27 ./general_purpose/lpp_AMR \
28 ./general_purpose/lpp_balise \
29 ./general_purpose/lpp_delay \
30 ./dsp/lpp_fft \
31 ./lpp_bootloader \
32 ./lpp_cna \
33 ./lpp_demux \
34 ./lpp_matrix \
35 ./lpp_uart \
36 ./lpp_usb \
37 ./lpp_Header \
38 ./lpp_sim \
39 ./lpp_lfr_pkg \
40 ./lpp_debug_lfr_pkg \
41 ./lpp_top_lfr
42
43 FILESKIP =lpp_lfr_ms.vhd \
44 i2cmst.vhd \
45 APB_MULTI_DIODE.vhd \
46 APB_SIMPLE_DIODE.vhd \
47 Top_MatrixSpec.vhd \
48 APB_FFT.vhd \
49 async_1Mx16.vhd \
50 CY7C1061DV33.vhd
51
52
53
54 include $(GRLIB)/bin/Makefile
55 include $(GRLIB)/software/leon3/Makefile
56
57 ################## project specific targets ##########################
58
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
30 LIBRARY gaisler;
31 USE gaisler.memctrl.ALL;
32 USE gaisler.leon3.ALL;
33 USE gaisler.uart.ALL;
34 USE gaisler.misc.ALL;
35 USE gaisler.spacewire.ALL; -- PLE
36 LIBRARY esa;
37 USE esa.memoryctrl.ALL;
38 LIBRARY lpp;
39 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_lfr_pkg.ALL;
42 USE lpp.iir_filter.ALL;
43 USE lpp.general_purpose.ALL;
44 USE lpp.lpp_lfr_time_management.ALL;
45 USE lpp.lpp_leon3_soc_pkg.ALL;
46
47 ENTITY UT8ER1M32_test_board_top IS
48
49 PORT (
50 clk_50 : IN STD_LOGIC;
51 clk_49 : IN STD_LOGIC;
52 reset : IN STD_LOGIC;
53 --BPs
54 BP0 : IN STD_LOGIC;
55 BP1 : IN STD_LOGIC;
56 --LEDs
57 LED0 : OUT STD_LOGIC;
58 LED1 : OUT STD_LOGIC;
59 LED2 : OUT STD_LOGIC;
60 --UARTs
61 TXD1 : IN STD_LOGIC;
62 RXD1 : OUT STD_LOGIC;
63 nCTS1 : OUT STD_LOGIC;
64 nRTS1 : IN STD_LOGIC;
65
66 TXD2 : IN STD_LOGIC;
67 RXD2 : OUT STD_LOGIC;
68
69 -- SRAM
70 SRAM_nWE : OUT STD_LOGIC;
71 SRAM_nCE1 : OUT STD_LOGIC;
72 SRAM_nCE2 : OUT STD_LOGIC;
73 SRAM_nOE : OUT STD_LOGIC;
74 SRAM_MBE : INOUT STD_LOGIC;
75 SRAM_nBUSY : IN STD_LOGIC;
76 --SRAM_nSCRUB : IN STD_LOGIC;
77 SRAM_A : OUT STD_LOGIC_VECTOR(18 DOWNTO 0);
78 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
79 );
80
81 END UT8ER1M32_test_board_top;
82
83
84 ARCHITECTURE beh OF UT8ER1M32_test_board_top IS
85 SIGNAL clk_25 : STD_LOGIC := '0';
86 -----------------------------------------------------------------------------
87 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
88 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
89 --
90 SIGNAL errorn : STD_LOGIC;
91 -- UART AHB ---------------------------------------------------------------
92 SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
93 SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
94
95 -- UART APB ---------------------------------------------------------------
96 SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
97 SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
98 --
99 SIGNAL I00_s : STD_LOGIC;
100 --
101 CONSTANT NB_APB_SLAVE : INTEGER := 1;
102 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
103 CONSTANT NB_AHB_MASTER : INTEGER := 1;
104
105 SIGNAL apbi_ext : apb_slv_in_type;
106 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5):= (OTHERS => apb_none);
107 SIGNAL ahbi_s_ext : ahb_slv_in_type;
108 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3):= (OTHERS => ahbs_none);
109 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
110 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1):= (OTHERS => ahbm_none);
111 --SRAM-----------------------------------------------------------------------
112 SIGNAL SRAM_CE : STD_LOGIC_VECTOR(1 downto 0);
113
114 BEGIN -- beh
115
116 -----------------------------------------------------------------------------
117 -- CLK
118 -----------------------------------------------------------------------------
119
120
121 PROCESS(clk_50)
122 BEGIN
123 IF clk_50'EVENT AND clk_50 = '1' THEN
124 clk_25 <= NOT clk_25;
125 END IF;
126 END PROCESS;
127
128 -----------------------------------------------------------------------------
129
130
131 PROCESS (clk_49, reset)
132 BEGIN -- PROCESS
133 IF reset = '0' THEN -- asynchronous reset (active low)
134 I00_s <= '0';
135 ELSIF clk_49'event AND clk_49 = '1' THEN -- rising clock edge
136 I00_s <= NOT I00_s;
137 END IF;
138 END PROCESS;
139
140 nCTS1 <= '1';
141
142 SRAM_nCE1 <= SRAM_CE(0);
143 SRAM_nCE2 <= SRAM_CE(1);
144
145
146
147 leon3_soc_1 : leon3_soc
148 GENERIC MAP (
149 fabtech => apa3e,
150 memtech => apa3e,
151 padtech => inferred,
152 clktech => inferred,
153 disas => 0,
154 dbguart => 0,
155 pclow => 2,
156 clk_freq => 25000,
157 NB_CPU => 1,
158 ENABLE_FPU => 0,
159 FPU_NETLIST => 0,
160 ENABLE_DSU => 1,
161 ENABLE_AHB_UART => 1,
162 ENABLE_APB_UART => 1,
163 ENABLE_IRQMP => 1,
164 ENABLE_GPT => 1,
165 NB_AHB_MASTER => NB_AHB_MASTER,
166 NB_AHB_SLAVE => NB_AHB_SLAVE,
167 NB_APB_SLAVE => NB_APB_SLAVE,
168 ADDRESS_SIZE => 19,
169 USES_IAP_MEMCTRLR => 1)
170 PORT MAP (
171 clk => clk_25,
172 reset => reset,
173 errorn => errorn,
174 ahbrxd => TXD1,
175 ahbtxd => RXD1,
176 urxd1 => TXD2,
177 utxd1 => RXD2,
178 address => SRAM_A,
179 data => SRAM_DQ,
180 nSRAM_BE0 => LED0,
181 nSRAM_BE1 => LED1,
182 nSRAM_BE2 => LED2,
183 nSRAM_BE3 => open,
184 nSRAM_WE => SRAM_nWE,
185 nSRAM_CE => SRAM_CE,
186 nSRAM_OE => SRAM_nOE,
187 nSRAM_READY => SRAM_nBUSY,
188 SRAM_MBE => SRAM_MBE,
189
190 apbi_ext => apbi_ext,
191 apbo_ext => apbo_ext,
192 ahbi_s_ext => ahbi_s_ext,
193 ahbo_s_ext => ahbo_s_ext,
194 ahbi_m_ext => ahbi_m_ext,
195 ahbo_m_ext => ahbo_m_ext);
196
197
198
199 END beh; No newline at end of file
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