##// END OF EJS Templates
HG_REPOSITORIES » LPP » INSTRUMENTATION » USERS » PELLION » VHD_Lib
RSS

Clone from http://pc-instru.lpp.polytechnique.fr:5000/VHD_Lib

Updated MINI-LFR Board and design with EM constraint files.
Jeandet Alexis -
r635:6428e5d35e0a simu_with_Leon3
parent child
Show More
Show file before | Show file after | Hide comments
@@ -0,0 +1,114
1 ################################################################################
2 # SDC WRITER VERSION "3.1";
3 # DESIGN "LFR_EQM";
4 # Timing constraints scenario: "Primary";
5 # DATE "Fri Apr 24 16:02:16 2015";
6 # VENDOR "Actel";
7 # PROGRAM "Actel Designer Software Release v9.1 SP5";
8 # VERSION "9.1.5.1" Copyright (C) 1989-2012 Actel Corp.
9 ################################################################################
10
11
12 set sdc_version 1.7
13
14
15 ######## Clock Constraints ########
16
17 create_clock -name { clk100MHz } -period 10.000 -waveform { 0.000 5.000 } { clk100MHz }
18
19 create_clock -name { clk49_152MHz } -period 20.345 -waveform { 0.000 10.172 } { clk49_152MHz }
20
21 create_clock -name { clk_25:Q } -period 40.000 -waveform { 0.000 20.000 } { clk_25:Q }
22
23 create_clock -name { clk_24:Q } -period 40.690 -waveform { 0.000 20.345 } { clk_24:Q }
24
25 create_clock -name { spw_inputloop.1.spw_phy0/rxclki_RNO:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.1.spw_phy0/rxclki_RNO:Y }
26
27 create_clock -name { spw_inputloop.0.spw_phy0/rxclki_RNO:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.0.spw_phy0/rxclki_RNO:Y }
28
29
30
31 ######## Generated Clock Constraints ########
32
33
34
35 ######## Clock Source Latency Constraints #########
36
37
38
39 ######## Input Delay Constraints ########
40
41 set_input_delay 0.000 -clock { clk_25:Q } [get_ports { SRAM_DQ[0] SRAM_DQ[10] SRAM_DQ[11] SRAM_DQ[12] SRAM_DQ[13] SRAM_DQ[14] SRAM_DQ[15] SRAM_DQ[16] SRAM_DQ[17] SRAM_DQ[18] SRAM_DQ[19] SRAM_DQ[1] SRAM_DQ[20] SRAM_DQ[21] SRAM_DQ[22] SRAM_DQ[23] SRAM_DQ[24] SRAM_DQ[25] SRAM_DQ[26] SRAM_DQ[27] SRAM_DQ[28] SRAM_DQ[29] SRAM_DQ[2] SRAM_DQ[30] SRAM_DQ[31] SRAM_DQ[3] SRAM_DQ[4] SRAM_DQ[5] SRAM_DQ[6] SRAM_DQ[7] SRAM_DQ[8] SRAM_DQ[9] }]
42 set_max_delay 30.000 -from [get_ports { SRAM_DQ[0] SRAM_DQ[10] SRAM_DQ[11] SRAM_DQ[12] SRAM_DQ[13] SRAM_DQ[14] \
43 data[15] SRAM_DQ[16] SRAM_DQ[17] SRAM_DQ[18] SRAM_DQ[19] SRAM_DQ[1] SRAM_DQ[20] SRAM_DQ[21] SRAM_DQ[22] SRAM_DQ[23] \
44 data[24] SRAM_DQ[25] SRAM_DQ[26] SRAM_DQ[27] SRAM_DQ[28] SRAM_DQ[29] SRAM_DQ[2] SRAM_DQ[30] SRAM_DQ[31] SRAM_DQ[3] \
45 data[4] SRAM_DQ[5] SRAM_DQ[6] SRAM_DQ[7] SRAM_DQ[8] SRAM_DQ[9] }] -to [get_clocks {clk_25:Q}]
46 set_min_delay 0.000 -from [get_ports { SRAM_DQ[0] SRAM_DQ[10] SRAM_DQ[11] SRAM_DQ[12] SRAM_DQ[13] SRAM_DQ[14] \
47 data[15] SRAM_DQ[16] SRAM_DQ[17] SRAM_DQ[18] SRAM_DQ[19] SRAM_DQ[1] SRAM_DQ[20] SRAM_DQ[21] SRAM_DQ[22] SRAM_DQ[23] \
48 data[24] SRAM_DQ[25] SRAM_DQ[26] SRAM_DQ[27] SRAM_DQ[28] SRAM_DQ[29] SRAM_DQ[2] SRAM_DQ[30] SRAM_DQ[31] SRAM_DQ[3] \
49 data[4] SRAM_DQ[5] SRAM_DQ[6] SRAM_DQ[7] SRAM_DQ[8] SRAM_DQ[9] }] -to [get_clocks {clk_25:Q}]
50
51 #set_input_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_BUSY }]
52 #set_max_delay 10.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}]
53 #set_min_delay 0.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}]
54
55
56
57 ######## Output Delay Constraints ########
58
59 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { SRAM_DQ[0] SRAM_DQ[10] SRAM_DQ[11] SRAM_DQ[12] SRAM_DQ[13] SRAM_DQ[14] SRAM_DQ[15] SRAM_DQ[16] SRAM_DQ[17] SRAM_DQ[18] SRAM_DQ[19] SRAM_DQ[1] SRAM_DQ[20] SRAM_DQ[21] SRAM_DQ[22] SRAM_DQ[23] SRAM_DQ[24] SRAM_DQ[25] SRAM_DQ[26] SRAM_DQ[27] SRAM_DQ[28] SRAM_DQ[29] SRAM_DQ[2] SRAM_DQ[30] SRAM_DQ[31] SRAM_DQ[3] SRAM_DQ[4] SRAM_DQ[5] SRAM_DQ[6] SRAM_DQ[7] SRAM_DQ[8] SRAM_DQ[9] }]
60 set_max_delay 18.000 -from [get_clocks {clk_25:Q}] -to [get_ports { SRAM_DQ[0] SRAM_DQ[10] SRAM_DQ[11] \
61 data[12] SRAM_DQ[13] SRAM_DQ[14] SRAM_DQ[15] SRAM_DQ[16] SRAM_DQ[17] SRAM_DQ[18] SRAM_DQ[19] SRAM_DQ[1] SRAM_DQ[20] \
62 data[21] SRAM_DQ[22] SRAM_DQ[23] SRAM_DQ[24] SRAM_DQ[25] SRAM_DQ[26] SRAM_DQ[27] SRAM_DQ[28] SRAM_DQ[29] SRAM_DQ[2] \
63 data[30] SRAM_DQ[31] SRAM_DQ[3] SRAM_DQ[4] SRAM_DQ[5] SRAM_DQ[6] SRAM_DQ[7] SRAM_DQ[8] SRAM_DQ[9] }]
64 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { SRAM_DQ[0] SRAM_DQ[10] SRAM_DQ[11] \
65 data[12] SRAM_DQ[13] SRAM_DQ[14] SRAM_DQ[15] SRAM_DQ[16] SRAM_DQ[17] SRAM_DQ[18] SRAM_DQ[19] SRAM_DQ[1] SRAM_DQ[20] \
66 data[21] SRAM_DQ[22] SRAM_DQ[23] SRAM_DQ[24] SRAM_DQ[25] SRAM_DQ[26] SRAM_DQ[27] SRAM_DQ[28] SRAM_DQ[29] SRAM_DQ[2] \
67 data[30] SRAM_DQ[31] SRAM_DQ[3] SRAM_DQ[4] SRAM_DQ[5] SRAM_DQ[6] SRAM_DQ[7] SRAM_DQ[8] SRAM_DQ[9] }]
68
69 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { SRAM_A[0] SRAM_A[10] SRAM_A[11] SRAM_A[12] SRAM_A[13] SRAM_A[14] SRAM_A[15] SRAM_A[16] SRAM_A[17] SRAM_A[18] SRAM_A[19] SRAM_A[1] SRAM_A[2] SRAM_A[3] SRAM_A[4] SRAM_A[5] SRAM_A[6] SRAM_A[7] SRAM_A[8] SRAM_A[9] }]
70 set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { SRAM_A[0] SRAM_A[10] \
71 address[11] SRAM_A[12] SRAM_A[13] SRAM_A[14] SRAM_A[15] SRAM_A[16] SRAM_A[17] \
72 address[18] SRAM_A[19] SRAM_A[1] SRAM_A[2] SRAM_A[3] SRAM_A[4] SRAM_A[5] SRAM_A[6] \
73 address[7] SRAM_A[8] SRAM_A[9] }]
74 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { SRAM_A[0] SRAM_A[10] \
75 address[11] SRAM_A[12] SRAM_A[13] SRAM_A[14] SRAM_A[15] SRAM_A[16] SRAM_A[17] \
76 address[18] SRAM_A[19] SRAM_A[1] SRAM_A[2] SRAM_A[3] SRAM_A[4] SRAM_A[5] SRAM_A[6] \
77 address[7] SRAM_A[8] SRAM_A[9] }]
78
79 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_BE[0] nSRAM_BE[1] nSRAM_BE[2] nSRAM_BE[3] nSRAM_WE nSRAM_CE nSRAM_OE }]
80 set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_BE[0] nSRAM_BE[1] nSRAM_BE[2] nSRAM_BE[3] nSRAM_WE nSRAM_CE nSRAM_OE }]
81 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_BE[0] nSRAM_BE[1] nSRAM_BE[2] nSRAM_BE[3] nSRAM_WE nSRAM_CE nSRAM_OE }]
82
83
84 ######## Delay Constraints ########
85
86 set_max_delay 4.000 -from [get_ports { SPW_RED_SIN SPW_RED_DIN SPW_NOM_SIN SPW_NOM_DIN reset }] -to [get_clocks { spw_inputloop.1.spw_phy0/ntstrxclk.rx_clkbuf/pa3e.pae30/buf1.buf_RNO:Y}]
87
88 set_max_delay 4.000 -from [get_ports { SPW_RED_SIN SPW_RED_DIN SPW_NOM_SIN SPW_NOM_DIN reset }] -to [get_clocks {spw_inputloop.0.spw_phy0/ntstrxclk.rx_clkbuf/pa3e.pae30/buf1.buf_RNO:Y}]
89
90
91 ######## Delay Constraints ########
92
93
94
95 ######## Multicycle Constraints ########
96
97
98
99 ######## False Path Constraints ########
100
101
102
103 ######## Output load Constraints ########
104
105
106
107 ######## Disable Timing Constraints #########
108
109
110
111 ######## Clock Uncertainty Constraints #########
112
113
114
Show file before | Show file after | Hide comments
@@ -1,639 +1,639
1 # Actel Physical design constraints file
1 ο»Ώ# Actel Physical design constraints file
2 # Generated file
2 # Generated file
3
3
4 # Version: 9.1 SP3 9.1.3.4
4 # Version: 9.1 SP3 9.1.3.4
5 # Family: ProASIC3L , Die: A3PE3000L , Package: 324 FBGA
5 # Family: ProASIC3L , Die: A3PE3000L , Package: 324 FBGA
6 # Date generated: Tue Oct 18 08:21:45 2011
6 # Date generated: Tue Oct 18 08:21:45 2011
7
7
8
8
9 #
9 #
10 # IO banks setting
10 # IO banks setting
11 #
11 #
12
12
13
13
14 #
14 #
15 # I/O constraints
15 # I/O constraints
16 #
16 #
17
17
18 set_io clk_50 \
18 set_io clk100MHz \
19 -pinname F7 \
19 -pinname F7 \
20 -fixed yes \
20 -fixed yes \
21 -DIRECTION Inout
21 -DIRECTION Inout
22
22
23 set_io clk_49 \
23 set_io clk49_152MHz \
24 -pinname K14 \
24 -pinname K14 \
25 -fixed yes \
25 -fixed yes \
26 -DIRECTION Inout
26 -DIRECTION Inout
27
27
28 set_io reset \
28 set_io reset \
29 -pinname T2 \
29 -pinname T2 \
30 -fixed yes \
30 -fixed yes \
31 -DIRECTION Inout
31 -DIRECTION Inout
32 #====================================================================
32 #====================================================================
33 # BPs
33 # BPs
34 #====================================================================
34 #====================================================================
35 set_io BP0 \
35 set_io BP0 \
36 -pinname L1 \
36 -pinname L1 \
37 -fixed yes \
37 -fixed yes \
38 -DIRECTION Inout
38 -DIRECTION Inout
39
39
40 set_io BP1 \
40 set_io BP1 \
41 -pinname R1 \
41 -pinname R1 \
42 -fixed yes \
42 -fixed yes \
43 -DIRECTION Inout
43 -DIRECTION Inout
44
44
45 #====================================================================
45 #====================================================================
46 # LEDs
46 # LEDs
47 #====================================================================
47 #====================================================================
48
48
49 set_io LED0 \
49 set_io LED0 \
50 -pinname V6 \
50 -pinname V6 \
51 -fixed yes \
51 -fixed yes \
52 -DIRECTION Inout
52 -DIRECTION Inout
53
53
54 set_io LED1 \
54 set_io LED1 \
55 -pinname V5 \
55 -pinname V5 \
56 -fixed yes \
56 -fixed yes \
57 -DIRECTION Inout
57 -DIRECTION Inout
58
58
59 set_io LED2 \
59 set_io LED2 \
60 -pinname T4 \
60 -pinname T4 \
61 -fixed yes \
61 -fixed yes \
62 -DIRECTION Inout
62 -DIRECTION Inout
63
63
64 #====================================================================
64 #====================================================================
65 # UARTS
65 # UARTS
66 #====================================================================
66 #====================================================================
67
67
68 set_io TXD1 \
68 set_io TXD1 \
69 -pinname N17 \
69 -pinname N17 \
70 -fixed yes \
70 -fixed yes \
71 -DIRECTION Inout
71 -DIRECTION Inout
72
72
73 set_io RXD1 \
73 set_io RXD1 \
74 -pinname N18 \
74 -pinname N18 \
75 -fixed yes \
75 -fixed yes \
76 -DIRECTION Inout
76 -DIRECTION Inout
77
77
78 set_io nCTS1 \
78 set_io nCTS1 \
79 -pinname P18 \
79 -pinname P18 \
80 -fixed yes \
80 -fixed yes \
81 -DIRECTION Inout
81 -DIRECTION Inout
82
82
83 set_io nRTS1 \
83 set_io nRTS1 \
84 -pinname P17 \
84 -pinname P17 \
85 -fixed yes \
85 -fixed yes \
86 -DIRECTION Inout
86 -DIRECTION Inout
87
87
88
88
89 set_io TXD2 \
89 set_io TXD2 \
90 -pinname P13 \
90 -pinname P13 \
91 -fixed yes \
91 -fixed yes \
92 -DIRECTION Inout
92 -DIRECTION Inout
93
93
94 set_io RXD2 \
94 set_io RXD2 \
95 -pinname T18 \
95 -pinname T18 \
96 -fixed yes \
96 -fixed yes \
97 -DIRECTION Inout
97 -DIRECTION Inout
98
98
99 set_io nCTS2 \
99 set_io nCTS2 \
100 -pinname V17 \
100 -pinname V17 \
101 -fixed yes \
101 -fixed yes \
102 -DIRECTION Inout
102 -DIRECTION Inout
103
103
104 set_io nDTR2 \
104 set_io nDTR2 \
105 -pinname L15 \
105 -pinname L15 \
106 -fixed yes \
106 -fixed yes \
107 -DIRECTION Inout
107 -DIRECTION Inout
108
108
109 set_io nRTS2 \
109 set_io nRTS2 \
110 -pinname M15 \
110 -pinname M15 \
111 -fixed yes \
111 -fixed yes \
112 -DIRECTION Inout
112 -DIRECTION Inout
113
113
114 set_io nDCD2 \
114 set_io nDCD2 \
115 -pinname N15 \
115 -pinname N15 \
116 -fixed yes \
116 -fixed yes \
117 -DIRECTION Inout
117 -DIRECTION Inout
118
118
119
119
120 #====================================================================
120 #====================================================================
121 # EXT CONNECTOR
121 # EXT CONNECTOR
122 #====================================================================
122 #====================================================================
123
123
124 set_io IO0 \
124 set_io IO0 \
125 -pinname E4 \
125 -pinname E4 \
126 -fixed yes \
126 -fixed yes \
127 -DIRECTION Inout
127 -DIRECTION Inout
128
128
129 set_io IO1 \
129 set_io IO1 \
130 -pinname D3 \
130 -pinname D3 \
131 -fixed yes \
131 -fixed yes \
132 -DIRECTION Inout
132 -DIRECTION Inout
133
133
134 set_io IO2 \
134 set_io IO2 \
135 -pinname C2 \
135 -pinname C2 \
136 -fixed yes \
136 -fixed yes \
137 -DIRECTION Inout
137 -DIRECTION Inout
138
138
139 set_io IO3 \
139 set_io IO3 \
140 -pinname D1 \
140 -pinname D1 \
141 -fixed yes \
141 -fixed yes \
142 -DIRECTION Inout
142 -DIRECTION Inout
143
143
144 set_io IO4 \
144 set_io IO4 \
145 -pinname F2 \
145 -pinname F2 \
146 -fixed yes \
146 -fixed yes \
147 -DIRECTION Inout
147 -DIRECTION Inout
148
148
149 set_io IO5 \
149 set_io IO5 \
150 -pinname F3 \
150 -pinname F3 \
151 -fixed yes \
151 -fixed yes \
152 -DIRECTION Inout
152 -DIRECTION Inout
153
153
154 set_io IO6 \
154 set_io IO6 \
155 -pinname G2 \
155 -pinname G2 \
156 -fixed yes \
156 -fixed yes \
157 -DIRECTION Inout
157 -DIRECTION Inout
158
158
159 set_io IO7 \
159 set_io IO7 \
160 -pinname H3 \
160 -pinname H3 \
161 -fixed yes \
161 -fixed yes \
162 -DIRECTION Inout
162 -DIRECTION Inout
163
163
164 set_io IO8 \
164 set_io IO8 \
165 -pinname H4 \
165 -pinname H4 \
166 -fixed yes \
166 -fixed yes \
167 -DIRECTION Inout
167 -DIRECTION Inout
168
168
169 set_io IO9 \
169 set_io IO9 \
170 -pinname J2 \
170 -pinname J2 \
171 -fixed yes \
171 -fixed yes \
172 -DIRECTION Inout
172 -DIRECTION Inout
173
173
174 set_io IO10 \
174 set_io IO10 \
175 -pinname P1 \
175 -pinname P1 \
176 -fixed yes \
176 -fixed yes \
177 -DIRECTION Inout
177 -DIRECTION Inout
178
178
179 set_io IO11 \
179 set_io IO11 \
180 -pinname N1 \
180 -pinname N1 \
181 -fixed yes \
181 -fixed yes \
182 -DIRECTION Inout
182 -DIRECTION Inout
183
183
184 #====================================================================
184 #====================================================================
185 # SPACE WIRE
185 # SPACE WIRE
186 #====================================================================
186 #====================================================================
187
187
188 set_io SPW_EN \
188 set_io SPW_EN \
189 -pinname R12 \
189 -pinname R12 \
190 -fixed yes \
190 -fixed yes \
191 -DIRECTION Inout
191 -DIRECTION Inout
192
192
193 #================================
193 #================================
194 # NOMINAL LINK
194 # NOMINAL LINK
195 #================================
195 #================================
196
196
197 set_io SPW_NOM_DIN \
197 set_io SPW_NOM_DIN \
198 -pinname R10 \
198 -pinname R10 \
199 -fixed yes \
199 -fixed yes \
200 -DIRECTION Inout
200 -DIRECTION Inout
201
201
202 set_io SPW_NOM_SIN \
202 set_io SPW_NOM_SIN \
203 -pinname R13 \
203 -pinname R13 \
204 -fixed yes \
204 -fixed yes \
205 -DIRECTION Inout
205 -DIRECTION Inout
206
206
207 set_io SPW_NOM_DOUT \
207 set_io SPW_NOM_DOUT \
208 -pinname T13 \
208 -pinname T13 \
209 -fixed yes \
209 -fixed yes \
210 -DIRECTION Inout
210 -DIRECTION Inout
211
211
212 set_io SPW_NOM_SOUT \
212 set_io SPW_NOM_SOUT \
213 -pinname T10 \
213 -pinname T10 \
214 -fixed yes \
214 -fixed yes \
215 -DIRECTION Inout
215 -DIRECTION Inout
216
216
217 #================================
217 #================================
218 # REDUNDANT LINK
218 # REDUNDANT LINK
219 #================================
219 #================================
220
220
221 set_io SPW_RED_DIN \
221 set_io SPW_RED_DIN \
222 -pinname U18 \
222 -pinname U18 \
223 -fixed yes \
223 -fixed yes \
224 -DIRECTION Inout
224 -DIRECTION Inout
225
225
226 set_io SPW_RED_SIN \
226 set_io SPW_RED_SIN \
227 -pinname T12 \
227 -pinname T12 \
228 -fixed yes \
228 -fixed yes \
229 -DIRECTION Inout
229 -DIRECTION Inout
230
230
231 set_io SPW_RED_DOUT \
231 set_io SPW_RED_DOUT \
232 -pinname U10 \
232 -pinname U10 \
233 -fixed yes \
233 -fixed yes \
234 -DIRECTION Inout
234 -DIRECTION Inout
235
235
236 set_io SPW_RED_SOUT \
236 set_io SPW_RED_SOUT \
237 -pinname P16 \
237 -pinname P16 \
238 -fixed yes \
238 -fixed yes \
239 -DIRECTION Inout
239 -DIRECTION Inout
240
240
241 #====================================================================
241 #====================================================================
242 # MINI LFR ADC INPUTS
242 # MINI LFR ADC INPUTS
243 #====================================================================
243 #====================================================================
244
244
245 set_io ADC_nCS \
245 set_io ADC_nCS \
246 -pinname K1 \
246 -pinname K1 \
247 -fixed yes \
247 -fixed yes \
248 -DIRECTION Inout
248 -DIRECTION Inout
249
249
250 set_io ADC_CLK \
250 set_io ADC_CLK \
251 -pinname T1 \
251 -pinname T1 \
252 -fixed yes \
252 -fixed yes \
253 -DIRECTION Inout
253 -DIRECTION Inout
254
254
255
255
256 #================================
256 #================================
257 # ADC DATA
257 # ADC DATA
258 #================================
258 #================================
259
259
260 set_io ADC_SDO\[0\] \
260 set_io ADC_SDO\[0\] \
261 -pinname V4 \
261 -pinname V4 \
262 -fixed yes \
262 -fixed yes \
263 -DIRECTION Inout
263 -DIRECTION Inout
264
264
265 set_io ADC_SDO\[1\] \
265 set_io ADC_SDO\[1\] \
266 -pinname V3 \
266 -pinname V3 \
267 -fixed yes \
267 -fixed yes \
268 -DIRECTION Inout
268 -DIRECTION Inout
269
269
270 set_io ADC_SDO\[2\] \
270 set_io ADC_SDO\[2\] \
271 -pinname V2 \
271 -pinname V2 \
272 -fixed yes \
272 -fixed yes \
273 -DIRECTION Inout
273 -DIRECTION Inout
274
274
275 set_io ADC_SDO\[3\] \
275 set_io ADC_SDO\[3\] \
276 -pinname U1 \
276 -pinname U1 \
277 -fixed yes \
277 -fixed yes \
278 -DIRECTION Inout
278 -DIRECTION Inout
279
279
280 set_io ADC_SDO\[4\] \
280 set_io ADC_SDO\[4\] \
281 -pinname J1 \
281 -pinname J1 \
282 -fixed yes \
282 -fixed yes \
283 -DIRECTION Inout
283 -DIRECTION Inout
284
284
285 set_io ADC_SDO\[5\] \
285 set_io ADC_SDO\[5\] \
286 -pinname H1 \
286 -pinname H1 \
287 -fixed yes \
287 -fixed yes \
288 -DIRECTION Inout
288 -DIRECTION Inout
289
289
290 set_io ADC_SDO\[6\] \
290 set_io ADC_SDO\[6\] \
291 -pinname F1 \
291 -pinname F1 \
292 -fixed yes \
292 -fixed yes \
293 -DIRECTION Inout
293 -DIRECTION Inout
294
294
295 set_io ADC_SDO\[7\] \
295 set_io ADC_SDO\[7\] \
296 -pinname E1 \
296 -pinname E1 \
297 -fixed yes \
297 -fixed yes \
298 -DIRECTION Inout
298 -DIRECTION Inout
299
299
300
300
301 #====================================================================
301 #====================================================================
302 # SRAM
302 # SRAM
303 #====================================================================
303 #====================================================================
304
304
305 #================================
305 #================================
306 # SRAM CTRL
306 # SRAM CTRL
307 #================================
307 #================================
308
308
309 set_io SRAM_nWE \
309 set_io SRAM_nWE \
310 -pinname C13 \
310 -pinname C13 \
311 -fixed yes \
311 -fixed yes \
312 -DIRECTION Inout
312 -DIRECTION Inout
313
313
314 set_io SRAM_CE \
314 set_io SRAM_CE \
315 -pinname J14 \
315 -pinname J14 \
316 -fixed yes \
316 -fixed yes \
317 -DIRECTION Inout
317 -DIRECTION Inout
318
318
319 set_io SRAM_nOE \
319 set_io SRAM_nOE \
320 -pinname B9 \
320 -pinname B9 \
321 -fixed yes \
321 -fixed yes \
322 -DIRECTION Inout
322 -DIRECTION Inout
323
323
324 set_io SRAM_nBE\[0\] \
324 set_io SRAM_nBE\[0\] \
325 -pinname H15 \
325 -pinname H15 \
326 -fixed yes \
326 -fixed yes \
327 -DIRECTION Inout
327 -DIRECTION Inout
328
328
329 set_io SRAM_nBE\[1\] \
329 set_io SRAM_nBE\[1\] \
330 -pinname C12 \
330 -pinname C12 \
331 -fixed yes \
331 -fixed yes \
332 -DIRECTION Inout
332 -DIRECTION Inout
333
333
334 set_io SRAM_nBE\[2\] \
334 set_io SRAM_nBE\[2\] \
335 -pinname A10 \
335 -pinname A10 \
336 -fixed yes \
336 -fixed yes \
337 -DIRECTION Inout
337 -DIRECTION Inout
338
338
339 set_io SRAM_nBE\[3\] \
339 set_io SRAM_nBE\[3\] \
340 -pinname A9 \
340 -pinname A9 \
341 -fixed yes \
341 -fixed yes \
342 -DIRECTION Inout
342 -DIRECTION Inout
343
343
344
344
345 #================================
345 #================================
346 # SRAM ADDRESS
346 # SRAM ADDRESS
347 #================================
347 #================================
348
348
349 set_io SRAM_A\[0\] \
349 set_io SRAM_A\[0\] \
350 -pinname C11 \
350 -pinname C11 \
351 -fixed yes \
351 -fixed yes \
352 -DIRECTION Inout
352 -DIRECTION Inout
353
353
354 set_io SRAM_A\[1\] \
354 set_io SRAM_A\[1\] \
355 -pinname C10 \
355 -pinname C10 \
356 -fixed yes \
356 -fixed yes \
357 -DIRECTION Inout
357 -DIRECTION Inout
358
358
359 set_io SRAM_A\[2\] \
359 set_io SRAM_A\[2\] \
360 -pinname C9 \
360 -pinname C9 \
361 -fixed yes \
361 -fixed yes \
362 -DIRECTION Inout
362 -DIRECTION Inout
363
363
364 set_io SRAM_A\[3\] \
364 set_io SRAM_A\[3\] \
365 -pinname C8 \
365 -pinname C8 \
366 -fixed yes \
366 -fixed yes \
367 -DIRECTION Inout
367 -DIRECTION Inout
368
368
369 set_io SRAM_A\[4\] \
369 set_io SRAM_A\[4\] \
370 -pinname C7 \
370 -pinname C7 \
371 -fixed yes \
371 -fixed yes \
372 -DIRECTION Inout
372 -DIRECTION Inout
373
373
374 set_io SRAM_A\[5\] \
374 set_io SRAM_A\[5\] \
375 -pinname A5 \
375 -pinname A5 \
376 -fixed yes \
376 -fixed yes \
377 -DIRECTION Inout
377 -DIRECTION Inout
378
378
379 set_io SRAM_A\[6\] \
379 set_io SRAM_A\[6\] \
380 -pinname A6 \
380 -pinname A6 \
381 -fixed yes \
381 -fixed yes \
382 -DIRECTION Inout
382 -DIRECTION Inout
383
383
384 set_io SRAM_A\[7\] \
384 set_io SRAM_A\[7\] \
385 -pinname B6 \
385 -pinname B6 \
386 -fixed yes \
386 -fixed yes \
387 -DIRECTION Inout
387 -DIRECTION Inout
388
388
389 set_io SRAM_A\[8\] \
389 set_io SRAM_A\[8\] \
390 -pinname B7 \
390 -pinname B7 \
391 -fixed yes \
391 -fixed yes \
392 -DIRECTION Inout
392 -DIRECTION Inout
393
393
394 set_io SRAM_A\[9\] \
394 set_io SRAM_A\[9\] \
395 -pinname A8 \
395 -pinname A8 \
396 -fixed yes \
396 -fixed yes \
397 -DIRECTION Inout
397 -DIRECTION Inout
398
398
399 set_io SRAM_A\[10\] \
399 set_io SRAM_A\[10\] \
400 -pinname B10 \
400 -pinname B10 \
401 -fixed yes \
401 -fixed yes \
402 -DIRECTION Inout
402 -DIRECTION Inout
403
403
404 set_io SRAM_A\[11\] \
404 set_io SRAM_A\[11\] \
405 -pinname A11 \
405 -pinname A11 \
406 -fixed yes \
406 -fixed yes \
407 -DIRECTION Inout
407 -DIRECTION Inout
408
408
409 set_io SRAM_A\[12\] \
409 set_io SRAM_A\[12\] \
410 -pinname B12 \
410 -pinname B12 \
411 -fixed yes \
411 -fixed yes \
412 -DIRECTION Inout
412 -DIRECTION Inout
413
413
414 set_io SRAM_A\[13\] \
414 set_io SRAM_A\[13\] \
415 -pinname A13 \
415 -pinname A13 \
416 -fixed yes \
416 -fixed yes \
417 -DIRECTION Inout
417 -DIRECTION Inout
418
418
419 set_io SRAM_A\[14\] \
419 set_io SRAM_A\[14\] \
420 -pinname B13 \
420 -pinname B13 \
421 -fixed yes \
421 -fixed yes \
422 -DIRECTION Inout
422 -DIRECTION Inout
423
423
424 set_io SRAM_A\[15\] \
424 set_io SRAM_A\[15\] \
425 -pinname C18 \
425 -pinname C18 \
426 -fixed yes \
426 -fixed yes \
427 -DIRECTION Inout
427 -DIRECTION Inout
428
428
429 set_io SRAM_A\[16\] \
429 set_io SRAM_A\[16\] \
430 -pinname C17 \
430 -pinname C17 \
431 -fixed yes \
431 -fixed yes \
432 -DIRECTION Inout
432 -DIRECTION Inout
433
433
434 set_io SRAM_A\[17\] \
434 set_io SRAM_A\[17\] \
435 -pinname B18 \
435 -pinname B18 \
436 -fixed yes \
436 -fixed yes \
437 -DIRECTION Inout
437 -DIRECTION Inout
438
438
439 set_io SRAM_A\[18\] \
439 set_io SRAM_A\[18\] \
440 -pinname C16 \
440 -pinname C16 \
441 -fixed yes \
441 -fixed yes \
442 -DIRECTION Inout
442 -DIRECTION Inout
443
443
444 set_io SRAM_A\[19\] \
444 set_io SRAM_A\[19\] \
445 -pinname D15 \
445 -pinname D15 \
446 -fixed yes \
446 -fixed yes \
447 -DIRECTION Inout
447 -DIRECTION Inout
448
448
449
449
450 #================================
450 #================================
451 # SRAM DATA
451 # SRAM DATA
452 #================================
452 #================================
453
453
454 set_io SRAM_DQ\[0\] \
454 set_io SRAM_DQ\[0\] \
455 -pinname D16 \
455 -pinname D16 \
456 -fixed yes \
456 -fixed yes \
457 -DIRECTION Inout
457 -DIRECTION Inout
458
458
459 set_io SRAM_DQ\[1\] \
459 set_io SRAM_DQ\[1\] \
460 -pinname D18 \
460 -pinname D18 \
461 -fixed yes \
461 -fixed yes \
462 -DIRECTION Inout
462 -DIRECTION Inout
463
463
464 set_io SRAM_DQ\[2\] \
464 set_io SRAM_DQ\[2\] \
465 -pinname E15 \
465 -pinname E15 \
466 -fixed yes \
466 -fixed yes \
467 -DIRECTION Inout
467 -DIRECTION Inout
468
468
469 set_io SRAM_DQ\[3\] \
469 set_io SRAM_DQ\[3\] \
470 -pinname E18 \
470 -pinname E18 \
471 -fixed yes \
471 -fixed yes \
472 -DIRECTION Inout
472 -DIRECTION Inout
473
473
474 set_io SRAM_DQ\[4\] \
474 set_io SRAM_DQ\[4\] \
475 -pinname F15 \
475 -pinname F15 \
476 -fixed yes \
476 -fixed yes \
477 -DIRECTION Inout
477 -DIRECTION Inout
478
478
479 set_io SRAM_DQ\[5\] \
479 set_io SRAM_DQ\[5\] \
480 -pinname F18 \
480 -pinname F18 \
481 -fixed yes \
481 -fixed yes \
482 -DIRECTION Inout
482 -DIRECTION Inout
483
483
484 set_io SRAM_DQ\[6\] \
484 set_io SRAM_DQ\[6\] \
485 -pinname G15 \
485 -pinname G15 \
486 -fixed yes \
486 -fixed yes \
487 -DIRECTION Inout
487 -DIRECTION Inout
488
488
489 set_io SRAM_DQ\[7\] \
489 set_io SRAM_DQ\[7\] \
490 -pinname G17 \
490 -pinname G17 \
491 -fixed yes \
491 -fixed yes \
492 -DIRECTION Inout
492 -DIRECTION Inout
493
493
494 set_io SRAM_DQ\[8\] \
494 set_io SRAM_DQ\[8\] \
495 -pinname K15 \
495 -pinname K15 \
496 -fixed yes \
496 -fixed yes \
497 -DIRECTION Inout
497 -DIRECTION Inout
498
498
499 set_io SRAM_DQ\[9\] \
499 set_io SRAM_DQ\[9\] \
500 -pinname J18 \
500 -pinname J18 \
501 -fixed yes \
501 -fixed yes \
502 -DIRECTION Inout
502 -DIRECTION Inout
503
503
504 set_io SRAM_DQ\[10\] \
504 set_io SRAM_DQ\[10\] \
505 -pinname J15 \
505 -pinname J15 \
506 -fixed yes \
506 -fixed yes \
507 -DIRECTION Inout
507 -DIRECTION Inout
508
508
509 set_io SRAM_DQ\[11\] \
509 set_io SRAM_DQ\[11\] \
510 -pinname H18 \
510 -pinname H18 \
511 -fixed yes \
511 -fixed yes \
512 -DIRECTION Inout
512 -DIRECTION Inout
513
513
514 set_io SRAM_DQ\[12\] \
514 set_io SRAM_DQ\[12\] \
515 -pinname C3 \
515 -pinname C3 \
516 -fixed yes \
516 -fixed yes \
517 -DIRECTION Inout
517 -DIRECTION Inout
518
518
519 set_io SRAM_DQ\[13\] \
519 set_io SRAM_DQ\[13\] \
520 -pinname D4 \
520 -pinname D4 \
521 -fixed yes \
521 -fixed yes \
522 -DIRECTION Inout
522 -DIRECTION Inout
523
523
524 set_io SRAM_DQ\[14\] \
524 set_io SRAM_DQ\[14\] \
525 -pinname D5 \
525 -pinname D5 \
526 -fixed yes \
526 -fixed yes \
527 -DIRECTION Inout
527 -DIRECTION Inout
528
528
529 set_io SRAM_DQ\[15\] \
529 set_io SRAM_DQ\[15\] \
530 -pinname C6 \
530 -pinname C6 \
531 -fixed yes \
531 -fixed yes \
532 -DIRECTION Inout
532 -DIRECTION Inout
533
533
534 set_io SRAM_DQ\[16\] \
534 set_io SRAM_DQ\[16\] \
535 -pinname D14 \
535 -pinname D14 \
536 -fixed yes \
536 -fixed yes \
537 -DIRECTION Inout
537 -DIRECTION Inout
538
538
539 set_io SRAM_DQ\[17\] \
539 set_io SRAM_DQ\[17\] \
540 -pinname A15 \
540 -pinname A15 \
541 -fixed yes \
541 -fixed yes \
542 -DIRECTION Inout
542 -DIRECTION Inout
543
543
544 set_io SRAM_DQ\[18\] \
544 set_io SRAM_DQ\[18\] \
545 -pinname C15 \
545 -pinname C15 \
546 -fixed yes \
546 -fixed yes \
547 -DIRECTION Inout
547 -DIRECTION Inout
548
548
549 set_io SRAM_DQ\[19\] \
549 set_io SRAM_DQ\[19\] \
550 -pinname B17 \
550 -pinname B17 \
551 -fixed yes \
551 -fixed yes \
552 -DIRECTION Inout
552 -DIRECTION Inout
553
553
554 set_io SRAM_DQ\[20\] \
554 set_io SRAM_DQ\[20\] \
555 -pinname A17 \
555 -pinname A17 \
556 -fixed yes \
556 -fixed yes \
557 -DIRECTION Inout
557 -DIRECTION Inout
558
558
559 set_io SRAM_DQ\[21\] \
559 set_io SRAM_DQ\[21\] \
560 -pinname B16 \
560 -pinname B16 \
561 -fixed yes \
561 -fixed yes \
562 -DIRECTION Inout
562 -DIRECTION Inout
563
563
564 set_io SRAM_DQ\[22\] \
564 set_io SRAM_DQ\[22\] \
565 -pinname A16 \
565 -pinname A16 \
566 -fixed yes \
566 -fixed yes \
567 -DIRECTION Inout
567 -DIRECTION Inout
568
568
569 set_io SRAM_DQ\[23\] \
569 set_io SRAM_DQ\[23\] \
570 -pinname A14 \
570 -pinname A14 \
571 -fixed yes \
571 -fixed yes \
572 -DIRECTION Inout
572 -DIRECTION Inout
573
573
574 set_io SRAM_DQ\[24\] \
574 set_io SRAM_DQ\[24\] \
575 -pinname A4 \
575 -pinname A4 \
576 -fixed yes \
576 -fixed yes \
577 -DIRECTION Inout
577 -DIRECTION Inout
578
578
579 set_io SRAM_DQ\[25\] \
579 set_io SRAM_DQ\[25\] \
580 -pinname A3 \
580 -pinname A3 \
581 -fixed yes \
581 -fixed yes \
582 -DIRECTION Inout
582 -DIRECTION Inout
583
583
584 set_io SRAM_DQ\[26\] \
584 set_io SRAM_DQ\[26\] \
585 -pinname A2 \
585 -pinname A2 \
586 -fixed yes \
586 -fixed yes \
587 -DIRECTION Inout
587 -DIRECTION Inout
588
588
589 set_io SRAM_DQ\[27\] \
589 set_io SRAM_DQ\[27\] \
590 -pinname B1 \
590 -pinname B1 \
591 -fixed yes \
591 -fixed yes \
592 -DIRECTION Inout
592 -DIRECTION Inout
593
593
594 set_io SRAM_DQ\[28\] \
594 set_io SRAM_DQ\[28\] \
595 -pinname C1 \
595 -pinname C1 \
596 -fixed yes \
596 -fixed yes \
597 -DIRECTION Inout
597 -DIRECTION Inout
598
598
599 set_io SRAM_DQ\[29\] \
599 set_io SRAM_DQ\[29\] \
600 -pinname B2 \
600 -pinname B2 \
601 -fixed yes \
601 -fixed yes \
602 -DIRECTION Inout
602 -DIRECTION Inout
603
603
604 set_io SRAM_DQ\[30\] \
604 set_io SRAM_DQ\[30\] \
605 -pinname B3 \
605 -pinname B3 \
606 -fixed yes \
606 -fixed yes \
607 -DIRECTION Inout
607 -DIRECTION Inout
608
608
609 set_io SRAM_DQ\[31\] \
609 set_io SRAM_DQ\[31\] \
610 -pinname C4 \
610 -pinname C4 \
611 -fixed yes \
611 -fixed yes \
612 -DIRECTION Inout
612 -DIRECTION Inout
613
613
614
614
615
615
616
616
617
617
618
618
619
619
620
620
621
621
622
622
623
623
624
624
625
625
626
626
627
627
628
628
629
629
630
630
631
631
632
632
633
633
634
634
635
635
636
636
637
637
638
638
639
639
Show file before | Show file after | Hide comments
@@ -1,114 +1,114
1 ################################################################################
1 ################################################################################
2 # SDC WRITER VERSION "3.1";
2 # SDC WRITER VERSION "3.1";
3 # DESIGN "LFR_EQM";
3 # DESIGN "LFR_EQM";
4 # Timing constraints scenario: "Primary";
4 # Timing constraints scenario: "Primary";
5 # DATE "Fri Apr 24 16:02:16 2015";
5 # DATE "Fri Apr 24 16:02:16 2015";
6 # VENDOR "Actel";
6 # VENDOR "Actel";
7 # PROGRAM "Actel Designer Software Release v9.1 SP5";
7 # PROGRAM "Actel Designer Software Release v9.1 SP5";
8 # VERSION "9.1.5.1" Copyright (C) 1989-2012 Actel Corp.
8 # VERSION "9.1.5.1" Copyright (C) 1989-2012 Actel Corp.
9 ################################################################################
9 ################################################################################
10
10
11
11
12 set sdc_version 1.7
12 set sdc_version 1.7
13
13
14
14
15 ######## Clock Constraints ########
15 ######## Clock Constraints ########
16
16
17 create_clock -name { clk100MHz } -period 10.000 -waveform { 0.000 5.000 } { clk100MHz }
17 create_clock -name { clk100MHz } -period 10.000 -waveform { 0.000 5.000 } { clk100MHz }
18
18
19 create_clock -name { clk49_152MHz } -period 20.345 -waveform { 0.000 10.172 } { clk49_152MHz }
19 create_clock -name { clk49_152MHz } -period 20.345 -waveform { 0.000 10.172 } { clk49_152MHz }
20
20
21 create_clock -name { clk_25:Q } -period 40.000 -waveform { 0.000 20.000 } { clk_25:Q }
21 create_clock -name { clk_25:Q } -period 40.000 -waveform { 0.000 20.000 } { clk_25:Q }
22
22
23 create_clock -name { clk_24:Q } -period 40.690 -waveform { 0.000 20.345 } { clk_24:Q }
23 create_clock -name { clk_24:Q } -period 40.690 -waveform { 0.000 20.345 } { clk_24:Q }
24
24
25 create_clock -name { spw_inputloop.1.spw_phy0/rxclki_RNO:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.1.spw_phy0/rxclki_RNO:Y }
25 create_clock -name { spw_inputloop.1.spw_phy0/rxclki_RNO:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.1.spw_phy0/rxclki_RNO:Y }
26
26
27 create_clock -name { spw_inputloop.0.spw_phy0/rxclki_RNO:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.0.spw_phy0/rxclki_RNO:Y }
27 create_clock -name { spw_inputloop.0.spw_phy0/rxclki_RNO:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.0.spw_phy0/rxclki_RNO:Y }
28
28
29
29
30
30
31 ######## Generated Clock Constraints ########
31 ######## Generated Clock Constraints ########
32
32
33
33
34
34
35 ######## Clock Source Latency Constraints #########
35 ######## Clock Source Latency Constraints #########
36
36
37
37
38
38
39 ######## Input Delay Constraints ########
39 ######## Input Delay Constraints ########
40
40
41 set_input_delay 0.000 -clock { clk_25:Q } [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
41 set_input_delay 0.000 -clock { clk_25:Q } [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
42 set_max_delay 30.000 -from [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] \
42 set_max_delay 30.000 -from [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] \
43 data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] \
43 data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] \
44 data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] \
44 data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] \
45 data[4] data[5] data[6] data[7] data[8] data[9] }] -to [get_clocks {clk_25:Q}]
45 data[4] data[5] data[6] data[7] data[8] data[9] }] -to [get_clocks {clk_25:Q}]
46 set_min_delay 0.000 -from [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] \
46 set_min_delay 0.000 -from [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] \
47 data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] \
47 data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] \
48 data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] \
48 data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] \
49 data[4] data[5] data[6] data[7] data[8] data[9] }] -to [get_clocks {clk_25:Q}]
49 data[4] data[5] data[6] data[7] data[8] data[9] }] -to [get_clocks {clk_25:Q}]
50
50
51 #set_input_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_BUSY }]
51 #set_input_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_BUSY }]
52 #set_max_delay 10.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}]
52 #set_max_delay 10.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}]
53 #set_min_delay 0.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}]
53 #set_min_delay 0.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}]
54
54
55
55
56
56
57 ######## Output Delay Constraints ########
57 ######## Output Delay Constraints ########
58
58
59 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
59 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
60 set_max_delay 18.000 -from [get_clocks {clk_25:Q}] -to [get_ports { data[0] data[10] data[11] \
60 set_max_delay 18.000 -from [get_clocks {clk_25:Q}] -to [get_ports { data[0] data[10] data[11] \
61 data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] \
61 data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] \
62 data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] \
62 data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] \
63 data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
63 data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
64 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { data[0] data[10] data[11] \
64 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { data[0] data[10] data[11] \
65 data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] \
65 data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] \
66 data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] \
66 data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] \
67 data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
67 data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
68
68
69 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { address[0] address[10] address[11] address[12] address[13] address[14] address[15] address[16] address[17] address[18] address[19] address[1] address[2] address[3] address[4] address[5] address[6] address[7] address[8] address[9] }]
69 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { address[0] address[10] address[11] address[12] address[13] address[14] address[15] address[16] address[17] address[18] address[19] address[1] address[2] address[3] address[4] address[5] address[6] address[7] address[8] address[9] }]
70 set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address[0] address[10] \
70 set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address[0] address[10] \
71 address[11] address[12] address[13] address[14] address[15] address[16] address[17] \
71 address[11] address[12] address[13] address[14] address[15] address[16] address[17] \
72 address[18] address[19] address[1] address[2] address[3] address[4] address[5] address[6] \
72 address[18] address[19] address[1] address[2] address[3] address[4] address[5] address[6] \
73 address[7] address[8] address[9] }]
73 address[7] address[8] address[9] }]
74 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address[0] address[10] \
74 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address[0] address[10] \
75 address[11] address[12] address[13] address[14] address[15] address[16] address[17] \
75 address[11] address[12] address[13] address[14] address[15] address[16] address[17] \
76 address[18] address[19] address[1] address[2] address[3] address[4] address[5] address[6] \
76 address[18] address[19] address[1] address[2] address[3] address[4] address[5] address[6] \
77 address[7] address[8] address[9] }]
77 address[7] address[8] address[9] }]
78
78
79 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_BE0 nSRAM_BE1 nSRAM_BE2 nSRAM_E3 nSRAM_WE nSRAM_CE nSRAM_OE }]
79 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_BE0 nSRAM_BE1 nSRAM_BE2 nSRAM_E3 nSRAM_WE nSRAM_CE nSRAM_OE }]
80 set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_BE0 nSRAM_BE1 nSRAM_BE2 nSRAM_E3 nSRAM_WE nSRAM_CE nSRAM_OE }]
80 set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_BE0 nSRAM_BE1 nSRAM_BE2 nSRAM_BE3 nSRAM_WE nSRAM_CE nSRAM_OE }]
81 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_BE0 nSRAM_BE1 nSRAM_BE2 nSRAM_E3 nSRAM_WE nSRAM_CE nSRAM_OE }]
81 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_BE0 nSRAM_BE1 nSRAM_BE2 nSRAM_BE3 nSRAM_WE nSRAM_CE nSRAM_OE }]
82
82
83
83
84 ######## Delay Constraints ########
84 ######## Delay Constraints ########
85
85
86 set_max_delay 4.000 -from [get_ports { spw2_sin spw2_din spw1_sin spw1_din reset }] -to [get_clocks { spw_inputloop.1.spw_phy0/ntstrxclk.rx_clkbuf/pa3e.pae30/buf1.buf_RNO:Y}]
86 set_max_delay 4.000 -from [get_ports { spw2_sin spw2_din spw1_sin spw1_din reset }] -to [get_clocks { spw_inputloop.1.spw_phy0/ntstrxclk.rx_clkbuf/pa3e.pae30/buf1.buf_RNO:Y}]
87
87
88 set_max_delay 4.000 -from [get_ports { spw2_sin spw2_din spw1_sin spw1_din reset }] -to [get_clocks {spw_inputloop.0.spw_phy0/ntstrxclk.rx_clkbuf/pa3e.pae30/buf1.buf_RNO:Y}]
88 set_max_delay 4.000 -from [get_ports { spw2_sin spw2_din spw1_sin spw1_din reset }] -to [get_clocks {spw_inputloop.0.spw_phy0/ntstrxclk.rx_clkbuf/pa3e.pae30/buf1.buf_RNO:Y}]
89
89
90
90
91 ######## Delay Constraints ########
91 ######## Delay Constraints ########
92
92
93
93
94
94
95 ######## Multicycle Constraints ########
95 ######## Multicycle Constraints ########
96
96
97
97
98
98
99 ######## False Path Constraints ########
99 ######## False Path Constraints ########
100
100
101
101
102
102
103 ######## Output load Constraints ########
103 ######## Output load Constraints ########
104
104
105
105
106
106
107 ######## Disable Timing Constraints #########
107 ######## Disable Timing Constraints #########
108
108
109
109
110
110
111 ######## Clock Uncertainty Constraints #########
111 ######## Clock Uncertainty Constraints #########
112
112
113
113
114
114
Show file before | Show file after | Hide comments
This diff has been collapsed as it changes many lines, (1309 lines changed) Show them Hide them
@@ -1,656 +1,653
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
29 USE techmap.gencomp.ALL;
30 LIBRARY gaisler;
30 LIBRARY gaisler;
31 USE gaisler.memctrl.ALL;
31 USE gaisler.memctrl.ALL;
32 USE gaisler.leon3.ALL;
32 USE gaisler.leon3.ALL;
33 USE gaisler.uart.ALL;
33 USE gaisler.uart.ALL;
34 USE gaisler.misc.ALL;
34 USE gaisler.misc.ALL;
35 USE gaisler.spacewire.ALL;
35 USE gaisler.spacewire.ALL;
36 LIBRARY esa;
36 LIBRARY esa;
37 USE esa.memoryctrl.ALL;
37 USE esa.memoryctrl.ALL;
38 LIBRARY lpp;
38 LIBRARY lpp;
39 USE lpp.lpp_memory.ALL;
39 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_ad_conv.ALL;
40 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 USE lpp.iir_filter.ALL;
43 USE lpp.iir_filter.ALL;
44 USE lpp.general_purpose.ALL;
44 USE lpp.general_purpose.ALL;
45 USE lpp.lpp_lfr_management.ALL;
45 USE lpp.lpp_lfr_management.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
47
47
48 ENTITY MINI_LFR_top IS
48 ENTITY MINI_LFR_top IS
49
49
50 PORT (
50 PORT (
51 -----------------------------------------------------------------------------
51 clk100MHz : IN STD_LOGIC;
52 -- WARNING !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
52 clk49_152MHz : IN STD_LOGIC;
53 -- clk_50 frequency is 100 Mhz !
53 reset : IN STD_LOGIC;
54 clk_50 : IN STD_LOGIC;
54 --BPs
55 -- WARNING !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
55 BP0 : IN STD_LOGIC;
56 -----------------------------------------------------------------------------
56 BP1 : IN STD_LOGIC;
57 clk_49 : IN STD_LOGIC;
57 --LEDs
58 reset : IN STD_LOGIC;
58 LED0 : OUT STD_LOGIC;
59 --BPs
59 LED1 : OUT STD_LOGIC;
60 BP0 : IN STD_LOGIC;
60 LED2 : OUT STD_LOGIC;
61 BP1 : IN STD_LOGIC;
61 --UARTs
62 --LEDs
62 TXD1 : IN STD_LOGIC;
63 LED0 : OUT STD_LOGIC;
63 RXD1 : OUT STD_LOGIC;
64 LED1 : OUT STD_LOGIC;
64 nCTS1 : OUT STD_LOGIC;
65 LED2 : OUT STD_LOGIC;
65 nRTS1 : IN STD_LOGIC;
66 --UARTs
66
67 TXD1 : IN STD_LOGIC;
67 TXD2 : IN STD_LOGIC;
68 RXD1 : OUT STD_LOGIC;
68 RXD2 : OUT STD_LOGIC;
69 nCTS1 : OUT STD_LOGIC;
69 nCTS2 : OUT STD_LOGIC;
70 nRTS1 : IN STD_LOGIC;
70 nDTR2 : IN STD_LOGIC;
71
71 nRTS2 : IN STD_LOGIC;
72 TXD2 : IN STD_LOGIC;
72 nDCD2 : OUT STD_LOGIC;
73 RXD2 : OUT STD_LOGIC;
73
74 nCTS2 : OUT STD_LOGIC;
74 --EXT CONNECTOR
75 nDTR2 : IN STD_LOGIC;
75 IO0 : INOUT STD_LOGIC;
76 nRTS2 : IN STD_LOGIC;
76 IO1 : INOUT STD_LOGIC;
77 nDCD2 : OUT STD_LOGIC;
77 IO2 : INOUT STD_LOGIC;
78
78 IO3 : INOUT STD_LOGIC;
79 --EXT CONNECTOR
79 IO4 : INOUT STD_LOGIC;
80 IO0 : INOUT STD_LOGIC;
80 IO5 : INOUT STD_LOGIC;
81 IO1 : INOUT STD_LOGIC;
81 IO6 : INOUT STD_LOGIC;
82 IO2 : INOUT STD_LOGIC;
82 IO7 : INOUT STD_LOGIC;
83 IO3 : INOUT STD_LOGIC;
83 IO8 : INOUT STD_LOGIC;
84 IO4 : INOUT STD_LOGIC;
84 IO9 : INOUT STD_LOGIC;
85 IO5 : INOUT STD_LOGIC;
85 IO10 : INOUT STD_LOGIC;
86 IO6 : INOUT STD_LOGIC;
86 IO11 : INOUT STD_LOGIC;
87 IO7 : INOUT STD_LOGIC;
87
88 IO8 : INOUT STD_LOGIC;
88 --SPACE WIRE
89 IO9 : INOUT STD_LOGIC;
89 SPW_EN : OUT STD_LOGIC; -- 0 => off
90 IO10 : INOUT STD_LOGIC;
90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
91 IO11 : INOUT STD_LOGIC;
91 SPW_NOM_SIN : IN STD_LOGIC;
92
92 SPW_NOM_DOUT : OUT STD_LOGIC;
93 --SPACE WIRE
93 SPW_NOM_SOUT : OUT STD_LOGIC;
94 SPW_EN : OUT STD_LOGIC; -- 0 => off
94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
95 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
95 SPW_RED_SIN : IN STD_LOGIC;
96 SPW_NOM_SIN : IN STD_LOGIC;
96 SPW_RED_DOUT : OUT STD_LOGIC;
97 SPW_NOM_DOUT : OUT STD_LOGIC;
97 SPW_RED_SOUT : OUT STD_LOGIC;
98 SPW_NOM_SOUT : OUT STD_LOGIC;
98 -- MINI LFR ADC INPUTS
99 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
99 ADC_nCS : OUT STD_LOGIC;
100 SPW_RED_SIN : IN STD_LOGIC;
100 ADC_CLK : OUT STD_LOGIC;
101 SPW_RED_DOUT : OUT STD_LOGIC;
101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
102 SPW_RED_SOUT : OUT STD_LOGIC;
102
103 -- MINI LFR ADC INPUTS
103 -- SRAM
104 ADC_nCS : OUT STD_LOGIC;
104 SRAM_nWE : OUT STD_LOGIC;
105 ADC_CLK : OUT STD_LOGIC;
105 SRAM_CE : OUT STD_LOGIC;
106 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
106 SRAM_nOE : OUT STD_LOGIC;
107
107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
108 -- SRAM
108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
109 SRAM_nWE : OUT STD_LOGIC;
109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
110 SRAM_CE : OUT STD_LOGIC;
110 );
111 SRAM_nOE : OUT STD_LOGIC;
111
112 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
112 END MINI_LFR_top;
113 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
113
114 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
114
115 );
115 ARCHITECTURE beh OF MINI_LFR_top IS
116
116
117 END MINI_LFR_top;
117 --==========================================================================
118
118 -- USE_IAP_MEMCTRL allow to use the srctrle-0ws on MINILFR board
119
119 -- when enabled, chip enable polarity should be reversed and bank size also
120 ARCHITECTURE beh OF MINI_LFR_top IS
120 -- MINILFR -> 1 bank of 4MBytes -> SRBANKSZ=9
121
121 -- LFR EQM & FM -> 2 banks of 2MBytes -> SRBANKSZ=8
122 --==========================================================================
122 --==========================================================================
123 -- USE_IAP_MEMCTRL allow to use the srctrle-0ws on MINILFR board
123 CONSTANT USE_IAP_MEMCTRL : integer := 1;
124 -- when enabled, chip enable polarity should be reversed and bank size also
124 --==========================================================================
125 -- MINILFR -> 1 bank of 4MBytes -> SRBANKSZ=9
125
126 -- LFR EQM & FM -> 2 banks of 2MBytes -> SRBANKSZ=8
126 SIGNAL clk_50_s : STD_LOGIC := '0';
127 --==========================================================================
127 SIGNAL clk_25 : STD_LOGIC := '0';
128 CONSTANT USE_IAP_MEMCTRL : integer := 1;
128 SIGNAL clk_24 : STD_LOGIC := '0';
129 --==========================================================================
129 -----------------------------------------------------------------------------
130
130 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
131 SIGNAL clk_50_s : STD_LOGIC := '0';
131 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
132 SIGNAL clk_25 : STD_LOGIC := '0';
132 --
133 SIGNAL clk_24 : STD_LOGIC := '0';
133 SIGNAL errorn : STD_LOGIC;
134 -----------------------------------------------------------------------------
134 -- UART AHB ---------------------------------------------------------------
135 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
135 -- SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
136 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
136 -- SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
137 --
137
138 SIGNAL errorn : STD_LOGIC;
138 -- UART APB ---------------------------------------------------------------
139 -- UART AHB ---------------------------------------------------------------
139 -- SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
140 -- SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
140 -- SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
141 -- SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
141 --
142
142 SIGNAL I00_s : STD_LOGIC;
143 -- UART APB ---------------------------------------------------------------
143
144 -- SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
144 -- CONSTANTS
145 -- SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
145 CONSTANT CFG_PADTECH : INTEGER := inferred;
146 --
146 --
147 SIGNAL I00_s : STD_LOGIC;
147 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
148
148 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
149 -- CONSTANTS
149 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
150 CONSTANT CFG_PADTECH : INTEGER := inferred;
150
151 --
151 SIGNAL apbi_ext : apb_slv_in_type;
152 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
152 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5); -- := (OTHERS => apb_none);
153 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
153 SIGNAL ahbi_s_ext : ahb_slv_in_type;
154 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
154 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3); -- := (OTHERS => ahbs_none);
155
155 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
156 SIGNAL apbi_ext : apb_slv_in_type;
156 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1); -- := (OTHERS => ahbm_none);
157 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5); -- := (OTHERS => apb_none);
157
158 SIGNAL ahbi_s_ext : ahb_slv_in_type;
158 -- Spacewire signals
159 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3); -- := (OTHERS => ahbs_none);
159 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
160 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
160 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
161 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1); -- := (OTHERS => ahbm_none);
161 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
162
162 SIGNAL spw_rxtxclk : STD_ULOGIC;
163 -- Spacewire signals
163 SIGNAL spw_rxclkn : STD_ULOGIC;
164 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
164 SIGNAL spw_clk : STD_LOGIC;
165 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
165 SIGNAL swni : grspw_in_type;
166 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
166 SIGNAL swno : grspw_out_type;
167 SIGNAL spw_rxtxclk : STD_ULOGIC;
167 -- SIGNAL clkmn : STD_ULOGIC;
168 SIGNAL spw_rxclkn : STD_ULOGIC;
168 -- SIGNAL txclk : STD_ULOGIC;
169 SIGNAL spw_clk : STD_LOGIC;
169
170 SIGNAL swni : grspw_in_type;
170 --GPIO
171 SIGNAL swno : grspw_out_type;
171 SIGNAL gpioi : gpio_in_type;
172 -- SIGNAL clkmn : STD_ULOGIC;
172 SIGNAL gpioo : gpio_out_type;
173 -- SIGNAL txclk : STD_ULOGIC;
173
174
174 -- AD Converter ADS7886
175 --GPIO
175 SIGNAL sample : Samples14v(7 DOWNTO 0);
176 SIGNAL gpioi : gpio_in_type;
176 SIGNAL sample_s : Samples(7 DOWNTO 0);
177 SIGNAL gpioo : gpio_out_type;
177 SIGNAL sample_val : STD_LOGIC;
178
178 SIGNAL ADC_nCS_sig : STD_LOGIC;
179 -- AD Converter ADS7886
179 SIGNAL ADC_CLK_sig : STD_LOGIC;
180 SIGNAL sample : Samples14v(7 DOWNTO 0);
180 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
181 SIGNAL sample_s : Samples(7 DOWNTO 0);
181
182 SIGNAL sample_val : STD_LOGIC;
182 SIGNAL bias_fail_sw_sig : STD_LOGIC;
183 SIGNAL ADC_nCS_sig : STD_LOGIC;
183
184 SIGNAL ADC_CLK_sig : STD_LOGIC;
184 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
185 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
185 SIGNAL observation_vector_0 : STD_LOGIC_VECTOR(11 DOWNTO 0);
186
186 SIGNAL observation_vector_1 : STD_LOGIC_VECTOR(11 DOWNTO 0);
187 SIGNAL bias_fail_sw_sig : STD_LOGIC;
187 -----------------------------------------------------------------------------
188
188
189 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
189 SIGNAL LFR_soft_rstn : STD_LOGIC;
190 SIGNAL observation_vector_0 : STD_LOGIC_VECTOR(11 DOWNTO 0);
190 SIGNAL LFR_rstn : STD_LOGIC;
191 SIGNAL observation_vector_1 : STD_LOGIC_VECTOR(11 DOWNTO 0);
191
192 -----------------------------------------------------------------------------
192
193
193 SIGNAL rstn_25 : STD_LOGIC;
194 SIGNAL LFR_soft_rstn : STD_LOGIC;
194 SIGNAL rstn_25_d1 : STD_LOGIC;
195 SIGNAL LFR_rstn : STD_LOGIC;
195 SIGNAL rstn_25_d2 : STD_LOGIC;
196
196 SIGNAL rstn_25_d3 : STD_LOGIC;
197
197
198 SIGNAL rstn_25 : STD_LOGIC;
198 SIGNAL rstn_24 : STD_LOGIC;
199 SIGNAL rstn_25_d1 : STD_LOGIC;
199 SIGNAL rstn_24_d1 : STD_LOGIC;
200 SIGNAL rstn_25_d2 : STD_LOGIC;
200 SIGNAL rstn_24_d2 : STD_LOGIC;
201 SIGNAL rstn_25_d3 : STD_LOGIC;
201 SIGNAL rstn_24_d3 : STD_LOGIC;
202
202
203 SIGNAL rstn_24 : STD_LOGIC;
203 SIGNAL rstn_50 : STD_LOGIC;
204 SIGNAL rstn_24_d1 : STD_LOGIC;
204 SIGNAL rstn_50_d1 : STD_LOGIC;
205 SIGNAL rstn_24_d2 : STD_LOGIC;
205 SIGNAL rstn_50_d2 : STD_LOGIC;
206 SIGNAL rstn_24_d3 : STD_LOGIC;
206 SIGNAL rstn_50_d3 : STD_LOGIC;
207
207
208 SIGNAL rstn_50 : STD_LOGIC;
208 SIGNAL lfr_debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
209 SIGNAL rstn_50_d1 : STD_LOGIC;
209 SIGNAL lfr_debug_vector_ms : STD_LOGIC_VECTOR(11 DOWNTO 0);
210 SIGNAL rstn_50_d2 : STD_LOGIC;
210
211 SIGNAL rstn_50_d3 : STD_LOGIC;
211 --
212
212 SIGNAL SRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
213 SIGNAL lfr_debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
213
214 SIGNAL lfr_debug_vector_ms : STD_LOGIC_VECTOR(11 DOWNTO 0);
214 --
215
215 SIGNAL sample_hk : STD_LOGIC_VECTOR(15 DOWNTO 0);
216 --
216 SIGNAL HK_SEL : STD_LOGIC_VECTOR(1 DOWNTO 0);
217 SIGNAL SRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
217
218
218 SIGNAL nSRAM_READY : STD_LOGIC;
219 --
219
220 SIGNAL sample_hk : STD_LOGIC_VECTOR(15 DOWNTO 0);
220 BEGIN -- beh
221 SIGNAL HK_SEL : STD_LOGIC_VECTOR(1 DOWNTO 0);
221
222
222 -----------------------------------------------------------------------------
223 SIGNAL nSRAM_READY : STD_LOGIC;
223 -- WARNING !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
224
224 -- clk_50 frequency is 100 Mhz !
225 BEGIN -- beh
225 PROCESS (clk100MHz, reset)
226
226 BEGIN -- PROCESS
227 -----------------------------------------------------------------------------
227 IF clk100MHz'EVENT AND clk100MHz = '1' THEN -- rising clock edge
228 -- WARNING !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
228 clk_50_s <= NOT clk_50_s;
229 -- clk_50 frequency is 100 Mhz !
229 END IF;
230 PROCESS (clk_50, reset)
230 END PROCESS;
231 BEGIN -- PROCESS
231 -- WARNING !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
232 IF clk_50'EVENT AND clk_50 = '1' THEN -- rising clock edge
232 -----------------------------------------------------------------------------
233 clk_50_s <= NOT clk_50_s;
233
234 END IF;
234 PROCESS (clk_50_s, reset)
235 END PROCESS;
235 BEGIN -- PROCESS
236 -- WARNING !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
236 IF reset = '0' THEN -- asynchronous reset (active low)
237 -----------------------------------------------------------------------------
237 clk_25 <= '0';
238
238 rstn_25 <= '0';
239 PROCESS (clk_50_s, reset)
239 rstn_25_d1 <= '0';
240 BEGIN -- PROCESS
240 rstn_25_d2 <= '0';
241 IF reset = '0' THEN -- asynchronous reset (active low)
241 rstn_25_d3 <= '0';
242 clk_25 <= '0';
242 ELSIF clk_50_s'EVENT AND clk_50_s = '1' THEN -- rising clock edge
243 rstn_25 <= '0';
243 clk_25 <= NOT clk_25;
244 rstn_25_d1 <= '0';
244 rstn_25_d1 <= '1';
245 rstn_25_d2 <= '0';
245 rstn_25_d2 <= rstn_25_d1;
246 rstn_25_d3 <= '0';
246 rstn_25_d3 <= rstn_25_d2;
247 ELSIF clk_50_s'EVENT AND clk_50_s = '1' THEN -- rising clock edge
247 rstn_25 <= rstn_25_d3;
248 clk_25 <= NOT clk_25;
248 END IF;
249 rstn_25_d1 <= '1';
249 END PROCESS;
250 rstn_25_d2 <= rstn_25_d1;
250
251 rstn_25_d3 <= rstn_25_d2;
251 PROCESS (clk49_152MHz, reset)
252 rstn_25 <= rstn_25_d3;
252 BEGIN -- PROCESS
253 END IF;
253 IF reset = '0' THEN -- asynchronous reset (active low)
254 END PROCESS;
254 clk_24 <= '0';
255
255 rstn_24_d1 <= '0';
256 PROCESS (clk_49, reset)
256 rstn_24_d2 <= '0';
257 BEGIN -- PROCESS
257 rstn_24_d3 <= '0';
258 IF reset = '0' THEN -- asynchronous reset (active low)
258 rstn_24 <= '0';
259 clk_24 <= '0';
259 ELSIF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN -- rising clock edge
260 rstn_24_d1 <= '0';
260 clk_24 <= NOT clk_24;
261 rstn_24_d2 <= '0';
261 rstn_24_d1 <= '1';
262 rstn_24_d3 <= '0';
262 rstn_24_d2 <= rstn_24_d1;
263 rstn_24 <= '0';
263 rstn_24_d3 <= rstn_24_d2;
264 ELSIF clk_49'EVENT AND clk_49 = '1' THEN -- rising clock edge
264 rstn_24 <= rstn_24_d3;
265 clk_24 <= NOT clk_24;
265 END IF;
266 rstn_24_d1 <= '1';
266 END PROCESS;
267 rstn_24_d2 <= rstn_24_d1;
267
268 rstn_24_d3 <= rstn_24_d2;
268 -----------------------------------------------------------------------------
269 rstn_24 <= rstn_24_d3;
269
270 END IF;
270 PROCESS (clk_25, rstn_25)
271 END PROCESS;
271 BEGIN -- PROCESS
272
272 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
273 -----------------------------------------------------------------------------
273 LED0 <= '0';
274
274 LED1 <= '0';
275 PROCESS (clk_25, rstn_25)
275 LED2 <= '0';
276 BEGIN -- PROCESS
276 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
277 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
277 LED0 <= '0';
278 LED0 <= '0';
278 LED1 <= '1';
279 LED1 <= '0';
279 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
280 LED2 <= '0';
280 END IF;
281 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
281 END PROCESS;
282 LED0 <= '0';
282
283 LED1 <= '1';
283 PROCESS (clk49_152MHz, rstn_24)
284 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
284 BEGIN -- PROCESS
285 END IF;
285 IF rstn_24 = '0' THEN -- asynchronous reset (active low)
286 END PROCESS;
286 I00_s <= '0';
287
287 ELSIF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN -- rising clock edge
288 PROCESS (clk_24, rstn_24)
288 I00_s <= NOT I00_s;
289 BEGIN -- PROCESS
289 END IF;
290 IF rstn_24 = '0' THEN -- asynchronous reset (active low)
290 END PROCESS;
291 I00_s <= '0';
291
292 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
292 --UARTs
293 I00_s <= NOT I00_s;
293 nCTS1 <= '1';
294 END IF;
294 nCTS2 <= '1';
295 END PROCESS;
295 nDCD2 <= '1';
296
296 -- No AHB UART
297 --UARTs
297 RXD1 <= TXD1;
298 nCTS1 <= '1';
298
299 nCTS2 <= '1';
299 --
300 nDCD2 <= '1';
300
301
301 leon3_soc_1 : leon3_soc
302 --
302 GENERIC MAP (
303
303 fabtech => apa3e,
304 leon3_soc_1 : leon3_soc
304 memtech => apa3e,
305 GENERIC MAP (
305 padtech => inferred,
306 fabtech => apa3e,
306 clktech => inferred,
307 memtech => apa3e,
307 disas => 0,
308 padtech => inferred,
308 dbguart => 0,
309 clktech => inferred,
309 pclow => 2,
310 disas => 0,
310 clk_freq => 25000,
311 dbguart => 0,
311 IS_RADHARD => 0,
312 pclow => 2,
312 NB_CPU => 1,
313 clk_freq => 25000,
313 ENABLE_FPU => 1,
314 IS_RADHARD => 0,
314 FPU_NETLIST => 0,
315 NB_CPU => 1,
315 ENABLE_DSU => 1,
316 ENABLE_FPU => 1,
316 ENABLE_AHB_UART => 0,
317 FPU_NETLIST => 0,
317 ENABLE_APB_UART => 1,
318 ENABLE_DSU => 1,
318 ENABLE_IRQMP => 1,
319 ENABLE_AHB_UART => 0,
319 ENABLE_GPT => 1,
320 ENABLE_APB_UART => 1,
320 NB_AHB_MASTER => NB_AHB_MASTER,
321 ENABLE_IRQMP => 1,
321 NB_AHB_SLAVE => NB_AHB_SLAVE,
322 ENABLE_GPT => 1,
322 NB_APB_SLAVE => NB_APB_SLAVE,
323 NB_AHB_MASTER => NB_AHB_MASTER,
323 ADDRESS_SIZE => 20,
324 NB_AHB_SLAVE => NB_AHB_SLAVE,
324 USES_IAP_MEMCTRLR => USE_IAP_MEMCTRL,
325 NB_APB_SLAVE => NB_APB_SLAVE,
325 BYPASS_EDAC_MEMCTRLR => '0',
326 ADDRESS_SIZE => 20,
326 SRBANKSZ => 9)
327 USES_IAP_MEMCTRLR => USE_IAP_MEMCTRL,
327 PORT MAP (
328 BYPASS_EDAC_MEMCTRLR => '0',
328 clk => clk_25,
329 SRBANKSZ => 9)
329 reset => rstn_25,
330 PORT MAP (
330 errorn => errorn,
331 clk => clk_25,
331 ahbrxd => OPEN,--TXD1,
332 reset => rstn_25,
332 ahbtxd => OPEN,--RXD1,
333 errorn => errorn,
333 urxd1 => TXD2,
334 ahbrxd => OPEN,--TXD1,
334 utxd1 => RXD2,
335 ahbtxd => OPEN,--RXD1,
335 address => SRAM_A,
336 urxd1 => TXD2,
336 data => SRAM_DQ,
337 utxd1 => RXD2,
337 nSRAM_BE0 => SRAM_nBE(0),
338 address => SRAM_A,
338 nSRAM_BE1 => SRAM_nBE(1),
339 data => SRAM_DQ,
339 nSRAM_BE2 => SRAM_nBE(2),
340 nSRAM_BE0 => SRAM_nBE(0),
340 nSRAM_BE3 => SRAM_nBE(3),
341 nSRAM_BE1 => SRAM_nBE(1),
341 nSRAM_WE => SRAM_nWE,
342 nSRAM_BE2 => SRAM_nBE(2),
342 nSRAM_CE => SRAM_CE_s,
343 nSRAM_BE3 => SRAM_nBE(3),
343 nSRAM_OE => SRAM_nOE,
344 nSRAM_WE => SRAM_nWE,
344 nSRAM_READY => nSRAM_READY,
345 nSRAM_CE => SRAM_CE_s,
345 SRAM_MBE => OPEN,
346 nSRAM_OE => SRAM_nOE,
346 apbi_ext => apbi_ext,
347 nSRAM_READY => nSRAM_READY,
347 apbo_ext => apbo_ext,
348 SRAM_MBE => OPEN,
348 ahbi_s_ext => ahbi_s_ext,
349 apbi_ext => apbi_ext,
349 ahbo_s_ext => ahbo_s_ext,
350 apbo_ext => apbo_ext,
350 ahbi_m_ext => ahbi_m_ext,
351 ahbi_s_ext => ahbi_s_ext,
351 ahbo_m_ext => ahbo_m_ext);
352 ahbo_s_ext => ahbo_s_ext,
352
353 ahbi_m_ext => ahbi_m_ext,
353 PROCESS (clk_25, rstn_25)
354 ahbo_m_ext => ahbo_m_ext);
354 BEGIN -- PROCESS
355
355 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
356 PROCESS (clk_25, rstn_25)
356 nSRAM_READY <= '1';
357 BEGIN -- PROCESS
357 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
358 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
358 nSRAM_READY <= '1';
359 nSRAM_READY <= '1';
359 IF IO0 = '1' THEN
360 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
360 nSRAM_READY <= '0';
361 nSRAM_READY <= '1';
361 END IF;
362 IF IO0 = '1' THEN
362 END IF;
363 nSRAM_READY <= '0';
363 END PROCESS;
364 END IF;
364
365 END IF;
365
366 END PROCESS;
366
367
367 IAP:if USE_IAP_MEMCTRL = 1 GENERATE
368
368 SRAM_CE <= not SRAM_CE_s(0);
369
369 END GENERATE;
370 IAP:if USE_IAP_MEMCTRL = 1 GENERATE
370
371 SRAM_CE <= not SRAM_CE_s(0);
371 NOIAP:if USE_IAP_MEMCTRL = 0 GENERATE
372 END GENERATE;
372 SRAM_CE <= SRAM_CE_s(0);
373
373 END GENERATE;
374 NOIAP:if USE_IAP_MEMCTRL = 0 GENERATE
374 -------------------------------------------------------------------------------
375 SRAM_CE <= SRAM_CE_s(0);
375 -- APB_LFR_MANAGEMENT ---------------------------------------------------------
376 END GENERATE;
376 -------------------------------------------------------------------------------
377 -------------------------------------------------------------------------------
377 apb_lfr_management_1 : apb_lfr_management
378 -- APB_LFR_MANAGEMENT ---------------------------------------------------------
378 GENERIC MAP (
379 -------------------------------------------------------------------------------
379 tech => apa3e,
380 apb_lfr_management_1 : apb_lfr_management
380 pindex => 6,
381 GENERIC MAP (
381 paddr => 6,
382 tech => apa3e,
382 pmask => 16#fff#,
383 pindex => 6,
383 -- FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
384 paddr => 6,
384 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
385 pmask => 16#fff#,
385 PORT MAP (
386 -- FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
386 clk25MHz => clk_25,
387 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
387 resetn_25MHz => rstn_25, -- TODO
388 PORT MAP (
388 -- clk24_576MHz => clk_24, -- 49.152MHz/2
389 clk25MHz => clk_25,
389 -- resetn_24_576MHz => rstn_24, -- TODO
390 resetn_25MHz => rstn_25, -- TODO
390 grspw_tick => swno.tickout,
391 -- clk24_576MHz => clk_24, -- 49.152MHz/2
391 apbi => apbi_ext,
392 -- resetn_24_576MHz => rstn_24, -- TODO
392 apbo => apbo_ext(6),
393 grspw_tick => swno.tickout,
393 HK_sample => sample_hk,
394 apbi => apbi_ext,
394 HK_val => sample_val,
395 apbo => apbo_ext(6),
395 HK_sel => HK_SEL,
396 HK_sample => sample_hk,
396 DAC_SDO => OPEN,
397 HK_val => sample_val,
397 DAC_SCK => OPEN,
398 HK_sel => HK_SEL,
398 DAC_SYNC => OPEN,
399 DAC_SDO => OPEN,
399 DAC_CAL_EN => OPEN,
400 DAC_SCK => OPEN,
400 coarse_time => coarse_time,
401 DAC_SYNC => OPEN,
401 fine_time => fine_time,
402 DAC_CAL_EN => OPEN,
402 LFR_soft_rstn => LFR_soft_rstn
403 coarse_time => coarse_time,
403 );
404 fine_time => fine_time,
404
405 LFR_soft_rstn => LFR_soft_rstn
405 -----------------------------------------------------------------------
406 );
406 --- SpaceWire --------------------------------------------------------
407
407 -----------------------------------------------------------------------
408 -----------------------------------------------------------------------
408
409 --- SpaceWire --------------------------------------------------------
409 SPW_EN <= '1';
410 -----------------------------------------------------------------------
410
411
411 spw_clk <= clk_50_s;
412 SPW_EN <= '1';
412 spw_rxtxclk <= spw_clk;
413
413 spw_rxclkn <= NOT spw_rxtxclk;
414 spw_clk <= clk_50_s;
414
415 spw_rxtxclk <= spw_clk;
415 -- PADS for SPW1
416 spw_rxclkn <= NOT spw_rxtxclk;
416 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
417
417 PORT MAP (SPW_NOM_DIN, dtmp(0));
418 -- PADS for SPW1
418 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
419 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
419 PORT MAP (SPW_NOM_SIN, stmp(0));
420 PORT MAP (SPW_NOM_DIN, dtmp(0));
420 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
421 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
421 PORT MAP (SPW_NOM_DOUT, swno.d(0));
422 PORT MAP (SPW_NOM_SIN, stmp(0));
422 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
423 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
423 PORT MAP (SPW_NOM_SOUT, swno.s(0));
424 PORT MAP (SPW_NOM_DOUT, swno.d(0));
424 -- PADS FOR SPW2
425 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
425 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
426 PORT MAP (SPW_NOM_SOUT, swno.s(0));
426 PORT MAP (SPW_RED_SIN, dtmp(1));
427 -- PADS FOR SPW2
427 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
428 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
428 PORT MAP (SPW_RED_DIN, stmp(1));
429 PORT MAP (SPW_RED_SIN, dtmp(1));
429 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
430 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
430 PORT MAP (SPW_RED_DOUT, swno.d(1));
431 PORT MAP (SPW_RED_DIN, stmp(1));
431 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
432 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
432 PORT MAP (SPW_RED_SOUT, swno.s(1));
433 PORT MAP (SPW_RED_DOUT, swno.d(1));
433
434 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
434 -- GRSPW PHY
435 PORT MAP (SPW_RED_SOUT, swno.s(1));
435 --spw1_input: if CFG_SPW_GRSPW = 1 generate
436
436 spw_inputloop : FOR j IN 0 TO 1 GENERATE
437 -- GRSPW PHY
437 spw_phy0 : grspw_phy
438 --spw1_input: if CFG_SPW_GRSPW = 1 generate
438 GENERIC MAP(
439 spw_inputloop : FOR j IN 0 TO 1 GENERATE
439 tech => apa3e,
440 spw_phy0 : grspw_phy
440 rxclkbuftype => 1,
441 GENERIC MAP(
441 scantest => 0)
442 tech => apa3e,
442 PORT MAP(
443 rxclkbuftype => 1,
443 rxrst => swno.rxrst,
444 scantest => 0)
444 di => dtmp(j),
445 PORT MAP(
445 si => stmp(j),
446 rxrst => swno.rxrst,
446 rxclko => spw_rxclk(j),
447 di => dtmp(j),
447 do => swni.d(j),
448 si => stmp(j),
448 ndo => swni.nd(j*5+4 DOWNTO j*5),
449 rxclko => spw_rxclk(j),
449 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
450 do => swni.d(j),
450 END GENERATE spw_inputloop;
451 ndo => swni.nd(j*5+4 DOWNTO j*5),
451
452 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
452 swni.rmapnodeaddr <= (OTHERS => '0');
453 END GENERATE spw_inputloop;
453
454
454 -- SPW core
455 swni.rmapnodeaddr <= (OTHERS => '0');
455 sw0 : grspwm GENERIC MAP(
456
456 tech => apa3e,
457 -- SPW core
457 hindex => 1,
458 sw0 : grspwm GENERIC MAP(
458 pindex => 5,
459 tech => apa3e,
459 paddr => 5,
460 hindex => 1,
460 pirq => 11,
461 pindex => 5,
461 sysfreq => 25000, -- CPU_FREQ
462 paddr => 5,
462 rmap => 1,
463 pirq => 11,
463 rmapcrc => 1,
464 sysfreq => 25000, -- CPU_FREQ
464 fifosize1 => 16,
465 rmap => 1,
465 fifosize2 => 16,
466 rmapcrc => 1,
466 rxclkbuftype => 1,
467 fifosize1 => 16,
467 rxunaligned => 0,
468 fifosize2 => 16,
468 rmapbufs => 4,
469 rxclkbuftype => 1,
469 ft => 0,
470 rxunaligned => 0,
470 netlist => 0,
471 rmapbufs => 4,
471 ports => 2,
472 ft => 0,
472 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
473 netlist => 0,
473 memtech => apa3e,
474 ports => 2,
474 destkey => 2,
475 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
475 spwcore => 1
476 memtech => apa3e,
476 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
477 destkey => 2,
477 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
478 spwcore => 1
478 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
479 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
479 )
480 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
480 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
481 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
481 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
482 )
482 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
483 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
483 swni, swno);
484 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
484
485 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
485 swni.tickin <= '0';
486 swni, swno);
486 swni.rmapen <= '1';
487
487 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
488 swni.tickin <= '0';
488 swni.tickinraw <= '0';
489 swni.rmapen <= '1';
489 swni.timein <= (OTHERS => '0');
490 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
490 swni.dcrstval <= (OTHERS => '0');
491 swni.tickinraw <= '0';
491 swni.timerrstval <= (OTHERS => '0');
492 swni.timein <= (OTHERS => '0');
492
493 swni.dcrstval <= (OTHERS => '0');
493 -------------------------------------------------------------------------------
494 swni.timerrstval <= (OTHERS => '0');
494 -- LFR ------------------------------------------------------------------------
495
495 -------------------------------------------------------------------------------
496 -------------------------------------------------------------------------------
496
497 -- LFR ------------------------------------------------------------------------
497
498 -------------------------------------------------------------------------------
498 LFR_rstn <= LFR_soft_rstn AND rstn_25;
499
499 --LFR_rstn <= rstn_25;
500
500
501 LFR_rstn <= LFR_soft_rstn AND rstn_25;
501 lpp_lfr_1 : lpp_lfr
502 --LFR_rstn <= rstn_25;
502 GENERIC MAP (
503
503 Mem_use => use_RAM,
504 lpp_lfr_1 : lpp_lfr
504 nb_data_by_buffer_size => 32,
505 GENERIC MAP (
505 nb_snapshot_param_size => 32,
506 Mem_use => use_RAM,
506 delta_vector_size => 32,
507 nb_data_by_buffer_size => 32,
507 delta_vector_size_f0_2 => 7, -- log2(96)
508 nb_snapshot_param_size => 32,
508 pindex => 15,
509 delta_vector_size => 32,
509 paddr => 15,
510 delta_vector_size_f0_2 => 7, -- log2(96)
510 pmask => 16#fff#,
511 pindex => 15,
511 pirq_ms => 6,
512 paddr => 15,
512 pirq_wfp => 14,
513 pmask => 16#fff#,
513 hindex => 2,
514 pirq_ms => 6,
514 top_lfr_version => X"000159") -- aa.bb.cc version
515 pirq_wfp => 14,
515 PORT MAP (
516 hindex => 2,
516 clk => clk_25,
517 top_lfr_version => X"000159") -- aa.bb.cc version
517 rstn => LFR_rstn,
518 PORT MAP (
518 sample_B => sample_s(2 DOWNTO 0),
519 clk => clk_25,
519 sample_E => sample_s(7 DOWNTO 3),
520 rstn => LFR_rstn,
520 sample_val => sample_val,
521 sample_B => sample_s(2 DOWNTO 0),
521 apbi => apbi_ext,
522 sample_E => sample_s(7 DOWNTO 3),
522 apbo => apbo_ext(15),
523 sample_val => sample_val,
523 ahbi => ahbi_m_ext,
524 apbi => apbi_ext,
524 ahbo => ahbo_m_ext(2),
525 apbo => apbo_ext(15),
525 coarse_time => coarse_time,
526 ahbi => ahbi_m_ext,
526 fine_time => fine_time,
527 ahbo => ahbo_m_ext(2),
527 data_shaping_BW => bias_fail_sw_sig,
528 coarse_time => coarse_time,
528 debug_vector => lfr_debug_vector,
529 fine_time => fine_time,
529 debug_vector_ms => lfr_debug_vector_ms
530 data_shaping_BW => bias_fail_sw_sig,
530 );
531 debug_vector => lfr_debug_vector,
531
532 debug_vector_ms => lfr_debug_vector_ms
532 observation_reg(11 DOWNTO 0) <= lfr_debug_vector;
533 );
533 observation_reg(31 DOWNTO 12) <= (OTHERS => '0');
534
534 observation_vector_0(11 DOWNTO 0) <= lfr_debug_vector;
535 observation_reg(11 DOWNTO 0) <= lfr_debug_vector;
535 observation_vector_1(11 DOWNTO 0) <= lfr_debug_vector;
536 observation_reg(31 DOWNTO 12) <= (OTHERS => '0');
536 -- IO0 <= rstn_25;
537 observation_vector_0(11 DOWNTO 0) <= lfr_debug_vector;
537 IO1 <= lfr_debug_vector_ms(0); -- LFR MS FFT data_valid
538 observation_vector_1(11 DOWNTO 0) <= lfr_debug_vector;
538 IO2 <= lfr_debug_vector_ms(0); -- LFR MS FFT ready
539 -- IO0 <= rstn_25;
539 IO3 <= lfr_debug_vector(0); -- LFR APBREG error_buffer_full
540 IO1 <= lfr_debug_vector_ms(0); -- LFR MS FFT data_valid
540 IO4 <= lfr_debug_vector(1); -- LFR APBREG reg_sp.status_error_buffer_full
541 IO2 <= lfr_debug_vector_ms(0); -- LFR MS FFT ready
541 IO5 <= lfr_debug_vector(8); -- LFR APBREG ready_matrix_f2
542 IO3 <= lfr_debug_vector(0); -- LFR APBREG error_buffer_full
542 IO6 <= lfr_debug_vector(9); -- LFR APBREG reg0_ready_matrix_f2
543 IO4 <= lfr_debug_vector(1); -- LFR APBREG reg_sp.status_error_buffer_full
543 IO7 <= lfr_debug_vector(10); -- LFR APBREG reg0_ready_matrix_f2
544 IO5 <= lfr_debug_vector(8); -- LFR APBREG ready_matrix_f2
544
545 IO6 <= lfr_debug_vector(9); -- LFR APBREG reg0_ready_matrix_f2
545 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
546 IO7 <= lfr_debug_vector(10); -- LFR APBREG reg0_ready_matrix_f2
546 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
547
547 END GENERATE all_sample;
548 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
548
549 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
549 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
550 END GENERATE all_sample;
550 GENERIC MAP(
551
551 ChannelCount => 8,
552 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
552 SampleNbBits => 14,
553 GENERIC MAP(
553 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
554 ChannelCount => 8,
554 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
555 SampleNbBits => 14,
555 PORT MAP (
556 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
556 -- CONV
557 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
557 cnv_clk => clk_24,
558 PORT MAP (
558 cnv_rstn => rstn_24,
559 -- CONV
559 cnv => ADC_nCS_sig,
560 cnv_clk => clk_24,
560 -- DATA
561 cnv_rstn => rstn_24,
561 clk => clk_25,
562 cnv => ADC_nCS_sig,
562 rstn => rstn_25,
563 -- DATA
563 sck => ADC_CLK_sig,
564 clk => clk_25,
564 sdo => ADC_SDO_sig,
565 rstn => rstn_25,
565 -- SAMPLE
566 sck => ADC_CLK_sig,
566 sample => sample,
567 sdo => ADC_SDO_sig,
567 sample_val => sample_val);
568 -- SAMPLE
568
569 sample => sample,
569 --IO10 <= ADC_SDO_sig(5);
570 sample_val => sample_val);
570 --IO9 <= ADC_SDO_sig(4);
571
571 --IO8 <= ADC_SDO_sig(3);
572 --IO10 <= ADC_SDO_sig(5);
572
573 --IO9 <= ADC_SDO_sig(4);
573 ADC_nCS <= ADC_nCS_sig;
574 --IO8 <= ADC_SDO_sig(3);
574 ADC_CLK <= ADC_CLK_sig;
575
575 ADC_SDO_sig <= ADC_SDO;
576 ADC_nCS <= ADC_nCS_sig;
576
577 ADC_CLK <= ADC_CLK_sig;
577 sample_hk <= "0001000100010001" WHEN HK_SEL = "00" ELSE
578 ADC_SDO_sig <= ADC_SDO;
578 "0010001000100010" WHEN HK_SEL = "01" ELSE
579
579 "0100010001000100" WHEN HK_SEL = "10" ELSE
580 sample_hk <= "0001000100010001" WHEN HK_SEL = "00" ELSE
580 (OTHERS => '0');
581 "0010001000100010" WHEN HK_SEL = "01" ELSE
581
582 "0100010001000100" WHEN HK_SEL = "10" ELSE
582
583 (OTHERS => '0');
583 ----------------------------------------------------------------------
584
584 --- GPIO -----------------------------------------------------------
585
585 ----------------------------------------------------------------------
586 ----------------------------------------------------------------------
586
587 --- GPIO -----------------------------------------------------------
587 grgpio0 : grgpio
588 ----------------------------------------------------------------------
588 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
589
589 PORT MAP(rstn_25, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
590 grgpio0 : grgpio
590
591 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
591 gpioi.sig_en <= (OTHERS => '0');
592 PORT MAP(rstn_25, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
592 gpioi.sig_in <= (OTHERS => '0');
593
593 gpioi.din <= (OTHERS => '0');
594 gpioi.sig_en <= (OTHERS => '0');
594 PROCESS (clk_25, rstn_25)
595 gpioi.sig_in <= (OTHERS => '0');
595 BEGIN -- PROCESS
596 gpioi.din <= (OTHERS => '0');
596 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
597 PROCESS (clk_25, rstn_25)
597 IO8 <= '0';
598 BEGIN -- PROCESS
598 IO9 <= '0';
599 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
599 IO10 <= '0';
600 IO8 <= '0';
600 IO11 <= '0';
601 IO9 <= '0';
601 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
602 IO10 <= '0';
602 CASE gpioo.dout(2 DOWNTO 0) IS
603 IO11 <= '0';
603 WHEN "011" =>
604 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
604 IO8 <= observation_reg(8);
605 CASE gpioo.dout(2 DOWNTO 0) IS
605 IO9 <= observation_reg(9);
606 WHEN "011" =>
606 IO10 <= observation_reg(10);
607 IO8 <= observation_reg(8);
607 IO11 <= observation_reg(11);
608 IO9 <= observation_reg(9);
608 WHEN "001" =>
609 IO10 <= observation_reg(10);
609 IO8 <= observation_reg(8 + 12);
610 IO11 <= observation_reg(11);
610 IO9 <= observation_reg(9 + 12);
611 WHEN "001" =>
611 IO10 <= observation_reg(10 + 12);
612 IO8 <= observation_reg(8 + 12);
612 IO11 <= observation_reg(11 + 12);
613 IO9 <= observation_reg(9 + 12);
613 WHEN "010" =>
614 IO10 <= observation_reg(10 + 12);
614 IO8 <= '0';
615 IO11 <= observation_reg(11 + 12);
615 IO9 <= '0';
616 WHEN "010" =>
616 IO10 <= '0';
617 IO8 <= '0';
617 IO11 <= '0';
618 IO9 <= '0';
618 WHEN "000" =>
619 IO10 <= '0';
619 IO8 <= observation_vector_0(8);
620 IO11 <= '0';
620 IO9 <= observation_vector_0(9);
621 WHEN "000" =>
621 IO10 <= observation_vector_0(10);
622 IO8 <= observation_vector_0(8);
622 IO11 <= observation_vector_0(11);
623 IO9 <= observation_vector_0(9);
623 WHEN "100" =>
624 IO10 <= observation_vector_0(10);
624 IO8 <= observation_vector_1(8);
625 IO11 <= observation_vector_0(11);
625 IO9 <= observation_vector_1(9);
626 WHEN "100" =>
626 IO10 <= observation_vector_1(10);
627 IO8 <= observation_vector_1(8);
627 IO11 <= observation_vector_1(11);
628 IO9 <= observation_vector_1(9);
628 WHEN OTHERS => NULL;
629 IO10 <= observation_vector_1(10);
629 END CASE;
630 IO11 <= observation_vector_1(11);
630
631 WHEN OTHERS => NULL;
631 END IF;
632 END CASE;
632 END PROCESS;
633
633 -----------------------------------------------------------------------------
634 END IF;
634 --
635 END PROCESS;
635 -----------------------------------------------------------------------------
636 -----------------------------------------------------------------------------
636 all_apbo_ext : FOR I IN NB_APB_SLAVE-1+5 DOWNTO 5 GENERATE
637 --
637 apbo_ext_not_used : IF I /= 5 AND I /= 6 AND I /= 11 AND I /= 15 GENERATE
638 -----------------------------------------------------------------------------
638 apbo_ext(I) <= apb_none;
639 all_apbo_ext : FOR I IN NB_APB_SLAVE-1+5 DOWNTO 5 GENERATE
639 END GENERATE apbo_ext_not_used;
640 apbo_ext_not_used : IF I /= 5 AND I /= 6 AND I /= 11 AND I /= 15 GENERATE
640 END GENERATE all_apbo_ext;
641 apbo_ext(I) <= apb_none;
641
642 END GENERATE apbo_ext_not_used;
642
643 END GENERATE all_apbo_ext;
643 all_ahbo_ext : FOR I IN NB_AHB_SLAVE-1+3 DOWNTO 3 GENERATE
644
644 ahbo_s_ext(I) <= ahbs_none;
645
645 END GENERATE all_ahbo_ext;
646 all_ahbo_ext : FOR I IN NB_AHB_SLAVE-1+3 DOWNTO 3 GENERATE
646
647 ahbo_s_ext(I) <= ahbs_none;
647 all_ahbo_m_ext : FOR I IN NB_AHB_MASTER-1+1 DOWNTO 1 GENERATE
648 END GENERATE all_ahbo_ext;
648 ahbo_m_ext_not_used : IF I /= 1 AND I /= 2 GENERATE
649
649 ahbo_m_ext(I) <= ahbm_none;
650 all_ahbo_m_ext : FOR I IN NB_AHB_MASTER-1+1 DOWNTO 1 GENERATE
650 END GENERATE ahbo_m_ext_not_used;
651 ahbo_m_ext_not_used : IF I /= 1 AND I /= 2 GENERATE
651 END GENERATE all_ahbo_m_ext;
652 ahbo_m_ext(I) <= ahbm_none;
652
653 END GENERATE ahbo_m_ext_not_used;
653 END beh;
654 END GENERATE all_ahbo_m_ext;
655
656 END beh;
Show file before | Show file after | Hide comments
@@ -1,53 +1,51
1 VHDLIB=../..
1 VHDLIB=../..
2 SCRIPTSDIR=$(VHDLIB)/scripts/
2 SCRIPTSDIR=$(VHDLIB)/scripts/
3 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
3 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
4 TOP=MINI_LFR_top
4 TOP=MINI_LFR_top
5 BOARD=MINI-LFR
5 BOARD=MINI-LFR
6 include $(VHDLIB)/boards/$(BOARD)/Makefile.inc
6 include $(VHDLIB)/boards/$(BOARD)/Makefile.inc
7 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
7 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
8 UCF=$(VHDLIB)/boards/$(BOARD)/$(TOP).ucf
8 UCF=$(VHDLIB)/boards/$(BOARD)/$(TOP).ucf
9 QSF=$(VHDLIB)/boards/$(BOARD)/$(TOP).qsf
9 QSF=$(VHDLIB)/boards/$(BOARD)/$(TOP).qsf
10 EFFORT=high
10 EFFORT=high
11 XSTOPT=
11 XSTOPT=
12 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
12 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
13 VHDLSYNFILES= MINI_LFR_top.vhd
13 VHDLSYNFILES= MINI_LFR_top.vhd
14 VHDLSIMFILES= testbench.vhd
14 VHDLSIMFILES= testbench.vhd
15 SIMTOP=testbench
15 SIMTOP=testbench
16 ##PDC=$(VHDLIB)/boards/$(BOARD)/default.pdc
16 PDC=$(VHDLIB)/boards/$(BOARD)/default.pdc
17 ##SDC=$(VHDLIB)/boards/$(BOARD)/default.sdc
17 SDCFILE=$(VHDLIB)/boards/$(BOARD)/MINI-LFR.sdc
18 PDC=$(VHDLIB)/boards/$(BOARD)/no_uart.pdc
18 SDC=$(VHDLIB)/boards/$(BOARD)/MINI-LFR.sdc
19 SDCFILE=$(VHDLIB)/boards/$(BOARD)/MINI_LFR_synthesis.sdc
20 SDC=$(VHDLIB)/boards/$(BOARD)/MINI_LFR_place_and_route.sdc
21 BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut
19 BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut
22 CLEAN=soft-clean
20 CLEAN=soft-clean
23
21
24 TECHLIBS = proasic3e
22 TECHLIBS = proasic3e
25
23
26 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
24 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
27 tmtc openchip hynix ihp gleichmann micron usbhc
25 tmtc openchip hynix ihp gleichmann micron usbhc
28
26
29 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
27 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
30 pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
28 pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
31 ./amba_lcd_16x2_ctrlr \
29 ./amba_lcd_16x2_ctrlr \
32 ./general_purpose/lpp_AMR \
30 ./general_purpose/lpp_AMR \
33 ./general_purpose/lpp_balise \
31 ./general_purpose/lpp_balise \
34 ./general_purpose/lpp_delay \
32 ./general_purpose/lpp_delay \
35 ./lpp_bootloader \
33 ./lpp_bootloader \
36 ./lpp_uart \
34 ./lpp_uart \
37 ./lpp_usb \
35 ./lpp_usb \
38 ./dsp/lpp_fft_rtax \
36 ./dsp/lpp_fft_rtax \
39 ./lpp_sim/CY7C1061DV33 \
37 ./lpp_sim/CY7C1061DV33 \
40
38
41 FILESKIP =i2cmst.vhd \
39 FILESKIP =i2cmst.vhd \
42 APB_MULTI_DIODE.vhd \
40 APB_MULTI_DIODE.vhd \
43 APB_SIMPLE_DIODE.vhd \
41 APB_SIMPLE_DIODE.vhd \
44 Top_MatrixSpec.vhd \
42 Top_MatrixSpec.vhd \
45 APB_FFT.vhd \
43 APB_FFT.vhd \
46 CoreFFT_simu.vhd \
44 CoreFFT_simu.vhd \
47 lpp_lfr_apbreg_simu.vhd
45 lpp_lfr_apbreg_simu.vhd
48
46
49 include $(GRLIB)/bin/Makefile
47 include $(GRLIB)/bin/Makefile
50 include $(GRLIB)/software/leon3/Makefile
48 include $(GRLIB)/software/leon3/Makefile
51
49
52 ################## project specific targets ##########################
50 ################## project specific targets ##########################
53
51
General Comments 0
You need to be logged in to leave comments. Login now