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sauvegarde modif waveform picker
pellion -
r230:61f51a42947c JC
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe PELLION
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
25
26 ENTITY RR_Arbiter_4 IS
27
28 GENERIC (
29 NB_INPUT : INTEGER := 4);
30
31 PORT (
32 clk : IN STD_LOGIC;
33 rstn : IN STD_LOGIC;
34 in_valid : IN STD_LOGIC_VECTOR(NB_INPUT DOWNTO 0);
35 out_grant : OUT STD_LOGIC_VECTOR(NB_INPUT DOWNTO 0)
36 );
37
38 END RR_Arbiter;
39
40 ARCHITECTURE beh OF RR_Arbiter IS
41
42 SIGNAL grant_vector : STD_LOGIC_VECTOR(NB_INPUT DOWNTO 0);
43
44 BEGIN -- beh
45
46
47
48 END beh;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe PELLION
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
25
26 ENTITY RR_Arbiter_4 IS
27
28 PORT (
29 clk : IN STD_LOGIC;
30 rstn : IN STD_LOGIC;
31 in_valid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
32 out_grant : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
33 );
34
35 END RR_Arbiter_4;
36
37 ARCHITECTURE beh OF RR_Arbiter_4 IS
38
39 SIGNAL out_grant_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
40 SIGNAL grant_sel : STD_LOGIC_VECTOR(1 DOWNTO 0);
41
42 BEGIN -- beh
43
44 out_grant <= out_grant_s;
45
46 out_grant_s <= "0001" WHEN grant_sel = "00" AND in_valid(0) = '1' ELSE
47 "0010" WHEN grant_sel = "00" AND in_valid(1) = '1' ELSE
48 "0100" WHEN grant_sel = "00" AND in_valid(2) = '1' ELSE
49 "1000" WHEN grant_sel = "00" AND in_valid(3) = '1' ELSE
50 "0010" WHEN grant_sel = "01" AND in_valid(1) = '1' ELSE
51 "0100" WHEN grant_sel = "01" AND in_valid(2) = '1' ELSE
52 "1000" WHEN grant_sel = "01" AND in_valid(3) = '1' ELSE
53 "0001" WHEN grant_sel = "01" AND in_valid(0) = '1' ELSE
54 "0100" WHEN grant_sel = "10" AND in_valid(2) = '1' ELSE
55 "1000" WHEN grant_sel = "10" AND in_valid(3) = '1' ELSE
56 "0001" WHEN grant_sel = "10" AND in_valid(0) = '1' ELSE
57 "0010" WHEN grant_sel = "10" AND in_valid(1) = '1' ELSE
58 "1000" WHEN grant_sel = "11" AND in_valid(3) = '1' ELSE
59 "0001" WHEN grant_sel = "11" AND in_valid(0) = '1' ELSE
60 "0010" WHEN grant_sel = "11" AND in_valid(1) = '1' ELSE
61 "0100" WHEN grant_sel = "11" AND in_valid(2) = '1' ELSE
62 "0000";
63
64 PROCESS (clk, rstn)
65 BEGIN -- PROCESS
66 IF rstn = '0' THEN -- asynchronous reset (active low)
67 grant_sel <= "00";
68 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
69 CASE out_grant_s IS
70 WHEN "0001" => grant_sel <= "01";
71 WHEN "0010" => grant_sel <= "10";
72 WHEN "0100" => grant_sel <= "11";
73 WHEN "1000" => grant_sel <= "00";
74 WHEN OTHERS => grant_sel <= grant_sel;
75 END CASE;
76 END IF;
77 END PROCESS;
78
79 END beh;
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1
2 ------------------------------------------------------------------------------
3 -- This file is a part of the LPP VHDL IP LIBRARY
4 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
5 --
6 -- This program is free software; you can redistribute it and/or modify
7 -- it under the terms of the GNU General Public License as published by
8 -- the Free Software Foundation; either version 3 of the License, or
9 -- (at your option) any later version.
10 --
11 -- This program is distributed in the hope that it will be useful,
12 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
13 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 -- GNU General Public License for more details.
15 --
16 -- You should have received a copy of the GNU General Public License
17 -- along with this program; if not, write to the Free Software
18 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 -------------------------------------------------------------------------------
20 -- Author : Jean-christophe Pellion
21 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
22 -- jean-christophe.pellion@easii-ic.com
23 -------------------------------------------------------------------------------
24 -- 1.0 - initial version
25 -- 1.1 - (01/11/2013) FIX boundary error (1kB address should not be crossed by BURSTS)
26 -------------------------------------------------------------------------------
27 LIBRARY ieee;
28 USE ieee.std_logic_1164.ALL;
29 USE ieee.numeric_std.ALL;
30 LIBRARY grlib;
31 USE grlib.amba.ALL;
32 USE grlib.stdlib.ALL;
33 USE grlib.devices.ALL;
34 USE GRLIB.DMA2AHB_Package.ALL;
35 LIBRARY lpp;
36 USE lpp.lpp_amba.ALL;
37 USE lpp.apb_devices_list.ALL;
38 USE lpp.lpp_memory.ALL;
39 USE lpp.lpp_dma_pkg.ALL;
40 USE lpp.lpp_waveform_pkg.ALL;
41 LIBRARY techmap;
42 USE techmap.gencomp.ALL;
43
44
45 ENTITY lpp_dma_multiSource IS
46 GENERIC (
47 tech : INTEGER := inferred;
48 hindex : INTEGER := 2
49 );
50 PORT (
51 -- AMBA AHB system signals
52 HCLK : IN STD_ULOGIC;
53 HRESETn : IN STD_ULOGIC;
54 --
55 run : IN STD_LOGIC;
56 -- AMBA AHB Master Interface
57 AHB_Master_In : IN AHB_Mst_In_Type;
58 AHB_Master_Out : OUT AHB_Mst_Out_Type;
59 --
60 send : IN STD_LOGIC;
61 valid_burst : IN STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
62 done : OUT STD_LOGIC;
63 ren : OUT STD_LOGIC;
64 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
65 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
66 );
67 END;
68
69 ARCHITECTURE Behavioral OF lpp_dma_multiSource IS
70 -----------------------------------------------------------------------------
71 SIGNAL DMAIn : DMA_In_Type;
72 SIGNAL DMAOut : DMA_OUt_Type;
73 -----------------------------------------------------------------------------
74 -----------------------------------------------------------------------------
75 -- CONTROL
76 SIGNAL single_send : STD_LOGIC;
77 SIGNAL burst_send : STD_LOGIC;
78
79 -----------------------------------------------------------------------------
80 -- SEND SINGLE MODULE
81 SIGNAL single_dmai : DMA_In_Type;
82 SIGNAL single_send : STD_LOGIC;
83 SIGNAL single_send_ok : STD_LOGIC;
84 SIGNAL single_send_ko : STD_LOGIC;
85 -----------------------------------------------------------------------------
86 -- SEND SINGLE MODULE
87 SIGNAL burst_dmai : DMA_In_Type;
88 SIGNAL burst_send : STD_LOGIC;
89 SIGNAL burst_send_ok : STD_LOGIC;
90 SIGNAL burst_send_ko : STD_LOGIC;
91 SIGNAL burst_ren : STD_LOGIC;
92 -----------------------------------------------------------------------------
93 SIGNAL data_2_halfword : STD_LOGIC_VECTOR(31 DOWNTO 0);
94 BEGIN
95
96 -----------------------------------------------------------------------------
97 -- DMA to AHB interface
98 DMA2AHB_1 : DMA2AHB
99 GENERIC MAP (
100 hindex => hindex,
101 vendorid => VENDOR_LPP,
102 deviceid => 10,
103 version => 0,
104 syncrst => 1,
105 boundary => 1) -- FIX 11/01/2013
106 PORT MAP (
107 HCLK => HCLK,
108 HRESETn => HRESETn,
109 DMAIn => DMAIn,
110 DMAOut => DMAOut,
111
112 AHBIn => AHB_Master_In,
113 AHBOut => AHB_Master_Out);
114 -----------------------------------------------------------------------------
115
116 single_send <= send WHEN valid_burst = '0' ELSE '0';
117 burst_send <= send WHEN valid_burst = '1' ELSE '0';
118 DMAIn <= single_dmai WHEN valid_burst = '0' ELSE burst_dmai;
119
120 done <= single_send_ok OR single_send_ko WHEN valid_burst = '0' ELSE
121 burst_send_ok OR burst_send_ko;
122
123 ren <= burst_fifo_ren WHEN valid_burst = '1' ELSE
124 NOT single_send_ok;
125
126 -----------------------------------------------------------------------------
127 -- SEND 1 word by DMA
128 -----------------------------------------------------------------------------
129 lpp_dma_send_1word_1 : lpp_dma_send_1word
130 PORT MAP (
131 HCLK => HCLK,
132 HRESETn => HRESETn,
133 DMAIn => single_dmai,
134 DMAOut => DMAOut,
135
136 send => single_send,
137 address => address,
138 data => data,
139
140 send_ok => single_send_ok, -- TODO
141 send_ko => single_send_ko -- TODO
142 );
143
144 -----------------------------------------------------------------------------
145 -- SEND 16 word by DMA (in burst mode)
146 -----------------------------------------------------------------------------
147 data_2_halfword(31 DOWNTO 0) <= data(15 DOWNTO 0) & data (31 DOWNTO 16);
148
149 lpp_dma_send_16word_1 : lpp_dma_send_16word
150 PORT MAP (
151 HCLK => HCLK,
152 HRESETn => HRESETn,
153 DMAIn => burst_dmai,
154 DMAOut => DMAOut,
155
156 send => burst_send,
157 address => address,
158 data => data_2_halfword,
159 ren => burst_ren,
160
161 send_ok => burst_send_ok,
162 send_ko => burst_send_ko);
163
164 END Behavioral;
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1
2 ------------------------------------------------------------------------------
3 -- This file is a part of the LPP VHDL IP LIBRARY
4 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
5 --
6 -- This program is free software; you can redistribute it and/or modify
7 -- it under the terms of the GNU General Public License as published by
8 -- the Free Software Foundation; either version 3 of the License, or
9 -- (at your option) any later version.
10 --
11 -- This program is distributed in the hope that it will be useful,
12 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
13 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 -- GNU General Public License for more details.
15 --
16 -- You should have received a copy of the GNU General Public License
17 -- along with this program; if not, write to the Free Software
18 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 -------------------------------------------------------------------------------
20 -- Author : Jean-christophe Pellion
21 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
22 -- jean-christophe.pellion@easii-ic.com
23 -------------------------------------------------------------------------------
24 -- 1.0 - initial version
25 -- 1.1 - (01/11/2013) FIX boundary error (1kB address should not be crossed by BURSTS)
26 -------------------------------------------------------------------------------
27 LIBRARY ieee;
28 USE ieee.std_logic_1164.ALL;
29 USE ieee.numeric_std.ALL;
30 LIBRARY grlib;
31 USE grlib.amba.ALL;
32 USE grlib.stdlib.ALL;
33 USE grlib.devices.ALL;
34 USE GRLIB.DMA2AHB_Package.ALL;
35 LIBRARY lpp;
36 USE lpp.lpp_amba.ALL;
37 USE lpp.apb_devices_list.ALL;
38 USE lpp.lpp_memory.ALL;
39 USE lpp.lpp_dma_pkg.ALL;
40 USE lpp.lpp_waveform_pkg.ALL;
41 LIBRARY techmap;
42 USE techmap.gencomp.ALL;
43
44
45 ENTITY lpp_dma_singleOrBurst IS
46 GENERIC (
47 tech : INTEGER := inferred;
48 hindex : INTEGER := 2
49 );
50 PORT (
51 -- AMBA AHB system signals
52 HCLK : IN STD_ULOGIC;
53 HRESETn : IN STD_ULOGIC;
54 --
55 run : IN STD_LOGIC;
56 -- AMBA AHB Master Interface
57 AHB_Master_In : IN AHB_Mst_In_Type;
58 AHB_Master_Out : OUT AHB_Mst_Out_Type;
59 --
60 send : IN STD_LOGIC;
61 valid_burst : IN STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
62 done : OUT STD_LOGIC;
63 ren : OUT STD_LOGIC;
64 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
65 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
66 );
67 END;
68
69 ARCHITECTURE Behavioral OF lpp_dma_singleOrBurst IS
70 -----------------------------------------------------------------------------
71 SIGNAL DMAIn : DMA_In_Type;
72 SIGNAL DMAOut : DMA_OUt_Type;
73 -----------------------------------------------------------------------------
74 -----------------------------------------------------------------------------
75 -- CONTROL
76 SIGNAL single_send : STD_LOGIC;
77 SIGNAL burst_send : STD_LOGIC;
78
79 -----------------------------------------------------------------------------
80 -- SEND SINGLE MODULE
81 SIGNAL single_dmai : DMA_In_Type;
82
83 SIGNAL single_send_ok : STD_LOGIC;
84 SIGNAL single_send_ko : STD_LOGIC;
85 -----------------------------------------------------------------------------
86 -- SEND SINGLE MODULE
87 SIGNAL burst_dmai : DMA_In_Type;
88
89 SIGNAL burst_send_ok : STD_LOGIC;
90 SIGNAL burst_send_ko : STD_LOGIC;
91 SIGNAL burst_ren : STD_LOGIC;
92 -----------------------------------------------------------------------------
93 SIGNAL data_2_halfword : STD_LOGIC_VECTOR(31 DOWNTO 0);
94 BEGIN
95
96 -----------------------------------------------------------------------------
97 -- DMA to AHB interface
98 DMA2AHB_1 : DMA2AHB
99 GENERIC MAP (
100 hindex => hindex,
101 vendorid => VENDOR_LPP,
102 deviceid => 10,
103 version => 0,
104 syncrst => 1,
105 boundary => 1) -- FIX 11/01/2013
106 PORT MAP (
107 HCLK => HCLK,
108 HRESETn => HRESETn,
109 DMAIn => DMAIn,
110 DMAOut => DMAOut,
111
112 AHBIn => AHB_Master_In,
113 AHBOut => AHB_Master_Out);
114 -----------------------------------------------------------------------------
115
116 single_send <= send WHEN valid_burst = '0' ELSE '0';
117 burst_send <= send WHEN valid_burst = '1' ELSE '0';
118 DMAIn <= single_dmai WHEN valid_burst = '0' ELSE burst_dmai;
119
120 done <= single_send_ok OR single_send_ko WHEN valid_burst = '0' ELSE
121 burst_send_ok OR burst_send_ko;
122
123 ren <= burst_ren WHEN valid_burst = '1' ELSE
124 NOT single_send_ok;
125
126 -----------------------------------------------------------------------------
127 -- SEND 1 word by DMA
128 -----------------------------------------------------------------------------
129 lpp_dma_send_1word_1 : lpp_dma_send_1word
130 PORT MAP (
131 HCLK => HCLK,
132 HRESETn => HRESETn,
133 DMAIn => single_dmai,
134 DMAOut => DMAOut,
135
136 send => single_send,
137 address => address,
138 data => data,
139
140 send_ok => single_send_ok, -- TODO
141 send_ko => single_send_ko -- TODO
142 );
143
144 -----------------------------------------------------------------------------
145 -- SEND 16 word by DMA (in burst mode)
146 -----------------------------------------------------------------------------
147 data_2_halfword(31 DOWNTO 0) <= data(15 DOWNTO 0) & data (31 DOWNTO 16);
148
149 lpp_dma_send_16word_1 : lpp_dma_send_16word
150 PORT MAP (
151 HCLK => HCLK,
152 HRESETn => HRESETn,
153 DMAIn => burst_dmai,
154 DMAOut => DMAOut,
155
156 send => burst_send,
157 address => address,
158 data => data_2_halfword,
159 ren => burst_ren,
160
161 send_ok => burst_send_ok,
162 send_ko => burst_send_ko);
163
164 END Behavioral;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
22 -------------------------------------------------------------------------------
23 LIBRARY IEEE;
24 USE IEEE.STD_LOGIC_1164.ALL;
25 USE ieee.numeric_std.ALL;
26
27 LIBRARY grlib;
28 USE grlib.amba.ALL;
29 USE grlib.stdlib.ALL;
30 USE grlib.devices.ALL;
31 USE GRLIB.DMA2AHB_Package.ALL;
32
33 LIBRARY lpp;
34 USE lpp.lpp_waveform_pkg.ALL;
35
36 LIBRARY techmap;
37 USE techmap.gencomp.ALL;
38
39 ENTITY lpp_waveform_genaddress IS
40
41 GENERIC (
42 nb_data_by_buffer_size : INTEGER);
43
44 PORT (
45 clk : IN STD_LOGIC;
46 rstn : IN STD_LOGIC;
47 run : IN STD_LOGIC;
48 -------------------------------------------------------------------------
49 -- CONFIG
50 -------------------------------------------------------------------------
51 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
52 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
53 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
54 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
55 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
56 -------------------------------------------------------------------------
57 -- CTRL
58 -------------------------------------------------------------------------
59 empty : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
60 empty_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
61 data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
62
63 -------------------------------------------------------------------------
64 -- STATUS
65 -------------------------------------------------------------------------
66 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
67 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
68 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
69
70 -------------------------------------------------------------------------
71 -- ADDR DATA OUT
72 -------------------------------------------------------------------------
73 data_f0_data_out_valid_burst : OUT STD_LOGIC;
74 data_f1_data_out_valid_burst : OUT STD_LOGIC;
75 data_f2_data_out_valid_burst : OUT STD_LOGIC;
76 data_f3_data_out_valid_burst : OUT STD_LOGIC;
77
78 data_f0_data_out_valid : OUT STD_LOGIC;
79 data_f1_data_out_valid : OUT STD_LOGIC;
80 data_f2_data_out_valid : OUT STD_LOGIC;
81 data_f3_data_out_valid : OUT STD_LOGIC;
82
83 data_f0_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
84 data_f1_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
85 data_f2_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
86 data_f3_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
87
88 );
89
90 END lpp_waveform_genaddress;
91
92 ARCHITECTURE beh OF lpp_waveform_genaddress IS
93 -----------------------------------------------------------------------------
94 -- Valid gen
95 -----------------------------------------------------------------------------
96 SIGNAL addr_burst_avail : STD_LOGIC_VECTOR(3 DOWNTO 0);
97 SIGNAL data_out_valid : STD_LOGIC_VECTOR(3 DOWNTO 0);
98 SIGNAL data_out_valid_burst : STD_LOGIC_VECTOR(3 DOWNTO 0);
99
100 -----------------------------------------------------------------------------
101 -- Register
102 -----------------------------------------------------------------------------
103 SIGNAL data_addr_v_pre : Data_Vector(3 DOWNTO 0, 31 DOWNTO 0);
104 SIGNAL data_addr_v_reg : Data_Vector(3 DOWNTO 0, 31 DOWNTO 0);
105 SIGNAL data_addr_v_base : Data_Vector(3 DOWNTO 0, 31 DOWNTO 0);
106 SIGNAL data_addr_pre : STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
107 SIGNAL data_addr_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
108 SIGNAL data_addr_base : STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
109
110 -----------------------------------------------------------------------------
111 --
112 -----------------------------------------------------------------------------
113 SIGNAL status_full_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
114
115 TYPE addr_VECTOR IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(31 DOWNTO 0);
116 SIGNAL addr_v_p : addr_VECTOR(3 DOWNTO 0);
117 SIGNAL addr_v_b : addr_VECTOR(3 DOWNTO 0);
118
119 BEGIN -- beh
120
121 -----------------------------------------------------------------------------
122 -- valid gen
123 -----------------------------------------------------------------------------
124 data_f0_data_out_valid <= data_out_valid(0);
125 data_f1_data_out_valid <= data_out_valid(1);
126 data_f2_data_out_valid <= data_out_valid(2);
127 data_f3_data_out_valid <= data_out_valid(3);
128
129 data_f0_data_out_valid_burst <= data_out_valid_burst(0);
130 data_f1_data_out_valid_burst <= data_out_valid_burst(1);
131 data_f2_data_out_valid_burst <= data_out_valid_burst(2);
132 data_f3_data_out_valid_burst <= data_out_valid_burst(3);
133
134
135 all_bit_data_valid_out: FOR I IN 3 DOWNTO 0 GENERATE
136 addr_burst_avail(I) <= '1' WHEN data_addr_v_pre(I,2) = '0' AND
137 data_addr_v_pre(I,3) = '0' AND
138 data_addr_v_pre(I,4) = '0' AND
139 data_addr_v_pre(I,5) = '0' ELSE '0';
140
141 data_out_valid(I) <= '0' WHEN (status_full_s(I) = '1' AND status_full_ack(I) = '0') ELSE
142 '0' WHEN empty(I) = '1' ELSE
143 '0' WHEN addr_burst_avail(I) = '1' ELSE
144 '0' WHEN (run = '0') ELSE
145 '1';
146
147 data_out_valid_burst(I) <= '0' WHEN (status_full_s(I) = '1' AND status_full_ack(I) = '0') ELSE
148 '0' WHEN empty(I) = '1' ELSE
149 '0' WHEN addr_burst_avail(I) = '0' ELSE
150 '0' WHEN empty_almost(I) = '1' ELSE
151 '0' WHEN (run = '0') ELSE
152 '1';
153 END GENERATE all_bit_data_valid_out;
154
155 -----------------------------------------------------------------------------
156 -- Register
157 -----------------------------------------------------------------------------
158 all_data_bit: FOR J IN 31 DOWNTO 0 GENERATE
159 all_data_addr: FOR I IN 3 DOWNTO 0 GENERATE
160 PROCESS (clk, rstn)
161 BEGIN -- PROCESS
162 IF rstn = '0' THEN -- asynchronous reset (active low)
163 data_addr_v_reg(I,J) <= '0';
164 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
165 IF run = '1' AND status_full_ack(I) = '0' THEN
166 data_addr_v_reg(I,J) <= data_addr_v_pre(I,J);
167 ELSE
168 data_addr_v_reg(I,J) <= data_addr_v_base(I,J);
169 END IF;
170 END IF;
171 END PROCESS;
172
173 data_addr_v_pre(I,J) <= data_addr_v_reg(I,J) WHEN data_ren(I) = '1' ELSE data_addr_pre(J);
174
175 END GENERATE all_data_addr;
176
177 data_addr_reg(J) <= data_addr_v_reg(0,J) WHEN data_ren(0) = '1' ELSE
178 data_addr_v_reg(1,J) WHEN data_ren(1) = '1' ELSE
179 data_addr_v_reg(2,J) WHEN data_ren(2) = '1' ELSE
180 data_addr_v_reg(3,J);
181
182 data_addr_v_base(0,J) <= addr_data_f0(J);
183 data_addr_v_base(1,J) <= addr_data_f1(J);
184 data_addr_v_base(2,J) <= addr_data_f2(J);
185 data_addr_v_base(3,J) <= addr_data_f3(J);
186
187 data_f0_addr_out(J) <= data_addr_v_reg(0,J);
188 data_f1_addr_out(J) <= data_addr_v_reg(1,J);
189 data_f2_addr_out(J) <= data_addr_v_reg(2,J);
190 data_f3_addr_out(J) <= data_addr_v_reg(3,J);
191
192 END GENERATE all_data_bit;
193
194
195
196
197 -----------------------------------------------------------------------------
198 -- ADDER
199 -----------------------------------------------------------------------------
200
201 data_addr_pre <= data_addr_reg + 1;
202
203 -----------------------------------------------------------------------------
204 -- FULL STATUS
205 -----------------------------------------------------------------------------
206 all_status: FOR I IN 3 DOWNTO 0 GENERATE
207 all_bit_addr: FOR J IN 31 DOWNTO 0 GENERATE
208 addr_v_p(I)(J) <= data_addr_v_pre(I,J);
209 addr_v_b(I)(J) <= data_addr_v_base(I,J);
210 END GENERATE all_bit_addr;
211
212 PROCESS (clk, rstn)
213 BEGIN -- PROCESS
214 IF rstn = '0' THEN -- asynchronous reset (active low)
215 status_full_s(I) <= '0';
216 status_full_err(I) <= '0';
217 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
218 IF run = '1' AND status_full_ack(I) = '0' THEN
219 IF addr_v_p(I) = addr_v_b(I) + nb_data_by_buffer THEN
220 status_full_s(I) <= '1';
221 IF status_full_s(I) = '1' AND data_ren(I)= '1' THEN
222 status_full_err(I) <= '1';
223 END IF;
224 END IF;
225 ELSE
226 status_full_s(I) <= '0';
227 status_full_err(I) <= '0';
228 END IF;
229 END IF;
230 END PROCESS;
231
232 END GENERATE all_status;
233
234 status_full <= status_full_s;
235
236
237 END beh;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
22 -------------------------------------------------------------------------------
23 LIBRARY IEEE;
24 USE IEEE.STD_LOGIC_1164.ALL;
25 USE ieee.numeric_std.ALL;
26
27 LIBRARY grlib;
28 USE grlib.amba.ALL;
29 USE grlib.stdlib.ALL;
30 USE grlib.devices.ALL;
31 USE GRLIB.DMA2AHB_Package.ALL;
32
33 LIBRARY lpp;
34 USE lpp.lpp_waveform_pkg.ALL;
35
36 LIBRARY techmap;
37 USE techmap.gencomp.ALL;
38
39 ENTITY lpp_waveform_genaddress_single IS
40
41 GENERIC (
42 nb_burst_available_size : INTEGER);
43
44 PORT (
45 clk : IN STD_LOGIC;
46 rstn : IN STD_LOGIC;
47 run : IN STD_LOGIC;
48 -------------------------------------------------------------------------
49 -- CONFIG
50 -------------------------------------------------------------------------
51 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
52 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
53 -------------------------------------------------------------------------
54 -- CTRL
55 -------------------------------------------------------------------------
56 empty : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
57 empty_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
58 data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
59 --burst : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
60
61 -------------------------------------------------------------------------
62 -- STATUS
63 -------------------------------------------------------------------------
64 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
65 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
66 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
67
68 -------------------------------------------------------------------------
69 -- ADDR DATA OUT
70 -------------------------------------------------------------------------
71 data_f0_data_out_valid_burst : OUT STD_LOGIC;
72 data_f1_data_out_valid_burst : OUT STD_LOGIC;
73 data_f2_data_out_valid_burst : OUT STD_LOGIC;
74 data_f3_data_out_valid_burst : OUT STD_LOGIC;
75
76 data_f0_data_out_valid : OUT STD_LOGIC;
77 data_f1_data_out_valid : OUT STD_LOGIC;
78 data_f2_data_out_valid : OUT STD_LOGIC;
79 data_f3_data_out_valid : OUT STD_LOGIC;
80
81 data_f0_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
82 data_f1_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
83 data_f2_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
84 data_f3_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
85
86 );
87
88 END lpp_waveform_genaddress_single;
89
90 ARCHITECTURE beh OF lpp_waveform_genaddress_single IS
91
92 BEGIN -- beh
93
94
95
96
97 END beh;
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@@ -1,358 +1,374
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
21 ----------------------------------------------------------------------------
22 --UPDATE
22 --UPDATE
23 -------------------------------------------------------------------------------
23 -------------------------------------------------------------------------------
24 -- 14-03-2013 - Jean-christophe Pellion
24 -- 14-03-2013 - Jean-christophe Pellion
25 -- ADD MUXN (a parametric multiplexor (N stage of MUX2))
25 -- ADD MUXN (a parametric multiplexor (N stage of MUX2))
26 -------------------------------------------------------------------------------
26 -------------------------------------------------------------------------------
27
27
28 LIBRARY ieee;
28 LIBRARY ieee;
29 USE ieee.std_logic_1164.ALL;
29 USE ieee.std_logic_1164.ALL;
30
30
31
31
32
32
33 PACKAGE general_purpose IS
33 PACKAGE general_purpose IS
34
34
35
35
36
36
37 COMPONENT Clk_divider IS
37 COMPONENT Clk_divider IS
38 GENERIC(OSC_freqHz : INTEGER := 50000000;
38 GENERIC(OSC_freqHz : INTEGER := 50000000;
39 TargetFreq_Hz : INTEGER := 50000);
39 TargetFreq_Hz : INTEGER := 50000);
40 PORT (clk : IN STD_LOGIC;
40 PORT (clk : IN STD_LOGIC;
41 reset : IN STD_LOGIC;
41 reset : IN STD_LOGIC;
42 clk_divided : OUT STD_LOGIC);
42 clk_divided : OUT STD_LOGIC);
43 END COMPONENT;
43 END COMPONENT;
44
44
45
45
46 COMPONENT Clk_divider2 IS
46 COMPONENT Clk_divider2 IS
47 generic(N : integer := 16);
47 generic(N : integer := 16);
48 port(
48 port(
49 clk_in : in std_logic;
49 clk_in : in std_logic;
50 clk_out : out std_logic);
50 clk_out : out std_logic);
51 END COMPONENT;
51 END COMPONENT;
52
52
53 COMPONENT Adder IS
53 COMPONENT Adder IS
54 GENERIC(
54 GENERIC(
55 Input_SZ_A : INTEGER := 16;
55 Input_SZ_A : INTEGER := 16;
56 Input_SZ_B : INTEGER := 16
56 Input_SZ_B : INTEGER := 16
57
57
58 );
58 );
59 PORT(
59 PORT(
60 clk : IN STD_LOGIC;
60 clk : IN STD_LOGIC;
61 reset : IN STD_LOGIC;
61 reset : IN STD_LOGIC;
62 clr : IN STD_LOGIC;
62 clr : IN STD_LOGIC;
63 load : IN STD_LOGIC;
63 load : IN STD_LOGIC;
64 add : IN STD_LOGIC;
64 add : IN STD_LOGIC;
65 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
65 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
66 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
66 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
67 RES : OUT STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0)
67 RES : OUT STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0)
68 );
68 );
69 END COMPONENT;
69 END COMPONENT;
70
70
71 COMPONENT Adder_V0 is
71 COMPONENT Adder_V0 is
72 generic(
72 generic(
73 Input_SZ_A : integer := 16;
73 Input_SZ_A : integer := 16;
74 Input_SZ_B : integer := 16
74 Input_SZ_B : integer := 16
75
75
76 );
76 );
77 port(
77 port(
78 clk : in std_logic;
78 clk : in std_logic;
79 reset : in std_logic;
79 reset : in std_logic;
80 clr : in std_logic;
80 clr : in std_logic;
81 add : in std_logic;
81 add : in std_logic;
82 OP1 : in std_logic_vector(Input_SZ_A-1 downto 0);
82 OP1 : in std_logic_vector(Input_SZ_A-1 downto 0);
83 OP2 : in std_logic_vector(Input_SZ_B-1 downto 0);
83 OP2 : in std_logic_vector(Input_SZ_B-1 downto 0);
84 RES : out std_logic_vector(Input_SZ_A-1 downto 0)
84 RES : out std_logic_vector(Input_SZ_A-1 downto 0)
85 );
85 );
86 end COMPONENT;
86 end COMPONENT;
87
87
88 COMPONENT ADDRcntr IS
88 COMPONENT ADDRcntr IS
89 PORT(
89 PORT(
90 clk : IN STD_LOGIC;
90 clk : IN STD_LOGIC;
91 reset : IN STD_LOGIC;
91 reset : IN STD_LOGIC;
92 count : IN STD_LOGIC;
92 count : IN STD_LOGIC;
93 clr : IN STD_LOGIC;
93 clr : IN STD_LOGIC;
94 Q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
94 Q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
95 );
95 );
96 END COMPONENT;
96 END COMPONENT;
97
97
98 COMPONENT ALU IS
98 COMPONENT ALU IS
99 GENERIC(
99 GENERIC(
100 Arith_en : INTEGER := 1;
100 Arith_en : INTEGER := 1;
101 Logic_en : INTEGER := 1;
101 Logic_en : INTEGER := 1;
102 Input_SZ_1 : INTEGER := 16;
102 Input_SZ_1 : INTEGER := 16;
103 Input_SZ_2 : INTEGER := 9;
103 Input_SZ_2 : INTEGER := 9;
104 COMP_EN : INTEGER := 0 -- 1 => No Comp
104 COMP_EN : INTEGER := 0 -- 1 => No Comp
105
105
106 );
106 );
107 PORT(
107 PORT(
108 clk : IN STD_LOGIC;
108 clk : IN STD_LOGIC;
109 reset : IN STD_LOGIC;
109 reset : IN STD_LOGIC;
110 ctrl : IN STD_LOGIC_VECTOR(2 downto 0);
110 ctrl : IN STD_LOGIC_VECTOR(2 downto 0);
111 comp : IN STD_LOGIC_VECTOR(1 downto 0);
111 comp : IN STD_LOGIC_VECTOR(1 downto 0);
112 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
112 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
113 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_2-1 DOWNTO 0);
113 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_2-1 DOWNTO 0);
114 RES : OUT STD_LOGIC_VECTOR(Input_SZ_1+Input_SZ_2-1 DOWNTO 0)
114 RES : OUT STD_LOGIC_VECTOR(Input_SZ_1+Input_SZ_2-1 DOWNTO 0)
115 );
115 );
116 END COMPONENT;
116 END COMPONENT;
117
117
118 COMPONENT ALU_V0 IS
118 COMPONENT ALU_V0 IS
119 GENERIC(
119 GENERIC(
120 Arith_en : INTEGER := 1;
120 Arith_en : INTEGER := 1;
121 Logic_en : INTEGER := 1;
121 Logic_en : INTEGER := 1;
122 Input_SZ_1 : INTEGER := 16;
122 Input_SZ_1 : INTEGER := 16;
123 Input_SZ_2 : INTEGER := 9
123 Input_SZ_2 : INTEGER := 9
124
124
125 );
125 );
126 PORT(
126 PORT(
127 clk : IN STD_LOGIC;
127 clk : IN STD_LOGIC;
128 reset : IN STD_LOGIC;
128 reset : IN STD_LOGIC;
129 ctrl : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
129 ctrl : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
130 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
130 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
131 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_2-1 DOWNTO 0);
131 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_2-1 DOWNTO 0);
132 RES : OUT STD_LOGIC_VECTOR(Input_SZ_1+Input_SZ_2-1 DOWNTO 0)
132 RES : OUT STD_LOGIC_VECTOR(Input_SZ_1+Input_SZ_2-1 DOWNTO 0)
133 );
133 );
134 END COMPONENT;
134 END COMPONENT;
135
135
136 COMPONENT MAC_V0 is
136 COMPONENT MAC_V0 is
137 generic(
137 generic(
138 Input_SZ_A : integer := 8;
138 Input_SZ_A : integer := 8;
139 Input_SZ_B : integer := 8
139 Input_SZ_B : integer := 8
140
140
141 );
141 );
142 port(
142 port(
143 clk : in std_logic;
143 clk : in std_logic;
144 reset : in std_logic;
144 reset : in std_logic;
145 clr_MAC : in std_logic;
145 clr_MAC : in std_logic;
146 MAC_MUL_ADD : in std_logic_vector(1 downto 0);
146 MAC_MUL_ADD : in std_logic_vector(1 downto 0);
147 OP1 : in std_logic_vector(Input_SZ_A-1 downto 0);
147 OP1 : in std_logic_vector(Input_SZ_A-1 downto 0);
148 OP2 : in std_logic_vector(Input_SZ_B-1 downto 0);
148 OP2 : in std_logic_vector(Input_SZ_B-1 downto 0);
149 RES : out std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0)
149 RES : out std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0)
150 );
150 );
151 end COMPONENT;
151 end COMPONENT;
152
152
153 ---------------------------------------------------------
153 ---------------------------------------------------------
154 -------- // Sélection grace a l'entrée "ctrl" \\ --------
154 -------- // Sélection grace a l'entrée "ctrl" \\ --------
155 ---------------------------------------------------------
155 ---------------------------------------------------------
156 Constant ctrl_IDLE : std_logic_vector(2 downto 0) := "000";
156 Constant ctrl_IDLE : std_logic_vector(2 downto 0) := "000";
157 Constant ctrl_MAC : std_logic_vector(2 downto 0) := "001";
157 Constant ctrl_MAC : std_logic_vector(2 downto 0) := "001";
158 Constant ctrl_MULT : std_logic_vector(2 downto 0) := "010";
158 Constant ctrl_MULT : std_logic_vector(2 downto 0) := "010";
159 Constant ctrl_ADD : std_logic_vector(2 downto 0) := "011";
159 Constant ctrl_ADD : std_logic_vector(2 downto 0) := "011";
160 Constant ctrl_CLRMAC : std_logic_vector(2 downto 0) := "100";
160 Constant ctrl_CLRMAC : std_logic_vector(2 downto 0) := "100";
161
161
162
162
163 Constant IDLE_V0 : std_logic_vector(3 downto 0) := "0000";
163 Constant IDLE_V0 : std_logic_vector(3 downto 0) := "0000";
164 Constant MAC_op_V0 : std_logic_vector(3 downto 0) := "0001";
164 Constant MAC_op_V0 : std_logic_vector(3 downto 0) := "0001";
165 Constant MULT_V0 : std_logic_vector(3 downto 0) := "0010";
165 Constant MULT_V0 : std_logic_vector(3 downto 0) := "0010";
166 Constant ADD_V0 : std_logic_vector(3 downto 0) := "0011";
166 Constant ADD_V0 : std_logic_vector(3 downto 0) := "0011";
167 Constant CLR_MAC_V0 : std_logic_vector(3 downto 0) := "0100";
167 Constant CLR_MAC_V0 : std_logic_vector(3 downto 0) := "0100";
168 ---------------------------------------------------------
168 ---------------------------------------------------------
169
169
170 COMPONENT MAC IS
170 COMPONENT MAC IS
171 GENERIC(
171 GENERIC(
172 Input_SZ_A : INTEGER := 8;
172 Input_SZ_A : INTEGER := 8;
173 Input_SZ_B : INTEGER := 8;
173 Input_SZ_B : INTEGER := 8;
174 COMP_EN : INTEGER := 0 -- 1 => No Comp
174 COMP_EN : INTEGER := 0 -- 1 => No Comp
175 );
175 );
176 PORT(
176 PORT(
177 clk : IN STD_LOGIC;
177 clk : IN STD_LOGIC;
178 reset : IN STD_LOGIC;
178 reset : IN STD_LOGIC;
179 clr_MAC : IN STD_LOGIC;
179 clr_MAC : IN STD_LOGIC;
180 MAC_MUL_ADD : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
180 MAC_MUL_ADD : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
181 Comp_2C : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
181 Comp_2C : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
182 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
182 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
183 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
183 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
184 RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0)
184 RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0)
185 );
185 );
186 END COMPONENT;
186 END COMPONENT;
187
187
188 COMPONENT TwoComplementer is
188 COMPONENT TwoComplementer is
189 generic(
189 generic(
190 Input_SZ : integer := 16);
190 Input_SZ : integer := 16);
191 port(
191 port(
192 clk : in std_logic; --! Horloge du composant
192 clk : in std_logic; --! Horloge du composant
193 reset : in std_logic; --! Reset general du composant
193 reset : in std_logic; --! Reset general du composant
194 clr : in std_logic; --! Un reset spécifique au programme
194 clr : in std_logic; --! Un reset spécifique au programme
195 TwoComp : in std_logic; --! Autorise l'utilisation du complément
195 TwoComp : in std_logic; --! Autorise l'utilisation du complément
196 OP : in std_logic_vector(Input_SZ-1 downto 0); --! Opérande d'entrée
196 OP : in std_logic_vector(Input_SZ-1 downto 0); --! Opérande d'entrée
197 RES : out std_logic_vector(Input_SZ-1 downto 0) --! Résultat, opérande complémenté ou non
197 RES : out std_logic_vector(Input_SZ-1 downto 0) --! Résultat, opérande complémenté ou non
198 );
198 );
199 end COMPONENT;
199 end COMPONENT;
200
200
201 COMPONENT MAC_CONTROLER IS
201 COMPONENT MAC_CONTROLER IS
202 PORT(
202 PORT(
203 ctrl : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
203 ctrl : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
204 MULT : OUT STD_LOGIC;
204 MULT : OUT STD_LOGIC;
205 ADD : OUT STD_LOGIC;
205 ADD : OUT STD_LOGIC;
206 LOAD_ADDER : out std_logic;
206 LOAD_ADDER : out std_logic;
207 MACMUX_sel : OUT STD_LOGIC;
207 MACMUX_sel : OUT STD_LOGIC;
208 MACMUX2_sel : OUT STD_LOGIC
208 MACMUX2_sel : OUT STD_LOGIC
209 );
209 );
210 END COMPONENT;
210 END COMPONENT;
211
211
212 COMPONENT MAC_MUX IS
212 COMPONENT MAC_MUX IS
213 GENERIC(
213 GENERIC(
214 Input_SZ_A : INTEGER := 16;
214 Input_SZ_A : INTEGER := 16;
215 Input_SZ_B : INTEGER := 16
215 Input_SZ_B : INTEGER := 16
216
216
217 );
217 );
218 PORT(
218 PORT(
219 sel : IN STD_LOGIC;
219 sel : IN STD_LOGIC;
220 INA1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
220 INA1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
221 INA2 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
221 INA2 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
222 INB1 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
222 INB1 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
223 INB2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
223 INB2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
224 OUTA : OUT STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
224 OUTA : OUT STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
225 OUTB : OUT STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0)
225 OUTB : OUT STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0)
226 );
226 );
227 END COMPONENT;
227 END COMPONENT;
228
228
229
229
230 COMPONENT MAC_MUX2 IS
230 COMPONENT MAC_MUX2 IS
231 GENERIC(Input_SZ : INTEGER := 16);
231 GENERIC(Input_SZ : INTEGER := 16);
232 PORT(
232 PORT(
233 sel : IN STD_LOGIC;
233 sel : IN STD_LOGIC;
234 RES1 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
234 RES1 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
235 RES2 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
235 RES2 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
236 RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0)
236 RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0)
237 );
237 );
238 END COMPONENT;
238 END COMPONENT;
239
239
240
240
241 COMPONENT MAC_REG IS
241 COMPONENT MAC_REG IS
242 GENERIC(size : INTEGER := 16);
242 GENERIC(size : INTEGER := 16);
243 PORT(
243 PORT(
244 reset : IN STD_LOGIC;
244 reset : IN STD_LOGIC;
245 clk : IN STD_LOGIC;
245 clk : IN STD_LOGIC;
246 D : IN STD_LOGIC_VECTOR(size-1 DOWNTO 0);
246 D : IN STD_LOGIC_VECTOR(size-1 DOWNTO 0);
247 Q : OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0)
247 Q : OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0)
248 );
248 );
249 END COMPONENT;
249 END COMPONENT;
250
250
251
251
252 COMPONENT MUX2 IS
252 COMPONENT MUX2 IS
253 GENERIC(Input_SZ : INTEGER := 16);
253 GENERIC(Input_SZ : INTEGER := 16);
254 PORT(
254 PORT(
255 sel : IN STD_LOGIC;
255 sel : IN STD_LOGIC;
256 IN1 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
256 IN1 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
257 IN2 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
257 IN2 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
258 RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0)
258 RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0)
259 );
259 );
260 END COMPONENT;
260 END COMPONENT;
261
261
262 TYPE MUX_INPUT_TYPE IS ARRAY (NATURAL RANGE <>, NATURAL RANGE <>) OF STD_LOGIC;
262 TYPE MUX_INPUT_TYPE IS ARRAY (NATURAL RANGE <>, NATURAL RANGE <>) OF STD_LOGIC;
263 TYPE MUX_OUTPUT_TYPE IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC;
263 TYPE MUX_OUTPUT_TYPE IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC;
264
264
265 COMPONENT MUXN
265 COMPONENT MUXN
266 GENERIC (
266 GENERIC (
267 Input_SZ : INTEGER;
267 Input_SZ : INTEGER;
268 NbStage : INTEGER);
268 NbStage : INTEGER);
269 PORT (
269 PORT (
270 sel : IN STD_LOGIC_VECTOR(NbStage-1 DOWNTO 0);
270 sel : IN STD_LOGIC_VECTOR(NbStage-1 DOWNTO 0);
271 INPUT : IN MUX_INPUT_TYPE(0 TO (2**NbStage)-1,Input_SZ-1 DOWNTO 0);
271 INPUT : IN MUX_INPUT_TYPE(0 TO (2**NbStage)-1,Input_SZ-1 DOWNTO 0);
272 --INPUT : IN ARRAY (0 TO (2**NbStage)-1) OF STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
272 --INPUT : IN ARRAY (0 TO (2**NbStage)-1) OF STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
273 RES : OUT MUX_OUTPUT_TYPE(Input_SZ-1 DOWNTO 0));
273 RES : OUT MUX_OUTPUT_TYPE(Input_SZ-1 DOWNTO 0));
274 END COMPONENT;
274 END COMPONENT;
275
275
276
276
277
277
278 COMPONENT Multiplier IS
278 COMPONENT Multiplier IS
279 GENERIC(
279 GENERIC(
280 Input_SZ_A : INTEGER := 16;
280 Input_SZ_A : INTEGER := 16;
281 Input_SZ_B : INTEGER := 16
281 Input_SZ_B : INTEGER := 16
282
282
283 );
283 );
284 PORT(
284 PORT(
285 clk : IN STD_LOGIC;
285 clk : IN STD_LOGIC;
286 reset : IN STD_LOGIC;
286 reset : IN STD_LOGIC;
287 mult : IN STD_LOGIC;
287 mult : IN STD_LOGIC;
288 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
288 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
289 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
289 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
290 RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0)
290 RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0)
291 );
291 );
292 END COMPONENT;
292 END COMPONENT;
293
293
294 COMPONENT REG IS
294 COMPONENT REG IS
295 GENERIC(size : INTEGER := 16; initial_VALUE : INTEGER := 0);
295 GENERIC(size : INTEGER := 16; initial_VALUE : INTEGER := 0);
296 PORT(
296 PORT(
297 reset : IN STD_LOGIC;
297 reset : IN STD_LOGIC;
298 clk : IN STD_LOGIC;
298 clk : IN STD_LOGIC;
299 D : IN STD_LOGIC_VECTOR(size-1 DOWNTO 0);
299 D : IN STD_LOGIC_VECTOR(size-1 DOWNTO 0);
300 Q : OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0)
300 Q : OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0)
301 );
301 );
302 END COMPONENT;
302 END COMPONENT;
303
303
304
304
305
305
306 COMPONENT RShifter IS
306 COMPONENT RShifter IS
307 GENERIC(
307 GENERIC(
308 Input_SZ : INTEGER := 16;
308 Input_SZ : INTEGER := 16;
309 shift_SZ : INTEGER := 4
309 shift_SZ : INTEGER := 4
310 );
310 );
311 PORT(
311 PORT(
312 clk : IN STD_LOGIC;
312 clk : IN STD_LOGIC;
313 reset : IN STD_LOGIC;
313 reset : IN STD_LOGIC;
314 shift : IN STD_LOGIC;
314 shift : IN STD_LOGIC;
315 OP : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
315 OP : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
316 cnt : IN STD_LOGIC_VECTOR(shift_SZ-1 DOWNTO 0);
316 cnt : IN STD_LOGIC_VECTOR(shift_SZ-1 DOWNTO 0);
317 RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0)
317 RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0)
318 );
318 );
319 END COMPONENT;
319 END COMPONENT;
320
320
321 COMPONENT SYNC_FF
321 COMPONENT SYNC_FF
322 GENERIC (
322 GENERIC (
323 NB_FF_OF_SYNC : INTEGER);
323 NB_FF_OF_SYNC : INTEGER);
324 PORT (
324 PORT (
325 clk : IN STD_LOGIC;
325 clk : IN STD_LOGIC;
326 rstn : IN STD_LOGIC;
326 rstn : IN STD_LOGIC;
327 A : IN STD_LOGIC;
327 A : IN STD_LOGIC;
328 A_sync : OUT STD_LOGIC);
328 A_sync : OUT STD_LOGIC);
329 END COMPONENT;
329 END COMPONENT;
330
330
331 COMPONENT lpp_front_to_level
331 COMPONENT lpp_front_to_level
332 PORT (
332 PORT (
333 clk : IN STD_LOGIC;
333 clk : IN STD_LOGIC;
334 rstn : IN STD_LOGIC;
334 rstn : IN STD_LOGIC;
335 sin : IN STD_LOGIC;
335 sin : IN STD_LOGIC;
336 sout : OUT STD_LOGIC);
336 sout : OUT STD_LOGIC);
337 END COMPONENT;
337 END COMPONENT;
338
338
339 COMPONENT lpp_front_detection
339 COMPONENT lpp_front_detection
340 PORT (
340 PORT (
341 clk : IN STD_LOGIC;
341 clk : IN STD_LOGIC;
342 rstn : IN STD_LOGIC;
342 rstn : IN STD_LOGIC;
343 sin : IN STD_LOGIC;
343 sin : IN STD_LOGIC;
344 sout : OUT STD_LOGIC);
344 sout : OUT STD_LOGIC);
345 END COMPONENT;
345 END COMPONENT;
346
346
347 COMPONENT lpp_front_positive_detection
348 PORT (
349 clk : IN STD_LOGIC;
350 rstn : IN STD_LOGIC;
351 sin : IN STD_LOGIC;
352 sout : OUT STD_LOGIC);
353 END COMPONENT;
354
347 COMPONENT SYNC_VALID_BIT
355 COMPONENT SYNC_VALID_BIT
348 GENERIC (
356 GENERIC (
349 NB_FF_OF_SYNC : INTEGER);
357 NB_FF_OF_SYNC : INTEGER);
350 PORT (
358 PORT (
351 clk_in : IN STD_LOGIC;
359 clk_in : IN STD_LOGIC;
352 clk_out : IN STD_LOGIC;
360 clk_out : IN STD_LOGIC;
353 rstn : IN STD_LOGIC;
361 rstn : IN STD_LOGIC;
354 sin : IN STD_LOGIC;
362 sin : IN STD_LOGIC;
355 sout : OUT STD_LOGIC);
363 sout : OUT STD_LOGIC);
356 END COMPONENT;
364 END COMPONENT;
357
365
366 COMPONENT RR_Arbiter_4
367 PORT (
368 clk : IN STD_LOGIC;
369 rstn : IN STD_LOGIC;
370 in_valid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
371 out_grant : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
372 END COMPONENT;
373
358 END;
374 END;
Show file before | Show file after | Hide comments
@@ -1,21 +1,23
1 general_purpose.vhd
1 general_purpose.vhd
2 ADDRcntr.vhd
2 ADDRcntr.vhd
3 ALU.vhd
3 ALU.vhd
4 Adder.vhd
4 Adder.vhd
5 Clk_Divider2.vhd
5 Clk_Divider2.vhd
6 Clk_divider.vhd
6 Clk_divider.vhd
7 MAC.vhd
7 MAC.vhd
8 MAC_CONTROLER.vhd
8 MAC_CONTROLER.vhd
9 MAC_MUX.vhd
9 MAC_MUX.vhd
10 MAC_MUX2.vhd
10 MAC_MUX2.vhd
11 MAC_REG.vhd
11 MAC_REG.vhd
12 MUX2.vhd
12 MUX2.vhd
13 MUXN.vhd
13 MUXN.vhd
14 Multiplier.vhd
14 Multiplier.vhd
15 REG.vhd
15 REG.vhd
16 SYNC_FF.vhd
16 SYNC_FF.vhd
17 Shifter.vhd
17 Shifter.vhd
18 TwoComplementer.vhd
18 TwoComplementer.vhd
19 lpp_front_to_level.vhd
19 lpp_front_to_level.vhd
20 lpp_front_detection.vhd
20 lpp_front_detection.vhd
21 lpp_front_positive_detection.vhd
21 SYNC_VALID_BIT.vhd
22 SYNC_VALID_BIT.vhd
23 RR_Arbiter_4.vhd
Show file before | Show file after | Hide comments
@@ -1,200 +1,218
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
22 ----------------------------------------------------------------------------
23 LIBRARY ieee;
23 LIBRARY ieee;
24 USE ieee.std_logic_1164.ALL;
24 USE ieee.std_logic_1164.ALL;
25 LIBRARY grlib;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
26 USE grlib.amba.ALL;
27 USE std.textio.ALL;
27 USE std.textio.ALL;
28 LIBRARY grlib;
28 LIBRARY grlib;
29 USE grlib.amba.ALL;
29 USE grlib.amba.ALL;
30 USE grlib.stdlib.ALL;
30 USE grlib.stdlib.ALL;
31 USE GRLIB.DMA2AHB_Package.ALL;
31 USE GRLIB.DMA2AHB_Package.ALL;
32 LIBRARY techmap;
32 LIBRARY techmap;
33 USE techmap.gencomp.ALL;
33 USE techmap.gencomp.ALL;
34 LIBRARY lpp;
34 LIBRARY lpp;
35 USE lpp.lpp_amba.ALL;
35 USE lpp.lpp_amba.ALL;
36 USE lpp.apb_devices_list.ALL;
36 USE lpp.apb_devices_list.ALL;
37 USE lpp.lpp_memory.ALL;
37 USE lpp.lpp_memory.ALL;
38
38
39 PACKAGE lpp_dma_pkg IS
39 PACKAGE lpp_dma_pkg IS
40
40
41 COMPONENT lpp_dma
41 COMPONENT lpp_dma
42 GENERIC (
42 GENERIC (
43 tech : INTEGER;
43 tech : INTEGER;
44 hindex : INTEGER;
44 hindex : INTEGER;
45 pindex : INTEGER;
45 pindex : INTEGER;
46 paddr : INTEGER;
46 paddr : INTEGER;
47 pmask : INTEGER;
47 pmask : INTEGER;
48 pirq : INTEGER);
48 pirq : INTEGER);
49 PORT (
49 PORT (
50 HCLK : IN STD_ULOGIC;
50 HCLK : IN STD_ULOGIC;
51 HRESETn : IN STD_ULOGIC;
51 HRESETn : IN STD_ULOGIC;
52 apbi : IN apb_slv_in_type;
52 apbi : IN apb_slv_in_type;
53 apbo : OUT apb_slv_out_type;
53 apbo : OUT apb_slv_out_type;
54 AHB_Master_In : IN AHB_Mst_In_Type;
54 AHB_Master_In : IN AHB_Mst_In_Type;
55 AHB_Master_Out : OUT AHB_Mst_Out_Type;
55 AHB_Master_Out : OUT AHB_Mst_Out_Type;
56 -- fifo interface
56 -- fifo interface
57 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
57 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
58 fifo_empty : IN STD_LOGIC;
58 fifo_empty : IN STD_LOGIC;
59 fifo_ren : OUT STD_LOGIC;
59 fifo_ren : OUT STD_LOGIC;
60 -- header
60 -- header
61 header : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
61 header : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
62 header_val : IN STD_LOGIC;
62 header_val : IN STD_LOGIC;
63 header_ack : OUT STD_LOGIC);
63 header_ack : OUT STD_LOGIC);
64 END COMPONENT;
64 END COMPONENT;
65
65
66 COMPONENT fifo_test_dma
66 COMPONENT fifo_test_dma
67 GENERIC (
67 GENERIC (
68 tech : INTEGER;
68 tech : INTEGER;
69 pindex : INTEGER;
69 pindex : INTEGER;
70 paddr : INTEGER;
70 paddr : INTEGER;
71 pmask : INTEGER);
71 pmask : INTEGER);
72 PORT (
72 PORT (
73 HCLK : IN STD_ULOGIC;
73 HCLK : IN STD_ULOGIC;
74 HRESETn : IN STD_ULOGIC;
74 HRESETn : IN STD_ULOGIC;
75 apbi : IN apb_slv_in_type;
75 apbi : IN apb_slv_in_type;
76 apbo : OUT apb_slv_out_type;
76 apbo : OUT apb_slv_out_type;
77 -- fifo interface
77 -- fifo interface
78 fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
78 fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
79 fifo_empty : OUT STD_LOGIC;
79 fifo_empty : OUT STD_LOGIC;
80 fifo_ren : IN STD_LOGIC;
80 fifo_ren : IN STD_LOGIC;
81 -- header
81 -- header
82 header : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
82 header : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
83 header_val : OUT STD_LOGIC;
83 header_val : OUT STD_LOGIC;
84 header_ack : IN STD_LOGIC
84 header_ack : IN STD_LOGIC
85 );
85 );
86 END COMPONENT;
86 END COMPONENT;
87
87
88 COMPONENT lpp_dma_apbreg
88 COMPONENT lpp_dma_apbreg
89 GENERIC (
89 GENERIC (
90 pindex : INTEGER;
90 pindex : INTEGER;
91 paddr : INTEGER;
91 paddr : INTEGER;
92 pmask : INTEGER;
92 pmask : INTEGER;
93 pirq : INTEGER);
93 pirq : INTEGER);
94 PORT (
94 PORT (
95 HCLK : IN STD_ULOGIC;
95 HCLK : IN STD_ULOGIC;
96 HRESETn : IN STD_ULOGIC;
96 HRESETn : IN STD_ULOGIC;
97 apbi : IN apb_slv_in_type;
97 apbi : IN apb_slv_in_type;
98 apbo : OUT apb_slv_out_type;
98 apbo : OUT apb_slv_out_type;
99 -- IN
99 -- IN
100 ready_matrix_f0_0 : IN STD_LOGIC;
100 ready_matrix_f0_0 : IN STD_LOGIC;
101 ready_matrix_f0_1 : IN STD_LOGIC;
101 ready_matrix_f0_1 : IN STD_LOGIC;
102 ready_matrix_f1 : IN STD_LOGIC;
102 ready_matrix_f1 : IN STD_LOGIC;
103 ready_matrix_f2 : IN STD_LOGIC;
103 ready_matrix_f2 : IN STD_LOGIC;
104 error_anticipating_empty_fifo : IN STD_LOGIC;
104 error_anticipating_empty_fifo : IN STD_LOGIC;
105 error_bad_component_error : IN STD_LOGIC;
105 error_bad_component_error : IN STD_LOGIC;
106 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
106 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
107
107
108 -- OUT
108 -- OUT
109 status_ready_matrix_f0_0 : OUT STD_LOGIC;
109 status_ready_matrix_f0_0 : OUT STD_LOGIC;
110 status_ready_matrix_f0_1 : OUT STD_LOGIC;
110 status_ready_matrix_f0_1 : OUT STD_LOGIC;
111 status_ready_matrix_f1 : OUT STD_LOGIC;
111 status_ready_matrix_f1 : OUT STD_LOGIC;
112 status_ready_matrix_f2 : OUT STD_LOGIC;
112 status_ready_matrix_f2 : OUT STD_LOGIC;
113 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
113 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
114 status_error_bad_component_error : OUT STD_LOGIC;
114 status_error_bad_component_error : OUT STD_LOGIC;
115
115
116 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
116 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
117 config_active_interruption_onError : OUT STD_LOGIC;
117 config_active_interruption_onError : OUT STD_LOGIC;
118 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
118 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
119 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
119 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
120 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
120 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
121 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
121 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
122 );
122 );
123 END COMPONENT;
123 END COMPONENT;
124
124
125 COMPONENT lpp_dma_send_1word
125 COMPONENT lpp_dma_send_1word
126 PORT (
126 PORT (
127 HCLK : IN STD_ULOGIC;
127 HCLK : IN STD_ULOGIC;
128 HRESETn : IN STD_ULOGIC;
128 HRESETn : IN STD_ULOGIC;
129 DMAIn : OUT DMA_In_Type;
129 DMAIn : OUT DMA_In_Type;
130 DMAOut : IN DMA_OUt_Type;
130 DMAOut : IN DMA_OUt_Type;
131 send : IN STD_LOGIC;
131 send : IN STD_LOGIC;
132 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
132 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
133 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
133 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
134 send_ok : OUT STD_LOGIC;
134 send_ok : OUT STD_LOGIC;
135 send_ko : OUT STD_LOGIC);
135 send_ko : OUT STD_LOGIC);
136 END COMPONENT;
136 END COMPONENT;
137
137
138 COMPONENT lpp_dma_send_16word
138 COMPONENT lpp_dma_send_16word
139 PORT (
139 PORT (
140 HCLK : IN STD_ULOGIC;
140 HCLK : IN STD_ULOGIC;
141 HRESETn : IN STD_ULOGIC;
141 HRESETn : IN STD_ULOGIC;
142 DMAIn : OUT DMA_In_Type;
142 DMAIn : OUT DMA_In_Type;
143 DMAOut : IN DMA_OUt_Type;
143 DMAOut : IN DMA_OUt_Type;
144 send : IN STD_LOGIC;
144 send : IN STD_LOGIC;
145 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
145 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
146 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
146 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
147 ren : OUT STD_LOGIC;
147 ren : OUT STD_LOGIC;
148 send_ok : OUT STD_LOGIC;
148 send_ok : OUT STD_LOGIC;
149 send_ko : OUT STD_LOGIC);
149 send_ko : OUT STD_LOGIC);
150 END COMPONENT;
150 END COMPONENT;
151
151
152 COMPONENT fifo_latency_correction
152 COMPONENT fifo_latency_correction
153 PORT (
153 PORT (
154 HCLK : IN STD_ULOGIC;
154 HCLK : IN STD_ULOGIC;
155 HRESETn : IN STD_ULOGIC;
155 HRESETn : IN STD_ULOGIC;
156 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
156 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
157 fifo_empty : IN STD_LOGIC;
157 fifo_empty : IN STD_LOGIC;
158 fifo_ren : OUT STD_LOGIC;
158 fifo_ren : OUT STD_LOGIC;
159 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
159 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
160 dma_empty : OUT STD_LOGIC;
160 dma_empty : OUT STD_LOGIC;
161 dma_ren : IN STD_LOGIC);
161 dma_ren : IN STD_LOGIC);
162 END COMPONENT;
162 END COMPONENT;
163
163
164 COMPONENT lpp_dma_ip
164 COMPONENT lpp_dma_ip
165 GENERIC (
165 GENERIC (
166 tech : INTEGER;
166 tech : INTEGER;
167 hindex : INTEGER);
167 hindex : INTEGER);
168 PORT (
168 PORT (
169 HCLK : IN STD_ULOGIC;
169 HCLK : IN STD_ULOGIC;
170 HRESETn : IN STD_ULOGIC;
170 HRESETn : IN STD_ULOGIC;
171 AHB_Master_In : IN AHB_Mst_In_Type;
171 AHB_Master_In : IN AHB_Mst_In_Type;
172 AHB_Master_Out : OUT AHB_Mst_Out_Type;
172 AHB_Master_Out : OUT AHB_Mst_Out_Type;
173 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
173 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
174 fifo_empty : IN STD_LOGIC;
174 fifo_empty : IN STD_LOGIC;
175 fifo_ren : OUT STD_LOGIC;
175 fifo_ren : OUT STD_LOGIC;
176 header : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
176 header : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
177 header_val : IN STD_LOGIC;
177 header_val : IN STD_LOGIC;
178 header_ack : OUT STD_LOGIC;
178 header_ack : OUT STD_LOGIC;
179 ready_matrix_f0_0 : OUT STD_LOGIC;
179 ready_matrix_f0_0 : OUT STD_LOGIC;
180 ready_matrix_f0_1 : OUT STD_LOGIC;
180 ready_matrix_f0_1 : OUT STD_LOGIC;
181 ready_matrix_f1 : OUT STD_LOGIC;
181 ready_matrix_f1 : OUT STD_LOGIC;
182 ready_matrix_f2 : OUT STD_LOGIC;
182 ready_matrix_f2 : OUT STD_LOGIC;
183 error_anticipating_empty_fifo : OUT STD_LOGIC;
183 error_anticipating_empty_fifo : OUT STD_LOGIC;
184 error_bad_component_error : OUT STD_LOGIC;
184 error_bad_component_error : OUT STD_LOGIC;
185 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
185 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
186 status_ready_matrix_f0_0 : IN STD_LOGIC;
186 status_ready_matrix_f0_0 : IN STD_LOGIC;
187 status_ready_matrix_f0_1 : IN STD_LOGIC;
187 status_ready_matrix_f0_1 : IN STD_LOGIC;
188 status_ready_matrix_f1 : IN STD_LOGIC;
188 status_ready_matrix_f1 : IN STD_LOGIC;
189 status_ready_matrix_f2 : IN STD_LOGIC;
189 status_ready_matrix_f2 : IN STD_LOGIC;
190 status_error_anticipating_empty_fifo : IN STD_LOGIC;
190 status_error_anticipating_empty_fifo : IN STD_LOGIC;
191 status_error_bad_component_error : IN STD_LOGIC;
191 status_error_bad_component_error : IN STD_LOGIC;
192 config_active_interruption_onNewMatrix : IN STD_LOGIC;
192 config_active_interruption_onNewMatrix : IN STD_LOGIC;
193 config_active_interruption_onError : IN STD_LOGIC;
193 config_active_interruption_onError : IN STD_LOGIC;
194 addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
194 addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
195 addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
195 addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
196 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
196 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
197 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
197 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
198 END COMPONENT;
198 END COMPONENT;
199
200 COMPONENT lpp_dma_singleOrBurst
201 GENERIC (
202 tech : INTEGER;
203 hindex : INTEGER);
204 PORT (
205 HCLK : IN STD_ULOGIC;
206 HRESETn : IN STD_ULOGIC;
207 run : IN STD_LOGIC;
208 AHB_Master_In : IN AHB_Mst_In_Type;
209 AHB_Master_Out : OUT AHB_Mst_Out_Type;
210 send : IN STD_LOGIC;
211 valid_burst : IN STD_LOGIC;
212 done : OUT STD_LOGIC;
213 ren : OUT STD_LOGIC;
214 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
215 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
216 END COMPONENT;
199
217
200 END;
218 END;
Show file before | Show file after | Hide comments
@@ -1,6 +1,7
1 lpp_dma_pkg.vhd
1 lpp_dma_pkg.vhd
2 fifo_latency_correction.vhd
2 fifo_latency_correction.vhd
3 lpp_dma.vhd
3 lpp_dma.vhd
4 lpp_dma_ip.vhd
4 lpp_dma_ip.vhd
5 lpp_dma_send_16word.vhd
5 lpp_dma_send_16word.vhd
6 lpp_dma_send_1word.vhd
6 lpp_dma_send_1word.vhd
7 lpp_dma_singleOrBurst.vhd
Show file before | Show file after | Hide comments
@@ -1,349 +1,548
1 LIBRARY ieee;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
2 USE ieee.std_logic_1164.ALL;
3 USE ieee.numeric_std.ALL;
3 USE ieee.numeric_std.ALL;
4
4
5 LIBRARY lpp;
5 LIBRARY lpp;
6 USE lpp.lpp_ad_conv.ALL;
6 USE lpp.lpp_ad_conv.ALL;
7 USE lpp.iir_filter.ALL;
7 USE lpp.iir_filter.ALL;
8 USE lpp.FILTERcfg.ALL;
8 USE lpp.FILTERcfg.ALL;
9 USE lpp.lpp_memory.ALL;
9 USE lpp.lpp_memory.ALL;
10 USE lpp.lpp_waveform_pkg.ALL;
10 USE lpp.lpp_waveform_pkg.ALL;
11 USE lpp.lpp_dma_pkg.ALL;
11 USE lpp.lpp_top_lfr_pkg.ALL;
12 USE lpp.lpp_top_lfr_pkg.ALL;
12 USE lpp.lpp_lfr_pkg.ALL;
13 USE lpp.lpp_lfr_pkg.ALL;
14 USE lpp.general_purpose.ALL;
13
15
14 LIBRARY techmap;
16 LIBRARY techmap;
15 USE techmap.gencomp.ALL;
17 USE techmap.gencomp.ALL;
16
18
17 LIBRARY grlib;
19 LIBRARY grlib;
18 USE grlib.amba.ALL;
20 USE grlib.amba.ALL;
19 USE grlib.stdlib.ALL;
21 USE grlib.stdlib.ALL;
20 USE grlib.devices.ALL;
22 USE grlib.devices.ALL;
21 USE GRLIB.DMA2AHB_Package.ALL;
23 USE GRLIB.DMA2AHB_Package.ALL;
22
24
23 ENTITY lpp_lfr IS
25 ENTITY lpp_lfr IS
24 GENERIC (
26 GENERIC (
25 Mem_use : INTEGER := use_RAM;
27 Mem_use : INTEGER := use_RAM;
26 nb_burst_available_size : INTEGER := 11;
28 nb_data_by_buffer_size : INTEGER := 11;
27 nb_snapshot_param_size : INTEGER := 11;
29 nb_snapshot_param_size : INTEGER := 11;
28 delta_snapshot_size : INTEGER := 16;
30 delta_vector_size : INTEGER := 20;
29 delta_f2_f0_size : INTEGER := 10;
31 delta_vector_size_f0_2 : INTEGER := 3;
30 delta_f2_f1_size : INTEGER := 10;
31
32
32 pindex : INTEGER := 4;
33 pindex : INTEGER := 4;
33 paddr : INTEGER := 4;
34 paddr : INTEGER := 4;
34 pmask : INTEGER := 16#fff#;
35 pmask : INTEGER := 16#fff#;
35 pirq_ms : INTEGER := 0;
36 pirq_ms : INTEGER := 0;
36 pirq_wfp : INTEGER := 1;
37 pirq_wfp : INTEGER := 1;
37
38
38 hindex_wfp : INTEGER := 2;
39 hindex : INTEGER := 2
39 hindex_ms : INTEGER := 3
40
40
41 );
41 );
42 PORT (
42 PORT (
43 clk : IN STD_LOGIC;
43 clk : IN STD_LOGIC;
44 rstn : IN STD_LOGIC;
44 rstn : IN STD_LOGIC;
45 --
45 -- SAMPLE
46 sample_B : IN Samples14v(2 DOWNTO 0);
46 sample_B : IN Samples14v(2 DOWNTO 0);
47 sample_E : IN Samples14v(4 DOWNTO 0);
47 sample_E : IN Samples14v(4 DOWNTO 0);
48 sample_val : IN STD_LOGIC;
48 sample_val : IN STD_LOGIC;
49 --
49 -- APB
50 apbi : IN apb_slv_in_type;
50 apbi : IN apb_slv_in_type;
51 apbo : OUT apb_slv_out_type;
51 apbo : OUT apb_slv_out_type;
52 --
52 -- AHB
53 ahbi_wfp : IN AHB_Mst_In_Type;
53 ahbi : IN AHB_Mst_In_Type;
54 ahbo_wfp : OUT AHB_Mst_Out_Type;
54 ahbo : OUT AHB_Mst_Out_Type;
55 --
55 -- TIME
56 ahbi_ms : IN AHB_Mst_In_Type;
56 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
57 ahbo_ms : OUT AHB_Mst_Out_Type;
57 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
58 --
58 --
59 coarse_time_0 : IN STD_LOGIC;
60 --
61 data_shaping_BW : OUT STD_LOGIC
59 data_shaping_BW : OUT STD_LOGIC
62 );
60 );
63 END lpp_lfr;
61 END lpp_lfr;
64
62
65 ARCHITECTURE beh OF lpp_lfr IS
63 ARCHITECTURE beh OF lpp_lfr IS
66 SIGNAL sample : Samples14v(7 DOWNTO 0);
64 SIGNAL sample : Samples14v(7 DOWNTO 0);
67 SIGNAL sample_s : Samples(7 DOWNTO 0);
65 SIGNAL sample_s : Samples(7 DOWNTO 0);
68 --
66 --
69 SIGNAL data_shaping_SP0 : STD_LOGIC;
67 SIGNAL data_shaping_SP0 : STD_LOGIC;
70 SIGNAL data_shaping_SP1 : STD_LOGIC;
68 SIGNAL data_shaping_SP1 : STD_LOGIC;
71 SIGNAL data_shaping_R0 : STD_LOGIC;
69 SIGNAL data_shaping_R0 : STD_LOGIC;
72 SIGNAL data_shaping_R1 : STD_LOGIC;
70 SIGNAL data_shaping_R1 : STD_LOGIC;
73 --
71 --
74 SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
72 SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
75 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
73 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
76 SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
74 SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
77 --
75 --
78 SIGNAL sample_f0_val : STD_LOGIC;
76 SIGNAL sample_f0_val : STD_LOGIC;
79 SIGNAL sample_f1_val : STD_LOGIC;
77 SIGNAL sample_f1_val : STD_LOGIC;
80 SIGNAL sample_f2_val : STD_LOGIC;
78 SIGNAL sample_f2_val : STD_LOGIC;
81 SIGNAL sample_f3_val : STD_LOGIC;
79 SIGNAL sample_f3_val : STD_LOGIC;
82 --
80 --
83 SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
81 SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
84 SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
82 SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
85 SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
83 SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
86 SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
84 SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
87 --
85 --
88 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
86 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
89 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
87 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
90 SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
88 SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
91
89
92 -- SM
90 -- SM
93 SIGNAL ready_matrix_f0_0 : STD_LOGIC;
91 SIGNAL ready_matrix_f0_0 : STD_LOGIC;
94 SIGNAL ready_matrix_f0_1 : STD_LOGIC;
92 SIGNAL ready_matrix_f0_1 : STD_LOGIC;
95 SIGNAL ready_matrix_f1 : STD_LOGIC;
93 SIGNAL ready_matrix_f1 : STD_LOGIC;
96 SIGNAL ready_matrix_f2 : STD_LOGIC;
94 SIGNAL ready_matrix_f2 : STD_LOGIC;
97 SIGNAL error_anticipating_empty_fifo : STD_LOGIC;
95 SIGNAL error_anticipating_empty_fifo : STD_LOGIC;
98 SIGNAL error_bad_component_error : STD_LOGIC;
96 SIGNAL error_bad_component_error : STD_LOGIC;
99 SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
97 SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
100 SIGNAL status_ready_matrix_f0_0 : STD_LOGIC;
98 SIGNAL status_ready_matrix_f0_0 : STD_LOGIC;
101 SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
99 SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
102 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
100 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
103 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
101 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
104 SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC;
102 SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC;
105 SIGNAL status_error_bad_component_error : STD_LOGIC;
103 SIGNAL status_error_bad_component_error : STD_LOGIC;
106 SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
104 SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
107 SIGNAL config_active_interruption_onError : STD_LOGIC;
105 SIGNAL config_active_interruption_onError : STD_LOGIC;
108 SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
106 SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
109 SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
107 SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
110 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
108 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
111 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
109 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
112
110
113 -- WFP
111 -- WFP
114 SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
112 SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
115 SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
113 SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
116 SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
114 SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
117 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
115 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
118 SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
116 SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
119 SIGNAL delta_f2_f1 : STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
117 SIGNAL delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
120 SIGNAL delta_f2_f0 : STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
118 SIGNAL delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
121 SIGNAL nb_burst_available : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
119 SIGNAL delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
120 SIGNAL delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
121
122 SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
122 SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
123 SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
123 SIGNAL enable_f0 : STD_LOGIC;
124 SIGNAL enable_f0 : STD_LOGIC;
124 SIGNAL enable_f1 : STD_LOGIC;
125 SIGNAL enable_f1 : STD_LOGIC;
125 SIGNAL enable_f2 : STD_LOGIC;
126 SIGNAL enable_f2 : STD_LOGIC;
126 SIGNAL enable_f3 : STD_LOGIC;
127 SIGNAL enable_f3 : STD_LOGIC;
127 SIGNAL burst_f0 : STD_LOGIC;
128 SIGNAL burst_f0 : STD_LOGIC;
128 SIGNAL burst_f1 : STD_LOGIC;
129 SIGNAL burst_f1 : STD_LOGIC;
129 SIGNAL burst_f2 : STD_LOGIC;
130 SIGNAL burst_f2 : STD_LOGIC;
130 SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
131 SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
131 SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
132 SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
132 SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
133 SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
133 SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
134 SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
134
135
135 --
136 SIGNAL run : STD_LOGIC;
136 SIGNAL time_info : STD_LOGIC_VECTOR( (4*16)-1 DOWNTO 0);
137 SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
137 SIGNAL data_f0_wfp : STD_LOGIC_VECTOR(159 DOWNTO 0) ;
138
138 SIGNAL data_f1_wfp : STD_LOGIC_VECTOR(159 DOWNTO 0) ;
139 SIGNAL data_f0_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
139 SIGNAL data_f2_wfp : STD_LOGIC_VECTOR(159 DOWNTO 0) ;
140 SIGNAL data_f0_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
140 SIGNAL data_f3_wfp : STD_LOGIC_VECTOR(159 DOWNTO 0) ;
141 SIGNAL data_f0_data_out_valid : STD_LOGIC;
142 SIGNAL data_f0_data_out_valid_burst : STD_LOGIC;
143 SIGNAL data_f0_data_out_ren : STD_LOGIC;
144 --f1
145 SIGNAL data_f1_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
146 SIGNAL data_f1_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
147 SIGNAL data_f1_data_out_valid : STD_LOGIC;
148 SIGNAL data_f1_data_out_valid_burst : STD_LOGIC;
149 SIGNAL data_f1_data_out_ren : STD_LOGIC;
150 --f2
151 SIGNAL data_f2_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
152 SIGNAL data_f2_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
153 SIGNAL data_f2_data_out_valid : STD_LOGIC;
154 SIGNAL data_f2_data_out_valid_burst : STD_LOGIC;
155 SIGNAL data_f2_data_out_ren : STD_LOGIC;
156 --f3
157 SIGNAL data_f3_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
158 SIGNAL data_f3_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
159 SIGNAL data_f3_data_out_valid : STD_LOGIC;
160 SIGNAL data_f3_data_out_valid_burst : STD_LOGIC;
161 SIGNAL data_f3_data_out_ren : STD_LOGIC;
141
162
142 SIGNAL run : STD_LOGIC;
163 -----------------------------------------------------------------------------
143 -- SIGNAL val_f0_wfp : STD_LOGIC;
164 --
144 -- SIGNAL val_f1_wfp : STD_LOGIC;
165 -----------------------------------------------------------------------------
145 -- SIGNAL val_f2_wfp : STD_LOGIC;
166 SIGNAL data_f0_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
146 -- SIGNAL val_f3_wfp : STD_LOGIC;
167 SIGNAL data_f0_data_out_valid_s : STD_LOGIC;
168 SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC;
169 --f1
170 SIGNAL data_f1_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
171 SIGNAL data_f1_data_out_valid_s : STD_LOGIC;
172 SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC;
173 --f2
174 SIGNAL data_f2_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
175 SIGNAL data_f2_data_out_valid_s : STD_LOGIC;
176 SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC;
177 --f3
178 SIGNAL data_f3_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
179 SIGNAL data_f3_data_out_valid_s : STD_LOGIC;
180 SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC;
181
182 -----------------------------------------------------------------------------
183 -- DMA RR
184 -----------------------------------------------------------------------------
185 SIGNAL dma_sel_valid : STD_LOGIC;
186 SIGNAL dma_sel : STD_LOGIC_VECTOR(3 DOWNTO 0);
187 SIGNAL dma_rr_valid : STD_LOGIC_VECTOR(3 DOWNTO 0);
188 SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(3 DOWNTO 0);
189
190 -----------------------------------------------------------------------------
191 -- DMA
192 -----------------------------------------------------------------------------
193 SIGNAL dma_send : STD_LOGIC;
194 SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
195 SIGNAL dma_done : STD_LOGIC;
196 SIGNAL dma_ren : STD_LOGIC;
197 SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0);
198 SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
199
147 BEGIN
200 BEGIN
148
201
149 sample(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
202 sample(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
150 sample(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
203 sample(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
151
204
152 all_channel: FOR i IN 7 DOWNTO 0 GENERATE
205 all_channel: FOR i IN 7 DOWNTO 0 GENERATE
153 sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i);
206 sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i);
154 END GENERATE all_channel;
207 END GENERATE all_channel;
155
208
156 -----------------------------------------------------------------------------
209 -----------------------------------------------------------------------------
157 lpp_lfr_filter_1 : lpp_lfr_filter
210 lpp_lfr_filter_1 : lpp_lfr_filter
158 GENERIC MAP (
211 GENERIC MAP (
159 Mem_use => Mem_use)
212 Mem_use => Mem_use)
160 PORT MAP (
213 PORT MAP (
161 sample => sample_s,
214 sample => sample_s,
162 sample_val => sample_val,
215 sample_val => sample_val,
163 clk => clk,
216 clk => clk,
164 rstn => rstn,
217 rstn => rstn,
165 data_shaping_SP0 => data_shaping_SP0,
218 data_shaping_SP0 => data_shaping_SP0,
166 data_shaping_SP1 => data_shaping_SP1,
219 data_shaping_SP1 => data_shaping_SP1,
167 data_shaping_R0 => data_shaping_R0,
220 data_shaping_R0 => data_shaping_R0,
168 data_shaping_R1 => data_shaping_R1,
221 data_shaping_R1 => data_shaping_R1,
169 sample_f0_val => sample_f0_val,
222 sample_f0_val => sample_f0_val,
170 sample_f1_val => sample_f1_val,
223 sample_f1_val => sample_f1_val,
171 sample_f2_val => sample_f2_val,
224 sample_f2_val => sample_f2_val,
172 sample_f3_val => sample_f3_val,
225 sample_f3_val => sample_f3_val,
173 sample_f0_wdata => sample_f0_data,
226 sample_f0_wdata => sample_f0_data,
174 sample_f1_wdata => sample_f1_data,
227 sample_f1_wdata => sample_f1_data,
175 sample_f2_wdata => sample_f2_data,
228 sample_f2_wdata => sample_f2_data,
176 sample_f3_wdata => sample_f3_data);
229 sample_f3_wdata => sample_f3_data);
177
230
178 -----------------------------------------------------------------------------
231 -----------------------------------------------------------------------------
179 lpp_top_apbreg_1 : lpp_lfr_apbreg
232 lpp_lfr_apbreg_1: lpp_lfr_apbreg
180 GENERIC MAP (
233 GENERIC MAP (
181 nb_burst_available_size => nb_burst_available_size,
234 nb_data_by_buffer_size => nb_data_by_buffer_size,
182 nb_snapshot_param_size => nb_snapshot_param_size,
235 nb_snapshot_param_size => nb_snapshot_param_size,
183 delta_snapshot_size => delta_snapshot_size,
236 delta_vector_size => delta_vector_size,
184 delta_f2_f0_size => delta_f2_f0_size,
237 delta_vector_size_f0_2 => delta_vector_size_f0_2,
185 delta_f2_f1_size => delta_f2_f1_size,
238 pindex => pindex,
186 pindex => pindex,
239 paddr => paddr,
187 paddr => paddr,
240 pmask => pmask,
188 pmask => pmask,
241 pirq_ms => pirq_ms,
189 pirq_ms => pirq_ms,
242 pirq_wfp => pirq_wfp)
190 pirq_wfp => pirq_wfp)
191 PORT MAP (
243 PORT MAP (
192 HCLK => clk,
244 HCLK => clk,
193 HRESETn => rstn,
245 HRESETn => rstn,
194 apbi => apbi,
246 apbi => apbi,
195 apbo => apbo,
247 apbo => apbo,
196
197 ready_matrix_f0_0 => ready_matrix_f0_0,
248 ready_matrix_f0_0 => ready_matrix_f0_0,
198 ready_matrix_f0_1 => ready_matrix_f0_1,
249 ready_matrix_f0_1 => ready_matrix_f0_1,
199 ready_matrix_f1 => ready_matrix_f1,
250 ready_matrix_f1 => ready_matrix_f1,
200 ready_matrix_f2 => ready_matrix_f2,
251 ready_matrix_f2 => ready_matrix_f2,
201 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
252 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
202 error_bad_component_error => error_bad_component_error,
253 error_bad_component_error => error_bad_component_error,
203 debug_reg => debug_reg,
254 debug_reg => debug_reg,
204 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
255 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
205 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
256 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
206 status_ready_matrix_f1 => status_ready_matrix_f1,
257 status_ready_matrix_f1 => status_ready_matrix_f1,
207 status_ready_matrix_f2 => status_ready_matrix_f2,
258 status_ready_matrix_f2 => status_ready_matrix_f2,
208 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
259 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
209 status_error_bad_component_error => status_error_bad_component_error,
260 status_error_bad_component_error => status_error_bad_component_error,
210 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
261 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
211 config_active_interruption_onError => config_active_interruption_onError,
262 config_active_interruption_onError => config_active_interruption_onError,
212 addr_matrix_f0_0 => addr_matrix_f0_0,
263 addr_matrix_f0_0 => addr_matrix_f0_0,
213 addr_matrix_f0_1 => addr_matrix_f0_1,
264 addr_matrix_f0_1 => addr_matrix_f0_1,
214 addr_matrix_f1 => addr_matrix_f1,
265 addr_matrix_f1 => addr_matrix_f1,
215 addr_matrix_f2 => addr_matrix_f2,
266 addr_matrix_f2 => addr_matrix_f2,
216
267 status_full => status_full,
217 status_full => status_full,
268 status_full_ack => status_full_ack,
218 status_full_ack => status_full_ack,
269 status_full_err => status_full_err,
219 status_full_err => status_full_err,
270 status_new_err => status_new_err,
220 status_new_err => status_new_err,
271 data_shaping_BW => data_shaping_BW,
221 data_shaping_BW => data_shaping_BW,
272 data_shaping_SP0 => data_shaping_SP0,
222 data_shaping_SP0 => data_shaping_SP0,
273 data_shaping_SP1 => data_shaping_SP1,
223 data_shaping_SP1 => data_shaping_SP1,
274 data_shaping_R0 => data_shaping_R0,
224 data_shaping_R0 => data_shaping_R0,
275 data_shaping_R1 => data_shaping_R1,
225 data_shaping_R1 => data_shaping_R1,
276 delta_snapshot => delta_snapshot,
226 delta_snapshot => delta_snapshot,
277 delta_f0 => delta_f0,
227 delta_f2_f1 => delta_f2_f1,
278 delta_f0_2 => delta_f0_2,
228 delta_f2_f0 => delta_f2_f0,
279 delta_f1 => delta_f1,
229 nb_burst_available => nb_burst_available,
280 delta_f2 => delta_f2,
230 nb_snapshot_param => nb_snapshot_param,
281 nb_data_by_buffer => nb_data_by_buffer,
231 enable_f0 => enable_f0,
282 nb_snapshot_param => nb_snapshot_param,
232 enable_f1 => enable_f1,
283 enable_f0 => enable_f0,
233 enable_f2 => enable_f2,
284 enable_f1 => enable_f1,
234 enable_f3 => enable_f3,
285 enable_f2 => enable_f2,
235 burst_f0 => burst_f0,
286 enable_f3 => enable_f3,
236 burst_f1 => burst_f1,
287 burst_f0 => burst_f0,
237 burst_f2 => burst_f2,
288 burst_f1 => burst_f1,
238 run => run,
289 burst_f2 => burst_f2,
239 addr_data_f0 => addr_data_f0,
290 run => run,
240 addr_data_f1 => addr_data_f1,
291 addr_data_f0 => addr_data_f0,
241 addr_data_f2 => addr_data_f2,
292 addr_data_f1 => addr_data_f1,
242 addr_data_f3 => addr_data_f3);
293 addr_data_f2 => addr_data_f2,
294 addr_data_f3 => addr_data_f3,
295 start_date => start_date);
243
296
244 -----------------------------------------------------------------------------
297 -----------------------------------------------------------------------------
245 lpp_waveform_1: lpp_waveform
298 lpp_waveform_1: lpp_waveform
246 GENERIC MAP (
299 GENERIC MAP (
247 hindex => hindex_wfp,
248 tech => inferred,
300 tech => inferred,
249 data_size => 160,
301 data_size => 6*16,
250 nb_burst_available_size => nb_burst_available_size,
302 nb_data_by_buffer_size => nb_data_by_buffer_size,
251 nb_snapshot_param_size => nb_snapshot_param_size,
303 nb_snapshot_param_size => nb_snapshot_param_size,
252 delta_snapshot_size => delta_snapshot_size,
304 delta_vector_size => delta_vector_size,
253 delta_f2_f0_size => delta_f2_f0_size,
305 delta_vector_size_f0_2 => delta_vector_size_f0_2
254 delta_f2_f1_size => delta_f2_f1_size)
306 )
255 PORT MAP (
307 PORT MAP (
256 clk => clk,
308 clk => clk,
257 rstn => rstn,
309 rstn => rstn,
258 AHB_Master_In => ahbi_wfp,
310
259 AHB_Master_Out => ahbo_wfp,
311 reg_run => run,
260 coarse_time_0 => coarse_time_0,
312 reg_start_date => start_date,
313 reg_delta_snapshot => delta_snapshot,
314 reg_delta_f0 => delta_f0,
315 reg_delta_f0_2 => delta_f0_2,
316 reg_delta_f1 => delta_f1,
317 reg_delta_f2 => delta_f2,
261
318
262 delta_snapshot => delta_snapshot,
263 delta_f2_f1 => delta_f2_f1,
264 delta_f2_f0 => delta_f2_f0,
265 enable_f0 => enable_f0,
319 enable_f0 => enable_f0,
266 enable_f1 => enable_f1,
320 enable_f1 => enable_f1,
267 enable_f2 => enable_f2,
321 enable_f2 => enable_f2,
268 enable_f3 => enable_f3,
322 enable_f3 => enable_f3,
269 burst_f0 => burst_f0,
323 burst_f0 => burst_f0,
270 burst_f1 => burst_f1,
324 burst_f1 => burst_f1,
271 burst_f2 => burst_f2,
325 burst_f2 => burst_f2,
272
326
273 run => run,
327 nb_data_by_buffer => nb_data_by_buffer,
274
275 nb_burst_available => nb_burst_available,
276 nb_snapshot_param => nb_snapshot_param,
328 nb_snapshot_param => nb_snapshot_param,
277 status_full => status_full,
329 status_full => status_full,
278 status_full_ack => status_full_ack,
330 status_full_ack => status_full_ack,
279 status_full_err => status_full_err,
331 status_full_err => status_full_err,
280 status_new_err => status_new_err,
332 status_new_err => status_new_err,
333
334 coarse_time => coarse_time,
335 fine_time => fine_time,
336
337 --f0
281 addr_data_f0 => addr_data_f0,
338 addr_data_f0 => addr_data_f0,
282 addr_data_f1 => addr_data_f1,
283 addr_data_f2 => addr_data_f2,
284 addr_data_f3 => addr_data_f3,
285
286 data_f0_in => data_f0_wfp,
287 data_f1_in => data_f1_wfp,
288 data_f2_in => data_f2_wfp,
289 data_f3_in => data_f3_wfp,
290 data_f0_in_valid => sample_f0_val,
339 data_f0_in_valid => sample_f0_val,
340 data_f0_in => sample_f0_data,
341 --f1
342 addr_data_f1 => addr_data_f1,
291 data_f1_in_valid => sample_f1_val,
343 data_f1_in_valid => sample_f1_val,
344 data_f1_in => sample_f1_data,
345 --f2
346 addr_data_f2 => addr_data_f2,
292 data_f2_in_valid => sample_f2_val,
347 data_f2_in_valid => sample_f2_val,
293 data_f3_in_valid => sample_f3_val);
348 data_f2_in => sample_f2_data,
294
349 --f3
295 time_info <= (others => '0');
350 addr_data_f3 => addr_data_f3,
296
351 data_f3_in_valid => sample_f3_val,
297 data_f0_wfp <= sample_f0_data & time_info;
352 data_f3_in => sample_f3_data,
298 data_f1_wfp <= sample_f1_data & time_info;
353 -- OUTPUT -- DMA interface
299 data_f2_wfp <= sample_f2_data & time_info;
354 --f0
300 data_f3_wfp <= sample_f3_data & time_info;
355 data_f0_addr_out => data_f0_addr_out_s,
356 data_f0_data_out => data_f0_data_out,
357 data_f0_data_out_valid => data_f0_data_out_valid_s,
358 data_f0_data_out_valid_burst => data_f0_data_out_valid_burst_s,
359 data_f0_data_out_ren => data_f0_data_out_ren,
360 --f1
361 data_f1_addr_out => data_f1_addr_out_s,
362 data_f1_data_out => data_f1_data_out,
363 data_f1_data_out_valid => data_f1_data_out_valid_s,
364 data_f1_data_out_valid_burst => data_f1_data_out_valid_burst_s,
365 data_f1_data_out_ren => data_f1_data_out_ren,
366 --f2
367 data_f2_addr_out => data_f2_addr_out_s,
368 data_f2_data_out => data_f2_data_out,
369 data_f2_data_out_valid => data_f2_data_out_valid_s,
370 data_f2_data_out_valid_burst => data_f2_data_out_valid_burst_s,
371 data_f2_data_out_ren => data_f2_data_out_ren,
372 --f3
373 data_f3_addr_out => data_f3_addr_out_s,
374 data_f3_data_out => data_f3_data_out,
375 data_f3_data_out_valid => data_f3_data_out_valid_s,
376 data_f3_data_out_valid_burst => data_f3_data_out_valid_burst_s,
377 data_f3_data_out_ren => data_f3_data_out_ren
378
379 );
380
301
381
302 -----------------------------------------------------------------------------
382 -----------------------------------------------------------------------------
303 sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) &
383 -- TEMP
304 NOT(sample_f0_val) & NOT(sample_f0_val) ;
384 -----------------------------------------------------------------------------
305 sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) &
306 NOT(sample_f1_val) & NOT(sample_f1_val) ;
307 sample_f3_wen <= NOT(sample_f3_val) & NOT(sample_f3_val) & NOT(sample_f3_val) &
308 NOT(sample_f3_val) & NOT(sample_f3_val) ;
309
385
310 sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB)
386 PROCESS (clk, rstn)
311 sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16));
387 BEGIN -- PROCESS
312 sample_f3_wdata <= sample_f3_data((3*16)-1 DOWNTO (1*16)) & sample_f3_data((6*16)-1 DOWNTO (3*16));
388 IF rstn = '0' THEN -- asynchronous reset (active low)
389 data_f0_addr_out <= (OTHERS => '0');
390 data_f0_data_out_valid <= '0';
391 data_f0_data_out_valid_burst <= '0';
392 data_f1_addr_out <= (OTHERS => '0');
393 data_f1_data_out_valid <= '0';
394 data_f1_data_out_valid_burst <= '0';
395 data_f2_addr_out <= (OTHERS => '0');
396 data_f2_data_out_valid <= '0';
397 data_f2_data_out_valid_burst <= '0';
398 data_f3_addr_out <= (OTHERS => '0');
399 data_f3_data_out_valid <= '0';
400 data_f3_data_out_valid_burst <= '0';
401 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
402 data_f0_addr_out <= data_f0_addr_out_s;
403 data_f0_data_out_valid <= data_f0_data_out_valid_s;
404 data_f0_data_out_valid_burst <= data_f0_data_out_valid_burst_s;
405 data_f1_addr_out <= data_f1_addr_out_s;
406 data_f1_data_out_valid <= data_f1_data_out_valid_s;
407 data_f1_data_out_valid_burst <= data_f1_data_out_valid_burst_s;
408 data_f2_addr_out <= data_f2_addr_out_s;
409 data_f2_data_out_valid <= data_f2_data_out_valid_s;
410 data_f2_data_out_valid_burst <= data_f2_data_out_valid_burst_s;
411 data_f3_addr_out <= data_f3_addr_out_s;
412 data_f3_data_out_valid <= data_f3_data_out_valid_s;
413 data_f3_data_out_valid_burst <= data_f3_data_out_valid_burst_s;
414 END IF;
415 END PROCESS;
416
417
313 -----------------------------------------------------------------------------
418 -----------------------------------------------------------------------------
314 lpp_lfr_ms_1: lpp_lfr_ms
419 -- RoundRobin Selection For DMA
315 GENERIC MAP (
420 -----------------------------------------------------------------------------
316 hindex => hindex_ms)
421
422 dma_rr_valid(0) <= data_f0_data_out_valid OR data_f0_data_out_valid_burst;
423 dma_rr_valid(1) <= data_f1_data_out_valid OR data_f1_data_out_valid_burst;
424 dma_rr_valid(2) <= data_f2_data_out_valid OR data_f2_data_out_valid_burst;
425 dma_rr_valid(3) <= data_f3_data_out_valid OR data_f3_data_out_valid_burst;
426
427 RR_Arbiter_4_1: RR_Arbiter_4
317 PORT MAP (
428 PORT MAP (
318 clk => clk,
429 clk => clk,
319 rstn => rstn,
430 rstn => rstn,
320 sample_f0_wen => sample_f0_wen,
431 in_valid => dma_rr_valid,
321 sample_f0_wdata => sample_f0_wdata,
432 out_grant => dma_rr_grant);
322 sample_f1_wen => sample_f1_wen,
433
323 sample_f1_wdata => sample_f1_wdata,
434 PROCESS (clk, rstn)
324 sample_f3_wen => sample_f3_wen,
435 BEGIN -- PROCESS
325 sample_f3_wdata => sample_f3_wdata,
436 IF rstn = '0' THEN -- asynchronous reset (active low)
326 AHB_Master_In => ahbi_ms,
437 dma_sel <= (OTHERS => '0');
327 AHB_Master_Out => ahbo_ms,
438 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
439 IF dma_sel = "0000" OR dma_send = '1' THEN
440 dma_sel <= dma_rr_grant;
441 ELSE
442 dma_sel <= dma_sel;
443 END IF;
444 END IF;
445 END PROCESS;
446
447
448 dma_address <= data_f0_addr_out WHEN dma_sel(0) = '1' ELSE
449 data_f1_addr_out WHEN dma_sel(1) = '1' ELSE
450 data_f2_addr_out WHEN dma_sel(2) = '1' ELSE
451 data_f3_addr_out ;
452
453 dma_data <= data_f0_data_out WHEN dma_sel(0) = '1' ELSE
454 data_f1_data_out WHEN dma_sel(1) = '1' ELSE
455 data_f2_data_out WHEN dma_sel(2) = '1' ELSE
456 data_f3_data_out ;
457
458 dma_valid_burst <= data_f0_data_out_valid_burst WHEN dma_sel(0) = '1' ELSE
459 data_f1_data_out_valid_burst WHEN dma_sel(1) = '1' ELSE
460 data_f2_data_out_valid_burst WHEN dma_sel(2) = '1' ELSE
461 data_f3_data_out_valid_burst WHEN dma_sel(3) = '1' ELSE
462 '0';
463
464 dma_sel_valid <= data_f0_data_out_valid WHEN dma_sel(0) = '1' ELSE
465 data_f1_data_out_valid WHEN dma_sel(1) = '1' ELSE
466 data_f2_data_out_valid WHEN dma_sel(2) = '1' ELSE
467 data_f3_data_out_valid WHEN dma_sel(3) = '1' ELSE
468 '0';
469
470 dma_send <= dma_sel_valid OR dma_valid_burst;
471
472 data_f0_data_out_ren <= dma_ren WHEN dma_sel(0) = '1' ELSE '1';
473 data_f1_data_out_ren <= dma_ren WHEN dma_sel(1) = '1' ELSE '1';
474 data_f2_data_out_ren <= dma_ren WHEN dma_sel(2) = '1' ELSE '1';
475 data_f3_data_out_ren <= dma_ren WHEN dma_sel(3) = '1' ELSE '1';
476
477 -----------------------------------------------------------------------------
478 -- DMA
479 -----------------------------------------------------------------------------
480 lpp_dma_singleOrBurst_1: lpp_dma_singleOrBurst
481 GENERIC MAP (
482 tech => inferred,
483 hindex => hindex)
484 PORT MAP (
485 HCLK => clk,
486 HRESETn => rstn,
487 run => run,
488 AHB_Master_In => ahbi,
489 AHB_Master_Out => ahbo,
328
490
329 ready_matrix_f0_0 => ready_matrix_f0_0,
491 send => dma_send,
330 ready_matrix_f0_1 => ready_matrix_f0_1,
492 valid_burst => dma_valid_burst,
331 ready_matrix_f1 => ready_matrix_f1,
493 done => dma_done,
332 ready_matrix_f2 => ready_matrix_f2,
494 ren => dma_ren,
333 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
495 address => dma_address,
334 error_bad_component_error => error_bad_component_error,
496 data => dma_data);
335 debug_reg => debug_reg,
497
336 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
498 -----------------------------------------------------------------------------
337 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
499 -- Matrix Spectral - TODO
338 status_ready_matrix_f1 => status_ready_matrix_f1,
500 -----------------------------------------------------------------------------
339 status_ready_matrix_f2 => status_ready_matrix_f2,
501 -----------------------------------------------------------------------------
340 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
502 --sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) &
341 status_error_bad_component_error => status_error_bad_component_error,
503 -- NOT(sample_f0_val) & NOT(sample_f0_val) ;
342 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
504 --sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) &
343 config_active_interruption_onError => config_active_interruption_onError,
505 -- NOT(sample_f1_val) & NOT(sample_f1_val) ;
344 addr_matrix_f0_0 => addr_matrix_f0_0,
506 --sample_f3_wen <= NOT(sample_f3_val) & NOT(sample_f3_val) & NOT(sample_f3_val) &
345 addr_matrix_f0_1 => addr_matrix_f0_1,
507 -- NOT(sample_f3_val) & NOT(sample_f3_val) ;
346 addr_matrix_f1 => addr_matrix_f1,
347 addr_matrix_f2 => addr_matrix_f2);
348
508
349 END beh; No newline at end of file
509 --sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB)
510 --sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16));
511 --sample_f3_wdata <= sample_f3_data((3*16)-1 DOWNTO (1*16)) & sample_f3_data((6*16)-1 DOWNTO (3*16));
512 -------------------------------------------------------------------------------
513 --lpp_lfr_ms_1: lpp_lfr_ms
514 -- GENERIC MAP (
515 -- hindex => hindex_ms)
516 -- PORT MAP (
517 -- clk => clk,
518 -- rstn => rstn,
519 -- sample_f0_wen => sample_f0_wen,
520 -- sample_f0_wdata => sample_f0_wdata,
521 -- sample_f1_wen => sample_f1_wen,
522 -- sample_f1_wdata => sample_f1_wdata,
523 -- sample_f3_wen => sample_f3_wen,
524 -- sample_f3_wdata => sample_f3_wdata,
525 -- AHB_Master_In => ahbi_ms,
526 -- AHB_Master_Out => ahbo_ms,
527
528 -- ready_matrix_f0_0 => ready_matrix_f0_0,
529 -- ready_matrix_f0_1 => ready_matrix_f0_1,
530 -- ready_matrix_f1 => ready_matrix_f1,
531 -- ready_matrix_f2 => ready_matrix_f2,
532 -- error_anticipating_empty_fifo => error_anticipating_empty_fifo,
533 -- error_bad_component_error => error_bad_component_error,
534 -- debug_reg => debug_reg,
535 -- status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
536 -- status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
537 -- status_ready_matrix_f1 => status_ready_matrix_f1,
538 -- status_ready_matrix_f2 => status_ready_matrix_f2,
539 -- status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
540 -- status_error_bad_component_error => status_error_bad_component_error,
541 -- config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
542 -- config_active_interruption_onError => config_active_interruption_onError,
543 -- addr_matrix_f0_0 => addr_matrix_f0_0,
544 -- addr_matrix_f0_1 => addr_matrix_f0_1,
545 -- addr_matrix_f1 => addr_matrix_f1,
546 -- addr_matrix_f2 => addr_matrix_f2);
547
548 END beh;
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@@ -1,415 +1,433
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
22 ----------------------------------------------------------------------------
23 LIBRARY ieee;
23 LIBRARY ieee;
24 USE ieee.std_logic_1164.ALL;
24 USE ieee.std_logic_1164.ALL;
25 USE ieee.numeric_std.ALL;
25 USE ieee.numeric_std.ALL;
26 LIBRARY grlib;
26 LIBRARY grlib;
27 USE grlib.amba.ALL;
27 USE grlib.amba.ALL;
28 USE grlib.stdlib.ALL;
28 USE grlib.stdlib.ALL;
29 USE grlib.devices.ALL;
29 USE grlib.devices.ALL;
30 LIBRARY lpp;
30 LIBRARY lpp;
31 USE lpp.lpp_amba.ALL;
31 USE lpp.lpp_amba.ALL;
32 USE lpp.apb_devices_list.ALL;
32 USE lpp.apb_devices_list.ALL;
33 USE lpp.lpp_memory.ALL;
33 USE lpp.lpp_memory.ALL;
34 LIBRARY techmap;
34 LIBRARY techmap;
35 USE techmap.gencomp.ALL;
35 USE techmap.gencomp.ALL;
36
36
37 ENTITY lpp_lfr_apbreg IS
37 ENTITY lpp_lfr_apbreg IS
38 GENERIC (
38 GENERIC (
39 nb_burst_available_size : INTEGER := 11;
39 nb_data_by_buffer_size : INTEGER := 11;
40 nb_snapshot_param_size : INTEGER := 11;
40 nb_snapshot_param_size : INTEGER := 11;
41 delta_snapshot_size : INTEGER := 16;
41 delta_vector_size : INTEGER := 20;
42 delta_f2_f0_size : INTEGER := 10;
42 delta_vector_size_f0_2 : INTEGER := 3;
43 delta_f2_f1_size : INTEGER := 10;
44
43
45 pindex : INTEGER := 4;
44 pindex : INTEGER := 4;
46 paddr : INTEGER := 4;
45 paddr : INTEGER := 4;
47 pmask : INTEGER := 16#fff#;
46 pmask : INTEGER := 16#fff#;
48 pirq_ms : INTEGER := 0;
47 pirq_ms : INTEGER := 0;
49 pirq_wfp : INTEGER := 1);
48 pirq_wfp : INTEGER := 1);
50 PORT (
49 PORT (
51 -- AMBA AHB system signals
50 -- AMBA AHB system signals
52 HCLK : IN STD_ULOGIC;
51 HCLK : IN STD_ULOGIC;
53 HRESETn : IN STD_ULOGIC;
52 HRESETn : IN STD_ULOGIC;
54
53
55 -- AMBA APB Slave Interface
54 -- AMBA APB Slave Interface
56 apbi : IN apb_slv_in_type;
55 apbi : IN apb_slv_in_type;
57 apbo : OUT apb_slv_out_type;
56 apbo : OUT apb_slv_out_type;
58
57
59 ---------------------------------------------------------------------------
58 ---------------------------------------------------------------------------
60 -- Spectral Matrix Reg
59 -- Spectral Matrix Reg
61 -- IN
60 -- IN
62 ready_matrix_f0_0 : IN STD_LOGIC;
61 ready_matrix_f0_0 : IN STD_LOGIC;
63 ready_matrix_f0_1 : IN STD_LOGIC;
62 ready_matrix_f0_1 : IN STD_LOGIC;
64 ready_matrix_f1 : IN STD_LOGIC;
63 ready_matrix_f1 : IN STD_LOGIC;
65 ready_matrix_f2 : IN STD_LOGIC;
64 ready_matrix_f2 : IN STD_LOGIC;
66 error_anticipating_empty_fifo : IN STD_LOGIC;
65 error_anticipating_empty_fifo : IN STD_LOGIC;
67 error_bad_component_error : IN STD_LOGIC;
66 error_bad_component_error : IN STD_LOGIC;
68 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
67 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
69
68
70 -- OUT
69 -- OUT
71 status_ready_matrix_f0_0 : OUT STD_LOGIC;
70 status_ready_matrix_f0_0 : OUT STD_LOGIC;
72 status_ready_matrix_f0_1 : OUT STD_LOGIC;
71 status_ready_matrix_f0_1 : OUT STD_LOGIC;
73 status_ready_matrix_f1 : OUT STD_LOGIC;
72 status_ready_matrix_f1 : OUT STD_LOGIC;
74 status_ready_matrix_f2 : OUT STD_LOGIC;
73 status_ready_matrix_f2 : OUT STD_LOGIC;
75 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
74 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
76 status_error_bad_component_error : OUT STD_LOGIC;
75 status_error_bad_component_error : OUT STD_LOGIC;
77
76
78 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
77 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
79 config_active_interruption_onError : OUT STD_LOGIC;
78 config_active_interruption_onError : OUT STD_LOGIC;
80 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
79 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
81 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
80 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
82 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
81 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
83 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
82 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
84 ---------------------------------------------------------------------------
83 ---------------------------------------------------------------------------
85 ---------------------------------------------------------------------------
84 ---------------------------------------------------------------------------
86 -- WaveForm picker Reg
85 -- WaveForm picker Reg
87 status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
86 status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
88 status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
87 status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
89 status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
88 status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
90 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
89 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
91
90
92 -- OUT
91 -- OUT
93 data_shaping_BW : OUT STD_LOGIC;
92 data_shaping_BW : OUT STD_LOGIC;
94 data_shaping_SP0 : OUT STD_LOGIC;
93 data_shaping_SP0 : OUT STD_LOGIC;
95 data_shaping_SP1 : OUT STD_LOGIC;
94 data_shaping_SP1 : OUT STD_LOGIC;
96 data_shaping_R0 : OUT STD_LOGIC;
95 data_shaping_R0 : OUT STD_LOGIC;
97 data_shaping_R1 : OUT STD_LOGIC;
96 data_shaping_R1 : OUT STD_LOGIC;
98
97
99 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
98 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
100 delta_f2_f1 : OUT STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
99 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
101 delta_f2_f0 : OUT STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
100 delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
102 nb_burst_available : OUT STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
101 delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
102 delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
103 nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
103 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
104 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
104
105
105 enable_f0 : OUT STD_LOGIC;
106 enable_f0 : OUT STD_LOGIC;
106 enable_f1 : OUT STD_LOGIC;
107 enable_f1 : OUT STD_LOGIC;
107 enable_f2 : OUT STD_LOGIC;
108 enable_f2 : OUT STD_LOGIC;
108 enable_f3 : OUT STD_LOGIC;
109 enable_f3 : OUT STD_LOGIC;
109
110
110 burst_f0 : OUT STD_LOGIC;
111 burst_f0 : OUT STD_LOGIC;
111 burst_f1 : OUT STD_LOGIC;
112 burst_f1 : OUT STD_LOGIC;
112 burst_f2 : OUT STD_LOGIC;
113 burst_f2 : OUT STD_LOGIC;
113
114
114 run : OUT STD_LOGIC;
115 run : OUT STD_LOGIC;
115
116
116 addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
117 addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
117 addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
118 addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
118 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
119 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
119 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
120 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
121 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0)
120
122
121 ---------------------------------------------------------------------------
123 ---------------------------------------------------------------------------
122 );
124 );
123
125
124 END lpp_lfr_apbreg;
126 END lpp_lfr_apbreg;
125
127
126 ARCHITECTURE beh OF lpp_lfr_apbreg IS
128 ARCHITECTURE beh OF lpp_lfr_apbreg IS
127
129
128 CONSTANT REVISION : INTEGER := 1;
130 CONSTANT REVISION : INTEGER := 1;
129
131
130 CONSTANT pconfig : apb_config_type := (
132 CONSTANT pconfig : apb_config_type := (
131 0 => ahb_device_reg (VENDOR_LPP, LPP_LFR, 2, REVISION, pirq_wfp),
133 0 => ahb_device_reg (VENDOR_LPP, LPP_LFR, 2, REVISION, pirq_wfp),
132 1 => apb_iobar(paddr, pmask));
134 1 => apb_iobar(paddr, pmask));
133
135
134 TYPE lpp_SpectralMatrix_regs IS RECORD
136 TYPE lpp_SpectralMatrix_regs IS RECORD
135 config_active_interruption_onNewMatrix : STD_LOGIC;
137 config_active_interruption_onNewMatrix : STD_LOGIC;
136 config_active_interruption_onError : STD_LOGIC;
138 config_active_interruption_onError : STD_LOGIC;
137 status_ready_matrix_f0_0 : STD_LOGIC;
139 status_ready_matrix_f0_0 : STD_LOGIC;
138 status_ready_matrix_f0_1 : STD_LOGIC;
140 status_ready_matrix_f0_1 : STD_LOGIC;
139 status_ready_matrix_f1 : STD_LOGIC;
141 status_ready_matrix_f1 : STD_LOGIC;
140 status_ready_matrix_f2 : STD_LOGIC;
142 status_ready_matrix_f2 : STD_LOGIC;
141 status_error_anticipating_empty_fifo : STD_LOGIC;
143 status_error_anticipating_empty_fifo : STD_LOGIC;
142 status_error_bad_component_error : STD_LOGIC;
144 status_error_bad_component_error : STD_LOGIC;
143 addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
145 addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
144 addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
146 addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
145 addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
147 addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
146 addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
148 addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
147 END RECORD;
149 END RECORD;
148 SIGNAL reg_sp : lpp_SpectralMatrix_regs;
150 SIGNAL reg_sp : lpp_SpectralMatrix_regs;
149
151
150 TYPE lpp_WaveformPicker_regs IS RECORD
152 TYPE lpp_WaveformPicker_regs IS RECORD
151 status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
153 status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
152 status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
154 status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
153 status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
155 status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
154 data_shaping_BW : STD_LOGIC;
156 data_shaping_BW : STD_LOGIC;
155 data_shaping_SP0 : STD_LOGIC;
157 data_shaping_SP0 : STD_LOGIC;
156 data_shaping_SP1 : STD_LOGIC;
158 data_shaping_SP1 : STD_LOGIC;
157 data_shaping_R0 : STD_LOGIC;
159 data_shaping_R0 : STD_LOGIC;
158 data_shaping_R1 : STD_LOGIC;
160 data_shaping_R1 : STD_LOGIC;
159 delta_snapshot : STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
161 delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
160 delta_f2_f1 : STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
162 delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
161 delta_f2_f0 : STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
163 delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
162 nb_burst_available : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
164 delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
165 delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
166 nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
163 nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
167 nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
164 enable_f0 : STD_LOGIC;
168 enable_f0 : STD_LOGIC;
165 enable_f1 : STD_LOGIC;
169 enable_f1 : STD_LOGIC;
166 enable_f2 : STD_LOGIC;
170 enable_f2 : STD_LOGIC;
167 enable_f3 : STD_LOGIC;
171 enable_f3 : STD_LOGIC;
168 burst_f0 : STD_LOGIC;
172 burst_f0 : STD_LOGIC;
169 burst_f1 : STD_LOGIC;
173 burst_f1 : STD_LOGIC;
170 burst_f2 : STD_LOGIC;
174 burst_f2 : STD_LOGIC;
171 run : STD_LOGIC;
175 run : STD_LOGIC;
172 addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
176 addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
173 addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
177 addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
174 addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
178 addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
175 addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
179 addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
180 start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
176 END RECORD;
181 END RECORD;
177 SIGNAL reg_wp : lpp_WaveformPicker_regs;
182 SIGNAL reg_wp : lpp_WaveformPicker_regs;
178
183
179 SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
184 SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
180
185
181 BEGIN -- beh
186 BEGIN -- beh
182
187
183 status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0;
188 status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0;
184 status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1;
189 status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1;
185 status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1;
190 status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1;
186 status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2;
191 status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2;
187 status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo;
192 status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo;
188 status_error_bad_component_error <= reg_sp.status_error_bad_component_error;
193 status_error_bad_component_error <= reg_sp.status_error_bad_component_error;
189
194
190 config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix;
195 config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix;
191 config_active_interruption_onError <= reg_sp.config_active_interruption_onError;
196 config_active_interruption_onError <= reg_sp.config_active_interruption_onError;
192 addr_matrix_f0_0 <= reg_sp.addr_matrix_f0_0;
197 addr_matrix_f0_0 <= reg_sp.addr_matrix_f0_0;
193 addr_matrix_f0_1 <= reg_sp.addr_matrix_f0_1;
198 addr_matrix_f0_1 <= reg_sp.addr_matrix_f0_1;
194 addr_matrix_f1 <= reg_sp.addr_matrix_f1;
199 addr_matrix_f1 <= reg_sp.addr_matrix_f1;
195 addr_matrix_f2 <= reg_sp.addr_matrix_f2;
200 addr_matrix_f2 <= reg_sp.addr_matrix_f2;
196
201
197
202
198 data_shaping_BW <= NOT reg_wp.data_shaping_BW;
203 data_shaping_BW <= NOT reg_wp.data_shaping_BW;
199 data_shaping_SP0 <= reg_wp.data_shaping_SP0;
204 data_shaping_SP0 <= reg_wp.data_shaping_SP0;
200 data_shaping_SP1 <= reg_wp.data_shaping_SP1;
205 data_shaping_SP1 <= reg_wp.data_shaping_SP1;
201 data_shaping_R0 <= reg_wp.data_shaping_R0;
206 data_shaping_R0 <= reg_wp.data_shaping_R0;
202 data_shaping_R1 <= reg_wp.data_shaping_R1;
207 data_shaping_R1 <= reg_wp.data_shaping_R1;
203
208
204 delta_snapshot <= reg_wp.delta_snapshot;
209 delta_snapshot <= reg_wp.delta_snapshot;
205 delta_f2_f1 <= reg_wp.delta_f2_f1;
210 delta_f0 <= reg_wp.delta_f0;
206 delta_f2_f0 <= reg_wp.delta_f2_f0;
211 delta_f0_2 <= reg_wp.delta_f0_2;
207 nb_burst_available <= reg_wp.nb_burst_available;
212 delta_f1 <= reg_wp.delta_f1;
213 delta_f2 <= reg_wp.delta_f2;
214 nb_data_by_buffer <= reg_wp.nb_data_by_buffer;
208 nb_snapshot_param <= reg_wp.nb_snapshot_param;
215 nb_snapshot_param <= reg_wp.nb_snapshot_param;
209
216
210 enable_f0 <= reg_wp.enable_f0;
217 enable_f0 <= reg_wp.enable_f0;
211 enable_f1 <= reg_wp.enable_f1;
218 enable_f1 <= reg_wp.enable_f1;
212 enable_f2 <= reg_wp.enable_f2;
219 enable_f2 <= reg_wp.enable_f2;
213 enable_f3 <= reg_wp.enable_f3;
220 enable_f3 <= reg_wp.enable_f3;
214
221
215 burst_f0 <= reg_wp.burst_f0;
222 burst_f0 <= reg_wp.burst_f0;
216 burst_f1 <= reg_wp.burst_f1;
223 burst_f1 <= reg_wp.burst_f1;
217 burst_f2 <= reg_wp.burst_f2;
224 burst_f2 <= reg_wp.burst_f2;
218
225
219 run <= reg_wp.run;
226 run <= reg_wp.run;
220
227
221 addr_data_f0 <= reg_wp.addr_data_f0;
228 addr_data_f0 <= reg_wp.addr_data_f0;
222 addr_data_f1 <= reg_wp.addr_data_f1;
229 addr_data_f1 <= reg_wp.addr_data_f1;
223 addr_data_f2 <= reg_wp.addr_data_f2;
230 addr_data_f2 <= reg_wp.addr_data_f2;
224 addr_data_f3 <= reg_wp.addr_data_f3;
231 addr_data_f3 <= reg_wp.addr_data_f3;
225
232
233 start_date <= reg_wp.start_date;
234
226 lpp_lfr_apbreg : PROCESS (HCLK, HRESETn)
235 lpp_lfr_apbreg : PROCESS (HCLK, HRESETn)
227 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
236 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
228 BEGIN -- PROCESS lpp_dma_top
237 BEGIN -- PROCESS lpp_dma_top
229 IF HRESETn = '0' THEN -- asynchronous reset (active low)
238 IF HRESETn = '0' THEN -- asynchronous reset (active low)
230 reg_sp.config_active_interruption_onNewMatrix <= '0';
239 reg_sp.config_active_interruption_onNewMatrix <= '0';
231 reg_sp.config_active_interruption_onError <= '0';
240 reg_sp.config_active_interruption_onError <= '0';
232 reg_sp.status_ready_matrix_f0_0 <= '0';
241 reg_sp.status_ready_matrix_f0_0 <= '0';
233 reg_sp.status_ready_matrix_f0_1 <= '0';
242 reg_sp.status_ready_matrix_f0_1 <= '0';
234 reg_sp.status_ready_matrix_f1 <= '0';
243 reg_sp.status_ready_matrix_f1 <= '0';
235 reg_sp.status_ready_matrix_f2 <= '0';
244 reg_sp.status_ready_matrix_f2 <= '0';
236 reg_sp.status_error_anticipating_empty_fifo <= '0';
245 reg_sp.status_error_anticipating_empty_fifo <= '0';
237 reg_sp.status_error_bad_component_error <= '0';
246 reg_sp.status_error_bad_component_error <= '0';
238 reg_sp.addr_matrix_f0_0 <= (OTHERS => '0');
247 reg_sp.addr_matrix_f0_0 <= (OTHERS => '0');
239 reg_sp.addr_matrix_f0_1 <= (OTHERS => '0');
248 reg_sp.addr_matrix_f0_1 <= (OTHERS => '0');
240 reg_sp.addr_matrix_f1 <= (OTHERS => '0');
249 reg_sp.addr_matrix_f1 <= (OTHERS => '0');
241 reg_sp.addr_matrix_f2 <= (OTHERS => '0');
250 reg_sp.addr_matrix_f2 <= (OTHERS => '0');
242 prdata <= (OTHERS => '0');
251 prdata <= (OTHERS => '0');
243
252
244 apbo.pirq <= (OTHERS => '0');
253 apbo.pirq <= (OTHERS => '0');
245
254
246 status_full_ack <= (OTHERS => '0');
255 status_full_ack <= (OTHERS => '0');
247
256
248 reg_wp.data_shaping_BW <= '0';
257 reg_wp.data_shaping_BW <= '0';
249 reg_wp.data_shaping_SP0 <= '0';
258 reg_wp.data_shaping_SP0 <= '0';
250 reg_wp.data_shaping_SP1 <= '0';
259 reg_wp.data_shaping_SP1 <= '0';
251 reg_wp.data_shaping_R0 <= '0';
260 reg_wp.data_shaping_R0 <= '0';
252 reg_wp.data_shaping_R1 <= '0';
261 reg_wp.data_shaping_R1 <= '0';
253 reg_wp.enable_f0 <= '0';
262 reg_wp.enable_f0 <= '0';
254 reg_wp.enable_f1 <= '0';
263 reg_wp.enable_f1 <= '0';
255 reg_wp.enable_f2 <= '0';
264 reg_wp.enable_f2 <= '0';
256 reg_wp.enable_f3 <= '0';
265 reg_wp.enable_f3 <= '0';
257 reg_wp.burst_f0 <= '0';
266 reg_wp.burst_f0 <= '0';
258 reg_wp.burst_f1 <= '0';
267 reg_wp.burst_f1 <= '0';
259 reg_wp.burst_f2 <= '0';
268 reg_wp.burst_f2 <= '0';
260 reg_wp.run <= '0';
269 reg_wp.run <= '0';
261 reg_wp.addr_data_f0 <= (OTHERS => '0');
270 reg_wp.addr_data_f0 <= (OTHERS => '0');
262 reg_wp.addr_data_f1 <= (OTHERS => '0');
271 reg_wp.addr_data_f1 <= (OTHERS => '0');
263 reg_wp.addr_data_f2 <= (OTHERS => '0');
272 reg_wp.addr_data_f2 <= (OTHERS => '0');
264 reg_wp.addr_data_f3 <= (OTHERS => '0');
273 reg_wp.addr_data_f3 <= (OTHERS => '0');
265 reg_wp.status_full <= (OTHERS => '0');
274 reg_wp.status_full <= (OTHERS => '0');
266 reg_wp.status_full_err <= (OTHERS => '0');
275 reg_wp.status_full_err <= (OTHERS => '0');
267 reg_wp.status_new_err <= (OTHERS => '0');
276 reg_wp.status_new_err <= (OTHERS => '0');
268 reg_wp.delta_snapshot <= (OTHERS => '0');
277 reg_wp.delta_snapshot <= (OTHERS => '0');
269 reg_wp.delta_f2_f1 <= (OTHERS => '0');
278 reg_wp.delta_f0 <= (OTHERS => '0');
270 reg_wp.delta_f2_f0 <= (OTHERS => '0');
279 reg_wp.delta_f0_2 <= (OTHERS => '0');
271 reg_wp.nb_burst_available <= (OTHERS => '0');
280 reg_wp.delta_f1 <= (OTHERS => '0');
281 reg_wp.delta_f2 <= (OTHERS => '0');
282 reg_wp.nb_data_by_buffer <= (OTHERS => '0');
272 reg_wp.nb_snapshot_param <= (OTHERS => '0');
283 reg_wp.nb_snapshot_param <= (OTHERS => '0');
284 reg_wp.start_date <= (OTHERS => '0');
273
285
274 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
286 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
275 status_full_ack <= (OTHERS => '0');
287 status_full_ack <= (OTHERS => '0');
276
288
277 reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR ready_matrix_f0_0;
289 reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR ready_matrix_f0_0;
278 reg_sp.status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1 OR ready_matrix_f0_1;
290 reg_sp.status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1 OR ready_matrix_f0_1;
279 reg_sp.status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1 OR ready_matrix_f1;
291 reg_sp.status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1 OR ready_matrix_f1;
280 reg_sp.status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2 OR ready_matrix_f2;
292 reg_sp.status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2 OR ready_matrix_f2;
281
293
282 reg_sp.status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo OR error_anticipating_empty_fifo;
294 reg_sp.status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo OR error_anticipating_empty_fifo;
283 reg_sp.status_error_bad_component_error <= reg_sp.status_error_bad_component_error OR error_bad_component_error;
295 reg_sp.status_error_bad_component_error <= reg_sp.status_error_bad_component_error OR error_bad_component_error;
284
296
285 reg_wp.status_full <= reg_wp.status_full OR status_full;
297 reg_wp.status_full <= reg_wp.status_full OR status_full;
286 reg_wp.status_full_err <= reg_wp.status_full_err OR status_full_err;
298 reg_wp.status_full_err <= reg_wp.status_full_err OR status_full_err;
287 reg_wp.status_new_err <= reg_wp.status_new_err OR status_new_err;
299 reg_wp.status_new_err <= reg_wp.status_new_err OR status_new_err;
288
300
289 paddr := "000000";
301 paddr := "000000";
290 paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
302 paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
291 prdata <= (OTHERS => '0');
303 prdata <= (OTHERS => '0');
292 IF apbi.psel(pindex) = '1' THEN
304 IF apbi.psel(pindex) = '1' THEN
293 -- APB DMA READ --
305 -- APB DMA READ --
294 CASE paddr(7 DOWNTO 2) IS
306 CASE paddr(7 DOWNTO 2) IS
295 --
307 --
296 WHEN "000000" => prdata(0) <= reg_sp.config_active_interruption_onNewMatrix;
308 WHEN "000000" => prdata(0) <= reg_sp.config_active_interruption_onNewMatrix;
297 prdata(1) <= reg_sp.config_active_interruption_onError;
309 prdata(1) <= reg_sp.config_active_interruption_onError;
298 WHEN "000001" => prdata(0) <= reg_sp.status_ready_matrix_f0_0;
310 WHEN "000001" => prdata(0) <= reg_sp.status_ready_matrix_f0_0;
299 prdata(1) <= reg_sp.status_ready_matrix_f0_1;
311 prdata(1) <= reg_sp.status_ready_matrix_f0_1;
300 prdata(2) <= reg_sp.status_ready_matrix_f1;
312 prdata(2) <= reg_sp.status_ready_matrix_f1;
301 prdata(3) <= reg_sp.status_ready_matrix_f2;
313 prdata(3) <= reg_sp.status_ready_matrix_f2;
302 prdata(4) <= reg_sp.status_error_anticipating_empty_fifo;
314 prdata(4) <= reg_sp.status_error_anticipating_empty_fifo;
303 prdata(5) <= reg_sp.status_error_bad_component_error;
315 prdata(5) <= reg_sp.status_error_bad_component_error;
304 WHEN "000010" => prdata <= reg_sp.addr_matrix_f0_0;
316 WHEN "000010" => prdata <= reg_sp.addr_matrix_f0_0;
305 WHEN "000011" => prdata <= reg_sp.addr_matrix_f0_1;
317 WHEN "000011" => prdata <= reg_sp.addr_matrix_f0_1;
306 WHEN "000100" => prdata <= reg_sp.addr_matrix_f1;
318 WHEN "000100" => prdata <= reg_sp.addr_matrix_f1;
307 WHEN "000101" => prdata <= reg_sp.addr_matrix_f2;
319 WHEN "000101" => prdata <= reg_sp.addr_matrix_f2;
308 WHEN "000110" => prdata <= debug_reg;
320 WHEN "000110" => prdata <= debug_reg;
309 --
321 --
310 WHEN "001000" => prdata(0) <= reg_wp.data_shaping_BW;
322 WHEN "001000" => prdata(0) <= reg_wp.data_shaping_BW;
311 prdata(1) <= reg_wp.data_shaping_SP0;
323 prdata(1) <= reg_wp.data_shaping_SP0;
312 prdata(2) <= reg_wp.data_shaping_SP1;
324 prdata(2) <= reg_wp.data_shaping_SP1;
313 prdata(3) <= reg_wp.data_shaping_R0;
325 prdata(3) <= reg_wp.data_shaping_R0;
314 prdata(4) <= reg_wp.data_shaping_R1;
326 prdata(4) <= reg_wp.data_shaping_R1;
315 WHEN "001001" => prdata(0) <= reg_wp.enable_f0;
327 WHEN "001001" => prdata(0) <= reg_wp.enable_f0;
316 prdata(1) <= reg_wp.enable_f1;
328 prdata(1) <= reg_wp.enable_f1;
317 prdata(2) <= reg_wp.enable_f2;
329 prdata(2) <= reg_wp.enable_f2;
318 prdata(3) <= reg_wp.enable_f3;
330 prdata(3) <= reg_wp.enable_f3;
319 prdata(4) <= reg_wp.burst_f0;
331 prdata(4) <= reg_wp.burst_f0;
320 prdata(5) <= reg_wp.burst_f1;
332 prdata(5) <= reg_wp.burst_f1;
321 prdata(6) <= reg_wp.burst_f2;
333 prdata(6) <= reg_wp.burst_f2;
322 prdata(7) <= reg_wp.run;
334 prdata(7) <= reg_wp.run;
323 WHEN "001010" => prdata <= reg_wp.addr_data_f0;
335 WHEN "001010" => prdata <= reg_wp.addr_data_f0;
324 WHEN "001011" => prdata <= reg_wp.addr_data_f1;
336 WHEN "001011" => prdata <= reg_wp.addr_data_f1;
325 WHEN "001100" => prdata <= reg_wp.addr_data_f2;
337 WHEN "001100" => prdata <= reg_wp.addr_data_f2;
326 WHEN "001101" => prdata <= reg_wp.addr_data_f3;
338 WHEN "001101" => prdata <= reg_wp.addr_data_f3;
327 WHEN "001110" => prdata(3 DOWNTO 0) <= reg_wp.status_full;
339 WHEN "001110" => prdata(3 DOWNTO 0) <= reg_wp.status_full;
328 prdata(7 DOWNTO 4) <= reg_wp.status_full_err;
340 prdata(7 DOWNTO 4) <= reg_wp.status_full_err;
329 prdata(11 DOWNTO 8) <= reg_wp.status_new_err;
341 prdata(11 DOWNTO 8) <= reg_wp.status_new_err;
330 WHEN "001111" => prdata(delta_snapshot_size-1 DOWNTO 0) <= reg_wp.delta_snapshot;
342 WHEN "001111" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_snapshot;
331 WHEN "010000" => prdata(delta_f2_f1_size-1 DOWNTO 0) <= reg_wp.delta_f2_f1;
343 WHEN "010000" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f0;
332 WHEN "010001" => prdata(delta_f2_f0_size-1 DOWNTO 0) <= reg_wp.delta_f2_f0;
344 WHEN "010001" => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2;
333 WHEN "010010" => prdata(nb_burst_available_size-1 DOWNTO 0) <= reg_wp.nb_burst_available;
345 WHEN "010010" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f1;
334 WHEN "010011" => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param;
346 WHEN "010011" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2;
347 WHEN "010100" => prdata(nb_data_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_data_by_buffer;
348 WHEN "010101" => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param;
349 WHEN "010110" => prdata(30 DOWNTO 0) <= reg_wp.start_date;
335 --
350 --
336 WHEN OTHERS => NULL;
351 WHEN OTHERS => NULL;
337 END CASE;
352 END CASE;
338 IF (apbi.pwrite AND apbi.penable) = '1' THEN
353 IF (apbi.pwrite AND apbi.penable) = '1' THEN
339 -- APB DMA WRITE --
354 -- APB DMA WRITE --
340 CASE paddr(7 DOWNTO 2) IS
355 CASE paddr(7 DOWNTO 2) IS
341 --
356 --
342 WHEN "000000" => reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0);
357 WHEN "000000" => reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0);
343 reg_sp.config_active_interruption_onError <= apbi.pwdata(1);
358 reg_sp.config_active_interruption_onError <= apbi.pwdata(1);
344 WHEN "000001" => reg_sp.status_ready_matrix_f0_0 <= apbi.pwdata(0);
359 WHEN "000001" => reg_sp.status_ready_matrix_f0_0 <= apbi.pwdata(0);
345 reg_sp.status_ready_matrix_f0_1 <= apbi.pwdata(1);
360 reg_sp.status_ready_matrix_f0_1 <= apbi.pwdata(1);
346 reg_sp.status_ready_matrix_f1 <= apbi.pwdata(2);
361 reg_sp.status_ready_matrix_f1 <= apbi.pwdata(2);
347 reg_sp.status_ready_matrix_f2 <= apbi.pwdata(3);
362 reg_sp.status_ready_matrix_f2 <= apbi.pwdata(3);
348 reg_sp.status_error_anticipating_empty_fifo <= apbi.pwdata(4);
363 reg_sp.status_error_anticipating_empty_fifo <= apbi.pwdata(4);
349 reg_sp.status_error_bad_component_error <= apbi.pwdata(5);
364 reg_sp.status_error_bad_component_error <= apbi.pwdata(5);
350 WHEN "000010" => reg_sp.addr_matrix_f0_0 <= apbi.pwdata;
365 WHEN "000010" => reg_sp.addr_matrix_f0_0 <= apbi.pwdata;
351 WHEN "000011" => reg_sp.addr_matrix_f0_1 <= apbi.pwdata;
366 WHEN "000011" => reg_sp.addr_matrix_f0_1 <= apbi.pwdata;
352 WHEN "000100" => reg_sp.addr_matrix_f1 <= apbi.pwdata;
367 WHEN "000100" => reg_sp.addr_matrix_f1 <= apbi.pwdata;
353 WHEN "000101" => reg_sp.addr_matrix_f2 <= apbi.pwdata;
368 WHEN "000101" => reg_sp.addr_matrix_f2 <= apbi.pwdata;
354 --
369 --
355 WHEN "001000" => reg_wp.data_shaping_BW <= apbi.pwdata(0);
370 WHEN "001000" => reg_wp.data_shaping_BW <= apbi.pwdata(0);
356 reg_wp.data_shaping_SP0 <= apbi.pwdata(1);
371 reg_wp.data_shaping_SP0 <= apbi.pwdata(1);
357 reg_wp.data_shaping_SP1 <= apbi.pwdata(2);
372 reg_wp.data_shaping_SP1 <= apbi.pwdata(2);
358 reg_wp.data_shaping_R0 <= apbi.pwdata(3);
373 reg_wp.data_shaping_R0 <= apbi.pwdata(3);
359 reg_wp.data_shaping_R1 <= apbi.pwdata(4);
374 reg_wp.data_shaping_R1 <= apbi.pwdata(4);
360 WHEN "001001" => reg_wp.enable_f0 <= apbi.pwdata(0);
375 WHEN "001001" => reg_wp.enable_f0 <= apbi.pwdata(0);
361 reg_wp.enable_f1 <= apbi.pwdata(1);
376 reg_wp.enable_f1 <= apbi.pwdata(1);
362 reg_wp.enable_f2 <= apbi.pwdata(2);
377 reg_wp.enable_f2 <= apbi.pwdata(2);
363 reg_wp.enable_f3 <= apbi.pwdata(3);
378 reg_wp.enable_f3 <= apbi.pwdata(3);
364 reg_wp.burst_f0 <= apbi.pwdata(4);
379 reg_wp.burst_f0 <= apbi.pwdata(4);
365 reg_wp.burst_f1 <= apbi.pwdata(5);
380 reg_wp.burst_f1 <= apbi.pwdata(5);
366 reg_wp.burst_f2 <= apbi.pwdata(6);
381 reg_wp.burst_f2 <= apbi.pwdata(6);
367 reg_wp.run <= apbi.pwdata(7);
382 reg_wp.run <= apbi.pwdata(7);
368 WHEN "001010" => reg_wp.addr_data_f0 <= apbi.pwdata;
383 WHEN "001010" => reg_wp.addr_data_f0 <= apbi.pwdata;
369 WHEN "001011" => reg_wp.addr_data_f1 <= apbi.pwdata;
384 WHEN "001011" => reg_wp.addr_data_f1 <= apbi.pwdata;
370 WHEN "001100" => reg_wp.addr_data_f2 <= apbi.pwdata;
385 WHEN "001100" => reg_wp.addr_data_f2 <= apbi.pwdata;
371 WHEN "001101" => reg_wp.addr_data_f3 <= apbi.pwdata;
386 WHEN "001101" => reg_wp.addr_data_f3 <= apbi.pwdata;
372 WHEN "001110" => reg_wp.status_full <= apbi.pwdata(3 DOWNTO 0);
387 WHEN "001110" => reg_wp.status_full <= apbi.pwdata(3 DOWNTO 0);
373 reg_wp.status_full_err <= apbi.pwdata(7 DOWNTO 4);
388 reg_wp.status_full_err <= apbi.pwdata(7 DOWNTO 4);
374 reg_wp.status_new_err <= apbi.pwdata(11 DOWNTO 8);
389 reg_wp.status_new_err <= apbi.pwdata(11 DOWNTO 8);
375 status_full_ack(0) <= reg_wp.status_full(0) AND NOT apbi.pwdata(0);
390 status_full_ack(0) <= reg_wp.status_full(0) AND NOT apbi.pwdata(0);
376 status_full_ack(1) <= reg_wp.status_full(1) AND NOT apbi.pwdata(1);
391 status_full_ack(1) <= reg_wp.status_full(1) AND NOT apbi.pwdata(1);
377 status_full_ack(2) <= reg_wp.status_full(2) AND NOT apbi.pwdata(2);
392 status_full_ack(2) <= reg_wp.status_full(2) AND NOT apbi.pwdata(2);
378 status_full_ack(3) <= reg_wp.status_full(3) AND NOT apbi.pwdata(3);
393 status_full_ack(3) <= reg_wp.status_full(3) AND NOT apbi.pwdata(3);
379 WHEN "001111" => reg_wp.delta_snapshot <= apbi.pwdata(delta_snapshot_size-1 DOWNTO 0);
394 WHEN "001111" => reg_wp.delta_snapshot <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
380 WHEN "010000" => reg_wp.delta_f2_f1 <= apbi.pwdata(delta_f2_f1_size-1 DOWNTO 0);
395 WHEN "010000" => reg_wp.delta_f0 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
381 WHEN "010001" => reg_wp.delta_f2_f0 <= apbi.pwdata(delta_f2_f0_size-1 DOWNTO 0);
396 WHEN "010001" => reg_wp.delta_f0_2 <= apbi.pwdata(delta_vector_size_f0_2-1 DOWNTO 0);
382 WHEN "010010" => reg_wp.nb_burst_available <= apbi.pwdata(nb_burst_available_size-1 DOWNTO 0);
397 WHEN "010010" => reg_wp.delta_f1 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
383 WHEN "010011" => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0);
398 WHEN "010011" => reg_wp.delta_f2 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
399 WHEN "010100" => reg_wp.nb_data_by_buffer <= apbi.pwdata(nb_data_by_buffer_size-1 DOWNTO 0);
400 WHEN "010101" => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0);
401 WHEN "010110" => reg_wp.start_date <= apbi.pwdata(30 DOWNTO 0);
384 --
402 --
385 WHEN OTHERS => NULL;
403 WHEN OTHERS => NULL;
386 END CASE;
404 END CASE;
387 END IF;
405 END IF;
388 END IF;
406 END IF;
389
407
390 apbo.pirq(pirq_ms) <= (reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0_0 OR
408 apbo.pirq(pirq_ms) <= (reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0_0 OR
391 ready_matrix_f0_1 OR
409 ready_matrix_f0_1 OR
392 ready_matrix_f1 OR
410 ready_matrix_f1 OR
393 ready_matrix_f2)
411 ready_matrix_f2)
394 )
412 )
395 OR
413 OR
396 (reg_sp.config_active_interruption_onError AND (error_anticipating_empty_fifo OR
414 (reg_sp.config_active_interruption_onError AND (error_anticipating_empty_fifo OR
397 error_bad_component_error)
415 error_bad_component_error)
398 );
416 );
399
417
400 apbo.pirq(pirq_wfp) <= (status_full(0) OR status_full_err(0) OR status_new_err(0) OR
418 apbo.pirq(pirq_wfp) <= (status_full(0) OR status_full_err(0) OR status_new_err(0) OR
401 status_full(1) OR status_full_err(1) OR status_new_err(1) OR
419 status_full(1) OR status_full_err(1) OR status_new_err(1) OR
402 status_full(2) OR status_full_err(2) OR status_new_err(2) OR
420 status_full(2) OR status_full_err(2) OR status_new_err(2) OR
403 status_full(3) OR status_full_err(3) OR status_new_err(3)
421 status_full(3) OR status_full_err(3) OR status_new_err(3)
404 );
422 );
405
423
406
424
407 END IF;
425 END IF;
408 END PROCESS lpp_lfr_apbreg;
426 END PROCESS lpp_lfr_apbreg;
409
427
410 apbo.pindex <= pindex;
428 apbo.pindex <= pindex;
411 apbo.pconfig <= pconfig;
429 apbo.pconfig <= pconfig;
412 apbo.prdata <= prdata;
430 apbo.prdata <= prdata;
413
431
414
432
415 END beh; No newline at end of file
433 END beh;
Show file before | Show file after | Hide comments
@@ -1,197 +1,196
1 LIBRARY ieee;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
2 USE ieee.std_logic_1164.ALL;
3
3
4 LIBRARY grlib;
4 LIBRARY grlib;
5 USE grlib.amba.ALL;
5 USE grlib.amba.ALL;
6
6
7 LIBRARY lpp;
7 LIBRARY lpp;
8 USE lpp.lpp_ad_conv.ALL;
8 USE lpp.lpp_ad_conv.ALL;
9 USE lpp.iir_filter.ALL;
9 USE lpp.iir_filter.ALL;
10 USE lpp.FILTERcfg.ALL;
10 USE lpp.FILTERcfg.ALL;
11 USE lpp.lpp_memory.ALL;
11 USE lpp.lpp_memory.ALL;
12 LIBRARY techmap;
12 LIBRARY techmap;
13 USE techmap.gencomp.ALL;
13 USE techmap.gencomp.ALL;
14
14
15 PACKAGE lpp_lfr_pkg IS
15 PACKAGE lpp_lfr_pkg IS
16
16
17 COMPONENT lpp_lfr_ms
17 COMPONENT lpp_lfr_ms
18 GENERIC (
18 GENERIC (
19 hindex : INTEGER);
19 hindex : INTEGER);
20 PORT (
20 PORT (
21 clk : IN STD_LOGIC;
21 clk : IN STD_LOGIC;
22 rstn : IN STD_LOGIC;
22 rstn : IN STD_LOGIC;
23 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
23 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
24 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
24 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
25 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
25 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
26 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
26 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
27 sample_f3_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
27 sample_f3_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
28 sample_f3_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
28 sample_f3_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
29 AHB_Master_In : IN AHB_Mst_In_Type;
29 AHB_Master_In : IN AHB_Mst_In_Type;
30 AHB_Master_Out : OUT AHB_Mst_Out_Type;
30 AHB_Master_Out : OUT AHB_Mst_Out_Type;
31 ready_matrix_f0_0 : OUT STD_LOGIC;
31 ready_matrix_f0_0 : OUT STD_LOGIC;
32 ready_matrix_f0_1 : OUT STD_LOGIC;
32 ready_matrix_f0_1 : OUT STD_LOGIC;
33 ready_matrix_f1 : OUT STD_LOGIC;
33 ready_matrix_f1 : OUT STD_LOGIC;
34 ready_matrix_f2 : OUT STD_LOGIC;
34 ready_matrix_f2 : OUT STD_LOGIC;
35 error_anticipating_empty_fifo : OUT STD_LOGIC;
35 error_anticipating_empty_fifo : OUT STD_LOGIC;
36 error_bad_component_error : OUT STD_LOGIC;
36 error_bad_component_error : OUT STD_LOGIC;
37 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
37 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
38 status_ready_matrix_f0_0 : IN STD_LOGIC;
38 status_ready_matrix_f0_0 : IN STD_LOGIC;
39 status_ready_matrix_f0_1 : IN STD_LOGIC;
39 status_ready_matrix_f0_1 : IN STD_LOGIC;
40 status_ready_matrix_f1 : IN STD_LOGIC;
40 status_ready_matrix_f1 : IN STD_LOGIC;
41 status_ready_matrix_f2 : IN STD_LOGIC;
41 status_ready_matrix_f2 : IN STD_LOGIC;
42 status_error_anticipating_empty_fifo : IN STD_LOGIC;
42 status_error_anticipating_empty_fifo : IN STD_LOGIC;
43 status_error_bad_component_error : IN STD_LOGIC;
43 status_error_bad_component_error : IN STD_LOGIC;
44 config_active_interruption_onNewMatrix : IN STD_LOGIC;
44 config_active_interruption_onNewMatrix : IN STD_LOGIC;
45 config_active_interruption_onError : IN STD_LOGIC;
45 config_active_interruption_onError : IN STD_LOGIC;
46 addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
46 addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
47 addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
47 addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
48 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
48 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
49 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
49 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
50 END COMPONENT;
50 END COMPONENT;
51
51
52 COMPONENT lpp_lfr_filter
52 COMPONENT lpp_lfr_filter
53 GENERIC (
53 GENERIC (
54 Mem_use : INTEGER);
54 Mem_use : INTEGER);
55 PORT (
55 PORT (
56 sample : IN Samples(7 DOWNTO 0);
56 sample : IN Samples(7 DOWNTO 0);
57 sample_val : IN STD_LOGIC;
57 sample_val : IN STD_LOGIC;
58 clk : IN STD_LOGIC;
58 clk : IN STD_LOGIC;
59 rstn : IN STD_LOGIC;
59 rstn : IN STD_LOGIC;
60 data_shaping_SP0 : IN STD_LOGIC;
60 data_shaping_SP0 : IN STD_LOGIC;
61 data_shaping_SP1 : IN STD_LOGIC;
61 data_shaping_SP1 : IN STD_LOGIC;
62 data_shaping_R0 : IN STD_LOGIC;
62 data_shaping_R0 : IN STD_LOGIC;
63 data_shaping_R1 : IN STD_LOGIC;
63 data_shaping_R1 : IN STD_LOGIC;
64 sample_f0_val : OUT STD_LOGIC;
64 sample_f0_val : OUT STD_LOGIC;
65 sample_f1_val : OUT STD_LOGIC;
65 sample_f1_val : OUT STD_LOGIC;
66 sample_f2_val : OUT STD_LOGIC;
66 sample_f2_val : OUT STD_LOGIC;
67 sample_f3_val : OUT STD_LOGIC;
67 sample_f3_val : OUT STD_LOGIC;
68 sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
68 sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
69 sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
69 sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
70 sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
70 sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
71 sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0));
71 sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0));
72 END COMPONENT;
72 END COMPONENT;
73
73
74 COMPONENT lpp_lfr
74 COMPONENT lpp_lfr
75 GENERIC (
75 GENERIC (
76 Mem_use : INTEGER;
76 Mem_use : INTEGER;
77 nb_burst_available_size : INTEGER;
77 nb_data_by_buffer_size : INTEGER;
78 nb_snapshot_param_size : INTEGER;
78 nb_snapshot_param_size : INTEGER;
79 delta_snapshot_size : INTEGER;
79 delta_vector_size : INTEGER;
80 delta_f2_f0_size : INTEGER;
80 delta_vector_size_f0_2 : INTEGER;
81 delta_f2_f1_size : INTEGER;
81 pindex : INTEGER;
82 pindex : INTEGER;
82 paddr : INTEGER;
83 paddr : INTEGER;
83 pmask : INTEGER;
84 pmask : INTEGER;
84 pirq_ms : INTEGER;
85 pirq_ms : INTEGER;
85 pirq_wfp : INTEGER;
86 pirq_wfp : INTEGER;
86 hindex : INTEGER);
87 hindex_wfp : INTEGER;
88 hindex_ms : INTEGER);
89 PORT (
87 PORT (
90 clk : IN STD_LOGIC;
88 clk : IN STD_LOGIC;
91 rstn : IN STD_LOGIC;
89 rstn : IN STD_LOGIC;
92 sample_B : IN Samples14v(2 DOWNTO 0);
90 sample_B : IN Samples14v(2 DOWNTO 0);
93 sample_E : IN Samples14v(4 DOWNTO 0);
91 sample_E : IN Samples14v(4 DOWNTO 0);
94 sample_val : IN STD_LOGIC;
92 sample_val : IN STD_LOGIC;
95 apbi : IN apb_slv_in_type;
93 apbi : IN apb_slv_in_type;
96 apbo : OUT apb_slv_out_type;
94 apbo : OUT apb_slv_out_type;
97 ahbi_wfp : IN AHB_Mst_In_Type;
95 ahbi : IN AHB_Mst_In_Type;
98 ahbo_wfp : OUT AHB_Mst_Out_Type;
96 ahbo : OUT AHB_Mst_Out_Type;
99 ahbi_ms : IN AHB_Mst_In_Type;
97 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
100 ahbo_ms : OUT AHB_Mst_Out_Type;
98 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
101 coarse_time_0 : IN STD_LOGIC;
102 data_shaping_BW : OUT STD_LOGIC);
99 data_shaping_BW : OUT STD_LOGIC);
103 END COMPONENT;
100 END COMPONENT;
104
101
105 COMPONENT lpp_lfr_apbreg
102 COMPONENT lpp_lfr_apbreg
106 GENERIC (
103 GENERIC (
107 nb_burst_available_size : INTEGER;
104 nb_data_by_buffer_size : INTEGER;
108 nb_snapshot_param_size : INTEGER;
105 nb_snapshot_param_size : INTEGER;
109 delta_snapshot_size : INTEGER;
106 delta_vector_size : INTEGER;
110 delta_f2_f0_size : INTEGER;
107 delta_vector_size_f0_2 : INTEGER;
111 delta_f2_f1_size : INTEGER;
108 pindex : INTEGER;
112 pindex : INTEGER;
109 paddr : INTEGER;
113 paddr : INTEGER;
110 pmask : INTEGER;
114 pmask : INTEGER;
111 pirq_ms : INTEGER;
115 pirq_ms : INTEGER;
112 pirq_wfp : INTEGER);
116 pirq_wfp : INTEGER);
117 PORT (
113 PORT (
118 HCLK : IN STD_ULOGIC;
114 HCLK : IN STD_ULOGIC;
119 HRESETn : IN STD_ULOGIC;
115 HRESETn : IN STD_ULOGIC;
120 apbi : IN apb_slv_in_type;
116 apbi : IN apb_slv_in_type;
121 apbo : OUT apb_slv_out_type;
117 apbo : OUT apb_slv_out_type;
122 ready_matrix_f0_0 : IN STD_LOGIC;
118 ready_matrix_f0_0 : IN STD_LOGIC;
123 ready_matrix_f0_1 : IN STD_LOGIC;
119 ready_matrix_f0_1 : IN STD_LOGIC;
124 ready_matrix_f1 : IN STD_LOGIC;
120 ready_matrix_f1 : IN STD_LOGIC;
125 ready_matrix_f2 : IN STD_LOGIC;
121 ready_matrix_f2 : IN STD_LOGIC;
126 error_anticipating_empty_fifo : IN STD_LOGIC;
122 error_anticipating_empty_fifo : IN STD_LOGIC;
127 error_bad_component_error : IN STD_LOGIC;
123 error_bad_component_error : IN STD_LOGIC;
128 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
124 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
129 status_ready_matrix_f0_0 : OUT STD_LOGIC;
125 status_ready_matrix_f0_0 : OUT STD_LOGIC;
130 status_ready_matrix_f0_1 : OUT STD_LOGIC;
126 status_ready_matrix_f0_1 : OUT STD_LOGIC;
131 status_ready_matrix_f1 : OUT STD_LOGIC;
127 status_ready_matrix_f1 : OUT STD_LOGIC;
132 status_ready_matrix_f2 : OUT STD_LOGIC;
128 status_ready_matrix_f2 : OUT STD_LOGIC;
133 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
129 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
134 status_error_bad_component_error : OUT STD_LOGIC;
130 status_error_bad_component_error : OUT STD_LOGIC;
135 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
131 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
136 config_active_interruption_onError : OUT STD_LOGIC;
132 config_active_interruption_onError : OUT STD_LOGIC;
137 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
133 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
138 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
134 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
139 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
135 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
140 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
136 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
141 status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
137 status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
142 status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
138 status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
143 status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
139 status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
144 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
140 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
145 data_shaping_BW : OUT STD_LOGIC;
141 data_shaping_BW : OUT STD_LOGIC;
146 data_shaping_SP0 : OUT STD_LOGIC;
142 data_shaping_SP0 : OUT STD_LOGIC;
147 data_shaping_SP1 : OUT STD_LOGIC;
143 data_shaping_SP1 : OUT STD_LOGIC;
148 data_shaping_R0 : OUT STD_LOGIC;
144 data_shaping_R0 : OUT STD_LOGIC;
149 data_shaping_R1 : OUT STD_LOGIC;
145 data_shaping_R1 : OUT STD_LOGIC;
150 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
146 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
151 delta_f2_f1 : OUT STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
147 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
152 delta_f2_f0 : OUT STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
148 delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
153 nb_burst_available : OUT STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
149 delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
150 delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
151 nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
154 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
152 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
155 enable_f0 : OUT STD_LOGIC;
153 enable_f0 : OUT STD_LOGIC;
156 enable_f1 : OUT STD_LOGIC;
154 enable_f1 : OUT STD_LOGIC;
157 enable_f2 : OUT STD_LOGIC;
155 enable_f2 : OUT STD_LOGIC;
158 enable_f3 : OUT STD_LOGIC;
156 enable_f3 : OUT STD_LOGIC;
159 burst_f0 : OUT STD_LOGIC;
157 burst_f0 : OUT STD_LOGIC;
160 burst_f1 : OUT STD_LOGIC;
158 burst_f1 : OUT STD_LOGIC;
161 burst_f2 : OUT STD_LOGIC;
159 burst_f2 : OUT STD_LOGIC;
162 run : OUT STD_LOGIC;
160 run : OUT STD_LOGIC;
163 addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
161 addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
164 addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
162 addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
165 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
163 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
166 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
164 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
165 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0));
167 END COMPONENT;
166 END COMPONENT;
168
167
169 COMPONENT lpp_top_ms
168 COMPONENT lpp_top_ms
170 GENERIC (
169 GENERIC (
171 Mem_use : INTEGER;
170 Mem_use : INTEGER;
172 nb_burst_available_size : INTEGER;
171 nb_burst_available_size : INTEGER;
173 nb_snapshot_param_size : INTEGER;
172 nb_snapshot_param_size : INTEGER;
174 delta_snapshot_size : INTEGER;
173 delta_snapshot_size : INTEGER;
175 delta_f2_f0_size : INTEGER;
174 delta_f2_f0_size : INTEGER;
176 delta_f2_f1_size : INTEGER;
175 delta_f2_f1_size : INTEGER;
177 pindex : INTEGER;
176 pindex : INTEGER;
178 paddr : INTEGER;
177 paddr : INTEGER;
179 pmask : INTEGER;
178 pmask : INTEGER;
180 pirq_ms : INTEGER;
179 pirq_ms : INTEGER;
181 pirq_wfp : INTEGER;
180 pirq_wfp : INTEGER;
182 hindex_wfp : INTEGER;
181 hindex_wfp : INTEGER;
183 hindex_ms : INTEGER);
182 hindex_ms : INTEGER);
184 PORT (
183 PORT (
185 clk : IN STD_LOGIC;
184 clk : IN STD_LOGIC;
186 rstn : IN STD_LOGIC;
185 rstn : IN STD_LOGIC;
187 sample_B : IN Samples14v(2 DOWNTO 0);
186 sample_B : IN Samples14v(2 DOWNTO 0);
188 sample_E : IN Samples14v(4 DOWNTO 0);
187 sample_E : IN Samples14v(4 DOWNTO 0);
189 sample_val : IN STD_LOGIC;
188 sample_val : IN STD_LOGIC;
190 apbi : IN apb_slv_in_type;
189 apbi : IN apb_slv_in_type;
191 apbo : OUT apb_slv_out_type;
190 apbo : OUT apb_slv_out_type;
192 ahbi_ms : IN AHB_Mst_In_Type;
191 ahbi_ms : IN AHB_Mst_In_Type;
193 ahbo_ms : OUT AHB_Mst_Out_Type;
192 ahbo_ms : OUT AHB_Mst_Out_Type;
194 data_shaping_BW : OUT STD_LOGIC);
193 data_shaping_BW : OUT STD_LOGIC);
195 END COMPONENT;
194 END COMPONENT;
196
195
197 END lpp_lfr_pkg;
196 END lpp_lfr_pkg;
Show file before | Show file after | Hide comments
@@ -1,278 +1,216
1 LIBRARY ieee;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
2 USE ieee.std_logic_1164.ALL;
3
3
4 LIBRARY grlib;
4 LIBRARY grlib;
5 USE grlib.amba.ALL;
5 USE grlib.amba.ALL;
6
6
7 LIBRARY lpp;
7 LIBRARY lpp;
8 USE lpp.lpp_ad_conv.ALL;
8 USE lpp.lpp_ad_conv.ALL;
9 USE lpp.iir_filter.ALL;
9 USE lpp.iir_filter.ALL;
10 USE lpp.FILTERcfg.ALL;
10 USE lpp.FILTERcfg.ALL;
11 USE lpp.lpp_memory.ALL;
11 USE lpp.lpp_memory.ALL;
12 LIBRARY techmap;
12 LIBRARY techmap;
13 USE techmap.gencomp.ALL;
13 USE techmap.gencomp.ALL;
14
14
15 PACKAGE lpp_top_lfr_pkg IS
15 PACKAGE lpp_top_lfr_pkg IS
16
16
17 COMPONENT lpp_top_acq
17 COMPONENT lpp_top_acq
18 GENERIC(
18 GENERIC(
19 tech : INTEGER := 0;
19 tech : INTEGER := 0;
20 Mem_use : integer := use_RAM
20 Mem_use : integer := use_RAM
21 );
21 );
22 PORT (
22 PORT (
23 -- ADS7886
23 -- ADS7886
24 cnv_run : IN STD_LOGIC;
24 cnv_run : IN STD_LOGIC;
25 cnv : OUT STD_LOGIC;
25 cnv : OUT STD_LOGIC;
26 sck : OUT STD_LOGIC;
26 sck : OUT STD_LOGIC;
27 sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
27 sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
28 --
28 --
29 cnv_clk : IN STD_LOGIC; -- 49 MHz
29 cnv_clk : IN STD_LOGIC; -- 49 MHz
30 cnv_rstn : IN STD_LOGIC;
30 cnv_rstn : IN STD_LOGIC;
31 --
31 --
32 clk : IN STD_LOGIC; -- 25 MHz
32 clk : IN STD_LOGIC; -- 25 MHz
33 rstn : IN STD_LOGIC;
33 rstn : IN STD_LOGIC;
34 --
34 --
35 sample_f0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
35 sample_f0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
36 sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
36 sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
37 --
37 --
38 sample_f1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
38 sample_f1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
39 sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
39 sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
40 --
40 --
41 sample_f2_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
41 sample_f2_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
42 sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
42 sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
43 --
43 --
44 sample_f3_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
44 sample_f3_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
45 sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0)
45 sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0)
46 );
46 );
47 END COMPONENT;
47 END COMPONENT;
48
48
49 COMPONENT lpp_top_apbreg
50 GENERIC (
51 nb_burst_available_size : INTEGER;
52 nb_snapshot_param_size : INTEGER;
53 delta_snapshot_size : INTEGER;
54 delta_f2_f0_size : INTEGER;
55 delta_f2_f1_size : INTEGER;
56 pindex : INTEGER;
57 paddr : INTEGER;
58 pmask : INTEGER;
59 pirq : INTEGER);
60 PORT (
61 HCLK : IN STD_ULOGIC;
62 HRESETn : IN STD_ULOGIC;
63 apbi : IN apb_slv_in_type;
64 apbo : OUT apb_slv_out_type;
65 ready_matrix_f0_0 : IN STD_LOGIC;
66 ready_matrix_f0_1 : IN STD_LOGIC;
67 ready_matrix_f1 : IN STD_LOGIC;
68 ready_matrix_f2 : IN STD_LOGIC;
69 error_anticipating_empty_fifo : IN STD_LOGIC;
70 error_bad_component_error : IN STD_LOGIC;
71 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
72 status_ready_matrix_f0_0 : OUT STD_LOGIC;
73 status_ready_matrix_f0_1 : OUT STD_LOGIC;
74 status_ready_matrix_f1 : OUT STD_LOGIC;
75 status_ready_matrix_f2 : OUT STD_LOGIC;
76 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
77 status_error_bad_component_error : OUT STD_LOGIC;
78 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
79 config_active_interruption_onError : OUT STD_LOGIC;
80 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
81 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
82 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
83 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
84 status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
85 status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
86 status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
87 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
88 data_shaping_BW : OUT STD_LOGIC;
89 data_shaping_SP0 : OUT STD_LOGIC;
90 data_shaping_SP1 : OUT STD_LOGIC;
91 data_shaping_R0 : OUT STD_LOGIC;
92 data_shaping_R1 : OUT STD_LOGIC;
93 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
94 delta_f2_f1 : OUT STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
95 delta_f2_f0 : OUT STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
96 nb_burst_available : OUT STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
97 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
98 enable_f0 : OUT STD_LOGIC;
99 enable_f1 : OUT STD_LOGIC;
100 enable_f2 : OUT STD_LOGIC;
101 enable_f3 : OUT STD_LOGIC;
102 burst_f0 : OUT STD_LOGIC;
103 burst_f1 : OUT STD_LOGIC;
104 burst_f2 : OUT STD_LOGIC;
105 addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
106 addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
107 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
108 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
109 END COMPONENT;
110
111 COMPONENT lpp_top_lfr_wf_picker
49 COMPONENT lpp_top_lfr_wf_picker
112 GENERIC (
50 GENERIC (
113 hindex : INTEGER;
51 hindex : INTEGER;
114 pindex : INTEGER;
52 pindex : INTEGER;
115 paddr : INTEGER;
53 paddr : INTEGER;
116 pmask : INTEGER;
54 pmask : INTEGER;
117 pirq : INTEGER;
55 pirq : INTEGER;
118 tech : INTEGER;
56 tech : INTEGER;
119 nb_burst_available_size : INTEGER;
57 nb_burst_available_size : INTEGER;
120 nb_snapshot_param_size : INTEGER;
58 nb_snapshot_param_size : INTEGER;
121 delta_snapshot_size : INTEGER;
59 delta_snapshot_size : INTEGER;
122 delta_f2_f0_size : INTEGER;
60 delta_f2_f0_size : INTEGER;
123 delta_f2_f1_size : INTEGER;
61 delta_f2_f1_size : INTEGER;
124 ENABLE_FILTER : STD_LOGIC);
62 ENABLE_FILTER : STD_LOGIC);
125 PORT (
63 PORT (
126 cnv_run : IN STD_LOGIC;
64 cnv_run : IN STD_LOGIC;
127 cnv : OUT STD_LOGIC;
65 cnv : OUT STD_LOGIC;
128 sck : OUT STD_LOGIC;
66 sck : OUT STD_LOGIC;
129 sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
67 sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
130 cnv_clk : IN STD_LOGIC;
68 cnv_clk : IN STD_LOGIC;
131 cnv_rstn : IN STD_LOGIC;
69 cnv_rstn : IN STD_LOGIC;
132 HCLK : IN STD_ULOGIC;
70 HCLK : IN STD_ULOGIC;
133 HRESETn : IN STD_ULOGIC;
71 HRESETn : IN STD_ULOGIC;
134 apbi : IN apb_slv_in_type;
72 apbi : IN apb_slv_in_type;
135 apbo : OUT apb_slv_out_type;
73 apbo : OUT apb_slv_out_type;
136 AHB_Master_In : IN AHB_Mst_In_Type;
74 AHB_Master_In : IN AHB_Mst_In_Type;
137 AHB_Master_Out : OUT AHB_Mst_Out_Type;
75 AHB_Master_Out : OUT AHB_Mst_Out_Type;
138 coarse_time_0 : IN STD_LOGIC;
76 coarse_time_0 : IN STD_LOGIC;
139 data_shaping_BW : OUT STD_LOGIC);
77 data_shaping_BW : OUT STD_LOGIC);
140 END COMPONENT;
78 END COMPONENT;
141
79
142
80
143 COMPONENT lpp_top_lfr_wf_picker_ip
81 COMPONENT lpp_top_lfr_wf_picker_ip
144 GENERIC (
82 GENERIC (
145 hindex : INTEGER;
83 hindex : INTEGER;
146 nb_burst_available_size : INTEGER;
84 nb_burst_available_size : INTEGER;
147 nb_snapshot_param_size : INTEGER;
85 nb_snapshot_param_size : INTEGER;
148 delta_snapshot_size : INTEGER;
86 delta_snapshot_size : INTEGER;
149 delta_f2_f0_size : INTEGER;
87 delta_f2_f0_size : INTEGER;
150 delta_f2_f1_size : INTEGER;
88 delta_f2_f1_size : INTEGER;
151 tech : INTEGER;
89 tech : INTEGER;
152 Mem_use : INTEGER);
90 Mem_use : INTEGER);
153 PORT (
91 PORT (
154 sample : IN Samples(7 DOWNTO 0);
92 sample : IN Samples(7 DOWNTO 0);
155 sample_val : IN STD_LOGIC;
93 sample_val : IN STD_LOGIC;
156 clk : IN STD_LOGIC;
94 clk : IN STD_LOGIC;
157 rstn : IN STD_LOGIC;
95 rstn : IN STD_LOGIC;
158 sample_f0_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
96 sample_f0_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
159 sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
97 sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
160 sample_f1_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
98 sample_f1_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
161 sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
99 sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
162 sample_f2_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
100 sample_f2_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
163 sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
101 sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
164 sample_f3_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
102 sample_f3_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
165 sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
103 sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
166 AHB_Master_In : IN AHB_Mst_In_Type;
104 AHB_Master_In : IN AHB_Mst_In_Type;
167 AHB_Master_Out : OUT AHB_Mst_Out_Type;
105 AHB_Master_Out : OUT AHB_Mst_Out_Type;
168 coarse_time_0 : IN STD_LOGIC;
106 coarse_time_0 : IN STD_LOGIC;
169 data_shaping_SP0 : IN STD_LOGIC;
107 data_shaping_SP0 : IN STD_LOGIC;
170 data_shaping_SP1 : IN STD_LOGIC;
108 data_shaping_SP1 : IN STD_LOGIC;
171 data_shaping_R0 : IN STD_LOGIC;
109 data_shaping_R0 : IN STD_LOGIC;
172 data_shaping_R1 : IN STD_LOGIC;
110 data_shaping_R1 : IN STD_LOGIC;
173 delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
111 delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
174 delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
112 delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
175 delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
113 delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
176 enable_f0 : IN STD_LOGIC;
114 enable_f0 : IN STD_LOGIC;
177 enable_f1 : IN STD_LOGIC;
115 enable_f1 : IN STD_LOGIC;
178 enable_f2 : IN STD_LOGIC;
116 enable_f2 : IN STD_LOGIC;
179 enable_f3 : IN STD_LOGIC;
117 enable_f3 : IN STD_LOGIC;
180 burst_f0 : IN STD_LOGIC;
118 burst_f0 : IN STD_LOGIC;
181 burst_f1 : IN STD_LOGIC;
119 burst_f1 : IN STD_LOGIC;
182 burst_f2 : IN STD_LOGIC;
120 burst_f2 : IN STD_LOGIC;
183 nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
121 nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
184 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
122 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
185 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
123 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
186 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
124 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
187 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
125 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
188 status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
126 status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
189 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
127 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
190 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
128 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
191 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
129 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
192 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
130 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
193 END COMPONENT;
131 END COMPONENT;
194
132
195 COMPONENT lpp_top_lfr_wf_picker_ip_whitout_filter
133 COMPONENT lpp_top_lfr_wf_picker_ip_whitout_filter
196 GENERIC (
134 GENERIC (
197 hindex : INTEGER;
135 hindex : INTEGER;
198 nb_burst_available_size : INTEGER;
136 nb_burst_available_size : INTEGER;
199 nb_snapshot_param_size : INTEGER;
137 nb_snapshot_param_size : INTEGER;
200 delta_snapshot_size : INTEGER;
138 delta_snapshot_size : INTEGER;
201 delta_f2_f0_size : INTEGER;
139 delta_f2_f0_size : INTEGER;
202 delta_f2_f1_size : INTEGER;
140 delta_f2_f1_size : INTEGER;
203 tech : INTEGER);
141 tech : INTEGER);
204 PORT (
142 PORT (
205 sample : IN Samples(7 DOWNTO 0);
143 sample : IN Samples(7 DOWNTO 0);
206 sample_val : IN STD_LOGIC;
144 sample_val : IN STD_LOGIC;
207 cnv_clk : IN STD_LOGIC;
145 cnv_clk : IN STD_LOGIC;
208 cnv_rstn : IN STD_LOGIC;
146 cnv_rstn : IN STD_LOGIC;
209 clk : IN STD_LOGIC;
147 clk : IN STD_LOGIC;
210 rstn : IN STD_LOGIC;
148 rstn : IN STD_LOGIC;
211 sample_f0_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
149 sample_f0_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
212 sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
150 sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
213 sample_f1_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
151 sample_f1_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
214 sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
152 sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
215 sample_f2_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
153 sample_f2_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
216 sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
154 sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
217 sample_f3_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
155 sample_f3_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
218 sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
156 sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
219 AHB_Master_In : IN AHB_Mst_In_Type;
157 AHB_Master_In : IN AHB_Mst_In_Type;
220 AHB_Master_Out : OUT AHB_Mst_Out_Type;
158 AHB_Master_Out : OUT AHB_Mst_Out_Type;
221 coarse_time_0 : IN STD_LOGIC;
159 coarse_time_0 : IN STD_LOGIC;
222 data_shaping_SP0 : IN STD_LOGIC;
160 data_shaping_SP0 : IN STD_LOGIC;
223 data_shaping_SP1 : IN STD_LOGIC;
161 data_shaping_SP1 : IN STD_LOGIC;
224 data_shaping_R0 : IN STD_LOGIC;
162 data_shaping_R0 : IN STD_LOGIC;
225 data_shaping_R1 : IN STD_LOGIC;
163 data_shaping_R1 : IN STD_LOGIC;
226 delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
164 delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
227 delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
165 delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
228 delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
166 delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
229 enable_f0 : IN STD_LOGIC;
167 enable_f0 : IN STD_LOGIC;
230 enable_f1 : IN STD_LOGIC;
168 enable_f1 : IN STD_LOGIC;
231 enable_f2 : IN STD_LOGIC;
169 enable_f2 : IN STD_LOGIC;
232 enable_f3 : IN STD_LOGIC;
170 enable_f3 : IN STD_LOGIC;
233 burst_f0 : IN STD_LOGIC;
171 burst_f0 : IN STD_LOGIC;
234 burst_f1 : IN STD_LOGIC;
172 burst_f1 : IN STD_LOGIC;
235 burst_f2 : IN STD_LOGIC;
173 burst_f2 : IN STD_LOGIC;
236 nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
174 nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
237 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
175 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
238 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
176 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
239 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
177 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
240 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
178 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
241 status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
179 status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
242 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
180 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
243 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
181 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
244 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
182 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
245 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
183 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
246 END COMPONENT;
184 END COMPONENT;
247
185
248 COMPONENT top_wf_picker
186 COMPONENT top_wf_picker
249 GENERIC (
187 GENERIC (
250 hindex : INTEGER;
188 hindex : INTEGER;
251 pindex : INTEGER;
189 pindex : INTEGER;
252 paddr : INTEGER;
190 paddr : INTEGER;
253 pmask : INTEGER;
191 pmask : INTEGER;
254 pirq : INTEGER;
192 pirq : INTEGER;
255 tech : INTEGER;
193 tech : INTEGER;
256 nb_burst_available_size : INTEGER;
194 nb_burst_available_size : INTEGER;
257 nb_snapshot_param_size : INTEGER;
195 nb_snapshot_param_size : INTEGER;
258 delta_snapshot_size : INTEGER;
196 delta_snapshot_size : INTEGER;
259 delta_f2_f0_size : INTEGER;
197 delta_f2_f0_size : INTEGER;
260 delta_f2_f1_size : INTEGER;
198 delta_f2_f1_size : INTEGER;
261 ENABLE_FILTER : STD_LOGIC);
199 ENABLE_FILTER : STD_LOGIC);
262 PORT (
200 PORT (
263 cnv_clk : IN STD_LOGIC;
201 cnv_clk : IN STD_LOGIC;
264 cnv_rstn : IN STD_LOGIC;
202 cnv_rstn : IN STD_LOGIC;
265 sample_B : IN Samples14v(2 DOWNTO 0);
203 sample_B : IN Samples14v(2 DOWNTO 0);
266 sample_E : IN Samples14v(4 DOWNTO 0);
204 sample_E : IN Samples14v(4 DOWNTO 0);
267 sample_val : IN STD_LOGIC;
205 sample_val : IN STD_LOGIC;
268 HCLK : IN STD_ULOGIC;
206 HCLK : IN STD_ULOGIC;
269 HRESETn : IN STD_ULOGIC;
207 HRESETn : IN STD_ULOGIC;
270 apbi : IN apb_slv_in_type;
208 apbi : IN apb_slv_in_type;
271 apbo : OUT apb_slv_out_type;
209 apbo : OUT apb_slv_out_type;
272 AHB_Master_In : IN AHB_Mst_In_Type;
210 AHB_Master_In : IN AHB_Mst_In_Type;
273 AHB_Master_Out : OUT AHB_Mst_Out_Type;
211 AHB_Master_Out : OUT AHB_Mst_Out_Type;
274 coarse_time_0 : IN STD_LOGIC;
212 coarse_time_0 : IN STD_LOGIC;
275 data_shaping_BW : OUT STD_LOGIC);
213 data_shaping_BW : OUT STD_LOGIC);
276 END COMPONENT;
214 END COMPONENT;
277
215
278 END lpp_top_lfr_pkg;
216 END lpp_top_lfr_pkg;
Show file before | Show file after | Hide comments
@@ -1,284 +1,426
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
22 -------------------------------------------------------------------------------
1 LIBRARY IEEE;
23 LIBRARY IEEE;
2 USE IEEE.STD_LOGIC_1164.ALL;
24 USE IEEE.STD_LOGIC_1164.ALL;
3 USE ieee.numeric_std.ALL;
25 USE ieee.numeric_std.ALL;
4
26
5 LIBRARY grlib;
27 LIBRARY grlib;
6 USE grlib.amba.ALL;
28 USE grlib.amba.ALL;
7 USE grlib.stdlib.ALL;
29 USE grlib.stdlib.ALL;
8 USE grlib.devices.ALL;
30 USE grlib.devices.ALL;
9 USE GRLIB.DMA2AHB_Package.ALL;
31 USE GRLIB.DMA2AHB_Package.ALL;
10
32
11 LIBRARY lpp;
33 LIBRARY lpp;
12 USE lpp.lpp_waveform_pkg.ALL;
34 USE lpp.lpp_waveform_pkg.ALL;
13
35
14 LIBRARY techmap;
36 LIBRARY techmap;
15 USE techmap.gencomp.ALL;
37 USE techmap.gencomp.ALL;
16
38
17 ENTITY lpp_waveform IS
39 ENTITY lpp_waveform IS
18
40
19 GENERIC (
41 GENERIC (
20 hindex : INTEGER := 2;
42 tech : INTEGER := inferred;
21 tech : INTEGER := inferred;
43 data_size : INTEGER := 96; --16*6
22 data_size : INTEGER := 160;
44 nb_data_by_buffer_size : INTEGER := 11;
23 nb_burst_available_size : INTEGER := 11;
45 nb_snapshot_param_size : INTEGER := 11;
24 nb_snapshot_param_size : INTEGER := 11;
46 delta_vector_size : INTEGER := 20;
25 delta_snapshot_size : INTEGER := 16;
47 delta_vector_size_f0_2 : INTEGER := 3);
26 delta_f2_f0_size : INTEGER := 10;
27 delta_f2_f1_size : INTEGER := 10);
28
48
29 PORT (
49 PORT (
30 clk : IN STD_LOGIC;
50 clk : IN STD_LOGIC;
31 rstn : IN STD_LOGIC;
51 rstn : IN STD_LOGIC;
32
52
33 -- AMBA AHB Master Interface
53 ---- AMBA AHB Master Interface
34 AHB_Master_In : IN AHB_Mst_In_Type;
54 --AHB_Master_In : IN AHB_Mst_In_Type; -- TODO
35 AHB_Master_Out : OUT AHB_Mst_Out_Type;
55 --AHB_Master_Out : OUT AHB_Mst_Out_Type; -- TODO
36
56
37 coarse_time_0 : IN STD_LOGIC;
38
39 --config
57 --config
40 delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
58 reg_run : IN STD_LOGIC;
41 delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
59 reg_start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
42 delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
60 reg_delta_snapshot : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
43
61 reg_delta_f0 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
62 reg_delta_f0_2 : IN STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
63 reg_delta_f1 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
64 reg_delta_f2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
65
44 enable_f0 : IN STD_LOGIC;
66 enable_f0 : IN STD_LOGIC;
45 enable_f1 : IN STD_LOGIC;
67 enable_f1 : IN STD_LOGIC;
46 enable_f2 : IN STD_LOGIC;
68 enable_f2 : IN STD_LOGIC;
47 enable_f3 : IN STD_LOGIC;
69 enable_f3 : IN STD_LOGIC;
48
70
49 burst_f0 : IN STD_LOGIC;
71 burst_f0 : IN STD_LOGIC;
50 burst_f1 : IN STD_LOGIC;
72 burst_f1 : IN STD_LOGIC;
51 burst_f2 : IN STD_LOGIC;
73 burst_f2 : IN STD_LOGIC;
52
74
53 run : IN STD_LOGIC; -- TODO
75 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
76 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
77 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
78 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
79 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
80 status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma
81 ---------------------------------------------------------------------------
82 -- INPUT
83 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
84 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
85
86 --f0
87 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
88 data_f0_in_valid : IN STD_LOGIC;
89 data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
90 --f1
91 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
92 data_f1_in_valid : IN STD_LOGIC;
93 data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
94 --f2
95 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
96 data_f2_in_valid : IN STD_LOGIC;
97 data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
98 --f3
99 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
100 data_f3_in_valid : IN STD_LOGIC;
101 data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
54
102
55 nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
103 ---------------------------------------------------------------------------
56 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
104 -- OUTPUT
57 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
105 --f0
58 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
106 data_f0_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
59 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
107 data_f0_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
60 status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma
108 data_f0_data_out_valid : OUT STD_LOGIC;
61 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
109 data_f0_data_out_valid_burst : OUT STD_LOGIC;
62 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
110 data_f0_data_out_ren : IN STD_LOGIC;
63 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
111 --f1
64 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
112 data_f1_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
113 data_f1_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
114 data_f1_data_out_valid : OUT STD_LOGIC;
115 data_f1_data_out_valid_burst : OUT STD_LOGIC;
116 data_f1_data_out_ren : IN STD_LOGIC;
117 --f2
118 data_f2_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
119 data_f2_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
120 data_f2_data_out_valid : OUT STD_LOGIC;
121 data_f2_data_out_valid_burst : OUT STD_LOGIC;
122 data_f2_data_out_ren : IN STD_LOGIC;
123 --f3
124 data_f3_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
125 data_f3_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
126 data_f3_data_out_valid : OUT STD_LOGIC;
127 data_f3_data_out_valid_burst : OUT STD_LOGIC;
128 data_f3_data_out_ren : IN STD_LOGIC
65
129
66 data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
130
67 data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
68 data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
69 data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
70
71 data_f0_in_valid : IN STD_LOGIC;
72 data_f1_in_valid : IN STD_LOGIC;
73 data_f2_in_valid : IN STD_LOGIC;
74 data_f3_in_valid : IN STD_LOGIC
75 );
131 );
76
132
77 END lpp_waveform;
133 END lpp_waveform;
78
134
79 ARCHITECTURE beh OF lpp_waveform IS
135 ARCHITECTURE beh OF lpp_waveform IS
80 SIGNAL start_snapshot_f0 : STD_LOGIC;
136 SIGNAL start_snapshot_f0 : STD_LOGIC;
81 SIGNAL start_snapshot_f1 : STD_LOGIC;
137 SIGNAL start_snapshot_f1 : STD_LOGIC;
82 SIGNAL start_snapshot_f2 : STD_LOGIC;
138 SIGNAL start_snapshot_f2 : STD_LOGIC;
83
139
84 SIGNAL data_f0_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
140 SIGNAL data_f0_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
85 SIGNAL data_f1_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
141 SIGNAL data_f1_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
86 SIGNAL data_f2_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
142 SIGNAL data_f2_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
87 SIGNAL data_f3_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
143 SIGNAL data_f3_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
88
144
89 SIGNAL data_f0_out_valid : STD_LOGIC;
145 SIGNAL data_f0_out_valid : STD_LOGIC;
90 SIGNAL data_f1_out_valid : STD_LOGIC;
146 SIGNAL data_f1_out_valid : STD_LOGIC;
91 SIGNAL data_f2_out_valid : STD_LOGIC;
147 SIGNAL data_f2_out_valid : STD_LOGIC;
92 SIGNAL data_f3_out_valid : STD_LOGIC;
148 SIGNAL data_f3_out_valid : STD_LOGIC;
93 SIGNAL nb_snapshot_param_more_one : STD_LOGIC_VECTOR(nb_snapshot_param_size DOWNTO 0);
149 SIGNAL nb_snapshot_param_more_one : STD_LOGIC_VECTOR(nb_snapshot_param_size DOWNTO 0);
94
95 --
150 --
96 SIGNAL valid_in : STD_LOGIC_VECTOR(3 DOWNTO 0);
151 SIGNAL valid_in : STD_LOGIC_VECTOR(3 DOWNTO 0);
97 SIGNAL valid_out : STD_LOGIC_VECTOR(3 DOWNTO 0);
152 SIGNAL valid_out : STD_LOGIC_VECTOR(3 DOWNTO 0);
98 SIGNAL valid_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
153 SIGNAL valid_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
99 SIGNAL time_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
154 SIGNAL time_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
100 SIGNAL data_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
155 SIGNAL data_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
101 SIGNAL ready_arb : STD_LOGIC_VECTOR(3 DOWNTO 0);
156 SIGNAL ready_arb : STD_LOGIC_VECTOR(3 DOWNTO 0);
102 SIGNAL data_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
157 SIGNAL data_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
103 SIGNAL time_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
158 SIGNAL time_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
104 SIGNAL wdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
159 SIGNAL wdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
160 SIGNAL full_almost : STD_LOGIC_VECTOR(3 DOWNTO 0);
161 SIGNAL full : STD_LOGIC_VECTOR(3 DOWNTO 0);
162 SIGNAL empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0);
163 SIGNAL empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
105 --
164 --
106 SIGNAL data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
165 SIGNAL data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
107 SIGNAL time_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
166 SIGNAL time_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
108 SIGNAL rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
167 SIGNAL rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
109 SIGNAL enable : STD_LOGIC_VECTOR(3 DOWNTO 0);
168 SIGNAL enable : STD_LOGIC_VECTOR(3 DOWNTO 0);
169 --
170 SIGNAL run : STD_LOGIC;
171 --
172 TYPE TIME_VECTOR IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(47 DOWNTO 0);
173 SIGNAL data_out : Data_Vector(3 DOWNTO 0, 95 DOWNTO 0);
174 SIGNAL time_out_2 : Data_Vector(3 DOWNTO 0, 47 DOWNTO 0);
175 SIGNAL time_out : TIME_VECTOR(3 DOWNTO 0);
176 SIGNAL time_reg1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
177 SIGNAL time_reg2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
110
178
111 BEGIN -- beh
179 BEGIN -- beh
112
180
113 lpp_waveform_snapshot_controler_1: lpp_waveform_snapshot_controler
181 lpp_waveform_snapshot_controler_1 : lpp_waveform_snapshot_controler
114 GENERIC MAP (
182 GENERIC MAP (
115 delta_snapshot_size => delta_snapshot_size,
183 delta_vector_size => delta_vector_size,
116 delta_f2_f0_size => delta_f2_f0_size,
184 delta_vector_size_f0_2 => delta_vector_size_f0_2
117 delta_f2_f1_size => delta_f2_f1_size)
185 )
118 PORT MAP (
186 PORT MAP (
119 clk => clk,
187 clk => clk,
120 rstn => rstn,
188 rstn => rstn,
121 run => run,
189 reg_run => reg_run,
122 delta_snapshot => delta_snapshot,
190 reg_start_date => reg_start_date,
123 delta_f2_f1 => delta_f2_f1,
191 reg_delta_snapshot => reg_delta_snapshot,
124 delta_f2_f0 => delta_f2_f0,
192 reg_delta_f0 => reg_delta_f0,
125 coarse_time_0 => coarse_time_0,
193 reg_delta_f0_2 => reg_delta_f0_2,
126 data_f0_in_valid => data_f0_in_valid,
194 reg_delta_f1 => reg_delta_f1,
127 data_f2_in_valid => data_f2_in_valid,
195 reg_delta_f2 => reg_delta_f2,
128 start_snapshot_f0 => start_snapshot_f0,
196 coarse_time => coarse_time(30 DOWNTO 0),
129 start_snapshot_f1 => start_snapshot_f1,
197 data_f0_valid => data_f0_in_valid,
130 start_snapshot_f2 => start_snapshot_f2);
198 data_f2_valid => data_f2_in_valid,
131
199 start_snapshot_f0 => start_snapshot_f0,
200 start_snapshot_f1 => start_snapshot_f1,
201 start_snapshot_f2 => start_snapshot_f2,
202 wfp_on => run);
203
132 lpp_waveform_snapshot_f0 : lpp_waveform_snapshot
204 lpp_waveform_snapshot_f0 : lpp_waveform_snapshot
133 GENERIC MAP (
205 GENERIC MAP (
134 data_size => data_size,
206 data_size => data_size,
135 nb_snapshot_param_size => nb_snapshot_param_size)
207 nb_snapshot_param_size => nb_snapshot_param_size)
136 PORT MAP (
208 PORT MAP (
137 clk => clk,
209 clk => clk,
138 rstn => rstn,
210 rstn => rstn,
139 run => run,
211 run => run,
140 enable => enable_f0,
212 enable => enable_f0,
141 burst_enable => burst_f0,
213 burst_enable => burst_f0,
142 nb_snapshot_param => nb_snapshot_param,
214 nb_snapshot_param => nb_snapshot_param,
143 start_snapshot => start_snapshot_f0,
215 start_snapshot => start_snapshot_f0,
144 data_in => data_f0_in,
216 data_in => data_f0_in,
145 data_in_valid => data_f0_in_valid,
217 data_in_valid => data_f0_in_valid,
146 data_out => data_f0_out,
218 data_out => data_f0_out,
147 data_out_valid => data_f0_out_valid);
219 data_out_valid => data_f0_out_valid);
148
220
149 nb_snapshot_param_more_one <= ('0' & nb_snapshot_param) + 1;
221 nb_snapshot_param_more_one <= ('0' & nb_snapshot_param) + 1;
150
222
151 lpp_waveform_snapshot_f1 : lpp_waveform_snapshot
223 lpp_waveform_snapshot_f1 : lpp_waveform_snapshot
152 GENERIC MAP (
224 GENERIC MAP (
153 data_size => data_size,
225 data_size => data_size,
154 nb_snapshot_param_size => nb_snapshot_param_size+1)
226 nb_snapshot_param_size => nb_snapshot_param_size+1)
155 PORT MAP (
227 PORT MAP (
156 clk => clk,
228 clk => clk,
157 rstn => rstn,
229 rstn => rstn,
158 run => run,
230 run => run,
159 enable => enable_f1,
231 enable => enable_f1,
160 burst_enable => burst_f1,
232 burst_enable => burst_f1,
161 nb_snapshot_param => nb_snapshot_param_more_one,
233 nb_snapshot_param => nb_snapshot_param_more_one,
162 start_snapshot => start_snapshot_f1,
234 start_snapshot => start_snapshot_f1,
163 data_in => data_f1_in,
235 data_in => data_f1_in,
164 data_in_valid => data_f1_in_valid,
236 data_in_valid => data_f1_in_valid,
165 data_out => data_f1_out,
237 data_out => data_f1_out,
166 data_out_valid => data_f1_out_valid);
238 data_out_valid => data_f1_out_valid);
167
239
168 lpp_waveform_snapshot_f2 : lpp_waveform_snapshot
240 lpp_waveform_snapshot_f2 : lpp_waveform_snapshot
169 GENERIC MAP (
241 GENERIC MAP (
170 data_size => data_size,
242 data_size => data_size,
171 nb_snapshot_param_size => nb_snapshot_param_size+1)
243 nb_snapshot_param_size => nb_snapshot_param_size+1)
172 PORT MAP (
244 PORT MAP (
173 clk => clk,
245 clk => clk,
174 rstn => rstn,
246 rstn => rstn,
175 run => run,
247 run => run,
176 enable => enable_f2,
248 enable => enable_f2,
177 burst_enable => burst_f2,
249 burst_enable => burst_f2,
178 nb_snapshot_param => nb_snapshot_param_more_one,
250 nb_snapshot_param => nb_snapshot_param_more_one,
179 start_snapshot => start_snapshot_f2,
251 start_snapshot => start_snapshot_f2,
180 data_in => data_f2_in,
252 data_in => data_f2_in,
181 data_in_valid => data_f2_in_valid,
253 data_in_valid => data_f2_in_valid,
182 data_out => data_f2_out,
254 data_out => data_f2_out,
183 data_out_valid => data_f2_out_valid);
255 data_out_valid => data_f2_out_valid);
184
256
185 lpp_waveform_burst_f3: lpp_waveform_burst
257 lpp_waveform_burst_f3 : lpp_waveform_burst
186 GENERIC MAP (
258 GENERIC MAP (
187 data_size => data_size)
259 data_size => data_size)
188 PORT MAP (
260 PORT MAP (
189 clk => clk,
261 clk => clk,
190 rstn => rstn,
262 rstn => rstn,
191 run => run,
263 run => run,
192 enable => enable_f3,
264 enable => enable_f3,
193 data_in => data_f3_in,
265 data_in => data_f3_in,
194 data_in_valid => data_f3_in_valid,
266 data_in_valid => data_f3_in_valid,
195 data_out => data_f3_out,
267 data_out => data_f3_out,
196 data_out_valid => data_f3_out_valid);
268 data_out_valid => data_f3_out_valid);
197
269
198
270 PROCESS (clk, rstn)
199 valid_in <= data_f3_out_valid & data_f2_out_valid & data_f1_out_valid & data_f0_out_valid;
271 BEGIN -- PROCESS
272 IF rstn = '0' THEN -- asynchronous reset (active low)
273 time_reg1 <= (OTHERS => '0');
274 time_reg2 <= (OTHERS => '0');
275 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
276 time_reg1 <= fine_time & coarse_time;
277 time_reg2 <= time_reg1;
278 END IF;
279 END PROCESS;
200
280
201 all_input_valid: FOR i IN 3 DOWNTO 0 GENERATE
281 valid_in <= data_f3_out_valid & data_f2_out_valid & data_f1_out_valid & data_f0_out_valid;
202 lpp_waveform_dma_gen_valid_I: lpp_waveform_dma_gen_valid
282 all_input_valid : FOR i IN 3 DOWNTO 0 GENERATE
283 lpp_waveform_dma_genvalid_I : lpp_waveform_dma_genvalid
203 PORT MAP (
284 PORT MAP (
204 HCLK => clk,
285 HCLK => clk,
205 HRESETn => rstn,
286 HRESETn => rstn,
206 run => run,
287 run => run,
207 valid_in => valid_in(I),
288 valid_in => valid_in(I),
208 ack_in => valid_ack(I),
289 ack_in => valid_ack(I),
290 time_in => time_reg2, -- Todo
209 valid_out => valid_out(I),
291 valid_out => valid_out(I),
292 time_out => time_out(I), -- Todo
210 error => status_new_err(I));
293 error => status_new_err(I));
211 END GENERATE all_input_valid;
294 END GENERATE all_input_valid;
212
295
213 lpp_waveform_fifo_arbiter_1: lpp_waveform_fifo_arbiter
296 all_bit_of_data_out: FOR I IN 95 DOWNTO 0 GENERATE
214 GENERIC MAP (tech => tech)
297 data_out(0,I) <= data_f0_out(I);
298 data_out(1,I) <= data_f1_out(I);
299 data_out(2,I) <= data_f2_out(I);
300 data_out(3,I) <= data_f3_out(I);
301 END GENERATE all_bit_of_data_out;
302
303 all_bit_of_time_out: FOR I IN 47 DOWNTO 0 GENERATE
304 all_sample_of_time_out: FOR J IN 3 DOWNTO 0 GENERATE
305 time_out_2(J,I) <= time_out(J)(I);
306 END GENERATE all_sample_of_time_out;
307 END GENERATE all_bit_of_time_out;
308
309 lpp_waveform_fifo_arbiter_1 : lpp_waveform_fifo_arbiter
310 GENERIC MAP (tech => tech,
311 nb_data_by_buffer_size =>nb_data_by_buffer_size)
215 PORT MAP (
312 PORT MAP (
216 clk => clk,
313 clk => clk,
217 rstn => rstn,
314 rstn => rstn,
218 run => run,
315 run => run,
219 data_f0_valid => valid_out(0),
316 nb_data_by_buffer => nb_data_by_buffer,
220 data_f1_valid => valid_out(1),
317 data_in_valid => valid_out,
221 data_f2_valid => valid_out(2),
318 data_in_ack => valid_ack,
222 data_f3_valid => valid_out(3),
319 data_in => data_out,
223
320 time_in => time_out_2,
224 data_valid_ack => valid_ack,
225
226 data_f0 => data_f0_out,
227 data_f1 => data_f1_out,
228 data_f2 => data_f2_out,
229 data_f3 => data_f3_out,
230
231 ready => ready_arb,
232 time_wen => time_wen,
233 data_wen => data_wen,
234 data => wdata);
235
321
236 ready_arb <= NOT data_ready;
322 data_out => wdata,
237
323 data_out_wen => data_wen,
238 lpp_waveform_fifo_1: lpp_waveform_fifo
324 full => full);
325
326 lpp_waveform_fifo_1 : lpp_waveform_fifo
239 GENERIC MAP (tech => tech)
327 GENERIC MAP (tech => tech)
240 PORT MAP (
328 PORT MAP (
241 clk => clk,
329 clk => clk,
242 rstn => rstn,
330 rstn => rstn,
243 run => run,
331 run => run,
244 time_ready => time_ready,
332
245 data_ready => data_ready,
333 empty => empty,
246 time_ren => time_ren, -- todo
334 empty_almost => empty_almost,
247 data_ren => data_ren, -- todo
335
248 rdata => rdata, -- todo
336 data_ren => data_ren,
337 rdata => rdata,
338
249
339
250 time_wen => time_wen,
340 full_almost => full_almost,
251 data_wen => data_wen,
341 full => full,
252 wdata => wdata);
342 data_wen => data_wen,
343 wdata => wdata);
344
345
346
347
348
349 -----------------------------------------------------------------------------
350 -- TODO : set the alterance : time, data, data, .....
351 -----------------------------------------------------------------------------
253
352
254 enable <= enable_f3 & enable_f2 & enable_f1 & enable_f0;
353
354 -----------------------------------------------------------------------------
355 --
356 -----------------------------------------------------------------------------
357
358 data_ren <= data_f3_data_out_ren &
359 data_f2_data_out_ren &
360 data_f1_data_out_ren &
361 data_f0_data_out_ren;
362
363 data_f3_data_out <= rdata;
364 data_f2_data_out <= rdata;
365 data_f1_data_out <= rdata;
366 data_f0_data_out <= rdata;
367
368
369
255
370
256 pp_waveform_dma_1: lpp_waveform_dma
371
257 GENERIC MAP (
372 -----------------------------------------------------------------------------
258 data_size => data_size,
373 -- TODO
259 tech => tech,
374 -----------------------------------------------------------------------------
260 hindex => hindex,
375 lpp_waveform_gen_address_1 : lpp_waveform_genaddress
261 nb_burst_available_size => nb_burst_available_size)
376 GENERIC MAP (
262 PORT MAP (
377 nb_data_by_buffer_size => nb_data_by_buffer_size)
263 HCLK => clk,
378 PORT MAP (
264 HRESETn => rstn,
379 clk => clk,
265 run => run,
380 rstn => rstn,
266
381 run => run,
267 AHB_Master_In => AHB_Master_In,
382
268 AHB_Master_Out => AHB_Master_Out,
383 -------------------------------------------------------------------------
269 enable => enable, -- todo
384 -- CONFIG
270 time_ready => time_ready, -- todo
385 -------------------------------------------------------------------------
271 data_ready => data_ready,
386 nb_data_by_buffer => nb_data_by_buffer,
272 data => rdata,
387
273 data_data_ren => data_ren,
388 addr_data_f0 => addr_data_f0,
274 data_time_ren => time_ren,
389 addr_data_f1 => addr_data_f1,
275 nb_burst_available => nb_burst_available,
390 addr_data_f2 => addr_data_f2,
276 status_full => status_full,
391 addr_data_f3 => addr_data_f3,
277 status_full_ack => status_full_ack,
392 -------------------------------------------------------------------------
278 status_full_err => status_full_err,
393 -- CTRL
279 addr_data_f0 => addr_data_f0,
394 -------------------------------------------------------------------------
280 addr_data_f1 => addr_data_f1,
395 -- IN
281 addr_data_f2 => addr_data_f2,
396 empty => empty,
282 addr_data_f3 => addr_data_f3);
397 empty_almost => empty_almost,
398 data_ren => data_ren,
399
400 -------------------------------------------------------------------------
401 -- STATUS
402 -------------------------------------------------------------------------
403 status_full => status_full,
404 status_full_ack => status_full_ack,
405 status_full_err => status_full_err,
406
407 -------------------------------------------------------------------------
408 -- ADDR DATA OUT
409 -------------------------------------------------------------------------
410 data_f0_data_out_valid_burst => data_f0_data_out_valid_burst,
411 data_f1_data_out_valid_burst => data_f1_data_out_valid_burst,
412 data_f2_data_out_valid_burst => data_f2_data_out_valid_burst,
413 data_f3_data_out_valid_burst => data_f3_data_out_valid_burst,
414
415 data_f0_data_out_valid => data_f0_data_out_valid,
416 data_f1_data_out_valid => data_f1_data_out_valid,
417 data_f2_data_out_valid => data_f2_data_out_valid,
418 data_f3_data_out_valid => data_f3_data_out_valid,
419
420 data_f0_addr_out => data_f0_addr_out,
421 data_f1_addr_out => data_f1_addr_out,
422 data_f2_addr_out => data_f2_addr_out,
423 data_f3_addr_out => data_f3_addr_out
424 );
283
425
284 END beh;
426 END beh;
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@@ -1,98 +1,98
1
2 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
3 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
4 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
5 --
4 --
6 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
7 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
8 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
9 -- (at your option) any later version.
8 -- (at your option) any later version.
10 --
9 --
11 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
12 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
13 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
15 --
14 --
16 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
17 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
18 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
20 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
21 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
22 -- jean-christophe.pellion@easii-ic.com
21 -- jean-christophe.pellion@easii-ic.com
23 -------------------------------------------------------------------------------
22 -------------------------------------------------------------------------------
24 -- 1.0 - initial version
23 -- 1.0 - initial version
25 -------------------------------------------------------------------------------
24 -------------------------------------------------------------------------------
26
25
27 LIBRARY ieee;
26 LIBRARY ieee;
28 USE ieee.std_logic_1164.ALL;
27 USE ieee.std_logic_1164.ALL;
29 USE ieee.numeric_std.ALL;
28 USE ieee.numeric_std.ALL;
30
29
31
30
32 ENTITY lpp_waveform_dma_gen_valid IS
31 ENTITY lpp_waveform_dma_genvalid IS
33 PORT (
32 PORT (
34 HCLK : IN STD_LOGIC;
33 HCLK : IN STD_LOGIC;
35 HRESETn : IN STD_LOGIC;
34 HRESETn : IN STD_LOGIC;
36 run : IN STD_LOGIC;
35 run : IN STD_LOGIC;
37
36
38 valid_in : IN STD_LOGIC;
37 valid_in : IN STD_LOGIC;
39 ack_in : IN STD_LOGIC;
38 time_in : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
40
39
40 ack_in : IN STD_LOGIC;
41 valid_out : OUT STD_LOGIC;
41 valid_out : OUT STD_LOGIC;
42 time_out : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
42 error : OUT STD_LOGIC
43 error : OUT STD_LOGIC
43 );
44 );
44 END;
45 END;
45
46
46 ARCHITECTURE Behavioral OF lpp_waveform_dma_gen_valid IS
47 ARCHITECTURE Behavioral OF lpp_waveform_dma_genvalid IS
47 TYPE state_fsm IS (IDLE, VALID);
48 TYPE state_fsm IS (IDLE, VALID);
48 SIGNAL state : state_fsm;
49 SIGNAL state : state_fsm;
49 BEGIN
50 BEGIN
50
51
51 FSM_SELECT_ADDRESS : PROCESS (HCLK, HRESETn)
52 FSM_SELECT_ADDRESS : PROCESS (HCLK, HRESETn)
52 BEGIN
53 BEGIN
53 IF HRESETn = '0' THEN
54 IF HRESETn = '0' THEN
54 state <= IDLE;
55 state <= IDLE;
55 valid_out <= '0';
56 valid_out <= '0';
56 error <= '0';
57 error <= '0';
58 time_out <= (OTHERS => '0');
57 ELSIF HCLK'EVENT AND HCLK = '1' THEN
59 ELSIF HCLK'EVENT AND HCLK = '1' THEN
58 CASE state IS
60 CASE state IS
59 WHEN IDLE =>
61 WHEN IDLE =>
62
60 valid_out <= '0';
63 valid_out <= '0';
61 error <= '0';
64 error <= '0';
62 IF run = '0' THEN
65 IF run = '1' AND valid_in = '1' THEN
63 state <= IDLE;
64 valid_out <= '0';
65 ELSIF valid_in = '1' THEN
66 state <= VALID;
66 state <= VALID;
67 valid_out <= '1';
67 valid_out <= '1';
68 time_out <= time_in;
68 END IF;
69 END IF;
69
70
70 WHEN VALID =>
71 WHEN VALID =>
71 IF run = '0' THEN
72 IF run = '0' THEN
72 state <= IDLE;
73 state <= IDLE;
73 valid_out <= '0';
74 valid_out <= '0';
74 error <= '0';
75 error <= '0';
75 ELSE
76 ELSE
76 valid_out <= '1';
77 error <= '0';
78 IF valid_in = '1' THEN
77 IF valid_in = '1' THEN
79 IF ack_in = '1' THEN
78 IF ack_in = '1' THEN
80 state <= VALID;
79 state <= VALID;
81 valid_out <= '1';
80 valid_out <= '1';
81 time_out <= time_in;
82 ELSE
82 ELSE
83 state <= IDLE;
83 state <= IDLE;
84 error <= '1';
84 error <= '1';
85 valid_out <= '0';
85 valid_out <= '0';
86 END IF;
86 END IF;
87 ELSIF ack_in = '1' THEN
87 ELSIF ack_in = '1' THEN
88 state <= IDLE;
88 state <= IDLE;
89 valid_out <= '0';
89 valid_out <= '0';
90 END IF;
90 END IF;
91 END IF;
91 END IF;
92
92
93 WHEN OTHERS => NULL;
93 WHEN OTHERS => NULL;
94 END CASE;
94 END CASE;
95 END IF;
95 END IF;
96 END PROCESS FSM_SELECT_ADDRESS;
96 END PROCESS FSM_SELECT_ADDRESS;
97
97
98 END Behavioral;
98 END Behavioral;
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@@ -1,181 +1,146
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Jean-christophe PELLION
19 -- Author : Jean-christophe PELLION
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.std_logic_1164.ALL;
23 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.numeric_std.ALL;
24 USE IEEE.numeric_std.ALL;
25 LIBRARY lpp;
25 LIBRARY lpp;
26 USE lpp.lpp_memory.ALL;
26 USE lpp.lpp_memory.ALL;
27 USE lpp.iir_filter.ALL;
27 USE lpp.iir_filter.ALL;
28 USE lpp.lpp_waveform_pkg.ALL;
28 USE lpp.lpp_waveform_pkg.ALL;
29
29
30 LIBRARY techmap;
30 LIBRARY techmap;
31 USE techmap.gencomp.ALL;
31 USE techmap.gencomp.ALL;
32
32
33 ENTITY lpp_waveform_fifo IS
33 ENTITY lpp_waveform_fifo IS
34 GENERIC(
34 GENERIC(
35 tech : INTEGER := 0
35 tech : INTEGER := 0
36 );
36 );
37 PORT(
37 PORT(
38 clk : IN STD_LOGIC;
38 clk : IN STD_LOGIC;
39 rstn : IN STD_LOGIC;
39 rstn : IN STD_LOGIC;
40 ---------------------------------------------------------------------------
40 ---------------------------------------------------------------------------
41 run : IN STD_LOGIC;
41 run : IN STD_LOGIC;
42
43 ---------------------------------------------------------------------------
44 time_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- FIFO_DATA occupancy is greater than 16 * 32b
45 data_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- FIFO_DATA occupancy is greater than 16 * 32b
46
42
47 ---------------------------------------------------------------------------
43 ---------------------------------------------------------------------------
48 time_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
44 empty_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --occupancy is lesser than 16 * 32b
49 data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
45 empty : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
50
46 data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
51 rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
47 rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
52
48
53 ---------------------------------------------------------------------------
49 ---------------------------------------------------------------------------
54 time_wen : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
50 full_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --occupancy is greater than MAX - 5 * 32b
55 data_wen : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
51 full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
56
52 data_wen : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
57 wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
53 wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
58 );
54 );
59 END ENTITY;
55 END ENTITY;
60
56
61
57
62 ARCHITECTURE ar_lpp_waveform_fifo OF lpp_waveform_fifo IS
58 ARCHITECTURE ar_lpp_waveform_fifo OF lpp_waveform_fifo IS
63
59
64
65 SIGNAL time_mem_addr_r : LPP_TYPE_ADDR_FIFO_WAVEFORM(3 DOWNTO 0);
66 SIGNAL time_mem_addr_w : LPP_TYPE_ADDR_FIFO_WAVEFORM(3 DOWNTO 0);
67 SIGNAL time_mem_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
68 SIGNAL time_mem_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
69
70 SIGNAL data_mem_addr_r : LPP_TYPE_ADDR_FIFO_WAVEFORM(3 DOWNTO 0);
60 SIGNAL data_mem_addr_r : LPP_TYPE_ADDR_FIFO_WAVEFORM(3 DOWNTO 0);
71 SIGNAL data_mem_addr_w : LPP_TYPE_ADDR_FIFO_WAVEFORM(3 DOWNTO 0);
61 SIGNAL data_mem_addr_w : LPP_TYPE_ADDR_FIFO_WAVEFORM(3 DOWNTO 0);
72 SIGNAL data_mem_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
62 SIGNAL data_mem_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
73 SIGNAL data_mem_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
63 SIGNAL data_mem_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
74
64
75 SIGNAL data_addr_r : STD_LOGIC_VECTOR(6 DOWNTO 0);
65 SIGNAL data_addr_r : STD_LOGIC_VECTOR(6 DOWNTO 0);
76 SIGNAL data_addr_w : STD_LOGIC_VECTOR(6 DOWNTO 0);
66 SIGNAL data_addr_w : STD_LOGIC_VECTOR(6 DOWNTO 0);
77 SIGNAL ren : STD_LOGIC;
67 SIGNAL ren : STD_LOGIC;
78 SIGNAL wen : STD_LOGIC;
68 SIGNAL wen : STD_LOGIC;
79
69
80 BEGIN
70 BEGIN
81
71
82 SRAM : syncram_2p
72 SRAM : syncram_2p
83 GENERIC MAP(tech, 7, 32)
73 GENERIC MAP(tech, 7, 32)
84 PORT MAP(clk, ren, data_addr_r, rdata,
74 PORT MAP(clk, ren, data_addr_r, rdata,
85 clk, wen, data_addr_w, wdata);
75 clk, wen, data_addr_w, wdata);
86
76
87
77 ren <= data_mem_ren(3) OR
88 ren <= time_mem_ren(3) OR data_mem_ren(3) OR
78 data_mem_ren(2) OR
89 time_mem_ren(2) OR data_mem_ren(2) OR
79 data_mem_ren(1) OR
90 time_mem_ren(1) OR data_mem_ren(1) OR
80 data_mem_ren(0);
91 time_mem_ren(0) OR data_mem_ren(0);
92
81
93 wen <= time_mem_wen(3) OR data_mem_wen(3) OR
82 wen <= data_mem_wen(3) OR
94 time_mem_wen(2) OR data_mem_wen(2) OR
83 data_mem_wen(2) OR
95 time_mem_wen(1) OR data_mem_wen(1) OR
84 data_mem_wen(1) OR
96 time_mem_wen(0) OR data_mem_wen(0);
85 data_mem_wen(0);
97
86
98 data_addr_r <= time_mem_addr_r(0) WHEN time_mem_ren(0) = '1' ELSE
87 data_addr_r <= data_mem_addr_r(0) WHEN data_mem_ren(0) = '1' ELSE
99 time_mem_addr_r(1) WHEN time_mem_ren(1) = '1' ELSE
100 time_mem_addr_r(2) WHEN time_mem_ren(2) = '1' ELSE
101 time_mem_addr_r(3) WHEN time_mem_ren(3) = '1' ELSE
102 data_mem_addr_r(0) WHEN data_mem_ren(0) = '1' ELSE
103 data_mem_addr_r(1) WHEN data_mem_ren(1) = '1' ELSE
88 data_mem_addr_r(1) WHEN data_mem_ren(1) = '1' ELSE
104 data_mem_addr_r(2) WHEN data_mem_ren(2) = '1' ELSE
89 data_mem_addr_r(2) WHEN data_mem_ren(2) = '1' ELSE
105 data_mem_addr_r(3);
90 data_mem_addr_r(3);
106
91
107 data_addr_w <= time_mem_addr_w(0) WHEN time_mem_wen(0) = '1' ELSE
92 data_addr_w <= data_mem_addr_w(0) WHEN data_mem_wen(0) = '1' ELSE
108 time_mem_addr_w(1) WHEN time_mem_wen(1) = '1' ELSE
109 time_mem_addr_w(2) WHEN time_mem_wen(2) = '1' ELSE
110 time_mem_addr_w(3) WHEN time_mem_wen(3) = '1' ELSE
111 data_mem_addr_w(0) WHEN data_mem_wen(0) = '1' ELSE
112 data_mem_addr_w(1) WHEN data_mem_wen(1) = '1' ELSE
93 data_mem_addr_w(1) WHEN data_mem_wen(1) = '1' ELSE
113 data_mem_addr_w(2) WHEN data_mem_wen(2) = '1' ELSE
94 data_mem_addr_w(2) WHEN data_mem_wen(2) = '1' ELSE
114 data_mem_addr_w(3);
95 data_mem_addr_w(3);
115
116 gen_fifo_ctrl_time: FOR I IN 3 DOWNTO 0 GENERATE
117 lpp_waveform_fifo_ctrl_time: lpp_waveform_fifo_ctrl
118 GENERIC MAP (
119 offset => 32*I + 20,
120 length => 10,
121 enable_ready => '1')
122 PORT MAP (
123 clk => clk,
124 rstn => rstn,
125 run => run,
126 ren => time_ren(I),
127 wen => time_wen(I),
128 mem_re => time_mem_ren(I),
129 mem_we => time_mem_wen(I),
130 mem_addr_ren => time_mem_addr_r(I),
131 mem_addr_wen => time_mem_addr_w(I),
132 ready => time_ready(I));
133 END GENERATE gen_fifo_ctrl_time;
134
96
135 gen_fifo_ctrl_data: FOR I IN 3 DOWNTO 0 GENERATE
97 gen_fifo_ctrl_data: FOR I IN 3 DOWNTO 0 GENERATE
136 lpp_waveform_fifo_ctrl_data: lpp_waveform_fifo_ctrl
98 lpp_waveform_fifo_ctrl_data: lpp_waveform_fifo_ctrl
137 GENERIC MAP (
99 GENERIC MAP (
138 offset => 32*I,
100 offset => 32*I,
139 length => 20,
101 length => 32)
140 enable_ready => '1')
141 PORT MAP (
102 PORT MAP (
142 clk => clk,
103 clk => clk,
143 rstn => rstn,
104 rstn => rstn,
144 run => run,
105 run => run,
145 ren => data_ren(I),
106 ren => data_ren(I),
146 wen => data_wen(I),
107 wen => data_wen(I),
147 mem_re => data_mem_ren(I),
108 mem_re => data_mem_ren(I),
148 mem_we => data_mem_wen(I),
109 mem_we => data_mem_wen(I),
149 mem_addr_ren => data_mem_addr_r(I),
110 mem_addr_ren => data_mem_addr_r(I),
150 mem_addr_wen => data_mem_addr_w(I),
111 mem_addr_wen => data_mem_addr_w(I),
151 ready => data_ready(I));
112 empty_almost => empty_almost(I),
113 empty => empty(I),
114 full_almost => full_almost(I),
115 full => full(I)
116 );
152 END GENERATE gen_fifo_ctrl_data;
117 END GENERATE gen_fifo_ctrl_data;
153
118
154
119
155 END ARCHITECTURE;
120 END ARCHITECTURE;
156
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@@ -1,190 +1,259
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Jean-christophe PELLION
19 -- Author : Jean-christophe PELLION
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.std_logic_1164.ALL;
23 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.numeric_std.ALL;
24 USE IEEE.numeric_std.ALL;
25
25
26 LIBRARY lpp;
26 LIBRARY lpp;
27 USE lpp.lpp_waveform_pkg.ALL;
27 USE lpp.lpp_waveform_pkg.ALL;
28 USE lpp.general_purpose.ALL;
28
29
29 ENTITY lpp_waveform_fifo_arbiter IS
30 ENTITY lpp_waveform_fifo_arbiter IS
30 GENERIC(
31 GENERIC(
31 tech : INTEGER := 0
32 tech : INTEGER := 0;
33 nb_data_by_buffer_size : INTEGER
32 );
34 );
33 PORT(
35 PORT(
34 clk : IN STD_LOGIC;
36 clk : IN STD_LOGIC;
35 rstn : IN STD_LOGIC;
37 rstn : IN STD_LOGIC;
36 ---------------------------------------------------------------------------
38 ---------------------------------------------------------------------------
37 run : IN STD_LOGIC;
39 run : IN STD_LOGIC;
40 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size - 1 DOWNTO 0);
38 ---------------------------------------------------------------------------
41 ---------------------------------------------------------------------------
39 data_f0_valid : IN STD_LOGIC;
42 -- SNAPSHOT INTERFACE (INPUT)
40 data_f1_valid : IN STD_LOGIC;
43 ---------------------------------------------------------------------------
41 data_f2_valid : IN STD_LOGIC;
44 data_in_valid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
42 data_f3_valid : IN STD_LOGIC;
45 data_in_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
43
46 data_in : IN Data_Vector(3 DOWNTO 0, 95 DOWNTO 0);
44 data_valid_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
47 time_in : IN Data_Vector(3 DOWNTO 0, 47 DOWNTO 0);
45
46 data_f0 : IN STD_LOGIC_VECTOR(159 DOWNTO 0);
47 data_f1 : IN STD_LOGIC_VECTOR(159 DOWNTO 0);
48 data_f2 : IN STD_LOGIC_VECTOR(159 DOWNTO 0);
49 data_f3 : IN STD_LOGIC_VECTOR(159 DOWNTO 0);
50
48
51 ---------------------------------------------------------------------------
49 ---------------------------------------------------------------------------
52 ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
50 -- FIFO INTERFACE (OUTPUT)
53
54 ---------------------------------------------------------------------------
51 ---------------------------------------------------------------------------
55 time_wen : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
52 data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
56 data_wen : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
53 data_out_wen : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
57 data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
54 full : IN STD_LOGIC_VECTOR(3 DOWNTO 0)
58
55
59 );
56 );
60 END ENTITY;
57 END ENTITY;
61
58
62
59
63 ARCHITECTURE ar_lpp_waveform_fifo_arbiter OF lpp_waveform_fifo_arbiter IS
60 ARCHITECTURE ar_lpp_waveform_fifo_arbiter OF lpp_waveform_fifo_arbiter IS
64 TYPE state_fsm IS (IDLE, T1, T2, D1, D2);
65 SIGNAL state : state_fsm;
66
61
67 SIGNAL data_valid_and_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
62 -----------------------------------------------------------------------------
68 SIGNAL data_selected : STD_LOGIC_VECTOR(159 DOWNTO 0);
63 -- DATA FLOW
69 SIGNAL data_valid_selected : STD_LOGIC_VECTOR(3 DOWNTO 0);
64 -----------------------------------------------------------------------------
70 SIGNAL data_ready_to_go : STD_LOGIC;
65 TYPE WORD_VECTOR IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(31 DOWNTO 0);
71
66 SIGNAL time_temp_0 : WORD_VECTOR(3 DOWNTO 0);
72 SIGNAL data_temp : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
67 SIGNAL time_temp_1 : WORD_VECTOR(3 DOWNTO 0);
73 SIGNAL time_en_temp : STD_LOGIC_VECTOR(3 DOWNTO 0);
68 SIGNAL data_temp_0 : WORD_VECTOR(3 DOWNTO 0);
69 SIGNAL data_temp_1 : WORD_VECTOR(3 DOWNTO 0);
70 SIGNAL data_temp_2 : WORD_VECTOR(3 DOWNTO 0);
71 SIGNAL data_temp_v : WORD_VECTOR(3 DOWNTO 0);
72 SIGNAL sel_input : STD_LOGIC_VECTOR(3 DOWNTO 0);
73 -----------------------------------------------------------------------------
74 -- CHANNEL SELECTION (RoundRobin)
75 -----------------------------------------------------------------------------
76 SIGNAL valid_in_rr : STD_LOGIC_VECTOR(3 DOWNTO 0);
77 SIGNAL valid_out_rr : STD_LOGIC_VECTOR(3 DOWNTO 0);
78 -----------------------------------------------------------------------------
79 -- FSM CONTROL
80 -----------------------------------------------------------------------------
81 TYPE Counter_Vector IS ARRAY (NATURAL RANGE <>) OF INTEGER;
82 SIGNAL reg_shift_data : Counter_Vector(3 DOWNTO 0);
83 SIGNAL reg_shift_time : Counter_Vector(3 DOWNTO 0);
84 SIGNAL reg_count_data : Counter_Vector(3 DOWNTO 0);
85 -- SHIFT_DATA ---------------------------------------------------------------
86 SIGNAL shift_data_pre : INTEGER;
87 SIGNAL shift_data : INTEGER;
88 SIGNAL reg_shift_data_s : Counter_Vector(3 DOWNTO 0);
89 -- SHIFT_TIME ---------------------------------------------------------------
90 SIGNAL shift_time_pre : INTEGER;
91 SIGNAL shift_time : INTEGER;
92 SIGNAL reg_shift_time_s : Counter_Vector(3 DOWNTO 0);
93 -- COUNT_DATA ---------------------------------------------------------------
94 SIGNAL count_data_pre : INTEGER;
95 SIGNAL count_data : INTEGER;
96 SIGNAL reg_count_data_s : Counter_Vector(3 DOWNTO 0);
97
74 BEGIN
98 BEGIN
75
99
76 data_valid_and_ready(0) <= ready(0) AND data_f0_valid;
100 -----------------------------------------------------------------------------
77 data_valid_and_ready(1) <= ready(1) AND data_f1_valid;
101 -- DATA FLOW
78 data_valid_and_ready(2) <= ready(2) AND data_f2_valid;
102 -----------------------------------------------------------------------------
79 data_valid_and_ready(3) <= ready(3) AND data_f3_valid;
80
103
81 data_selected <= data_f0 WHEN data_valid_and_ready(0) = '1' ELSE
82 data_f1 WHEN data_valid_and_ready(1) = '1' ELSE
83 data_f2 WHEN data_valid_and_ready(2) = '1' ELSE
84 data_f3;
85
104
86 data_valid_selected <= "0001" WHEN data_valid_and_ready(0) = '1' ELSE
105 all_input : FOR I IN 3 DOWNTO 0 GENERATE
87 "0010" WHEN data_valid_and_ready(1) = '1' ELSE
106
88 "0100" WHEN data_valid_and_ready(2) = '1' ELSE
107 all_bit_of_time: FOR J IN 31 DOWNTO 0 GENERATE
89 "1000" WHEN data_valid_and_ready(3) = '1' ELSE
108 time_temp_0(I)(J) <= time_in(I,J);
90 "0000";
109 J_47DOWNTO32: IF J+32 < 48 GENERATE
91
110 time_temp_1(I)(J) <= time_in(I,32+J);
92 data_ready_to_go <= data_valid_and_ready(0) OR
111 END GENERATE J_47DOWNTO32;
93 data_valid_and_ready(1) OR
112 J_63DOWNTO48: IF J+32 > 47 GENERATE
94 data_valid_and_ready(2) OR
113 time_temp_1(I)(J) <= '0';
95 data_valid_and_ready(3);
114 END GENERATE J_63DOWNTO48;
115 data_temp_0(I)(J) <= data_in(I,J);
116 data_temp_1(I)(J) <= data_in(I,J+32);
117 data_temp_2(I)(J) <= data_in(I,J+32*2);
118 END GENERATE all_bit_of_time;
119
120 data_temp_v(I) <= time_temp_0(I) WHEN shift_time = 0 ELSE
121 time_temp_1(I) WHEN shift_time = 1 ELSE
122 data_temp_0(I) WHEN shift_data = 0 ELSE
123 data_temp_1(I) WHEN shift_data = 1 ELSE
124 data_temp_2(I);
125 END GENERATE all_input;
126
127 data_out <= data_temp_v(0) WHEN sel_input = "0001" ELSE
128 data_temp_v(1) WHEN sel_input = "0010" ELSE
129 data_temp_v(2) WHEN sel_input = "0100" ELSE
130 data_temp_v(3);
131
132 -----------------------------------------------------------------------------
133 -- CHANNEL SELECTION (RoundRobin)
134 -----------------------------------------------------------------------------
135 all_input_rr : FOR I IN 3 DOWNTO 0 GENERATE
136 -- valid_in_rr(I) <= data_in_valid(I) AND NOT full_almost(I);
137 valid_in_rr(I) <= data_in_valid(I) AND NOT full(I);
138 END GENERATE all_input_rr;
139
140 RR_Arbiter_4_1 : RR_Arbiter_4
141 PORT MAP (
142 clk => clk,
143 rstn => rstn,
144 in_valid => valid_in_rr,
145 out_grant => valid_out_rr);
146
147 -----------------------------------------------------------------------------
148 -- FSM CONTROL
149 -----------------------------------------------------------------------------
96
150
97 PROCESS (clk, rstn)
151 PROCESS (clk, rstn)
98 BEGIN
152 BEGIN -- PROCESS
99 IF rstn = '0' THEN
153 IF rstn = '0' THEN -- asynchronous reset (active low)
100 state <= IDLE;
154 reg_shift_data <= (0, 0, 0, 0);
101 data_valid_ack <= (OTHERS => '0');
155 reg_shift_time <= (0, 0, 0, 0);
102 data_wen <= (OTHERS => '1');
156 reg_count_data <= (0, 0, 0, 0);
103 time_wen <= (OTHERS => '1');
157 sel_input <= (OTHERS => '0');
104 data <= (OTHERS => '0');
158 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
105 data_temp <= (OTHERS => '0');
159 IF run = '0' THEN
106 time_en_temp <= (OTHERS => '0');
160 reg_shift_data <= (0, 0, 0, 0);
107 ELSIF clk'EVENT AND clk = '1' THEN
161 reg_shift_time <= (0, 0, 0, 0);
108 CASE state IS
162 reg_count_data <= (0, 0, 0, 0);
109 WHEN IDLE =>
163 sel_input <= (OTHERS => '0');
110 data_valid_ack <= (OTHERS => '0');
164 ELSE
111 time_wen <= (OTHERS => '1');
165 sel_input <= valid_out_rr;
112 data_wen <= (OTHERS => '1');
166
113 data <= (OTHERS => '0');
167 IF count_data_pre = 0 THEN -- first buffer data
114 data_temp <= (OTHERS => '0');
168 IF shift_time_pre < 2 THEN -- TIME not completly send
115 IF data_ready_to_go = '1' AND run = '1' THEN
169 reg_shift_time <= reg_shift_time_s;
116 state <= T1;
117 data_valid_ack <= data_valid_selected;
118 time_wen <= NOT data_valid_selected;
119 time_en_temp <= NOT data_valid_selected;
120 data <= data_selected(31 DOWNTO 0);
121 data_temp <= data_selected(159 DOWNTO 32);
122 END IF;
123 WHEN T1 =>
124 IF run = '0' THEN
125 state <= IDLE;
126 ELSE
170 ELSE
127 state <= T2;
171 reg_shift_data <= reg_shift_data_s;
172 IF shift_data_pre = 2 THEN
173 reg_count_data <= reg_count_data_s;
174 END IF;
128 END IF;
175 END IF;
129 data_valid_ack <= (OTHERS => '0');
176 ELSE
130 data <= data_temp(31 DOWNTO 0);
177 reg_shift_data <= reg_shift_data_s;
131 data_temp(32*3-1 DOWNTO 0) <= data_temp(32*4-1 DOWNTO 32);
178 IF shift_data_pre = 2 THEN
132
179 reg_count_data <= reg_count_data_s;
133 WHEN T2 =>
180 IF count_data = 0 THEN
134 IF run = '0' THEN
181 reg_shift_time <= reg_shift_time_s;
135 state <= IDLE;
182 END IF;
136 ELSE
137 state <= D1;
138 END IF;
183 END IF;
139 time_wen <= (OTHERS => '1');
184 END IF;
140 data_wen <= time_en_temp;
185 END IF;
141 data <= data_temp(31 DOWNTO 0);
142 data_temp(32*3-1 DOWNTO 0) <= data_temp(32*4-1 DOWNTO 32);
143
144 WHEN D1 =>
145 IF run = '0' THEN
146 state <= IDLE;
147 ELSE
148 state <= D2;
149 END IF;
150 data <= data_temp(31 DOWNTO 0);
151 data_temp(32*3-1 DOWNTO 0) <= data_temp(32*4-1 DOWNTO 32);
152
153 WHEN D2 =>
154 state <= IDLE;
155 data <= data_temp(31 DOWNTO 0);
156 data_temp(32*3-1 DOWNTO 0) <= data_temp(32*4-1 DOWNTO 32);
157
158 WHEN OTHERS => NULL;
159 END CASE;
160
161 END IF;
186 END IF;
162 END PROCESS;
187 END PROCESS;
163
188
189 -----------------------------------------------------------------------------
190 data_out_wen <= NOT sel_input;
191 data_in_ack <= sel_input;
192
193 -- SHIFT_DATA ---------------------------------------------------------------
194 shift_data_pre <= reg_shift_data(0) WHEN valid_out_rr(0) = '1' ELSE
195 reg_shift_data(1) WHEN valid_out_rr(1) = '1' ELSE
196 reg_shift_data(2) WHEN valid_out_rr(2) = '1' ELSE
197 reg_shift_data(3);
198
199 shift_data <= shift_data_pre + 1 WHEN shift_data_pre < 2 ELSE 0;
200
201 reg_shift_data_s(0) <= shift_data WHEN valid_out_rr(0) = '1' ELSE reg_shift_data_s(0);
202 reg_shift_data_s(1) <= shift_data WHEN valid_out_rr(1) = '1' ELSE reg_shift_data_s(1);
203 reg_shift_data_s(2) <= shift_data WHEN valid_out_rr(2) = '1' ELSE reg_shift_data_s(2);
204 reg_shift_data_s(3) <= shift_data WHEN valid_out_rr(3) = '1' ELSE reg_shift_data_s(3);
205
206 -- SHIFT_TIME ---------------------------------------------------------------
207 shift_time_pre <= reg_shift_time(0) WHEN valid_out_rr(0) = '1' ELSE
208 reg_shift_time(1) WHEN valid_out_rr(1) = '1' ELSE
209 reg_shift_time(2) WHEN valid_out_rr(2) = '1' ELSE
210 reg_shift_time(3);
211
212 shift_time <= shift_time_pre + 1 WHEN shift_time_pre < 2 ELSE 0;
213
214 reg_shift_time_s(0) <= shift_time WHEN valid_out_rr(0) = '1' ELSE reg_shift_time_s(0);
215 reg_shift_time_s(1) <= shift_time WHEN valid_out_rr(1) = '1' ELSE reg_shift_time_s(1);
216 reg_shift_time_s(2) <= shift_time WHEN valid_out_rr(2) = '1' ELSE reg_shift_time_s(2);
217 reg_shift_time_s(3) <= shift_time WHEN valid_out_rr(3) = '1' ELSE reg_shift_time_s(3);
218
219 -- COUNT_DATA ---------------------------------------------------------------
220 count_data_pre <= reg_count_data(0) WHEN valid_out_rr(0) = '1' ELSE
221 reg_count_data(1) WHEN valid_out_rr(1) = '1' ELSE
222 reg_count_data(2) WHEN valid_out_rr(2) = '1' ELSE
223 reg_count_data(3);
224
225 count_data <= count_data_pre + 1 WHEN count_data_pre < UNSIGNED(nb_data_by_buffer) ELSE 0;
226
227 reg_count_data_s(0) <= count_data WHEN valid_out_rr(0) = '1' ELSE reg_count_data_s(0);
228 reg_count_data_s(1) <= count_data WHEN valid_out_rr(1) = '1' ELSE reg_count_data_s(1);
229 reg_count_data_s(2) <= count_data WHEN valid_out_rr(2) = '1' ELSE reg_count_data_s(2);
230 reg_count_data_s(3) <= count_data WHEN valid_out_rr(3) = '1' ELSE reg_count_data_s(3);
231 -----------------------------------------------------------------------------
232
164 END ARCHITECTURE;
233 END ARCHITECTURE;
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Show file before | Show file after | Hide comments
@@ -1,178 +1,201
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Jean-christophe PELLION
19 -- Author : Jean-christophe PELLION
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.std_logic_1164.ALL;
23 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.numeric_std.ALL;
24 USE IEEE.numeric_std.ALL;
25 LIBRARY lpp;
25 LIBRARY lpp;
26 USE lpp.lpp_memory.ALL;
26 USE lpp.lpp_memory.ALL;
27 USE lpp.iir_filter.ALL;
27 USE lpp.iir_filter.ALL;
28 USE lpp.lpp_waveform_pkg.ALL;
28 USE lpp.lpp_waveform_pkg.ALL;
29
29
30 LIBRARY techmap;
30 LIBRARY techmap;
31 USE techmap.gencomp.ALL;
31 USE techmap.gencomp.ALL;
32
32
33 ENTITY lpp_waveform_fifo_ctrl IS
33 ENTITY lpp_waveform_fifo_ctrl IS
34 generic(
34 generic(
35 offset : INTEGER := 0;
35 offset : INTEGER := 0;
36 length : INTEGER := 20;
36 length : INTEGER := 20
37 enable_ready : STD_LOGIC := '1'
38 );
37 );
39 PORT(
38 PORT(
40 clk : IN STD_LOGIC;
39 clk : IN STD_LOGIC;
41 rstn : IN STD_LOGIC;
40 rstn : IN STD_LOGIC;
42
41
43 run : IN STD_LOGIC;
42 run : IN STD_LOGIC;
44
43
45 ren : IN STD_LOGIC;
44 ren : IN STD_LOGIC;
46 wen : IN STD_LOGIC;
45 wen : IN STD_LOGIC;
47
46
48 mem_re : OUT STD_LOGIC;
47 mem_re : OUT STD_LOGIC;
49 mem_we : OUT STD_LOGIC;
48 mem_we : OUT STD_LOGIC;
50
49
51 mem_addr_ren : out STD_LOGIC_VECTOR(6 DOWNTO 0);
50 mem_addr_ren : out STD_LOGIC_VECTOR(6 DOWNTO 0);
52 mem_addr_wen : out STD_LOGIC_VECTOR(6 DOWNTO 0);
51 mem_addr_wen : out STD_LOGIC_VECTOR(6 DOWNTO 0);
53
52 ---------------------------------------------------------------------------
54 ready : OUT STD_LOGIC
53 empty_almost : OUT STD_LOGIC; --occupancy is lesser than 16 * 32b
54 empty : OUT STD_LOGIC;
55 full_almost : OUT STD_LOGIC; --occupancy is greater than MAX - 5 * 32b
56 full : OUT STD_LOGIC
57
55 );
58 );
56 END ENTITY;
59 END ENTITY;
57
60
58
61
59 ARCHITECTURE ar_lpp_waveform_fifo_ctrl OF lpp_waveform_fifo_ctrl IS
62 ARCHITECTURE ar_lpp_waveform_fifo_ctrl OF lpp_waveform_fifo_ctrl IS
60
63
61 SIGNAL sFull : STD_LOGIC;
64 SIGNAL sFull : STD_LOGIC;
62 SIGNAL sFull_s : STD_LOGIC;
65 SIGNAL sFull_s : STD_LOGIC;
63 SIGNAL sEmpty_s : STD_LOGIC;
66 SIGNAL sEmpty_s : STD_LOGIC;
64
67
65 SIGNAL sEmpty : STD_LOGIC;
68 SIGNAL sEmpty : STD_LOGIC;
66 SIGNAL sREN : STD_LOGIC;
69 SIGNAL sREN : STD_LOGIC;
67 SIGNAL sWEN : STD_LOGIC;
70 SIGNAL sWEN : STD_LOGIC;
68 SIGNAL sRE : STD_LOGIC;
71 SIGNAL sRE : STD_LOGIC;
69 SIGNAL sWE : STD_LOGIC;
72 SIGNAL sWE : STD_LOGIC;
70
73
71 SIGNAL Waddr_vect : INTEGER RANGE 0 TO length := 0;
74 SIGNAL Waddr_vect : INTEGER RANGE 0 TO length := 0;
72 SIGNAL Raddr_vect : INTEGER RANGE 0 TO length := 0;
75 SIGNAL Raddr_vect : INTEGER RANGE 0 TO length := 0;
73 SIGNAL Waddr_vect_s : INTEGER RANGE 0 TO length := 0;
76 SIGNAL Waddr_vect_s : INTEGER RANGE 0 TO length := 0;
74 SIGNAL Raddr_vect_s : INTEGER RANGE 0 TO length := 0;
77 SIGNAL Raddr_vect_s : INTEGER RANGE 0 TO length := 0;
75
78
79 SIGNAL space_busy : INTEGER RANGE 0 TO length := 0;
80 SIGNAL space_free : INTEGER RANGE 0 TO length := 0;
81
76 BEGIN
82 BEGIN
77 mem_re <= sRE;
83 mem_re <= sRE;
78 mem_we <= sWE;
84 mem_we <= sWE;
79 --=============================
85 --=============================
80 -- Read section
86 -- Read section
81 --=============================
87 --=============================
82 sREN <= REN OR sEmpty;
88 sREN <= REN OR sEmpty;
83 sRE <= NOT sREN;
89 sRE <= NOT sREN;
84
90
85 sEmpty_s <= '1' WHEN sEmpty = '1' AND Wen = '1' ELSE
91 sEmpty_s <= '1' WHEN sEmpty = '1' AND Wen = '1' ELSE
86 '1' WHEN sEmpty = '0' AND (Wen = '1' AND Ren = '0' AND Raddr_vect_s = Waddr_vect) ELSE
92 '1' WHEN sEmpty = '0' AND (Wen = '1' AND Ren = '0' AND Raddr_vect_s = Waddr_vect) ELSE
87 '0';
93 '0';
88
94
89 Raddr_vect_s <= Raddr_vect +1 WHEN Raddr_vect < length -1 ELSE 0 ;
95 Raddr_vect_s <= Raddr_vect +1 WHEN Raddr_vect < length -1 ELSE 0 ;
90
96
91 PROCESS (clk, rstn)
97 PROCESS (clk, rstn)
92 BEGIN
98 BEGIN
93 IF(rstn = '0')then
99 IF(rstn = '0')then
94 Raddr_vect <= 0;
100 Raddr_vect <= 0;
95 sempty <= '1';
101 sempty <= '1';
96 ELSIF(clk'EVENT AND clk = '1')then
102 ELSIF(clk'EVENT AND clk = '1')then
97 IF run = '0' THEN
103 IF run = '0' THEN
98 Raddr_vect <= 0;
104 Raddr_vect <= 0;
99 sempty <= '1';
105 sempty <= '1';
100 ELSE
106 ELSE
101 sEmpty <= sempty_s;
107 sEmpty <= sempty_s;
102 IF(sREN = '0' and sempty = '0')then
108 IF(sREN = '0' and sempty = '0')then
103 Raddr_vect <= Raddr_vect_s;
109 Raddr_vect <= Raddr_vect_s;
104 END IF;
110 END IF;
105 END IF;
111 END IF;
106 END IF;
112 END IF;
107 END PROCESS;
113 END PROCESS;
108
114
109 --=============================
115 --=============================
110 -- Write section
116 -- Write section
111 --=============================
117 --=============================
112 sWEN <= WEN OR sFull;
118 sWEN <= WEN OR sFull;
113 sWE <= NOT sWEN;
119 sWE <= NOT sWEN;
114
120
115 sFull_s <= '1' WHEN Waddr_vect_s = Raddr_vect AND REN = '1' AND WEN = '0' ELSE
121 sFull_s <= '1' WHEN Waddr_vect_s = Raddr_vect AND REN = '1' AND WEN = '0' ELSE
116 '1' WHEN sFull = '1' AND REN = '1' ELSE
122 '1' WHEN sFull = '1' AND REN = '1' ELSE
117 '0';
123 '0';
118
124
119 Waddr_vect_s <= Waddr_vect +1 WHEN Waddr_vect < length -1 ELSE 0 ;
125 Waddr_vect_s <= Waddr_vect +1 WHEN Waddr_vect < length -1 ELSE 0 ;
120
126
121 PROCESS (clk, rstn)
127 PROCESS (clk, rstn)
122 BEGIN
128 BEGIN
123 IF(rstn = '0')then
129 IF(rstn = '0')then
124 Waddr_vect <= 0;
130 Waddr_vect <= 0;
125 sfull <= '0';
131 sfull <= '0';
126 ELSIF(clk'EVENT AND clk = '1')THEN
132 ELSIF(clk'EVENT AND clk = '1')THEN
127 IF run = '0' THEN
133 IF run = '0' THEN
128 Waddr_vect <= 0;
134 Waddr_vect <= 0;
129 sfull <= '0';
135 sfull <= '0';
130 ELSE
136 ELSE
131 sfull <= sfull_s;
137 sfull <= sfull_s;
132 IF(sWEN = '0' and sfull = '0')THEN
138 IF(sWEN = '0' and sfull = '0')THEN
133 Waddr_vect <= Waddr_vect_s;
139 Waddr_vect <= Waddr_vect_s;
134 END IF;
140 END IF;
135 END IF;
141 END IF;
136 END IF;
142 END IF;
137 END PROCESS;
143 END PROCESS;
138
144
139
145
140 mem_addr_wen <= std_logic_vector(to_unsigned((Waddr_vect + offset), mem_addr_wen'length));
146 mem_addr_wen <= std_logic_vector(to_unsigned((Waddr_vect + offset), mem_addr_wen'length));
141 mem_addr_ren <= std_logic_vector(to_unsigned((Raddr_vect + offset), mem_addr_ren'length));
147 mem_addr_ren <= std_logic_vector(to_unsigned((Raddr_vect + offset), mem_addr_ren'length));
142
148
143 ready_gen: IF enable_ready = '1' GENERATE
149
144 ready <= '1' WHEN Waddr_vect > Raddr_vect AND (Waddr_vect - Raddr_vect) > 15 ELSE
150 -----------------------------------------------------------------------------
145 '1' WHEN Waddr_vect < Raddr_vect AND (length + Waddr_vect - Raddr_vect) > 15 ELSE
151 --
146 '0';
152 -----------------------------------------------------------------------------
147 END GENERATE ready_gen;
153 --empty_almost <= '0' WHEN Waddr_vect > Raddr_vect AND ( Waddr_vect - Raddr_vect) > 15 ELSE
154 -- '0' WHEN Waddr_vect < Raddr_vect AND (length + Waddr_vect - Raddr_vect) > 15 ELSE
155 -- '1';
156 empty_almost <= '0' WHEN space_busy > 15 ELSE '1';
157 empty <= sEmpty;
148
158
149 ready_not_gen: IF enable_ready = '0' GENERATE
159 --full_almost <= '0' WHEN Waddr_vect > Raddr_vect AND (length + Raddr_vect - Waddr_vect) > 5 ELSE
150 ready <= '0';
160 -- '0' WHEN Waddr_vect < Raddr_vect AND ( Raddr_vect - Waddr_vect) > 5 ELSE
151 END GENERATE ready_not_gen;
161 -- sfull WHEN Waddr_vect = Raddr_vect ELSE
162 -- '1';
163 full_almost <= '0' WHEN space_free > 4 ELSE '1';
164 full <= sfull;
165
166 -----------------------------------------------------------------------------
167 --
168 -----------------------------------------------------------------------------
169 space_busy <= length WHEN sfull = '1' ELSE
170 length + Waddr_vect - Raddr_vect WHEN Waddr_vect < Raddr_vect ELSE
171 Waddr_vect - Raddr_vect;
172
173 space_free <= length - space_busy;
174
152
175
153 END ARCHITECTURE;
176 END ARCHITECTURE;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
22 -------------------------------------------------------------------------------
1 LIBRARY IEEE;
23 LIBRARY IEEE;
2 USE IEEE.STD_LOGIC_1164.ALL;
24 USE IEEE.STD_LOGIC_1164.ALL;
3
25
4 LIBRARY grlib;
26 LIBRARY grlib;
5 USE grlib.amba.ALL;
27 USE grlib.amba.ALL;
6 USE grlib.stdlib.ALL;
28 USE grlib.stdlib.ALL;
7 USE grlib.devices.ALL;
29 USE grlib.devices.ALL;
8 USE GRLIB.DMA2AHB_Package.ALL;
30 USE GRLIB.DMA2AHB_Package.ALL;
9
31
10 LIBRARY techmap;
32 LIBRARY techmap;
11 USE techmap.gencomp.ALL;
33 USE techmap.gencomp.ALL;
12
34
13 PACKAGE lpp_waveform_pkg IS
35 PACKAGE lpp_waveform_pkg IS
14
36
15 TYPE LPP_TYPE_ADDR_FIFO_WAVEFORM IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(6 DOWNTO 0);
37 TYPE LPP_TYPE_ADDR_FIFO_WAVEFORM IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(6 DOWNTO 0);
38
39 TYPE Data_Vector IS ARRAY (NATURAL RANGE <>,NATURAL RANGE <>) OF STD_LOGIC;
40
41 -----------------------------------------------------------------------------
42 -- SNAPSHOT
43 -----------------------------------------------------------------------------
16
44
17 COMPONENT lpp_waveform_snapshot
45 COMPONENT lpp_waveform_snapshot
18 GENERIC (
46 GENERIC (
19 data_size : INTEGER;
47 data_size : INTEGER;
20 nb_snapshot_param_size : INTEGER);
48 nb_snapshot_param_size : INTEGER);
21 PORT (
49 PORT (
22 clk : IN STD_LOGIC;
50 clk : IN STD_LOGIC;
23 rstn : IN STD_LOGIC;
51 rstn : IN STD_LOGIC;
24 run : IN STD_LOGIC;
52 run : IN STD_LOGIC;
25 enable : IN STD_LOGIC;
53 enable : IN STD_LOGIC;
26 burst_enable : IN STD_LOGIC;
54 burst_enable : IN STD_LOGIC;
27 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
55 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
28 start_snapshot : IN STD_LOGIC;
56 start_snapshot : IN STD_LOGIC;
29 data_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
57 data_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
30 data_in_valid : IN STD_LOGIC;
58 data_in_valid : IN STD_LOGIC;
31 data_out : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
59 data_out : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
32 data_out_valid : OUT STD_LOGIC);
60 data_out_valid : OUT STD_LOGIC);
33 END COMPONENT;
61 END COMPONENT;
34
62
35 COMPONENT lpp_waveform_burst
63 COMPONENT lpp_waveform_burst
36 GENERIC (
64 GENERIC (
37 data_size : INTEGER);
65 data_size : INTEGER);
38 PORT (
66 PORT (
39 clk : IN STD_LOGIC;
67 clk : IN STD_LOGIC;
40 rstn : IN STD_LOGIC;
68 rstn : IN STD_LOGIC;
41 run : IN STD_LOGIC;
69 run : IN STD_LOGIC;
42 enable : IN STD_LOGIC;
70 enable : IN STD_LOGIC;
43 data_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
71 data_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
44 data_in_valid : IN STD_LOGIC;
72 data_in_valid : IN STD_LOGIC;
45 data_out : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
73 data_out : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
46 data_out_valid : OUT STD_LOGIC);
74 data_out_valid : OUT STD_LOGIC);
47 END COMPONENT;
75 END COMPONENT;
48
76
49 COMPONENT lpp_waveform_snapshot_controler
77 COMPONENT lpp_waveform_snapshot_controler
50 GENERIC (
78 GENERIC (
51 delta_snapshot_size : INTEGER;
79 delta_vector_size : INTEGER;
52 delta_f2_f0_size : INTEGER;
80 delta_vector_size_f0_2 : INTEGER);
53 delta_f2_f1_size : INTEGER);
54 PORT (
81 PORT (
55 clk : IN STD_LOGIC;
82 clk : IN STD_LOGIC;
56 rstn : IN STD_LOGIC;
83 rstn : IN STD_LOGIC;
57 run : IN STD_LOGIC;
84 reg_run : IN STD_LOGIC;
58 delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
85 reg_start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
59 delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
86 reg_delta_snapshot : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
60 delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
87 reg_delta_f0 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
61 coarse_time_0 : IN STD_LOGIC;
88 reg_delta_f0_2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
62 data_f0_in_valid : IN STD_LOGIC;
89 reg_delta_f1 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
63 data_f2_in_valid : IN STD_LOGIC;
90 reg_delta_f2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
64 start_snapshot_f0 : OUT STD_LOGIC;
91 coarse_time : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
65 start_snapshot_f1 : OUT STD_LOGIC;
92 data_f0_valid : IN STD_LOGIC;
66 start_snapshot_f2 : OUT STD_LOGIC);
93 data_f2_valid : IN STD_LOGIC;
94 start_snapshot_f0 : OUT STD_LOGIC;
95 start_snapshot_f1 : OUT STD_LOGIC;
96 start_snapshot_f2 : OUT STD_LOGIC;
97 wfp_on : OUT STD_LOGIC);
67 END COMPONENT;
98 END COMPONENT;
68
99
69
100 -----------------------------------------------------------------------------
70
101 --
102 -----------------------------------------------------------------------------
71 COMPONENT lpp_waveform
103 COMPONENT lpp_waveform
72 GENERIC (
104 GENERIC (
73 hindex : INTEGER;
105 tech : INTEGER;
74 tech : INTEGER;
106 data_size : INTEGER;
75 data_size : INTEGER;
107 nb_data_by_buffer_size : INTEGER;
76 nb_burst_available_size : INTEGER;
108 nb_snapshot_param_size : INTEGER;
77 nb_snapshot_param_size : INTEGER;
109 delta_vector_size : INTEGER;
78 delta_snapshot_size : INTEGER;
110 delta_vector_size_f0_2 : INTEGER);
79 delta_f2_f0_size : INTEGER;
80 delta_f2_f1_size : INTEGER);
81 PORT (
111 PORT (
82 clk : IN STD_LOGIC;
112 clk : IN STD_LOGIC;
83 rstn : IN STD_LOGIC;
113 rstn : IN STD_LOGIC;
84 AHB_Master_In : IN AHB_Mst_In_Type;
114 reg_run : IN STD_LOGIC;
85 AHB_Master_Out : OUT AHB_Mst_Out_Type;
115 reg_start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
86 coarse_time_0 : IN STD_LOGIC;
116 reg_delta_snapshot : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
87 delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
117 reg_delta_f0 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
88 delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
118 reg_delta_f0_2 : IN STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
89 delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
119 reg_delta_f1 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
90 enable_f0 : IN STD_LOGIC;
120 reg_delta_f2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
91 enable_f1 : IN STD_LOGIC;
121 enable_f0 : IN STD_LOGIC;
92 enable_f2 : IN STD_LOGIC;
122 enable_f1 : IN STD_LOGIC;
93 enable_f3 : IN STD_LOGIC;
123 enable_f2 : IN STD_LOGIC;
94 burst_f0 : IN STD_LOGIC;
124 enable_f3 : IN STD_LOGIC;
95 burst_f1 : IN STD_LOGIC;
125 burst_f0 : IN STD_LOGIC;
96 burst_f2 : IN STD_LOGIC;
126 burst_f1 : IN STD_LOGIC;
97 run : IN STD_LOGIC;
127 burst_f2 : IN STD_LOGIC;
98 nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
128 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
99 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
129 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
100 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
130 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
101 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
131 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
102 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
132 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
103 status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
133 status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
104 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
134 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
105 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
135 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
106 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
136 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
107 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
137 data_f0_in_valid : IN STD_LOGIC;
108 data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
138 data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
109 data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
139 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
110 data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
140 data_f1_in_valid : IN STD_LOGIC;
111 data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
141 data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
112 data_f0_in_valid : IN STD_LOGIC;
142 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
113 data_f1_in_valid : IN STD_LOGIC;
143 data_f2_in_valid : IN STD_LOGIC;
114 data_f2_in_valid : IN STD_LOGIC;
144 data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
115 data_f3_in_valid : IN STD_LOGIC);
145 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
116 END COMPONENT;
146 data_f3_in_valid : IN STD_LOGIC;
117
147 data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
118 COMPONENT lpp_waveform_dma_send_Nword
148 data_f0_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
119 PORT (
149 data_f0_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
120 HCLK : IN STD_ULOGIC;
150 data_f0_data_out_valid : OUT STD_LOGIC;
121 HRESETn : IN STD_ULOGIC;
151 data_f0_data_out_valid_burst : OUT STD_LOGIC;
122 DMAIn : OUT DMA_In_Type;
152 data_f0_data_out_ren : IN STD_LOGIC;
123 DMAOut : IN DMA_OUt_Type;
153 data_f1_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
124 Nb_word_less1 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
154 data_f1_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
125 send : IN STD_LOGIC;
155 data_f1_data_out_valid : OUT STD_LOGIC;
126 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
156 data_f1_data_out_valid_burst : OUT STD_LOGIC;
127 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
157 data_f1_data_out_ren : IN STD_LOGIC;
128 ren : OUT STD_LOGIC;
158 data_f2_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
129 send_ok : OUT STD_LOGIC;
159 data_f2_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
130 send_ko : OUT STD_LOGIC);
160 data_f2_data_out_valid : OUT STD_LOGIC;
161 data_f2_data_out_valid_burst : OUT STD_LOGIC;
162 data_f2_data_out_ren : IN STD_LOGIC;
163 data_f3_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
164 data_f3_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
165 data_f3_data_out_valid : OUT STD_LOGIC;
166 data_f3_data_out_valid_burst : OUT STD_LOGIC;
167 data_f3_data_out_ren : IN STD_LOGIC);
131 END COMPONENT;
168 END COMPONENT;
132
169
133 COMPONENT lpp_waveform_dma_selectaddress
170 COMPONENT lpp_waveform_dma_genvalid
134 GENERIC (
135 nb_burst_available_size : INTEGER);
136 PORT (
137 HCLK : IN STD_ULOGIC;
138 HRESETn : IN STD_ULOGIC;
139 run : IN STD_LOGIC;
140 enable : IN STD_LOGIC;
141 update : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
142 nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
143 addr_data_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
144 addr_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
145 status_full : OUT STD_LOGIC;
146 status_full_ack : IN STD_LOGIC;
147 status_full_err : OUT STD_LOGIC);
148 END COMPONENT;
149
150 COMPONENT lpp_waveform_dma_gen_valid
151 PORT (
171 PORT (
152 HCLK : IN STD_LOGIC;
172 HCLK : IN STD_LOGIC;
153 HRESETn : IN STD_LOGIC;
173 HRESETn : IN STD_LOGIC;
154 run : IN STD_LOGIC;
174 run : IN STD_LOGIC;
155 valid_in : IN STD_LOGIC;
175 valid_in : IN STD_LOGIC;
156 ack_in : IN STD_LOGIC;
176 ack_in : IN STD_LOGIC;
177 time_in : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
157 valid_out : OUT STD_LOGIC;
178 valid_out : OUT STD_LOGIC;
179 time_out : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
158 error : OUT STD_LOGIC);
180 error : OUT STD_LOGIC);
159 END COMPONENT;
181 END COMPONENT;
160
182
161 COMPONENT lpp_waveform_dma
183 -----------------------------------------------------------------------------
162 GENERIC (
184 -- FIFO
163 data_size : INTEGER;
185 -----------------------------------------------------------------------------
164 tech : INTEGER;
165 hindex : INTEGER;
166 nb_burst_available_size : INTEGER);
167 PORT (
168 HCLK : IN STD_ULOGIC;
169 HRESETn : IN STD_ULOGIC;
170 run : IN STD_LOGIC;
171 AHB_Master_In : IN AHB_Mst_In_Type;
172 AHB_Master_Out : OUT AHB_Mst_Out_Type;
173 enable : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -- todo
174 time_ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -- todo
175 data_ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
176 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
177 data_data_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
178 data_time_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
179 --data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
180 --data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
181 --data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
182 --data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
183 --data_f0_in_valid : IN STD_LOGIC;
184 --data_f1_in_valid : IN STD_LOGIC;
185 --data_f2_in_valid : IN STD_LOGIC;
186 --data_f3_in_valid : IN STD_LOGIC;
187 nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
188 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
189 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
190 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
191 -- status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
192 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
193 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
194 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
195 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
196 END COMPONENT;
197
198 COMPONENT lpp_waveform_fifo_ctrl
186 COMPONENT lpp_waveform_fifo_ctrl
199 GENERIC (
187 GENERIC (
200 offset : INTEGER;
188 offset : INTEGER;
201 length : INTEGER;
189 length : INTEGER);
202 enable_ready : STD_LOGIC);
203 PORT (
190 PORT (
204 clk : IN STD_LOGIC;
191 clk : IN STD_LOGIC;
205 rstn : IN STD_LOGIC;
192 rstn : IN STD_LOGIC;
206 run : IN STD_LOGIC;
193 run : IN STD_LOGIC;
207 ren : IN STD_LOGIC;
194 ren : IN STD_LOGIC;
208 wen : IN STD_LOGIC;
195 wen : IN STD_LOGIC;
209 mem_re : OUT STD_LOGIC;
196 mem_re : OUT STD_LOGIC;
210 mem_we : OUT STD_LOGIC;
197 mem_we : OUT STD_LOGIC;
211 mem_addr_ren : out STD_LOGIC_VECTOR(6 DOWNTO 0);
198 mem_addr_ren : out STD_LOGIC_VECTOR(6 DOWNTO 0);
212 mem_addr_wen : out STD_LOGIC_VECTOR(6 DOWNTO 0);
199 mem_addr_wen : out STD_LOGIC_VECTOR(6 DOWNTO 0);
213 ready : OUT STD_LOGIC);
200 empty_almost : OUT STD_LOGIC;
201 empty : OUT STD_LOGIC;
202 full_almost : OUT STD_LOGIC;
203 full : OUT STD_LOGIC);
214 END COMPONENT;
204 END COMPONENT;
215
205
216 COMPONENT lpp_waveform_fifo_arbiter
206 COMPONENT lpp_waveform_fifo_arbiter
217 GENERIC (
207 GENERIC (
218 tech : INTEGER);
208 tech : INTEGER;
209 nb_data_by_buffer_size : INTEGER);
219 PORT (
210 PORT (
220 clk : IN STD_LOGIC;
211 clk : IN STD_LOGIC;
221 rstn : IN STD_LOGIC;
212 rstn : IN STD_LOGIC;
222 run : IN STD_LOGIC;
213 run : IN STD_LOGIC;
223 data_f0_valid : IN STD_LOGIC;
214 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size - 1 DOWNTO 0);
224 data_f1_valid : IN STD_LOGIC;
215 data_in_valid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
225 data_f2_valid : IN STD_LOGIC;
216 data_in_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
226 data_f3_valid : IN STD_LOGIC;
217 data_in : IN Data_Vector(3 DOWNTO 0, 95 DOWNTO 0);
227 data_valid_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
218 time_in : IN Data_Vector(3 DOWNTO 0, 47 DOWNTO 0);
228 data_f0 : IN STD_LOGIC_VECTOR(159 DOWNTO 0);
219 data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
229 data_f1 : IN STD_LOGIC_VECTOR(159 DOWNTO 0);
220 data_out_wen : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
230 data_f2 : IN STD_LOGIC_VECTOR(159 DOWNTO 0);
221 full : IN STD_LOGIC_VECTOR(3 DOWNTO 0));
231 data_f3 : IN STD_LOGIC_VECTOR(159 DOWNTO 0);
232 ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
233 time_wen : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
234 data_wen : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
235 data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
236 END COMPONENT;
222 END COMPONENT;
237
223
238 COMPONENT lpp_waveform_fifo
224 COMPONENT lpp_waveform_fifo
239 GENERIC (
225 GENERIC (
240 tech : INTEGER);
226 tech : INTEGER);
241 PORT (
227 PORT (
242 clk : IN STD_LOGIC;
228 clk : IN STD_LOGIC;
243 rstn : IN STD_LOGIC;
229 rstn : IN STD_LOGIC;
244 run : IN STD_LOGIC;
230 run : IN STD_LOGIC;
245 time_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
231 empty_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
246 data_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
232 empty : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
247 time_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
233 data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
248 data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
234 rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
249 rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
235 full_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
250 time_wen : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
236 full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
251 data_wen : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
237 data_wen : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
252 wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
238 wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
253 END COMPONENT;
239 END COMPONENT;
254
240
255
241 -----------------------------------------------------------------------------
242 -- GEN ADDRESS
243 -----------------------------------------------------------------------------
244 COMPONENT lpp_waveform_genaddress
245 GENERIC (
246 nb_data_by_buffer_size : INTEGER);
247 PORT (
248 clk : IN STD_LOGIC;
249 rstn : IN STD_LOGIC;
250 run : IN STD_LOGIC;
251 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
252 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
253 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
254 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
255 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
256 empty : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
257 empty_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
258 data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
259 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
260 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
261 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
262 data_f0_data_out_valid_burst : OUT STD_LOGIC;
263 data_f1_data_out_valid_burst : OUT STD_LOGIC;
264 data_f2_data_out_valid_burst : OUT STD_LOGIC;
265 data_f3_data_out_valid_burst : OUT STD_LOGIC;
266 data_f0_data_out_valid : OUT STD_LOGIC;
267 data_f1_data_out_valid : OUT STD_LOGIC;
268 data_f2_data_out_valid : OUT STD_LOGIC;
269 data_f3_data_out_valid : OUT STD_LOGIC;
270 data_f0_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
271 data_f1_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
272 data_f2_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
273 data_f3_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
274 END COMPONENT;
275
256
276
257 END lpp_waveform_pkg;
277 END lpp_waveform_pkg;
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@@ -1,128 +1,226
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
22 -------------------------------------------------------------------------------
1 LIBRARY IEEE;
23 LIBRARY IEEE;
2 USE IEEE.STD_LOGIC_1164.ALL;
24 USE IEEE.STD_LOGIC_1164.ALL;
3 USE ieee.numeric_std.ALL;
25 USE ieee.numeric_std.ALL;
4
26
27 LIBRARY lpp;
28 USE lpp.general_purpose.ALL;
29
5 ENTITY lpp_waveform_snapshot_controler IS
30 ENTITY lpp_waveform_snapshot_controler IS
6
31
7 GENERIC (
32 GENERIC (
8 delta_snapshot_size : INTEGER := 16;
33 delta_vector_size : INTEGER := 20;
9 delta_f2_f0_size : INTEGER := 10;
34 delta_vector_size_f0_2 : INTEGER := 3
10 delta_f2_f1_size : INTEGER := 10);
35 );
11
36
12 PORT (
37 PORT (
13 clk : IN STD_LOGIC;
38 clk : IN STD_LOGIC;
14 rstn : IN STD_LOGIC;
39 rstn : IN STD_LOGIC;
15 --
40 ---------------------------------------------------------------------------
16 run : IN STD_LOGIC;
41 --REGISTER CONTROL
17 --config
42 reg_run : IN STD_LOGIC;
18 delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
43 reg_start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
19 delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
44 reg_delta_snapshot : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
20 delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
45 reg_delta_f0 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
21
46 reg_delta_f0_2 : IN STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
22 --input
47 reg_delta_f1 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
23 coarse_time_0 : IN STD_LOGIC;
48 reg_delta_f2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
24 data_f0_in_valid : IN STD_LOGIC;
49 ---------------------------------------------------------------------------
25 data_f2_in_valid : IN STD_LOGIC;
50 -- INPUT
26 --output
51 coarse_time : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
27 start_snapshot_f0 : OUT STD_LOGIC;
52 data_f0_valid : IN STD_LOGIC;
28 start_snapshot_f1 : OUT STD_LOGIC;
53 data_f2_valid : IN STD_LOGIC;
29 start_snapshot_f2 : OUT STD_LOGIC
54 ---------------------------------------------------------------------------
55 -- OUTPUT
56 start_snapshot_f0 : OUT STD_LOGIC;
57 start_snapshot_f1 : OUT STD_LOGIC;
58 start_snapshot_f2 : OUT STD_LOGIC;
59 wfp_on : OUT STD_LOGIC
30 );
60 );
31
61
32 END lpp_waveform_snapshot_controler;
62 END lpp_waveform_snapshot_controler;
33
63
34 ARCHITECTURE beh OF lpp_waveform_snapshot_controler IS
64 ARCHITECTURE beh OF lpp_waveform_snapshot_controler IS
65 -----------------------------------------------------------------------------
66 -- WAVEFORM ON/OFF FSM
67 SIGNAL state_on : STD_LOGIC;
68 SIGNAL wfp_on_s : STD_LOGIC;
69 -----------------------------------------------------------------------------
70 -- StartSnapshot Generator for f2, f1 and f0_pre
71 SIGNAL start_snapshot_f0_pre : STD_LOGIC;
72 -- SIGNAL first_decount_s : STD_LOGIC;
73 SIGNAL first_decount : STD_LOGIC;
74 SIGNAL first_init : STD_LOGIC;
35 SIGNAL counter_delta_snapshot : INTEGER;
75 SIGNAL counter_delta_snapshot : INTEGER;
76 -----------------------------------------------------------------------------
77 -- StartSnapshot Generator for f0
36 SIGNAL counter_delta_f0 : INTEGER;
78 SIGNAL counter_delta_f0 : INTEGER;
79 SIGNAL send_start_snapshot_f0 : STD_LOGIC;
80 BEGIN -- beh
81 wfp_on <= wfp_on_s;
37
82
38 SIGNAL coarse_time_0_r : STD_LOGIC;
83 -----------------------------------------------------------------------------
39 SIGNAL start_snapshot_f2_temp : STD_LOGIC;
84 -- WAVEFORM ON/OFF FSM
40 SIGNAL start_snapshot_fothers_temp : STD_LOGIC;
85 -----------------------------------------------------------------------------
41 BEGIN -- beh
86 -- INPUT reg_run
42
87 -- coarse_time
43 PROCESS (clk, rstn)
88 -- reg_start_date
89 -- OUTPUT wfp_on_s
90 -----------------------------------------------------------------------------
91 waveform_on_off_fsm : PROCESS (clk, rstn)
44 BEGIN
92 BEGIN
45 IF rstn = '0' THEN
93 IF rstn = '0' THEN
46 start_snapshot_f0 <= '0';
94 state_on <= '0';
47 start_snapshot_f1 <= '0';
48 start_snapshot_f2 <= '0';
49 counter_delta_snapshot <= 0;
50 counter_delta_f0 <= 0;
51 coarse_time_0_r <= '0';
52 start_snapshot_f2_temp <= '0';
53 start_snapshot_fothers_temp <= '0';
54 ELSIF clk'EVENT AND clk = '1' THEN
95 ELSIF clk'EVENT AND clk = '1' THEN
55 IF run = '0' THEN
96 IF state_on = '1' THEN -- Waveform Picker ON
56 start_snapshot_f0 <= '0';
97 state_on <= reg_run;
57 start_snapshot_f1 <= '0';
98 ELSE -- Waveform Picker OFF
58 start_snapshot_f2 <= '0';
99 IF coarse_time = reg_start_date THEN
59 counter_delta_snapshot <= 0;
100 state_on <= reg_run;
60 counter_delta_f0 <= 0;
101 END IF;
61 coarse_time_0_r <= '0';
102 END IF;
62 start_snapshot_f2_temp <= '0';
103 END IF;
63 start_snapshot_fothers_temp <= '0';
104 END PROCESS waveform_on_off_fsm;
105 wfp_on_s <= state_on;
106 -----------------------------------------------------------------------------
107
108 -----------------------------------------------------------------------------
109 -- StartSnapshot Generator for f2, f1 and f0_pre
110 -----------------------------------------------------------------------------
111 -- INPUT wfp_on_s
112 -- reg_delta_snapshot
113 -- reg_delta_f0
114 -- reg_delta_f1
115 -- reg_delta_f2
116 -- data_f2_valid
117 -- OUTPUT start_snapshot_f0_pre
118 -- start_snapshot_f1
119 -- start_snapshot_f2
120 -----------------------------------------------------------------------------
121 --lpp_front_positive_detection_1 : lpp_front_positive_detection
122 -- PORT MAP (
123 -- clk => clk,
124 -- rstn => rstn,
125 -- sin => wfp_on_s,
126 -- sout => first_decount_s);
127
128 Decounter_Cyclic_DeltaSnapshot : PROCESS (clk, rstn)
129 BEGIN -- PROCESS Decounter_Cyclic_DeltaSnapshot
130 IF rstn = '0' THEN -- asynchronous reset (active low)
131 counter_delta_snapshot <= 0;
132 first_decount <= '0';
133 first_init <= '0';
134 start_snapshot_f0_pre <= '0';
135 start_snapshot_f1 <= '0';
136 start_snapshot_f2 <= '0';
137 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
138 IF wfp_on_s = '0' THEN
139 counter_delta_snapshot <= 0;
140 first_decount <= '1';
141 first_init <= '1';
142 start_snapshot_f0_pre <= '0';
143 start_snapshot_f1 <= '0';
144 start_snapshot_f2 <= '0';
64 ELSE
145 ELSE
65 IF counter_delta_snapshot = UNSIGNED(delta_snapshot) THEN
146 start_snapshot_f0_pre <= '0';
66 start_snapshot_f2_temp <= '1';
147 start_snapshot_f1 <= '0';
67 ELSE
148 start_snapshot_f2 <= '0';
68 start_snapshot_f2_temp <= '0';
149
69 END IF;
150 IF data_f2_valid = '1' THEN
70 -------------------------------------------------------------------------
151 IF first_init = '1' THEN
71 IF counter_delta_snapshot = UNSIGNED(delta_snapshot) AND start_snapshot_f2_temp = '0' THEN
152 counter_delta_snapshot <= to_integer(UNSIGNED(reg_delta_f2));
72 start_snapshot_f2 <= '1';
153 first_init <= '0';
73 ELSE
74 start_snapshot_f2 <= '0';
75 END IF;
76 -------------------------------------------------------------------------
77 coarse_time_0_r <= coarse_time_0;
78 IF coarse_time_0 = NOT coarse_time_0_r THEN --AND coarse_time_0 = '1' THEN
79 IF counter_delta_snapshot = 0 THEN
80 counter_delta_snapshot <= to_integer(UNSIGNED(delta_snapshot));
81 ELSE
154 ELSE
82 counter_delta_snapshot <= counter_delta_snapshot - 1;
155 IF counter_delta_snapshot > 0 THEN
156 counter_delta_snapshot <= counter_delta_snapshot - 1;
157 ELSE
158 counter_delta_snapshot <= to_integer(UNSIGNED(reg_delta_snapshot));
159 first_decount <= '0';
160 END IF;
161
162 IF counter_delta_snapshot = to_integer(UNSIGNED(reg_delta_f0)) THEN
163 IF first_decount = '0' THEN
164 start_snapshot_f0_pre <= '1';
165 END IF;
166 END IF;
167
168 IF counter_delta_snapshot = to_integer(UNSIGNED(reg_delta_f1)) THEN
169 IF first_decount = '0' THEN
170 start_snapshot_f1 <= '1';
171 END IF;
172 END IF;
173
174 IF counter_delta_snapshot = 0 THEN
175 start_snapshot_f2 <= '1';
176 END IF;
83 END IF;
177 END IF;
84 END IF;
178 END IF;
179 END IF;
180 END IF;
181 END PROCESS Decounter_Cyclic_DeltaSnapshot;
182 -----------------------------------------------------------------------------
85
183
86
184
87 -------------------------------------------------------------------------
185 -----------------------------------------------------------------------------
88
186 -- StartSnapshot Generator for f0
89
187 -----------------------------------------------------------------------------
90
188 -- INPUT wfp_on_s
91 IF counter_delta_f0 = UNSIGNED(delta_f2_f1) THEN
189 -- start_snapshot_f0_pre
92 start_snapshot_f1 <= '1';
190 -- reg_delta_snapshot
93 ELSE
191 -- reg_delta_f0_2
94 start_snapshot_f1 <= '0';
192 -- data_f0_valid
95 END IF;
193 -- OUTPUT start_snapshot_f0
96
194 -----------------------------------------------------------------------------
97 IF counter_delta_f0 = 1 THEN --UNSIGNED(delta_f2_f0) THEN
195 Decounter_DeltaSnapshot_f0 : PROCESS (clk, rstn)
98 start_snapshot_f0 <= '1';
196 BEGIN -- PROCESS Decounter_Cyclic_DeltaSnapshot
99 ELSE
197 IF rstn = '0' THEN -- asynchronous reset (active low)
100 start_snapshot_f0 <= '0';
198 counter_delta_f0 <= 0;
101 END IF;
199 start_snapshot_f0 <= '0';
102
200 send_start_snapshot_f0 <= '0';
103 IF counter_delta_snapshot = UNSIGNED(delta_snapshot)
201 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
104 AND start_snapshot_f2_temp = '0'
202 start_snapshot_f0 <= '0';
105 THEN --
203 IF wfp_on_s = '0' THEN
106 start_snapshot_fothers_temp <= '1';
204 counter_delta_f0 <= 0;
107 ELSIF counter_delta_f0 > 0 THEN
205 send_start_snapshot_f0 <= '1';
108 start_snapshot_fothers_temp <= '0';
206 ELSE
109 END IF;
207 IF start_snapshot_f0_pre = '1' THEN
110
208 send_start_snapshot_f0 <= '0';
111
209 counter_delta_f0 <= to_integer(UNSIGNED(reg_delta_f0_2));
112 -------------------------------------------------------------------------
210 ELSIF data_f0_valid = '1' THEN
113 IF (start_snapshot_fothers_temp = '1' OR (counter_delta_snapshot = UNSIGNED(delta_snapshot) AND start_snapshot_f2_temp = '0')) AND data_f2_in_valid = '1' THEN
211 IF counter_delta_f0 > 0 THEN
114 --counter_delta_snapshot = UNSIGNED(delta_snapshot) AND start_snapshot_f2_temp = '0' THEN --
212 send_start_snapshot_f0 <= '0';
115 --counter_delta_snapshot = UNSIGNED(delta_snapshot) THEN
213 counter_delta_f0 <= counter_delta_f0 - 1;
116 counter_delta_f0 <= to_integer(UNSIGNED(delta_f2_f0)); --0;
214 ELSE
117 ELSE
215 IF send_start_snapshot_f0 = '0' THEN
118 IF ((counter_delta_f0 > 0) AND (data_f0_in_valid = '1')) THEN --<= UNSIGNED(delta_f2_f0) THEN
216 send_start_snapshot_f0 <= '1';
119 counter_delta_f0 <= counter_delta_f0 - 1; --counter_delta_f0 + 1;
217 start_snapshot_f0 <= '1';
218 END IF;
120 END IF;
219 END IF;
121 END IF;
220 END IF;
122 -------------------------------------------------------------------------
123
124 END IF;
221 END IF;
125 END IF;
222 END IF;
126 END PROCESS;
223 END PROCESS Decounter_DeltaSnapshot_f0;
224 -----------------------------------------------------------------------------
127
225
128 END beh;
226 END beh;
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@@ -1,12 +1,10
1 lpp_waveform_pkg.vhd
1 lpp_waveform_pkg.vhd
2 lpp_waveform.vhd
2 lpp_waveform.vhd
3 lpp_waveform_burst.vhd
3 lpp_waveform_burst.vhd
4 lpp_waveform_dma.vhd
5 lpp_waveform_dma_genvalid.vhd
6 lpp_waveform_dma_selectaddress.vhd
7 lpp_waveform_dma_send_Nword.vhd
8 lpp_waveform_fifo.vhd
4 lpp_waveform_fifo.vhd
9 lpp_waveform_fifo_arbiter.vhd
5 lpp_waveform_fifo_arbiter.vhd
10 lpp_waveform_fifo_ctrl.vhd
6 lpp_waveform_fifo_ctrl.vhd
11 lpp_waveform_snapshot.vhd
7 lpp_waveform_snapshot.vhd
12 lpp_waveform_snapshot_controler.vhd
8 lpp_waveform_snapshot_controler.vhd
9 lpp_waveform_genaddress.vhd
10 lpp_waveform_dma_genvalid.vhd
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