HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Commit - r221:61667259e0ed

Sync

Alexis Jeandet -

r221:61667259e0ed alexis

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Context file:

r221:61667259e0ed

designs/EGSE_ICI/EGSE_ICI.vhd +3 -2

                 elsif clk'event and clk = '1' then
                     NwDatR   <= NwDat;
                     if NwDat = '1' and NwDatR = '0'  then
-                        PROTO_DATAIN  <=  std_logic_vector(unsigned(PROTO_DATAIN) + 1 );
+            --            PROTO_DATAIN  <=  std_logic_vector(unsigned(PROTO_DATAIN) + 1 );
-                        PROTO_WEN       <= '0';
+                          PROTO_DATAIN  <=  DATA;
+                          PROTO_WEN       <= '0';
                     else
                         PROTO_WEN       <= '1';
                     end if;

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