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debug lpp_uart and comment lpp_cna
martin -
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1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 21 ------------------------------------------------------------------------------
22 22 library ieee;
23 23 use ieee.std_logic_1164.all;
24 24 library grlib;
25 25 use grlib.amba.all;
26 26 use grlib.stdlib.all;
27 27 use grlib.devices.all;
28 28 library lpp;
29 29 use lpp.lpp_amba.all;
30 30 use lpp.apb_devices_list.all;
31 31 use lpp.lpp_cna.all;
32 32
33 33 --! Driver APB, va faire le lien entre l'IP VHDL du convertisseur et le bus Amba
34 34
35 35 entity APB_CNA is
36 36 generic (
37 37 pindex : integer := 0;
38 38 paddr : integer := 0;
39 39 pmask : integer := 16#fff#;
40 40 pirq : integer := 0;
41 41 abits : integer := 8);
42 42 port (
43 43 clk : in std_logic; --! Horloge du composant
44 44 rst : in std_logic; --! Reset general du composant
45 45 apbi : in apb_slv_in_type; --! Registre de gestion des entrοΏ½es du bus
46 46 apbo : out apb_slv_out_type; --! Registre de gestion des sorties du bus
47 47 SYNC : out std_logic; --! Signal de synchronisation du convertisseur
48 48 SCLK : out std_logic; --! Horloge systeme du convertisseur
49 49 DATA : out std_logic --! DonnοΏ½e numοΏ½rique sοΏ½rialisοΏ½
50 50 );
51 51 end APB_CNA;
52 52
53 53 --! @details Les deux registres (apbi,apbo) permettent de gοΏ½rer la communication sur le bus
54 54 --! et les sorties seront cablοΏ½es vers le convertisseur.
55 55
56 56 architecture ar_APB_CNA of APB_CNA is
57 57
58 58 constant REVISION : integer := 1;
59 59
60 60 constant pconfig : apb_config_type := (
61 61 0 => ahb_device_reg (VENDOR_LPP, LPP_CNA, 0, REVISION, 0),
62 62 1 => apb_iobar(paddr, pmask));
63 63
64 64 signal enable : std_logic;
65 65 signal flag_sd : std_logic;
66 66
67 67 type CNA_ctrlr_Reg is record
68 68 CNA_Cfg : std_logic_vector(1 downto 0);
69 69 CNA_Data : std_logic_vector(15 downto 0);
70 70 end record;
71 71
72 72 signal Rec : CNA_ctrlr_Reg;
73 73 signal Rdata : std_logic_vector(31 downto 0);
74 74
75 75 begin
76 76
77 77 enable <= Rec.CNA_Cfg(0);
78 78 Rec.CNA_Cfg(1) <= flag_sd;
79 79
80 80 CONVERTER : entity Work.CNA_TabloC
81 81 port map(clk,rst,enable,Rec.CNA_Data,SYNC,SCLK,flag_sd,Data);
82 82
83 83
84 84 process(rst,clk)
85 85 begin
86 86 if(rst='0')then
87 87 Rec.CNA_Data <= (others => '0');
88 88
89 89 elsif(clk'event and clk='1')then
90 90
91 91
92 92 --APB Write OP
93 93 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
94 94 case apbi.paddr(abits-1 downto 2) is
95 95 when "000000" =>
96 96 Rec.CNA_Cfg(0) <= apbi.pwdata(0);
97 97 when "000001" =>
98 98 Rec.CNA_Data <= apbi.pwdata(15 downto 0);
99 99 when others =>
100 100 null;
101 101 end case;
102 102 end if;
103 103
104 104 --APB READ OP
105 105 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
106 106 case apbi.paddr(abits-1 downto 2) is
107 107 when "000000" =>
108 108 Rdata(31 downto 2) <= X"ABCDEF5" & "00";
109 109 Rdata(1 downto 0) <= Rec.CNA_Cfg;
110 110 when "000001" =>
111 111 Rdata(31 downto 16) <= X"FD18";
112 112 Rdata(15 downto 0) <= Rec.CNA_Data;
113 113 when others =>
114 114 Rdata <= (others => '0');
115 115 end case;
116 116 end if;
117 117
118 118 end if;
119 119 apbo.pconfig <= pconfig;
120 120 end process;
121 121
122 122 apbo.prdata <= Rdata when apbi.penable = '1';
123 123 end ar_APB_CNA;
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1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 ------------------------------------------------------------------------------
19 19 -- Author : Martin Morlot
20 20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 21 ------------------------------------------------------------------------------
22 22 library ieee;
23 23 use ieee.std_logic_1164.all;
24 24 library grlib;
25 25 use grlib.amba.all;
26 26 use grlib.stdlib.all;
27 27 use grlib.devices.all;
28 28 library lpp;
29 29 use lpp.lpp_amba.all;
30 30 use lpp.apb_devices_list.all;
31 31 use lpp.lpp_uart.all;
32 32
33 33 --! Driver APB, va faire le lien entre l'IP VHDL de l'UART et le bus Amba
34 34
35 35 entity APB_UART is
36 36 generic (
37 37 pindex : integer := 0;
38 38 paddr : integer := 0;
39 39 pmask : integer := 16#fff#;
40 40 pirq : integer := 0;
41 41 abits : integer := 8;
42 42 Data_sz : integer := 8);
43 43 port (
44 44 clk : in std_logic; --! Horloge du composant
45 45 rst : in std_logic; --! Reset general du composant
46 46 apbi : in apb_slv_in_type; --! Registre de gestion des entrοΏ½es du bus
47 47 apbo : out apb_slv_out_type; --! Registre de gestion des sorties du bus
48 48 TXD : out std_logic; --! Transmission sοΏ½rie, cοΏ½tοΏ½ composant
49 49 RXD : in std_logic --! Reception sοΏ½rie, cοΏ½tοΏ½ composant
50 50 );
51 51 end APB_UART;
52 52
53 53
54 54 architecture ar_APB_UART of APB_UART is
55 55
56 56 constant REVISION : integer := 1;
57 57
58 58 constant pconfig : apb_config_type := (
59 59 0 => ahb_device_reg (VENDOR_LPP, LPP_UART, 0, REVISION, 0),
60 60 1 => apb_iobar(paddr, pmask));
61 61
62 62 signal NwData : std_logic;
63 63 signal ACK : std_logic;
64 64 signal Capture : std_logic;
65 65 signal Send : std_logic;
66 66 signal Sended : std_logic;
67 67
68 68 type UART_ctrlr_Reg is record
69 69 UART_Cfg : std_logic_vector(2 downto 0);
70 70 UART_Wdata : std_logic_vector(7 downto 0);
71 71 UART_Rdata : std_logic_vector(7 downto 0);
72 72 UART_BTrig : std_logic_vector(11 downto 0);
73 73 end record;
74 74
75 75 signal Rec : UART_ctrlr_Reg;
76 76 signal Rdata : std_logic_vector(31 downto 0);
77 77 signal temp_ND : std_logic;
78 78
79 79 begin
80 80
81 81 Capture <= Rec.UART_Cfg(0);
82 --ACK <= Rec.UART_Cfg(1);
83 --Send <= Rec.UART_Cfg(1);
84 82 Rec.UART_Cfg(1) <= Sended;
85 83 Rec.UART_Cfg(2) <= NwData;
86 84
87 85
88 86 COM0 : entity work.UART
89 87 generic map (Data_sz)
90 88 port map (clk,rst,TXD,RXD,Capture,NwData,ACK,Send,Sended,Rec.UART_BTrig,Rec.UART_Rdata,Rec.UART_Wdata);
91 89
92 90
93 91 process(rst,clk)
94 92 begin
95 93 if(rst='0')then
96 94 Rec.UART_Wdata <= (others => '0');
97 95
98 96
99 97 elsif(clk'event and clk='1')then
100 98 temp_ND <= NwData;
101 99 if(NwData='1' and temp_ND='1')then
102 100 ACK <= '1';
103 101 else
104 102 ACK <= '0';
105 103 end if;
106 104
107 105 --APB Write OP
108 106 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
109 107 case apbi.paddr(7 downto 2) is
110 108 when "000000" =>
111 109 Rec.UART_Cfg(0) <= apbi.pwdata(0);
112 --Rec.UART_Cfg(1) <= apbi.pwdata(4);
113 110 when "000001" =>
114 111 Rec.UART_Wdata(7 downto 0) <= apbi.pwdata(7 downto 0);
115 112 Send <= '1';
116 113 when others =>
117 114 null;
118 115 end case;
119 116 else
120 117 Send <= '0';
121 118 end if;
122 119
123 120 --APB READ OP
124 121 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
125 122 case apbi.paddr(7 downto 2) is
126 123 when "000000" =>
127 124 Rdata(3 downto 0) <= "000" & Rec.UART_Cfg(0);
128 125 Rdata(7 downto 4) <= "000" & Rec.UART_Cfg(1);
129 126 Rdata(11 downto 8) <= "000" & Rec.UART_Cfg(2);
130 127 Rdata(19 downto 12) <= X"EE";
131 128 Rdata(31 downto 20) <= Rec.UART_BTrig;
132 129 when "000001" =>
133 130 Rdata(31 downto 8) <= X"EEEEEE";
134 131 Rdata(7 downto 0) <= Rec.UART_Wdata;
135 132 when "000010" =>
136 133 Rdata(31 downto 8) <= X"EEEEEE";
137 134 Rdata(7 downto 0) <= Rec.UART_Rdata;
138 --Ack <= '1';
139 135 when others =>
140 136 Rdata <= (others => '0');
141 137 end case;
142 --else
143 --Ack <= '0';
144 138 end if;
145 139
146 140 end if;
147 141 apbo.pconfig <= pconfig;
148 142 end process;
149 143
150 144 apbo.prdata <= Rdata when apbi.penable = '1';
151 145
152 146 end ar_APB_UART;
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