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1 | ------------------------------------------------------------------------------ |
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1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
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2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
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3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
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4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
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5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
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6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
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7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
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8 | -- (at your option) any later version. | |
9 | -- |
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9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
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10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
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11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
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13 | -- GNU General Public License for more details. | |
14 | -- |
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14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
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15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
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16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
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17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------- |
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18 | ------------------------------------------------------------------------------- | |
19 | -- Author : Jean-christophe PELLION |
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19 | -- Author : Jean-christophe PELLION | |
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
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20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |
21 | ------------------------------------------------------------------------------- |
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21 | ------------------------------------------------------------------------------- | |
22 | LIBRARY IEEE; |
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22 | LIBRARY IEEE; | |
23 | USE IEEE.STD_LOGIC_1164.ALL; |
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23 | USE IEEE.STD_LOGIC_1164.ALL; | |
24 | USE IEEE.std_logic_arith.ALL; |
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24 | USE IEEE.std_logic_arith.ALL; | |
25 | USE IEEE.std_logic_signed.ALL; |
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25 | USE IEEE.std_logic_signed.ALL; | |
26 | USE IEEE.MATH_real.ALL; |
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26 | USE IEEE.MATH_real.ALL; | |
27 |
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27 | |||
28 | ENTITY TestModule_ADS7886 IS |
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28 | ENTITY TestModule_ADS7886 IS | |
29 | GENERIC ( |
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29 | GENERIC ( | |
30 | freq : INTEGER := 24; |
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30 | freq : INTEGER := 24; | |
31 | amplitude : INTEGER := 3000; |
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31 | amplitude : INTEGER := 3000; | |
32 | impulsion : INTEGER := 0 -- 1 => impulsion generation |
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32 | impulsion : INTEGER := 0 -- 1 => impulsion generation | |
33 | ); |
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33 | ); | |
34 | PORT ( |
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34 | PORT ( | |
35 | -- CONV -- |
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35 | -- CONV -- | |
36 | cnv_run : IN STD_LOGIC; |
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36 | cnv_run : IN STD_LOGIC; | |
37 | cnv : IN STD_LOGIC; |
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37 | cnv : IN STD_LOGIC; | |
38 |
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38 | |||
39 | -- DATA -- |
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39 | -- DATA -- | |
40 | sck : IN STD_LOGIC; |
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40 | sck : IN STD_LOGIC; | |
41 | sdo : OUT STD_LOGIC |
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41 | sdo : OUT STD_LOGIC | |
42 | ); |
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42 | ); | |
43 | END TestModule_ADS7886; |
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43 | END TestModule_ADS7886; | |
44 |
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44 | |||
45 | ARCHITECTURE beh OF TestModule_ADS7886 IS |
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45 | ARCHITECTURE beh OF TestModule_ADS7886 IS | |
46 | SIGNAL reg : STD_LOGIC_VECTOR(15 DOWNTO 0); |
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46 | SIGNAL reg : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
47 | SIGNAL n : INTEGER := 0; |
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47 | SIGNAL n : INTEGER := 0; | |
48 | BEGIN -- beh |
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48 | BEGIN -- beh | |
49 |
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49 | |||
50 | PROCESS (cnv, sck) |
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50 | PROCESS (cnv, sck) | |
51 | BEGIN -- PROCESS |
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51 | BEGIN -- PROCESS | |
52 | IF cnv = '0' AND cnv'EVENT THEN |
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52 | IF cnv = '0' AND cnv'EVENT THEN | |
53 | n <= n + 1; |
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53 | n <= n + 1; | |
54 | IF impulsion = 1 THEN |
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54 | IF impulsion = 1 THEN | |
55 | IF n = 1 THEN |
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55 | IF n = 1 THEN | |
56 | reg <= conv_std_logic_vector(integer(REAL(amplitude)) , 16); |
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56 | reg <= conv_std_logic_vector(integer(REAL(amplitude)) , 16); | |
57 | ELSE |
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57 | ELSE | |
58 | reg <= conv_std_logic_vector(integer(REAL(0)) , 16); |
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58 | reg <= conv_std_logic_vector(integer(REAL(0)) , 16); | |
59 | END IF; |
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59 | END IF; | |
60 | ELSE |
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60 | ELSE | |
61 | reg <= conv_std_logic_vector(integer(REAL(amplitude) * SIN(MATH_2_PI*REAL(n)/REAL(freq))) , 16); |
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61 | reg <= conv_std_logic_vector(integer(REAL(amplitude) * SIN(MATH_2_PI*REAL(n)/REAL(freq))) , 16); | |
62 | END IF; |
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62 | END IF; | |
63 | ELSIF sck'EVENT AND sck = '0' THEN -- rising clock edge |
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63 | ELSIF sck'EVENT AND sck = '0' THEN -- rising clock edge | |
64 |
reg( |
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64 | reg(0) <= 'X'; | |
65 | reg(14 DOWNTO 0) <= reg(15 DOWNTO 1); |
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65 | reg(15 DOWNTO 1) <= reg(14 DOWNTO 0); | |
66 | END IF; |
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66 | END IF; | |
67 | END PROCESS; |
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67 | END PROCESS; | |
68 |
sdo <= reg( |
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68 | sdo <= reg(15); | |
69 |
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69 | |||
70 | END beh; |
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70 | END beh; |
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