@@ -61,10 +61,10 BEGIN -- beh | |||
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61 | 61 | reg <= conv_std_logic_vector(integer(REAL(amplitude) * SIN(MATH_2_PI*REAL(n)/REAL(freq))) , 16); |
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62 | 62 | END IF; |
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63 | 63 | ELSIF sck'EVENT AND sck = '0' THEN -- rising clock edge |
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64 |
reg( |
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65 | reg(14 DOWNTO 0) <= reg(15 DOWNTO 1); | |
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64 | reg(0) <= 'X'; | |
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65 | reg(15 DOWNTO 1) <= reg(14 DOWNTO 0); | |
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66 | 66 | END IF; |
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67 | 67 | END PROCESS; |
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68 |
sdo <= reg( |
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68 | sdo <= reg(15); | |
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69 | 69 | |
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70 | 70 | END beh; |
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