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1 | 1 | ------------------------------------------------------------------------------ |
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2 | 2 | -- This file is a part of the LPP VHDL IP LIBRARY |
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3 | 3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
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4 | 4 | -- |
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5 | 5 | -- This program is free software; you can redistribute it and/or modify |
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6 | 6 | -- it under the terms of the GNU General Public License as published by |
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7 | 7 | -- the Free Software Foundation; either version 3 of the License, or |
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8 | 8 | -- (at your option) any later version. |
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9 | 9 | -- |
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10 | 10 | -- This program is distributed in the hope that it will be useful, |
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11 | 11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
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12 | 12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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13 | 13 | -- GNU General Public License for more details. |
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14 | 14 | -- |
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15 | 15 | -- You should have received a copy of the GNU General Public License |
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16 | 16 | -- along with this program; if not, write to the Free Software |
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17 | 17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
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18 | 18 | ------------------------------------------------------------------------------- |
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19 | 19 | -- Author : Jean-christophe PELLION |
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20 | 20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
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21 | 21 | ------------------------------------------------------------------------------- |
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22 | 22 | LIBRARY IEEE; |
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23 | 23 | USE IEEE.STD_LOGIC_1164.ALL; |
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24 | 24 | USE IEEE.std_logic_arith.ALL; |
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25 | 25 | USE IEEE.std_logic_signed.ALL; |
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26 | 26 | USE IEEE.MATH_real.ALL; |
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27 | 27 | |
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28 | 28 | ENTITY TestModule_ADS7886 IS |
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29 | 29 | GENERIC ( |
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30 | 30 | freq : INTEGER := 24; |
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31 | 31 | amplitude : INTEGER := 3000; |
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32 | 32 | impulsion : INTEGER := 0 -- 1 => impulsion generation |
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33 | 33 | ); |
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34 | 34 | PORT ( |
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35 | 35 | -- CONV -- |
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36 | 36 | cnv_run : IN STD_LOGIC; |
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37 | 37 | cnv : IN STD_LOGIC; |
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38 | 38 | |
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39 | 39 | -- DATA -- |
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40 | 40 | sck : IN STD_LOGIC; |
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41 | 41 | sdo : OUT STD_LOGIC |
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42 | 42 | ); |
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43 | 43 | END TestModule_ADS7886; |
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44 | 44 | |
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45 | 45 | ARCHITECTURE beh OF TestModule_ADS7886 IS |
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46 | 46 | SIGNAL reg : STD_LOGIC_VECTOR(15 DOWNTO 0); |
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47 | 47 | SIGNAL n : INTEGER := 0; |
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48 | 48 | BEGIN -- beh |
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49 | 49 | |
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50 | 50 | PROCESS (cnv, sck) |
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51 | 51 | BEGIN -- PROCESS |
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52 | 52 | IF cnv = '0' AND cnv'EVENT THEN |
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53 | 53 | n <= n + 1; |
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54 | 54 | IF impulsion = 1 THEN |
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55 | 55 | IF n = 1 THEN |
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56 | 56 | reg <= conv_std_logic_vector(integer(REAL(amplitude)) , 16); |
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57 | 57 | ELSE |
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58 | 58 | reg <= conv_std_logic_vector(integer(REAL(0)) , 16); |
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59 | 59 | END IF; |
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60 | 60 | ELSE |
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61 | 61 | reg <= conv_std_logic_vector(integer(REAL(amplitude) * SIN(MATH_2_PI*REAL(n)/REAL(freq))) , 16); |
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62 | 62 | END IF; |
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63 | 63 | ELSIF sck'EVENT AND sck = '0' THEN -- rising clock edge |
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64 |
reg( |
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65 | reg(14 DOWNTO 0) <= reg(15 DOWNTO 1); | |
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64 | reg(0) <= 'X'; | |
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65 | reg(15 DOWNTO 1) <= reg(14 DOWNTO 0); | |
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66 | 66 | END IF; |
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67 | 67 | END PROCESS; |
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68 |
sdo <= reg( |
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68 | sdo <= reg(15); | |
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69 | 69 | |
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70 | 70 | END beh; |
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