@@ -61,10 +61,10 BEGIN -- beh | |||||
61 | reg <= conv_std_logic_vector(integer(REAL(amplitude) * SIN(MATH_2_PI*REAL(n)/REAL(freq))) , 16); |
|
61 | reg <= conv_std_logic_vector(integer(REAL(amplitude) * SIN(MATH_2_PI*REAL(n)/REAL(freq))) , 16); | |
62 | END IF; |
|
62 | END IF; | |
63 | ELSIF sck'EVENT AND sck = '0' THEN -- rising clock edge |
|
63 | ELSIF sck'EVENT AND sck = '0' THEN -- rising clock edge | |
64 |
reg( |
|
64 | reg(0) <= 'X'; | |
65 | reg(14 DOWNTO 0) <= reg(15 DOWNTO 1); |
|
65 | reg(15 DOWNTO 1) <= reg(14 DOWNTO 0); | |
66 | END IF; |
|
66 | END IF; | |
67 | END PROCESS; |
|
67 | END PROCESS; | |
68 |
sdo <= reg( |
|
68 | sdo <= reg(15); | |
69 |
|
69 | |||
70 | END beh; |
|
70 | END beh; |
General Comments 0
You need to be logged in to leave comments.
Login now