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modif alexis - CNA
pellion -
r541:5b67570c5718 (LFR-EM) 1-1-63 JC
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@@ -391,7 +391,7 BEGIN -- beh
391 pirq_ms => 6,
391 pirq_ms => 6,
392 pirq_wfp => 14,
392 pirq_wfp => 14,
393 hindex => 2,
393 hindex => 2,
394 top_lfr_version => X"01013E") -- aa.bb.cc version
394 top_lfr_version => X"01013F") -- aa.bb.cc version
395 -- AA : BOARD NUMBER
395 -- AA : BOARD NUMBER
396 -- 0 => MINI_LFR
396 -- 0 => MINI_LFR
397 -- 1 => EM
397 -- 1 => EM
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@@ -50,7 +50,6 ARCHITECTURE behav OF SPI_DAC_DRIVER IS
50 SIGNAL shifting_R : STD_LOGIC := '0';
50 SIGNAL shifting_R : STD_LOGIC := '0';
51 BEGIN
51 BEGIN
52
52
53 DOUT <= SHIFTREG(datawidth-1);
54
53
55 MSB : IF MSBFIRST = 1 GENERATE
54 MSB : IF MSBFIRST = 1 GENERATE
56 INPUTREG <= DATA;
55 INPUTREG <= DATA;
@@ -64,10 +63,10 BEGIN
64
63
65 PROCESS(clk, rstn)
64 PROCESS(clk, rstn)
66 BEGIN
65 BEGIN
67 IF rstn = '0' then
66 IF rstn = '0' THEN
68 -- shifting_R <= '0';
67 -- shifting_R <= '0';
69 SMP_CLK_R <= '0';
68 SMP_CLK_R <= '0';
70 ELSIF clk'EVENT AND clk = '1' then
69 ELSIF clk'EVENT AND clk = '1' THEN
71 SMP_CLK_R <= SMP_CLK;
70 SMP_CLK_R <= SMP_CLK;
72 -- shifting_R <= shifting;
71 -- shifting_R <= shifting;
73 END IF;
72 END IF;
@@ -75,13 +74,15 BEGIN
75
74
76 PROCESS(clk, rstn)
75 PROCESS(clk, rstn)
77 BEGIN
76 BEGIN
78 IF rstn = '0' then
77 IF rstn = '0' THEN
79 shifting <= '0';
78 shifting <= '0';
80 SHIFTREG <= (OTHERS => '0');
79 SHIFTREG <= (OTHERS => '0');
81 SYNC <= '0';
80 SYNC <= '0';
82 shiftcnt <= 0;
81 shiftcnt <= 0;
83 ELSIF clk'EVENT AND clk = '1' then
82 DOUT <= '0';
84 IF(SMP_CLK = '1' and SMP_CLK_R = '0') THEN
83 ELSIF clk'EVENT AND clk = '1' THEN
84 DOUT <= SHIFTREG(datawidth-1);
85 IF(SMP_CLK = '1' AND SMP_CLK_R = '0') THEN
85 SYNC <= '1';
86 SYNC <= '1';
86 shifting <= '1';
87 shifting <= '1';
87 ELSE
88 ELSE
@@ -90,9 +91,10 BEGIN
90 shifting <= '0';
91 shifting <= '0';
91 END IF;
92 END IF;
92 END IF;
93 END IF;
93 IF shifting = '1' then
94 IF shifting = '1' THEN
94 shiftcnt <= shiftcnt + 1;
95 shiftcnt <= shiftcnt + 1;
95 SHIFTREG <= SHIFTREG (datawidth-2 DOWNTO 0) & '0';
96 SHIFTREG <= SHIFTREG (datawidth-2 DOWNTO 0) & '0';
97
96 ELSE
98 ELSE
97 SHIFTREG <= INPUTREG;
99 SHIFTREG <= INPUTREG;
98 shiftcnt <= 0;
100 shiftcnt <= 0;
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