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(MINI-LFR) WFP_MS_0-1-39...
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r484:5ac3ea1d915f JC
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1 LIBRARY ieee;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
2 USE ieee.std_logic_1164.ALL;
3 USE ieee.numeric_std.ALL;
3 USE ieee.numeric_std.ALL;
4 use IEEE.std_logic_textio.all;
4 use IEEE.std_logic_textio.all;
5 LIBRARY STD;
5 LIBRARY STD;
6 use std.textio.all;
6 use std.textio.all;
7
7
8 LIBRARY grlib;
8 LIBRARY grlib;
9 USE grlib.stdlib.ALL;
9 USE grlib.stdlib.ALL;
10 LIBRARY gaisler;
10 LIBRARY gaisler;
11 USE gaisler.libdcom.ALL;
11 USE gaisler.libdcom.ALL;
12 USE gaisler.sim.ALL;
12 USE gaisler.sim.ALL;
13 USE gaisler.jtagtst.ALL;
13 USE gaisler.jtagtst.ALL;
14 LIBRARY techmap;
14 LIBRARY techmap;
15 USE techmap.gencomp.ALL;
15 USE techmap.gencomp.ALL;
16
16
17 LIBRARY lpp;
17 LIBRARY lpp;
18 USE lpp.lpp_sim_pkg.ALL;
18 USE lpp.lpp_sim_pkg.ALL;
19 USE lpp.lpp_lfr_sim_pkg.ALL;
19 USE lpp.lpp_lfr_sim_pkg.ALL;
20 USE lpp.lpp_lfr_apbreg_pkg.ALL;
20 USE lpp.lpp_lfr_apbreg_pkg.ALL;
21 USE lpp.lpp_lfr_time_management_apbreg_pkg.ALL;
21 USE lpp.lpp_lfr_time_management_apbreg_pkg.ALL;
22
22
23
23
24 ENTITY testbench IS
24 ENTITY testbench IS
25 END;
25 END;
26
26
27 ARCHITECTURE behav OF testbench IS
27 ARCHITECTURE behav OF testbench IS
28
28
29 COMPONENT MINI_LFR_top
29 COMPONENT MINI_LFR_top
30 PORT (
30 PORT (
31 clk_50 : IN STD_LOGIC;
31 clk_50 : IN STD_LOGIC;
32 clk_49 : IN STD_LOGIC;
32 clk_49 : IN STD_LOGIC;
33 reset : IN STD_LOGIC;
33 reset : IN STD_LOGIC;
34 BP0 : IN STD_LOGIC;
34 BP0 : IN STD_LOGIC;
35 BP1 : IN STD_LOGIC;
35 BP1 : IN STD_LOGIC;
36 LED0 : OUT STD_LOGIC;
36 LED0 : OUT STD_LOGIC;
37 LED1 : OUT STD_LOGIC;
37 LED1 : OUT STD_LOGIC;
38 LED2 : OUT STD_LOGIC;
38 LED2 : OUT STD_LOGIC;
39 TXD1 : IN STD_LOGIC;
39 TXD1 : IN STD_LOGIC;
40 RXD1 : OUT STD_LOGIC;
40 RXD1 : OUT STD_LOGIC;
41 nCTS1 : OUT STD_LOGIC;
41 nCTS1 : OUT STD_LOGIC;
42 nRTS1 : IN STD_LOGIC;
42 nRTS1 : IN STD_LOGIC;
43 TXD2 : IN STD_LOGIC;
43 TXD2 : IN STD_LOGIC;
44 RXD2 : OUT STD_LOGIC;
44 RXD2 : OUT STD_LOGIC;
45 nCTS2 : OUT STD_LOGIC;
45 nCTS2 : OUT STD_LOGIC;
46 nDTR2 : IN STD_LOGIC;
46 nDTR2 : IN STD_LOGIC;
47 nRTS2 : IN STD_LOGIC;
47 nRTS2 : IN STD_LOGIC;
48 nDCD2 : OUT STD_LOGIC;
48 nDCD2 : OUT STD_LOGIC;
49 IO0 : INOUT STD_LOGIC;
49 IO0 : INOUT STD_LOGIC;
50 IO1 : INOUT STD_LOGIC;
50 IO1 : INOUT STD_LOGIC;
51 IO2 : INOUT STD_LOGIC;
51 IO2 : INOUT STD_LOGIC;
52 IO3 : INOUT STD_LOGIC;
52 IO3 : INOUT STD_LOGIC;
53 IO4 : INOUT STD_LOGIC;
53 IO4 : INOUT STD_LOGIC;
54 IO5 : INOUT STD_LOGIC;
54 IO5 : INOUT STD_LOGIC;
55 IO6 : INOUT STD_LOGIC;
55 IO6 : INOUT STD_LOGIC;
56 IO7 : INOUT STD_LOGIC;
56 IO7 : INOUT STD_LOGIC;
57 IO8 : INOUT STD_LOGIC;
57 IO8 : INOUT STD_LOGIC;
58 IO9 : INOUT STD_LOGIC;
58 IO9 : INOUT STD_LOGIC;
59 IO10 : INOUT STD_LOGIC;
59 IO10 : INOUT STD_LOGIC;
60 IO11 : INOUT STD_LOGIC;
60 IO11 : INOUT STD_LOGIC;
61 SPW_EN : OUT STD_LOGIC;
61 SPW_EN : OUT STD_LOGIC;
62 SPW_NOM_DIN : IN STD_LOGIC;
62 SPW_NOM_DIN : IN STD_LOGIC;
63 SPW_NOM_SIN : IN STD_LOGIC;
63 SPW_NOM_SIN : IN STD_LOGIC;
64 SPW_NOM_DOUT : OUT STD_LOGIC;
64 SPW_NOM_DOUT : OUT STD_LOGIC;
65 SPW_NOM_SOUT : OUT STD_LOGIC;
65 SPW_NOM_SOUT : OUT STD_LOGIC;
66 SPW_RED_DIN : IN STD_LOGIC;
66 SPW_RED_DIN : IN STD_LOGIC;
67 SPW_RED_SIN : IN STD_LOGIC;
67 SPW_RED_SIN : IN STD_LOGIC;
68 SPW_RED_DOUT : OUT STD_LOGIC;
68 SPW_RED_DOUT : OUT STD_LOGIC;
69 SPW_RED_SOUT : OUT STD_LOGIC;
69 SPW_RED_SOUT : OUT STD_LOGIC;
70 ADC_nCS : OUT STD_LOGIC;
70 ADC_nCS : OUT STD_LOGIC;
71 ADC_CLK : OUT STD_LOGIC;
71 ADC_CLK : OUT STD_LOGIC;
72 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
72 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
73 SRAM_nWE : OUT STD_LOGIC;
73 SRAM_nWE : OUT STD_LOGIC;
74 SRAM_CE : OUT STD_LOGIC;
74 SRAM_CE : OUT STD_LOGIC;
75 SRAM_nOE : OUT STD_LOGIC;
75 SRAM_nOE : OUT STD_LOGIC;
76 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
76 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
77 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
77 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
78 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0));
78 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0));
79 END COMPONENT;
79 END COMPONENT;
80
80
81 -----------------------------------------------------------------------------
81 -----------------------------------------------------------------------------
82 SIGNAL clk_50 : STD_LOGIC := '0';
82 SIGNAL clk_50 : STD_LOGIC := '0';
83 SIGNAL clk_49 : STD_LOGIC := '0';
83 SIGNAL clk_49 : STD_LOGIC := '0';
84 SIGNAL reset : STD_LOGIC;
84 SIGNAL reset : STD_LOGIC;
85 SIGNAL BP0 : STD_LOGIC;
85 SIGNAL BP0 : STD_LOGIC;
86 SIGNAL BP1 : STD_LOGIC;
86 SIGNAL BP1 : STD_LOGIC;
87 SIGNAL LED0 : STD_LOGIC;
87 SIGNAL LED0 : STD_LOGIC;
88 SIGNAL LED1 : STD_LOGIC;
88 SIGNAL LED1 : STD_LOGIC;
89 SIGNAL LED2 : STD_LOGIC;
89 SIGNAL LED2 : STD_LOGIC;
90 SIGNAL TXD1 : STD_LOGIC;
90 SIGNAL TXD1 : STD_LOGIC;
91 SIGNAL RXD1 : STD_LOGIC;
91 SIGNAL RXD1 : STD_LOGIC;
92 SIGNAL nCTS1 : STD_LOGIC;
92 SIGNAL nCTS1 : STD_LOGIC;
93 SIGNAL nRTS1 : STD_LOGIC;
93 SIGNAL nRTS1 : STD_LOGIC;
94 SIGNAL TXD2 : STD_LOGIC;
94 SIGNAL TXD2 : STD_LOGIC;
95 SIGNAL RXD2 : STD_LOGIC;
95 SIGNAL RXD2 : STD_LOGIC;
96 SIGNAL nCTS2 : STD_LOGIC;
96 SIGNAL nCTS2 : STD_LOGIC;
97 SIGNAL nDTR2 : STD_LOGIC;
97 SIGNAL nDTR2 : STD_LOGIC;
98 SIGNAL nRTS2 : STD_LOGIC;
98 SIGNAL nRTS2 : STD_LOGIC;
99 SIGNAL nDCD2 : STD_LOGIC;
99 SIGNAL nDCD2 : STD_LOGIC;
100 SIGNAL IO0 : STD_LOGIC;
100 SIGNAL IO0 : STD_LOGIC;
101 SIGNAL IO1 : STD_LOGIC;
101 SIGNAL IO1 : STD_LOGIC;
102 SIGNAL IO2 : STD_LOGIC;
102 SIGNAL IO2 : STD_LOGIC;
103 SIGNAL IO3 : STD_LOGIC;
103 SIGNAL IO3 : STD_LOGIC;
104 SIGNAL IO4 : STD_LOGIC;
104 SIGNAL IO4 : STD_LOGIC;
105 SIGNAL IO5 : STD_LOGIC;
105 SIGNAL IO5 : STD_LOGIC;
106 SIGNAL IO6 : STD_LOGIC;
106 SIGNAL IO6 : STD_LOGIC;
107 SIGNAL IO7 : STD_LOGIC;
107 SIGNAL IO7 : STD_LOGIC;
108 SIGNAL IO8 : STD_LOGIC;
108 SIGNAL IO8 : STD_LOGIC;
109 SIGNAL IO9 : STD_LOGIC;
109 SIGNAL IO9 : STD_LOGIC;
110 SIGNAL IO10 : STD_LOGIC;
110 SIGNAL IO10 : STD_LOGIC;
111 SIGNAL IO11 : STD_LOGIC;
111 SIGNAL IO11 : STD_LOGIC;
112 SIGNAL SPW_EN : STD_LOGIC;
112 SIGNAL SPW_EN : STD_LOGIC;
113 SIGNAL SPW_NOM_DIN : STD_LOGIC;
113 SIGNAL SPW_NOM_DIN : STD_LOGIC;
114 SIGNAL SPW_NOM_SIN : STD_LOGIC;
114 SIGNAL SPW_NOM_SIN : STD_LOGIC;
115 SIGNAL SPW_NOM_DOUT : STD_LOGIC;
115 SIGNAL SPW_NOM_DOUT : STD_LOGIC;
116 SIGNAL SPW_NOM_SOUT : STD_LOGIC;
116 SIGNAL SPW_NOM_SOUT : STD_LOGIC;
117 SIGNAL SPW_RED_DIN : STD_LOGIC;
117 SIGNAL SPW_RED_DIN : STD_LOGIC;
118 SIGNAL SPW_RED_SIN : STD_LOGIC;
118 SIGNAL SPW_RED_SIN : STD_LOGIC;
119 SIGNAL SPW_RED_DOUT : STD_LOGIC;
119 SIGNAL SPW_RED_DOUT : STD_LOGIC;
120 SIGNAL SPW_RED_SOUT : STD_LOGIC;
120 SIGNAL SPW_RED_SOUT : STD_LOGIC;
121 SIGNAL ADC_nCS : STD_LOGIC;
121 SIGNAL ADC_nCS : STD_LOGIC;
122 SIGNAL ADC_CLK : STD_LOGIC;
122 SIGNAL ADC_CLK : STD_LOGIC;
123 SIGNAL ADC_SDO : STD_LOGIC_VECTOR(7 DOWNTO 0);
123 SIGNAL ADC_SDO : STD_LOGIC_VECTOR(7 DOWNTO 0);
124 SIGNAL SRAM_nWE : STD_LOGIC;
124 SIGNAL SRAM_nWE : STD_LOGIC;
125 SIGNAL SRAM_CE : STD_LOGIC;
125 SIGNAL SRAM_CE : STD_LOGIC;
126 SIGNAL SRAM_nOE : STD_LOGIC;
126 SIGNAL SRAM_nOE : STD_LOGIC;
127 SIGNAL SRAM_nBE : STD_LOGIC_VECTOR(3 DOWNTO 0);
127 SIGNAL SRAM_nBE : STD_LOGIC_VECTOR(3 DOWNTO 0);
128 SIGNAL SRAM_A : STD_LOGIC_VECTOR(19 DOWNTO 0);
128 SIGNAL SRAM_A : STD_LOGIC_VECTOR(19 DOWNTO 0);
129 SIGNAL SRAM_DQ : STD_LOGIC_VECTOR(31 DOWNTO 0);
129 SIGNAL SRAM_DQ : STD_LOGIC_VECTOR(31 DOWNTO 0);
130 -----------------------------------------------------------------------------
130 -----------------------------------------------------------------------------
131
131
132 CONSTANT ADDR_BASE_LFR : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000F";
132 CONSTANT ADDR_BASE_LFR : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000F";
133 CONSTANT ADDR_BASE_TIME_MANAGMENT : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"800006";
133 CONSTANT ADDR_BASE_TIME_MANAGMENT : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"800006";
134 CONSTANT ADDR_BASE_GPIO : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000B";
134 CONSTANT ADDR_BASE_GPIO : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000B";
135
135
136
136
137 SIGNAL message_simu : STRING(1 TO 15) := "---------------";
137 SIGNAL message_simu : STRING(1 TO 15) := "---------------";
138 SIGNAL data_message : STRING(1 TO 15) := "---------------";
138 SIGNAL data_message : STRING(1 TO 15) := "---------------";
139 SIGNAL data_read : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
139 SIGNAL data_read : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
140
140
141 BEGIN
141 BEGIN
142
142
143 -----------------------------------------------------------------------------
143 -----------------------------------------------------------------------------
144 -- TB
144 -- TB
145 -----------------------------------------------------------------------------
145 -----------------------------------------------------------------------------
146 PROCESS
146 PROCESS
147 CONSTANT txp : TIME := 320 ns;
147 CONSTANT txp : TIME := 320 ns;
148 VARIABLE data_read_v : STD_LOGIC_VECTOR(31 DOWNTO 0);
148 VARIABLE data_read_v : STD_LOGIC_VECTOR(31 DOWNTO 0);
149 BEGIN -- PROCESS
149 BEGIN -- PROCESS
150 TXD1 <= '1';
150 TXD1 <= '1';
151 reset <= '0';
151 reset <= '0';
152 WAIT FOR 500 ns;
152 WAIT FOR 500 ns;
153 reset <= '1';
153 reset <= '1';
154 WAIT FOR 10000 ns;
154 WAIT FOR 10000 ns;
155 message_simu <= "0 - UART init ";
155 message_simu <= "0 - UART init ";
156 UART_INIT(TXD1,txp);
156 UART_INIT(TXD1,txp);
157
157
158 message_simu <= "1 - UART test ";
158 message_simu <= "1 - UART test ";
159 UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000010",X"0000FFFF");
159 UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000010",X"0000FFFF");
160 UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000001",X"00000A0A");
160 UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000001",X"00000A0A");
161 UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000001",X"00000B0B");
161 UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000001",X"00000B0B");
162 UART_READ(TXD1,RXD1,txp,ADDR_BASE_GPIO & "000001",data_read_v);
162 UART_READ(TXD1,RXD1,txp,ADDR_BASE_GPIO & "000001",data_read_v);
163 data_read <= data_read_v;
163 data_read <= data_read_v;
164 data_message <= "GPIO_data_write";
164 data_message <= "GPIO_data_write";
165
165
166 -- UNSET the LFR reset
166 -- UNSET the LFR reset
167 message_simu <= "2 - LFR UNRESET";
167 message_simu <= "2 - LFR UNRESET";
168 UNRESET_LFR(TXD1,txp,ADDR_BASE_TIME_MANAGMENT);
168 UNRESET_LFR(TXD1,txp,ADDR_BASE_TIME_MANAGMENT);
169 --UART_WRITE(TXD1,txp,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_CONTROL , X"00000000");
169 --UART_WRITE(TXD1,txp,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_CONTROL , X"00000000");
170 --UART_WRITE(TXD1,txp,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_TIME_LOAD , X"00000000");
170 --UART_WRITE(TXD1,txp,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_TIME_LOAD , X"00000000");
171 --
171 --
172 message_simu <= "3 - LFR CONFIG ";
172 message_simu <= "3 - LFR CONFIG ";
173 --UART_WRITE(TXD1,txp,ADDR_BASE_LFR & ADDR_LFR_SM_F0_0_ADDR , X"00000B0B");
173 --UART_WRITE(TXD1,txp,ADDR_BASE_LFR & ADDR_LFR_SM_F0_0_ADDR , X"00000B0B");
174 LAUNCH_SPECTRAL_MATRIX(TXD1,RXD1,txp,ADDR_BASE_LFR,
174 LAUNCH_SPECTRAL_MATRIX(TXD1,RXD1,txp,ADDR_BASE_LFR,
175 X"40000000",
175 X"40000000",
176 X"40001000",
176 X"40001000",
177 X"40002000",
177 X"40002000",
178 X"40003000",
178 X"40003000",
179 X"40004000",
179 X"40004000",
180 X"40005000");
180 X"40005000");
181
181
182
182
183 LAUNCH_WAVEFORM_PICKER(TXD1,RXD1,txp,
183 LAUNCH_WAVEFORM_PICKER(TXD1,RXD1,txp,
184 LFR_MODE_SBM1,
184 LFR_MODE_SBM1,
185 X"7FFFFFFF", -- START DATE
185 X"7FFFFFFF", -- START DATE
186
186
187 "00000",--DATA_SHAPING ( 4 DOWNTO 0)
187 "00000",--DATA_SHAPING ( 4 DOWNTO 0)
188 X"00012BFF",--DELTA_SNAPSHOT(31 DOWNTO 0)
188 X"00012BFF",--DELTA_SNAPSHOT(31 DOWNTO 0)
189 X"0001280A",--DELTA_F0 (31 DOWNTO 0)
189 X"0001280A",--DELTA_F0 (31 DOWNTO 0)
190 X"00000007",--DELTA_F0_2 (31 DOWNTO 0)
190 X"00000007",--DELTA_F0_2 (31 DOWNTO 0)
191 X"0001283F",--DELTA_F1 (31 DOWNTO 0)
191 X"0001283F",--DELTA_F1 (31 DOWNTO 0)
192 X"000127FF",--DELTA_F2 (31 DOWNTO 0)
192 X"000127FF",--DELTA_F2 (31 DOWNTO 0)
193
193
194 ADDR_BASE_LFR,
194 ADDR_BASE_LFR,
195 X"40006000",
195 X"40006000",
196 X"40007000",
196 X"40007000",
197 X"40008000",
197 X"40008000",
198 X"40009000",
198 X"40009000",
199 X"4000A000",
199 X"4000A000",
200 X"4000B000",
200 X"4000B000",
201 X"4000C000",
201 X"4000C000",
202 X"4000D000");
202 X"4000D000");
203
203
204 UART_WRITE(TXD1 ,txp,ADDR_BASE_LFR & ADDR_LFR_WP_LENGTH, X"0000000F");
204 UART_WRITE(TXD1 ,txp,ADDR_BASE_LFR & ADDR_LFR_WP_LENGTH, X"0000000F");
205 UART_WRITE(TXD1 ,txp,ADDR_BASE_LFR & ADDR_LFR_WP_DATA_IN_BUFFER, X"00000050");
205
206
206 message_simu <= "4 - GO GO GO !!";
207 message_simu <= "4 - GO GO GO !!";
207 UART_WRITE (TXD1 ,txp,ADDR_BASE_LFR & ADDR_LFR_WP_START_DATE,X"00000000");
208 UART_WRITE (TXD1 ,txp,ADDR_BASE_LFR & ADDR_LFR_WP_START_DATE,X"00000000");
208
209
209 READ_STATUS: LOOP
210 READ_STATUS: LOOP
210 WAIT FOR 2 ms;
211 WAIT FOR 2 ms;
211 data_message <= "READ_NEW_STATUS";
212 data_message <= "READ_NEW_STATUS";
212 UART_READ(TXD1,RXD1,txp,ADDR_BASE_LFR & ADDR_LFR_SM_STATUS,data_read_v);
213 UART_READ(TXD1,RXD1,txp,ADDR_BASE_LFR & ADDR_LFR_SM_STATUS,data_read_v);
213 data_read <= data_read_v;
214 data_read <= data_read_v;
214 UART_WRITE(TXD1, txp,ADDR_BASE_LFR & ADDR_LFR_SM_STATUS,data_read_v);
215 UART_WRITE(TXD1, txp,ADDR_BASE_LFR & ADDR_LFR_SM_STATUS,data_read_v);
215
216
216 UART_READ(TXD1,RXD1,txp,ADDR_BASE_LFR & ADDR_LFR_WP_STATUS,data_read_v);
217 UART_READ(TXD1,RXD1,txp,ADDR_BASE_LFR & ADDR_LFR_WP_STATUS,data_read_v);
217 data_read <= data_read_v;
218 data_read <= data_read_v;
218 UART_WRITE(TXD1, txp,ADDR_BASE_LFR & ADDR_LFR_WP_STATUS,data_read_v);
219 UART_WRITE(TXD1, txp,ADDR_BASE_LFR & ADDR_LFR_WP_STATUS,data_read_v);
219 END LOOP READ_STATUS;
220 END LOOP READ_STATUS;
220
221
221 WAIT;
222 WAIT;
222 END PROCESS;
223 END PROCESS;
223
224
224 -----------------------------------------------------------------------------
225 -----------------------------------------------------------------------------
225 -- CLOCK
226 -- CLOCK
226 -----------------------------------------------------------------------------
227 -----------------------------------------------------------------------------
227 clk_50 <= NOT clk_50 AFTER 5 ns;
228 clk_50 <= NOT clk_50 AFTER 5 ns;
228 clk_49 <= NOT clk_49 AFTER 10172 ps;
229 clk_49 <= NOT clk_49 AFTER 10172 ps;
229
230
230 -----------------------------------------------------------------------------
231 -----------------------------------------------------------------------------
231 -- DON'T CARE
232 -- DON'T CARE
232 -----------------------------------------------------------------------------
233 -----------------------------------------------------------------------------
233 BP0 <= '0';
234 BP0 <= '0';
234 BP1 <= '0';
235 BP1 <= '0';
235 nRTS1 <= '0' ;
236 nRTS1 <= '0' ;
236
237
237 TXD2 <= '1';
238 TXD2 <= '1';
238 nRTS2 <= '1';
239 nRTS2 <= '1';
239 nDTR2 <= '1';
240 nDTR2 <= '1';
240
241
241 SPW_NOM_DIN <= '1';
242 SPW_NOM_DIN <= '1';
242 SPW_NOM_SIN <= '1';
243 SPW_NOM_SIN <= '1';
243 SPW_RED_DIN <= '1';
244 SPW_RED_DIN <= '1';
244 SPW_RED_SIN <= '1';
245 SPW_RED_SIN <= '1';
245
246
246 ADC_SDO <= x"AA";
247 ADC_SDO <= x"AA";
247
248
248 SRAM_DQ <= (OTHERS => 'Z');
249 SRAM_DQ <= (OTHERS => 'Z');
249 --IO0 <= 'Z';
250 --IO0 <= 'Z';
250 --IO1 <= 'Z';
251 --IO1 <= 'Z';
251 --IO2 <= 'Z';
252 --IO2 <= 'Z';
252 --IO3 <= 'Z';
253 --IO3 <= 'Z';
253 --IO4 <= 'Z';
254 --IO4 <= 'Z';
254 --IO5 <= 'Z';
255 --IO5 <= 'Z';
255 --IO6 <= 'Z';
256 --IO6 <= 'Z';
256 --IO7 <= 'Z';
257 --IO7 <= 'Z';
257 --IO8 <= 'Z';
258 --IO8 <= 'Z';
258 --IO9 <= 'Z';
259 --IO9 <= 'Z';
259 --IO10 <= 'Z';
260 --IO10 <= 'Z';
260 --IO11 <= 'Z';
261 --IO11 <= 'Z';
261
262
262 -----------------------------------------------------------------------------
263 -----------------------------------------------------------------------------
263 -- DUT
264 -- DUT
264 -----------------------------------------------------------------------------
265 -----------------------------------------------------------------------------
265 MINI_LFR_top_1: MINI_LFR_top
266 MINI_LFR_top_1: MINI_LFR_top
266 PORT MAP (
267 PORT MAP (
267 clk_50 => clk_50,
268 clk_50 => clk_50,
268 clk_49 => clk_49,
269 clk_49 => clk_49,
269 reset => reset,
270 reset => reset,
270
271
271 BP0 => BP0,
272 BP0 => BP0,
272 BP1 => BP1,
273 BP1 => BP1,
273
274
274 LED0 => LED0,
275 LED0 => LED0,
275 LED1 => LED1,
276 LED1 => LED1,
276 LED2 => LED2,
277 LED2 => LED2,
277
278
278 TXD1 => TXD1,
279 TXD1 => TXD1,
279 RXD1 => RXD1,
280 RXD1 => RXD1,
280 nCTS1 => nCTS1,
281 nCTS1 => nCTS1,
281 nRTS1 => nRTS1,
282 nRTS1 => nRTS1,
282
283
283 TXD2 => TXD2,
284 TXD2 => TXD2,
284 RXD2 => RXD2,
285 RXD2 => RXD2,
285 nCTS2 => nCTS2,
286 nCTS2 => nCTS2,
286 nDTR2 => nDTR2,
287 nDTR2 => nDTR2,
287 nRTS2 => nRTS2,
288 nRTS2 => nRTS2,
288 nDCD2 => nDCD2,
289 nDCD2 => nDCD2,
289
290
290 IO0 => IO0,
291 IO0 => IO0,
291 IO1 => IO1,
292 IO1 => IO1,
292 IO2 => IO2,
293 IO2 => IO2,
293 IO3 => IO3,
294 IO3 => IO3,
294 IO4 => IO4,
295 IO4 => IO4,
295 IO5 => IO5,
296 IO5 => IO5,
296 IO6 => IO6,
297 IO6 => IO6,
297 IO7 => IO7,
298 IO7 => IO7,
298 IO8 => IO8,
299 IO8 => IO8,
299 IO9 => IO9,
300 IO9 => IO9,
300 IO10 => IO10,
301 IO10 => IO10,
301 IO11 => IO11,
302 IO11 => IO11,
302
303
303 SPW_EN => SPW_EN,
304 SPW_EN => SPW_EN,
304 SPW_NOM_DIN => SPW_NOM_DIN,
305 SPW_NOM_DIN => SPW_NOM_DIN,
305 SPW_NOM_SIN => SPW_NOM_SIN,
306 SPW_NOM_SIN => SPW_NOM_SIN,
306 SPW_NOM_DOUT => SPW_NOM_DOUT,
307 SPW_NOM_DOUT => SPW_NOM_DOUT,
307 SPW_NOM_SOUT => SPW_NOM_SOUT,
308 SPW_NOM_SOUT => SPW_NOM_SOUT,
308 SPW_RED_DIN => SPW_RED_DIN,
309 SPW_RED_DIN => SPW_RED_DIN,
309 SPW_RED_SIN => SPW_RED_SIN,
310 SPW_RED_SIN => SPW_RED_SIN,
310 SPW_RED_DOUT => SPW_RED_DOUT,
311 SPW_RED_DOUT => SPW_RED_DOUT,
311 SPW_RED_SOUT => SPW_RED_SOUT,
312 SPW_RED_SOUT => SPW_RED_SOUT,
312
313
313 ADC_nCS => ADC_nCS,
314 ADC_nCS => ADC_nCS,
314 ADC_CLK => ADC_CLK,
315 ADC_CLK => ADC_CLK,
315 ADC_SDO => ADC_SDO,
316 ADC_SDO => ADC_SDO,
316
317
317 SRAM_nWE => SRAM_nWE,
318 SRAM_nWE => SRAM_nWE,
318 SRAM_CE => SRAM_CE,
319 SRAM_CE => SRAM_CE,
319 SRAM_nOE => SRAM_nOE,
320 SRAM_nOE => SRAM_nOE,
320 SRAM_nBE => SRAM_nBE,
321 SRAM_nBE => SRAM_nBE,
321 SRAM_A => SRAM_A,
322 SRAM_A => SRAM_A,
322 SRAM_DQ => SRAM_DQ);
323 SRAM_DQ => SRAM_DQ);
323
324
324
325
325 END;
326 END;
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@@ -1,471 +1,476
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
21 -- jean-christophe.pellion@easii-ic.com
22 -------------------------------------------------------------------------------
22 -------------------------------------------------------------------------------
23 LIBRARY IEEE;
23 LIBRARY IEEE;
24 USE IEEE.STD_LOGIC_1164.ALL;
24 USE IEEE.STD_LOGIC_1164.ALL;
25 USE ieee.numeric_std.ALL;
25 USE ieee.numeric_std.ALL;
26
26
27 LIBRARY grlib;
27 LIBRARY grlib;
28 USE grlib.amba.ALL;
28 USE grlib.amba.ALL;
29 USE grlib.stdlib.ALL;
29 USE grlib.stdlib.ALL;
30 USE grlib.devices.ALL;
30 USE grlib.devices.ALL;
31 USE GRLIB.DMA2AHB_Package.ALL;
31 USE GRLIB.DMA2AHB_Package.ALL;
32
32
33 LIBRARY lpp;
33 LIBRARY lpp;
34 USE lpp.lpp_waveform_pkg.ALL;
34 USE lpp.lpp_waveform_pkg.ALL;
35 USE lpp.iir_filter.ALL;
35 USE lpp.iir_filter.ALL;
36 USE lpp.lpp_memory.ALL;
36 USE lpp.lpp_memory.ALL;
37
37
38 LIBRARY techmap;
38 LIBRARY techmap;
39 USE techmap.gencomp.ALL;
39 USE techmap.gencomp.ALL;
40
40
41 ENTITY lpp_waveform IS
41 ENTITY lpp_waveform IS
42
42
43 GENERIC (
43 GENERIC (
44 tech : INTEGER := inferred;
44 tech : INTEGER := inferred;
45 data_size : INTEGER := 96; --16*6
45 data_size : INTEGER := 96; --16*6
46 nb_data_by_buffer_size : INTEGER := 11;
46 nb_data_by_buffer_size : INTEGER := 11;
47 -- nb_word_by_buffer_size : INTEGER := 11;
47 -- nb_word_by_buffer_size : INTEGER := 11;
48 nb_snapshot_param_size : INTEGER := 11;
48 nb_snapshot_param_size : INTEGER := 11;
49 delta_vector_size : INTEGER := 20;
49 delta_vector_size : INTEGER := 20;
50 delta_vector_size_f0_2 : INTEGER := 3);
50 delta_vector_size_f0_2 : INTEGER := 3);
51
51
52 PORT (
52 PORT (
53 clk : IN STD_LOGIC;
53 clk : IN STD_LOGIC;
54 rstn : IN STD_LOGIC;
54 rstn : IN STD_LOGIC;
55
55
56 ---- AMBA AHB Master Interface
56 ---- AMBA AHB Master Interface
57 --AHB_Master_In : IN AHB_Mst_In_Type; -- TODO
57 --AHB_Master_In : IN AHB_Mst_In_Type; -- TODO
58 --AHB_Master_Out : OUT AHB_Mst_Out_Type; -- TODO
58 --AHB_Master_Out : OUT AHB_Mst_Out_Type; -- TODO
59
59
60 --config
60 --config
61 reg_run : IN STD_LOGIC;
61 reg_run : IN STD_LOGIC;
62 reg_start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
62 reg_start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
63 reg_delta_snapshot : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
63 reg_delta_snapshot : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
64 reg_delta_f0 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
64 reg_delta_f0 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
65 reg_delta_f0_2 : IN STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
65 reg_delta_f0_2 : IN STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
66 reg_delta_f1 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
66 reg_delta_f1 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
67 reg_delta_f2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
67 reg_delta_f2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
68
68
69 enable_f0 : IN STD_LOGIC;
69 enable_f0 : IN STD_LOGIC;
70 enable_f1 : IN STD_LOGIC;
70 enable_f1 : IN STD_LOGIC;
71 enable_f2 : IN STD_LOGIC;
71 enable_f2 : IN STD_LOGIC;
72 enable_f3 : IN STD_LOGIC;
72 enable_f3 : IN STD_LOGIC;
73
73
74 burst_f0 : IN STD_LOGIC;
74 burst_f0 : IN STD_LOGIC;
75 burst_f1 : IN STD_LOGIC;
75 burst_f1 : IN STD_LOGIC;
76 burst_f2 : IN STD_LOGIC;
76 burst_f2 : IN STD_LOGIC;
77
77
78 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
78 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
79 -- nb_word_by_buffer : IN STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
79 -- nb_word_by_buffer : IN STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
80 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
80 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
81
81
82 status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma
82 status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma
83
83
84
84
85 -- REG DMA
85 -- REG DMA
86 status_buffer_ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
86 status_buffer_ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
87 addr_buffer : IN STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
87 addr_buffer : IN STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
88 length_buffer : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
88 length_buffer : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
89
89
90 ready_buffer : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
90 ready_buffer : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
91 buffer_time : OUT STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
91 buffer_time : OUT STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
92 error_buffer_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
92 error_buffer_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
93
93
94 ---------------------------------------------------------------------------
94 ---------------------------------------------------------------------------
95 -- INPUT
95 -- INPUT
96 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
96 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
97 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
97 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
98
98
99 --f0
99 --f0
100 data_f0_in_valid : IN STD_LOGIC;
100 data_f0_in_valid : IN STD_LOGIC;
101 data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
101 data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
102 --f1
102 --f1
103 data_f1_in_valid : IN STD_LOGIC;
103 data_f1_in_valid : IN STD_LOGIC;
104 data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
104 data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
105 --f2
105 --f2
106 data_f2_in_valid : IN STD_LOGIC;
106 data_f2_in_valid : IN STD_LOGIC;
107 data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
107 data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
108 --f3
108 --f3
109 data_f3_in_valid : IN STD_LOGIC;
109 data_f3_in_valid : IN STD_LOGIC;
110 data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
110 data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
111
111
112 ---------------------------------------------------------------------------
112 ---------------------------------------------------------------------------
113 -- DMA --------------------------------------------------------------------
113 -- DMA --------------------------------------------------------------------
114
114
115 dma_fifo_valid_burst : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
115 dma_fifo_valid_burst : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
116 dma_fifo_data : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
116 dma_fifo_data : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
117 dma_fifo_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
117 dma_fifo_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
118 dma_buffer_new : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
118 dma_buffer_new : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
119 dma_buffer_addr : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
119 dma_buffer_addr : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
120 dma_buffer_length : OUT STD_LOGIC_VECTOR(26*4-1 DOWNTO 0);
120 dma_buffer_length : OUT STD_LOGIC_VECTOR(26*4-1 DOWNTO 0);
121 dma_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
121 dma_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
122 dma_buffer_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0)
122 dma_buffer_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0)
123
123
124 );
124 );
125
125
126 END lpp_waveform;
126 END lpp_waveform;
127
127
128 ARCHITECTURE beh OF lpp_waveform IS
128 ARCHITECTURE beh OF lpp_waveform IS
129 SIGNAL start_snapshot_f0 : STD_LOGIC;
129 SIGNAL start_snapshot_f0 : STD_LOGIC;
130 SIGNAL start_snapshot_f1 : STD_LOGIC;
130 SIGNAL start_snapshot_f1 : STD_LOGIC;
131 SIGNAL start_snapshot_f2 : STD_LOGIC;
131 SIGNAL start_snapshot_f2 : STD_LOGIC;
132
132
133 SIGNAL data_f0_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
133 SIGNAL data_f0_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
134 SIGNAL data_f1_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
134 SIGNAL data_f1_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
135 SIGNAL data_f2_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
135 SIGNAL data_f2_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
136 SIGNAL data_f3_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
136 SIGNAL data_f3_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
137
137
138 SIGNAL data_f0_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
138 SIGNAL data_f0_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
139 SIGNAL data_f1_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
139 SIGNAL data_f1_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
140 SIGNAL data_f2_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
140 SIGNAL data_f2_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
141 SIGNAL data_f3_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
141 SIGNAL data_f3_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
142
142
143 SIGNAL data_f0_out_valid : STD_LOGIC;
143 SIGNAL data_f0_out_valid : STD_LOGIC;
144 SIGNAL data_f1_out_valid : STD_LOGIC;
144 SIGNAL data_f1_out_valid : STD_LOGIC;
145 SIGNAL data_f2_out_valid : STD_LOGIC;
145 SIGNAL data_f2_out_valid : STD_LOGIC;
146 SIGNAL data_f3_out_valid : STD_LOGIC;
146 SIGNAL data_f3_out_valid : STD_LOGIC;
147 SIGNAL nb_snapshot_param_more_one : STD_LOGIC_VECTOR(nb_snapshot_param_size DOWNTO 0);
147 SIGNAL nb_snapshot_param_more_one : STD_LOGIC_VECTOR(nb_snapshot_param_size DOWNTO 0);
148 --
148 --
149 SIGNAL valid_in : STD_LOGIC_VECTOR(3 DOWNTO 0);
149 SIGNAL valid_in : STD_LOGIC_VECTOR(3 DOWNTO 0);
150 SIGNAL valid_out : STD_LOGIC_VECTOR(3 DOWNTO 0);
150 SIGNAL valid_out : STD_LOGIC_VECTOR(3 DOWNTO 0);
151 SIGNAL valid_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
151 SIGNAL valid_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
152 SIGNAL time_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
152 SIGNAL time_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
153 SIGNAL data_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
153 SIGNAL data_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
154 SIGNAL ready_arb : STD_LOGIC_VECTOR(3 DOWNTO 0);
154 SIGNAL ready_arb : STD_LOGIC_VECTOR(3 DOWNTO 0);
155 SIGNAL data_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
155 SIGNAL data_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
156 SIGNAL time_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
156 SIGNAL time_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
157 SIGNAL wdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
157 SIGNAL wdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
158 SIGNAL full_almost : STD_LOGIC_VECTOR(3 DOWNTO 0);
158 SIGNAL full_almost : STD_LOGIC_VECTOR(3 DOWNTO 0);
159 SIGNAL full : STD_LOGIC_VECTOR(3 DOWNTO 0);
159 SIGNAL full : STD_LOGIC_VECTOR(3 DOWNTO 0);
160 SIGNAL empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0);
160 SIGNAL empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0);
161 SIGNAL empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
161 SIGNAL empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
162 --
162 --
163 SIGNAL data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
163 SIGNAL data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
164 SIGNAL time_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
164 SIGNAL time_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
165 SIGNAL rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
165 SIGNAL rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
166 SIGNAL enable : STD_LOGIC_VECTOR(3 DOWNTO 0);
166 SIGNAL enable : STD_LOGIC_VECTOR(3 DOWNTO 0);
167 --
167 --
168 SIGNAL run : STD_LOGIC;
168 SIGNAL run : STD_LOGIC;
169 --
169 --
170 TYPE TIME_VECTOR IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(47 DOWNTO 0);
170 TYPE TIME_VECTOR IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(47 DOWNTO 0);
171 SIGNAL data_out : Data_Vector(3 DOWNTO 0, 95 DOWNTO 0);
171 SIGNAL data_out : Data_Vector(3 DOWNTO 0, 95 DOWNTO 0);
172 SIGNAL time_out_2 : Data_Vector(3 DOWNTO 0, 47 DOWNTO 0);
172 SIGNAL time_out_2 : Data_Vector(3 DOWNTO 0, 47 DOWNTO 0);
173 SIGNAL time_out : TIME_VECTOR(3 DOWNTO 0);
173 SIGNAL time_out : TIME_VECTOR(3 DOWNTO 0);
174 SIGNAL time_out_debug : TIME_VECTOR(3 DOWNTO 0); -- TODO : debug
174 SIGNAL time_out_debug : TIME_VECTOR(3 DOWNTO 0); -- TODO : debug
175 SIGNAL time_reg1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
175 SIGNAL time_reg1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
176 SIGNAL time_reg2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
176 SIGNAL time_reg2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
177 --
177 --
178
178
179 SIGNAL s_empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0); --occupancy is lesser than 16 * 32b
179 SIGNAL s_empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0); --occupancy is lesser than 16 * 32b
180 SIGNAL s_empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
180 SIGNAL s_empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
181 SIGNAL s_data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
181 SIGNAL s_data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
182 -- SIGNAL s_rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
182 -- SIGNAL s_rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
183 SIGNAL s_rdata_v : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
183 SIGNAL s_rdata_v : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
184
184
185 --
185 --
186 SIGNAL arbiter_time_out : STD_LOGIC_VECTOR(47 DOWNTO 0);
186 SIGNAL arbiter_time_out : STD_LOGIC_VECTOR(47 DOWNTO 0);
187 SIGNAL arbiter_time_out_new : STD_LOGIC_VECTOR(3 DOWNTO 0);
187 SIGNAL arbiter_time_out_new : STD_LOGIC_VECTOR(3 DOWNTO 0);
188
188
189 SIGNAL fifo_buffer_time : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
189 SIGNAL fifo_buffer_time : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
190
190
191 SIGNAL fifo_buffer_time_s : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
192
191 BEGIN -- beh
193 BEGIN -- beh
192
194
193 -----------------------------------------------------------------------------
195 -----------------------------------------------------------------------------
194
196
195 lpp_waveform_snapshot_controler_1 : lpp_waveform_snapshot_controler
197 lpp_waveform_snapshot_controler_1 : lpp_waveform_snapshot_controler
196 GENERIC MAP (
198 GENERIC MAP (
197 delta_vector_size => delta_vector_size,
199 delta_vector_size => delta_vector_size,
198 delta_vector_size_f0_2 => delta_vector_size_f0_2
200 delta_vector_size_f0_2 => delta_vector_size_f0_2
199 )
201 )
200 PORT MAP (
202 PORT MAP (
201 clk => clk,
203 clk => clk,
202 rstn => rstn,
204 rstn => rstn,
203 reg_run => reg_run,
205 reg_run => reg_run,
204 reg_start_date => reg_start_date,
206 reg_start_date => reg_start_date,
205 reg_delta_snapshot => reg_delta_snapshot,
207 reg_delta_snapshot => reg_delta_snapshot,
206 reg_delta_f0 => reg_delta_f0,
208 reg_delta_f0 => reg_delta_f0,
207 reg_delta_f0_2 => reg_delta_f0_2,
209 reg_delta_f0_2 => reg_delta_f0_2,
208 reg_delta_f1 => reg_delta_f1,
210 reg_delta_f1 => reg_delta_f1,
209 reg_delta_f2 => reg_delta_f2,
211 reg_delta_f2 => reg_delta_f2,
210 coarse_time => coarse_time(30 DOWNTO 0),
212 coarse_time => coarse_time(30 DOWNTO 0),
211 data_f0_valid => data_f0_in_valid,
213 data_f0_valid => data_f0_in_valid,
212 data_f2_valid => data_f2_in_valid,
214 data_f2_valid => data_f2_in_valid,
213 start_snapshot_f0 => start_snapshot_f0,
215 start_snapshot_f0 => start_snapshot_f0,
214 start_snapshot_f1 => start_snapshot_f1,
216 start_snapshot_f1 => start_snapshot_f1,
215 start_snapshot_f2 => start_snapshot_f2,
217 start_snapshot_f2 => start_snapshot_f2,
216 wfp_on => run);
218 wfp_on => run);
217
219
218 lpp_waveform_snapshot_f0 : lpp_waveform_snapshot
220 lpp_waveform_snapshot_f0 : lpp_waveform_snapshot
219 GENERIC MAP (
221 GENERIC MAP (
220 data_size => data_size,
222 data_size => data_size,
221 nb_snapshot_param_size => nb_snapshot_param_size)
223 nb_snapshot_param_size => nb_snapshot_param_size)
222 PORT MAP (
224 PORT MAP (
223 clk => clk,
225 clk => clk,
224 rstn => rstn,
226 rstn => rstn,
225 run => run,
227 run => run,
226 enable => enable_f0,
228 enable => enable_f0,
227 burst_enable => burst_f0,
229 burst_enable => burst_f0,
228 nb_snapshot_param => nb_snapshot_param,
230 nb_snapshot_param => nb_snapshot_param,
229 start_snapshot => start_snapshot_f0,
231 start_snapshot => start_snapshot_f0,
230 data_in => data_f0_in,
232 data_in => data_f0_in,
231 data_in_valid => data_f0_in_valid,
233 data_in_valid => data_f0_in_valid,
232 data_out => data_f0_out,
234 data_out => data_f0_out,
233 data_out_valid => data_f0_out_valid);
235 data_out_valid => data_f0_out_valid);
234
236
235 nb_snapshot_param_more_one <= ('0' & nb_snapshot_param) ;--+ 1;
237 nb_snapshot_param_more_one <= ('0' & nb_snapshot_param) ;--+ 1;
236
238
237 lpp_waveform_snapshot_f1 : lpp_waveform_snapshot
239 lpp_waveform_snapshot_f1 : lpp_waveform_snapshot
238 GENERIC MAP (
240 GENERIC MAP (
239 data_size => data_size,
241 data_size => data_size,
240 nb_snapshot_param_size => nb_snapshot_param_size+1)
242 nb_snapshot_param_size => nb_snapshot_param_size+1)
241 PORT MAP (
243 PORT MAP (
242 clk => clk,
244 clk => clk,
243 rstn => rstn,
245 rstn => rstn,
244 run => run,
246 run => run,
245 enable => enable_f1,
247 enable => enable_f1,
246 burst_enable => burst_f1,
248 burst_enable => burst_f1,
247 nb_snapshot_param => nb_snapshot_param_more_one,
249 nb_snapshot_param => nb_snapshot_param_more_one,
248 start_snapshot => start_snapshot_f1,
250 start_snapshot => start_snapshot_f1,
249 data_in => data_f1_in,
251 data_in => data_f1_in,
250 data_in_valid => data_f1_in_valid,
252 data_in_valid => data_f1_in_valid,
251 data_out => data_f1_out,
253 data_out => data_f1_out,
252 data_out_valid => data_f1_out_valid);
254 data_out_valid => data_f1_out_valid);
253
255
254 lpp_waveform_snapshot_f2 : lpp_waveform_snapshot
256 lpp_waveform_snapshot_f2 : lpp_waveform_snapshot
255 GENERIC MAP (
257 GENERIC MAP (
256 data_size => data_size,
258 data_size => data_size,
257 nb_snapshot_param_size => nb_snapshot_param_size+1)
259 nb_snapshot_param_size => nb_snapshot_param_size+1)
258 PORT MAP (
260 PORT MAP (
259 clk => clk,
261 clk => clk,
260 rstn => rstn,
262 rstn => rstn,
261 run => run,
263 run => run,
262 enable => enable_f2,
264 enable => enable_f2,
263 burst_enable => burst_f2,
265 burst_enable => burst_f2,
264 nb_snapshot_param => nb_snapshot_param_more_one,
266 nb_snapshot_param => nb_snapshot_param_more_one,
265 start_snapshot => start_snapshot_f2,
267 start_snapshot => start_snapshot_f2,
266 data_in => data_f2_in,
268 data_in => data_f2_in,
267 data_in_valid => data_f2_in_valid,
269 data_in_valid => data_f2_in_valid,
268 data_out => data_f2_out,
270 data_out => data_f2_out,
269 data_out_valid => data_f2_out_valid);
271 data_out_valid => data_f2_out_valid);
270
272
271 lpp_waveform_burst_f3 : lpp_waveform_burst
273 lpp_waveform_burst_f3 : lpp_waveform_burst
272 GENERIC MAP (
274 GENERIC MAP (
273 data_size => data_size)
275 data_size => data_size)
274 PORT MAP (
276 PORT MAP (
275 clk => clk,
277 clk => clk,
276 rstn => rstn,
278 rstn => rstn,
277 run => run,
279 run => run,
278 enable => enable_f3,
280 enable => enable_f3,
279 data_in => data_f3_in,
281 data_in => data_f3_in,
280 data_in_valid => data_f3_in_valid,
282 data_in_valid => data_f3_in_valid,
281 data_out => data_f3_out,
283 data_out => data_f3_out,
282 data_out_valid => data_f3_out_valid);
284 data_out_valid => data_f3_out_valid);
283
285
284 -----------------------------------------------------------------------------
286 -----------------------------------------------------------------------------
285 -- DEBUG -- SNAPSHOT OUT
287 -- DEBUG -- SNAPSHOT OUT
286 --debug_f0_data_valid <= data_f0_out_valid;
288 --debug_f0_data_valid <= data_f0_out_valid;
287 --debug_f0_data <= data_f0_out;
289 --debug_f0_data <= data_f0_out;
288 --debug_f1_data_valid <= data_f1_out_valid;
290 --debug_f1_data_valid <= data_f1_out_valid;
289 --debug_f1_data <= data_f1_out;
291 --debug_f1_data <= data_f1_out;
290 --debug_f2_data_valid <= data_f2_out_valid;
292 --debug_f2_data_valid <= data_f2_out_valid;
291 --debug_f2_data <= data_f2_out;
293 --debug_f2_data <= data_f2_out;
292 --debug_f3_data_valid <= data_f3_out_valid;
294 --debug_f3_data_valid <= data_f3_out_valid;
293 --debug_f3_data <= data_f3_out;
295 --debug_f3_data <= data_f3_out;
294 -----------------------------------------------------------------------------
296 -----------------------------------------------------------------------------
295
297
296 PROCESS (clk, rstn)
298 PROCESS (clk, rstn)
297 BEGIN -- PROCESS
299 BEGIN -- PROCESS
298 IF rstn = '0' THEN -- asynchronous reset (active low)
300 IF rstn = '0' THEN -- asynchronous reset (active low)
299 time_reg1 <= (OTHERS => '0');
301 time_reg1 <= (OTHERS => '0');
300 time_reg2 <= (OTHERS => '0');
302 time_reg2 <= (OTHERS => '0');
301 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
303 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
302 time_reg1 <= fine_time & coarse_time;
304 time_reg1 <= fine_time & coarse_time;
303 time_reg2 <= time_reg1;
305 time_reg2 <= time_reg1;
304 END IF;
306 END IF;
305 END PROCESS;
307 END PROCESS;
306
308
307 valid_in <= data_f3_out_valid & data_f2_out_valid & data_f1_out_valid & data_f0_out_valid;
309 valid_in <= data_f3_out_valid & data_f2_out_valid & data_f1_out_valid & data_f0_out_valid;
308 all_input_valid : FOR i IN 3 DOWNTO 0 GENERATE
310 all_input_valid : FOR i IN 3 DOWNTO 0 GENERATE
309 lpp_waveform_dma_genvalid_I : lpp_waveform_dma_genvalid
311 lpp_waveform_dma_genvalid_I : lpp_waveform_dma_genvalid
310 PORT MAP (
312 PORT MAP (
311 HCLK => clk,
313 HCLK => clk,
312 HRESETn => rstn,
314 HRESETn => rstn,
313 run => run,
315 run => run,
314 valid_in => valid_in(I),
316 valid_in => valid_in(I),
315 ack_in => valid_ack(I),
317 ack_in => valid_ack(I),
316 time_in => time_reg2, -- Todo
318 time_in => time_reg2, -- Todo
317 valid_out => valid_out(I),
319 valid_out => valid_out(I),
318 time_out => time_out(I), -- Todo
320 time_out => time_out(I), -- Todo
319 error => status_new_err(I));
321 error => status_new_err(I));
320 END GENERATE all_input_valid;
322 END GENERATE all_input_valid;
321
323
322 data_f0_out_swap <= data_f0_out((16*5)-1 DOWNTO 16*4) &
324 data_f0_out_swap <= data_f0_out((16*5)-1 DOWNTO 16*4) &
323 data_f0_out((16*6)-1 DOWNTO 16*5) &
325 data_f0_out((16*6)-1 DOWNTO 16*5) &
324 data_f0_out((16*3)-1 DOWNTO 16*2) &
326 data_f0_out((16*3)-1 DOWNTO 16*2) &
325 data_f0_out((16*4)-1 DOWNTO 16*3) &
327 data_f0_out((16*4)-1 DOWNTO 16*3) &
326 data_f0_out((16*1)-1 DOWNTO 16*0) &
328 data_f0_out((16*1)-1 DOWNTO 16*0) &
327 data_f0_out((16*2)-1 DOWNTO 16*1) ;
329 data_f0_out((16*2)-1 DOWNTO 16*1) ;
328
330
329 data_f1_out_swap <= data_f1_out((16*5)-1 DOWNTO 16*4) &
331 data_f1_out_swap <= data_f1_out((16*5)-1 DOWNTO 16*4) &
330 data_f1_out((16*6)-1 DOWNTO 16*5) &
332 data_f1_out((16*6)-1 DOWNTO 16*5) &
331 data_f1_out((16*3)-1 DOWNTO 16*2) &
333 data_f1_out((16*3)-1 DOWNTO 16*2) &
332 data_f1_out((16*4)-1 DOWNTO 16*3) &
334 data_f1_out((16*4)-1 DOWNTO 16*3) &
333 data_f1_out((16*1)-1 DOWNTO 16*0) &
335 data_f1_out((16*1)-1 DOWNTO 16*0) &
334 data_f1_out((16*2)-1 DOWNTO 16*1) ;
336 data_f1_out((16*2)-1 DOWNTO 16*1) ;
335
337
336 data_f2_out_swap <= data_f2_out((16*5)-1 DOWNTO 16*4) &
338 data_f2_out_swap <= data_f2_out((16*5)-1 DOWNTO 16*4) &
337 data_f2_out((16*6)-1 DOWNTO 16*5) &
339 data_f2_out((16*6)-1 DOWNTO 16*5) &
338 data_f2_out((16*3)-1 DOWNTO 16*2) &
340 data_f2_out((16*3)-1 DOWNTO 16*2) &
339 data_f2_out((16*4)-1 DOWNTO 16*3) &
341 data_f2_out((16*4)-1 DOWNTO 16*3) &
340 data_f2_out((16*1)-1 DOWNTO 16*0) &
342 data_f2_out((16*1)-1 DOWNTO 16*0) &
341 data_f2_out((16*2)-1 DOWNTO 16*1) ;
343 data_f2_out((16*2)-1 DOWNTO 16*1) ;
342
344
343 data_f3_out_swap <= data_f3_out((16*5)-1 DOWNTO 16*4) &
345 data_f3_out_swap <= data_f3_out((16*5)-1 DOWNTO 16*4) &
344 data_f3_out((16*6)-1 DOWNTO 16*5) &
346 data_f3_out((16*6)-1 DOWNTO 16*5) &
345 data_f3_out((16*3)-1 DOWNTO 16*2) &
347 data_f3_out((16*3)-1 DOWNTO 16*2) &
346 data_f3_out((16*4)-1 DOWNTO 16*3) &
348 data_f3_out((16*4)-1 DOWNTO 16*3) &
347 data_f3_out((16*1)-1 DOWNTO 16*0) &
349 data_f3_out((16*1)-1 DOWNTO 16*0) &
348 data_f3_out((16*2)-1 DOWNTO 16*1) ;
350 data_f3_out((16*2)-1 DOWNTO 16*1) ;
349
351
350 all_bit_of_data_out : FOR I IN 95 DOWNTO 0 GENERATE
352 all_bit_of_data_out : FOR I IN 95 DOWNTO 0 GENERATE
351 data_out(0, I) <= data_f0_out_swap(I);
353 data_out(0, I) <= data_f0_out_swap(I);
352 data_out(1, I) <= data_f1_out_swap(I);
354 data_out(1, I) <= data_f1_out_swap(I);
353 data_out(2, I) <= data_f2_out_swap(I);
355 data_out(2, I) <= data_f2_out_swap(I);
354 data_out(3, I) <= data_f3_out_swap(I);
356 data_out(3, I) <= data_f3_out_swap(I);
355 END GENERATE all_bit_of_data_out;
357 END GENERATE all_bit_of_data_out;
356
358
357 -----------------------------------------------------------------------------
359 -----------------------------------------------------------------------------
358 -- TODO : debug
360 -- TODO : debug
359 -----------------------------------------------------------------------------
361 -----------------------------------------------------------------------------
360 all_bit_of_time_out : FOR I IN 47 DOWNTO 0 GENERATE
362 all_bit_of_time_out : FOR I IN 47 DOWNTO 0 GENERATE
361 all_sample_of_time_out : FOR J IN 3 DOWNTO 0 GENERATE
363 all_sample_of_time_out : FOR J IN 3 DOWNTO 0 GENERATE
362 time_out_2(J, I) <= time_out(J)(I);
364 time_out_2(J, I) <= time_out(J)(I);
363 END GENERATE all_sample_of_time_out;
365 END GENERATE all_sample_of_time_out;
364 END GENERATE all_bit_of_time_out;
366 END GENERATE all_bit_of_time_out;
365
367
366 lpp_waveform_fifo_arbiter_1 : lpp_waveform_fifo_arbiter
368 lpp_waveform_fifo_arbiter_1 : lpp_waveform_fifo_arbiter
367 GENERIC MAP (tech => tech,
369 GENERIC MAP (tech => tech,
368 nb_data_by_buffer_size => nb_data_by_buffer_size)
370 nb_data_by_buffer_size => nb_data_by_buffer_size)
369 PORT MAP (
371 PORT MAP (
370 clk => clk,
372 clk => clk,
371 rstn => rstn,
373 rstn => rstn,
372 run => run,
374 run => run,
373 nb_data_by_buffer => nb_data_by_buffer,
375 nb_data_by_buffer => nb_data_by_buffer,
374 data_in_valid => valid_out,
376 data_in_valid => valid_out,
375 data_in_ack => valid_ack,
377 data_in_ack => valid_ack,
376 data_in => data_out,
378 data_in => data_out,
377 time_in => time_out_2,
379 time_in => time_out_2,
378
380
379 data_out => wdata,
381 data_out => wdata,
380 data_out_wen => data_wen,
382 data_out_wen => data_wen,
381 full_almost => full_almost,
383 full_almost => full_almost,
382 full => full,
384 full => full,
383
385
384 time_out => arbiter_time_out,
386 time_out => arbiter_time_out,
385 time_out_new => arbiter_time_out_new
387 time_out_new => arbiter_time_out_new
386
388
387 );
389 );
388
390
389 -----------------------------------------------------------------------------
391 -----------------------------------------------------------------------------
390 -----------------------------------------------------------------------------
392 -----------------------------------------------------------------------------
391
393
392 generate_all_fifo: FOR I IN 0 TO 3 GENERATE
394 generate_all_fifo: FOR I IN 0 TO 3 GENERATE
393 lpp_fifo_1: lpp_fifo
395 lpp_fifo_1: lpp_fifo
394 GENERIC MAP (
396 GENERIC MAP (
395 tech => tech,
397 tech => tech,
396 Mem_use => use_RAM,
398 Mem_use => use_RAM,
397 EMPTY_THRESHOLD_LIMIT => 15,
399 EMPTY_THRESHOLD_LIMIT => 15,
398 FULL_THRESHOLD_LIMIT => 3,
400 FULL_THRESHOLD_LIMIT => 3,
399 DataSz => 32,
401 DataSz => 32,
400 AddrSz => 7)
402 AddrSz => 7)
401 PORT MAP (
403 PORT MAP (
402 clk => clk,
404 clk => clk,
403 rstn => rstn,
405 rstn => rstn,
404 reUse => '0',
406 reUse => '0',
405 run => run,
407 run => run,
406 ren => data_ren(I),
408 ren => data_ren(I),
407 rdata => s_rdata_v((I+1)*32-1 downto I*32),
409 rdata => s_rdata_v((I+1)*32-1 downto I*32),
408 wen => data_wen(I),
410 wen => data_wen(I),
409 wdata => wdata,
411 wdata => wdata,
410 empty => empty(I),
412 empty => empty(I),
411 full => full(I),
413 full => full(I),
412 full_almost => OPEN,
414 full_almost => OPEN,
413 empty_threshold => empty_almost(I),
415 empty_threshold => empty_almost(I),
414 full_threshold => full_almost(I) );
416 full_threshold => full_almost(I) );
415
417
416 END GENERATE generate_all_fifo;
418 END GENERATE generate_all_fifo;
417
419
418 -----------------------------------------------------------------------------
420 -----------------------------------------------------------------------------
419 --
421 --
420 -----------------------------------------------------------------------------
422 -----------------------------------------------------------------------------
421
423
422 all_channel: FOR I IN 3 DOWNTO 0 GENERATE
424 all_channel: FOR I IN 3 DOWNTO 0 GENERATE
423
425
424 PROCESS (clk, rstn)
426 PROCESS (clk, rstn)
425 BEGIN
427 BEGIN
426 IF rstn = '0' THEN
428 IF rstn = '0' THEN
427 fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I) <= (OTHERS => '0');
429 fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I) <= (OTHERS => '0');
428 ELSIF clk'event AND clk = '1' THEN
430 ELSIF clk'event AND clk = '1' THEN
429 IF run = '0' THEN
431 IF run = '0' THEN
430 fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I) <= (OTHERS => '0');
432 fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I) <= (OTHERS => '0');
431 ELSE
433 ELSE
432 IF arbiter_time_out_new(I) = '0' THEN
434 IF arbiter_time_out_new(I) = '1' THEN -- modif JC 15-01-2015
433 fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I) <= arbiter_time_out;
435 fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I) <= arbiter_time_out;
434 END IF;
436 END IF;
435 END IF;
437 END IF;
436 END IF;
438 END IF;
437 END PROCESS;
439 END PROCESS;
438
440
441 fifo_buffer_time_s(48*(I+1)-1 DOWNTO 48*I) <= arbiter_time_out WHEN arbiter_time_out_new(I) = '1' ELSE
442 fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I);
443
439 lpp_waveform_fsmdma_I: lpp_waveform_fsmdma
444 lpp_waveform_fsmdma_I: lpp_waveform_fsmdma
440 PORT MAP (
445 PORT MAP (
441 clk => clk,
446 clk => clk,
442 rstn => rstn,
447 rstn => rstn,
443 run => run,
448 run => run,
444
449
445 fifo_buffer_time => fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I),
450 fifo_buffer_time => fifo_buffer_time_s(48*(I+1)-1 DOWNTO 48*I),
446
451
447 fifo_data => s_rdata_v(32*(I+1)-1 DOWNTO 32*I),
452 fifo_data => s_rdata_v(32*(I+1)-1 DOWNTO 32*I),
448 fifo_empty => empty(I),
453 fifo_empty => empty(I),
449 fifo_empty_threshold => empty_almost(I),
454 fifo_empty_threshold => empty_almost(I),
450 fifo_ren => data_ren(I),
455 fifo_ren => data_ren(I),
451
456
452 dma_fifo_valid_burst => dma_fifo_valid_burst(I),
457 dma_fifo_valid_burst => dma_fifo_valid_burst(I),
453 dma_fifo_data => dma_fifo_data(32*(I+1)-1 DOWNTO 32*I),
458 dma_fifo_data => dma_fifo_data(32*(I+1)-1 DOWNTO 32*I),
454 dma_fifo_ren => dma_fifo_ren(I),
459 dma_fifo_ren => dma_fifo_ren(I),
455 dma_buffer_new => dma_buffer_new(I),
460 dma_buffer_new => dma_buffer_new(I),
456 dma_buffer_addr => dma_buffer_addr(32*(I+1)-1 DOWNTO 32*I),
461 dma_buffer_addr => dma_buffer_addr(32*(I+1)-1 DOWNTO 32*I),
457 dma_buffer_length => dma_buffer_length(26*(I+1)-1 DOWNTO 26*I),
462 dma_buffer_length => dma_buffer_length(26*(I+1)-1 DOWNTO 26*I),
458 dma_buffer_full => dma_buffer_full(I),
463 dma_buffer_full => dma_buffer_full(I),
459 dma_buffer_full_err => dma_buffer_full_err(I),
464 dma_buffer_full_err => dma_buffer_full_err(I),
460
465
461 status_buffer_ready => status_buffer_ready(I), -- TODO
466 status_buffer_ready => status_buffer_ready(I), -- TODO
462 addr_buffer => addr_buffer(32*(I+1)-1 DOWNTO 32*I), -- TODO
467 addr_buffer => addr_buffer(32*(I+1)-1 DOWNTO 32*I), -- TODO
463 length_buffer => length_buffer,--(26*(I+1)-1 DOWNTO 26*I), -- TODO
468 length_buffer => length_buffer,--(26*(I+1)-1 DOWNTO 26*I), -- TODO
464 ready_buffer => ready_buffer(I), -- TODO
469 ready_buffer => ready_buffer(I), -- TODO
465 buffer_time => buffer_time(48*(I+1)-1 DOWNTO 48*I), -- TODO
470 buffer_time => buffer_time(48*(I+1)-1 DOWNTO 48*I), -- TODO
466 error_buffer_full => error_buffer_full(I)); -- TODO
471 error_buffer_full => error_buffer_full(I)); -- TODO
467
472
468 END GENERATE all_channel;
473 END GENERATE all_channel;
469
474
470
475
471 END beh;
476 END beh;
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